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WO2018150776A1 - Substrat de réseau, élément monté, dispositif comprenant un substrat de réseau et procédé de production d'un substrat de réseau - Google Patents

Substrat de réseau, élément monté, dispositif comprenant un substrat de réseau et procédé de production d'un substrat de réseau Download PDF

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Publication number
WO2018150776A1
WO2018150776A1 PCT/JP2018/000747 JP2018000747W WO2018150776A1 WO 2018150776 A1 WO2018150776 A1 WO 2018150776A1 JP 2018000747 W JP2018000747 W JP 2018000747W WO 2018150776 A1 WO2018150776 A1 WO 2018150776A1
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WO
WIPO (PCT)
Prior art keywords
elements
array substrate
bump
mounting
main body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/000747
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English (en)
Japanese (ja)
Inventor
研 足立
修一 岡
周作 柳川
出穂 畑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to CN201880010798.4A priority Critical patent/CN110268459A/zh
Publication of WO2018150776A1 publication Critical patent/WO2018150776A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Definitions

  • This technology relates to a technology such as an array substrate on which a large number of elements are mounted.
  • Patent Document 1 describes a mounting method including a step of manufacturing an EL display device by transferring a TFT chip from a transfer source substrate to a mounting substrate.
  • the transfer source substrate is opposed to a mounting substrate including bumps covered with an adhesive (see FIG. 2E).
  • the connection terminal of the TET chip attached to the transfer source substrate through the release layer is pressure-bonded to the bump (see FIG. 2F).
  • a release member attached on another TFT chip also adheres to the adhesive.
  • Light is irradiated to the TFT chip through the mask (see FIG. 2G).
  • peeling of the peeling layer is induced, and the TFT chip is mounted on the mounting substrate via the adhesive (see FIG. 2H) (see, for example, paragraphs [0024] and [0025] of the specification of Patent Document 1). .)
  • Patent Document 1 since the method of Patent Document 1 includes a step of forming a release member in each region of the non-transfer chip while avoiding the region of the transfer chip, the necessary materials increase and the process becomes complicated. . Further, since the release member remains on the mounting substrate, it becomes difficult to mount the chip on the remaining portion.
  • an array substrate includes a mounting substrate and a plurality of elements.
  • the plurality of elements include two or more first elements and one or more second elements different from the first elements, and are mounted so as to be arranged in an array structure on the mounting substrate.
  • Each of the plurality of elements may have a main body and one or more bumps provided on the main body.
  • the length of one side of the main body of the second element may be shorter than that of the first element. This facilitates the mounting of the second element in the removal region after removal of the specific or arbitrary first element.
  • the mounting substrate has lands to which bumps of the plurality of elements are connected.
  • the difference between the length of one side of the main body of the second element and that of the first element may be twice or more the sum of the radius of the land and the radius of the bump of the second element.
  • the length of one side of the main body of the first element may be not less than 60 ⁇ m and not more than 2000 ⁇ m, and the length of one side of the main body of the second element may be not less than 50 ⁇ m and not more than 1990 ⁇ m.
  • the first element may have a first bump group.
  • the second element may include a second bump group having an arrangement that matches the arrangement of the first bump group.
  • the arrangement of the first bump group includes the arrangement of the second bump group. You may do it.
  • the first element may include a first bump group
  • the second element may include a second bump group having an arrangement different from the entire arrangement of the first bump group.
  • the bump height of the second element may be lower than the bump height of the first element.
  • the bumps of the second element may have at least two different heights.
  • the mounting element which concerns on one form is the said 2nd element mounted in the mounting board
  • the plurality of elements are arranged in an array structure on the mounting substrate.
  • the mounting element includes a main body configured such that the length of one side is shorter than the length of one side of the main body of the first element, and one or more bumps provided on the main body.
  • a device includes the array substrate.
  • a method for manufacturing an array substrate includes transferring and mounting a plurality of first elements arranged in an array structure on a mounting substrate. One or more first elements of the plurality of first elements are removed from the mounting substrate. One or more second elements different from the first element are mounted in the removal region on the mounting substrate where the first element is removed.
  • the plurality of first elements are mounted on the mounting substrate by transfer, and the second element is mounted in the removal region from which the first element has been removed.
  • An array substrate including elements can be easily manufactured.
  • Each of the plurality of elements may have a main body and one or more bumps provided on the main body.
  • the mounting board may have lands to which bumps of the plurality of elements are connected.
  • the height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element. You may be comprised lower than the height of the bump of an element.
  • the second element may be configured as follows. That is, after mounting the second element, the bumps of the second element before mounting the second element are at least two different heights so that the mounting substrate and the main body of the second element are parallel to each other. You may have.
  • the second element may be arranged on the mounting substrate so that a main body of the second element is inclined with respect to the mounting substrate after mounting the second element.
  • the bumps of the second element may have at least two different heights.
  • FIG. 1 is a diagram illustrating an array substrate according to an embodiment of the present technology.
  • 2A to 2E are views showing a method of manufacturing an array substrate.
  • FIG. 3 shows a state where the manufactured array substrate is cut and divided at a position indicated by a broken line to form a plurality of array substrates.
  • FIG. 4 is a diagram showing a device using an array substrate.
  • FIG. 5 is a diagram for illustrating the sizes of the first element 1 and the second element.
  • 6A to 6C are sectional views showing manufacturing steps of the array substrate shown in FIGS. 2C to 2E.
  • FIG. 7 shows a mounting example when the sizes of the first element and the second element are the same.
  • FIG. 8 is a diagram for explaining the shift amount of the second element, and is an enlarged view of a portion surrounded by a one-dot chain line in FIG. 6C.
  • 9A to 9D are diagrams showing various forms of the arrangement of the bump groups of the element.
  • FIG. 10 shows a form in which the arrangement of the second bump group is not included in the arrangement of the first bump group.
  • FIG. 11 is a cross-sectional view showing a mounting substrate having residual solder of the first bump group.
  • 12A and 12B are cross-sectional views showing a first element and a second element for explaining the height of the bump, respectively.
  • 13A and 13B show a mounting process in the case where the bump height of the first element is the same as that of the second element.
  • FIG. 14A and 14B show a mounting process in the case where the bump height of the first element is different from that of the second element.
  • FIG. 15 shows a case where the amount of residual solder on the land is different in one removal region.
  • FIG. 16 shows a form in which the bump diameter of the second element is different when the amount of residual solder on the land is different in one removal region.
  • FIG. 17 shows a form in which the bump diameter of the second element is different when the amount of residual solder on the land is the same in one removal region.
  • FIG. 1 is a diagram illustrating an array substrate 50 according to an embodiment of the present technology.
  • the array substrate 50 includes a mounting substrate 10 and a plurality of elements 15 on the mounting substrate 10.
  • the plurality of elements 15 are mounted on the mounting substrate 10 so as to be arranged in an array structure.
  • the plurality of elements 15 include two or more (plural) first elements 11 and one or more second elements 12 (mounting elements) different from the first elements 11. In the present embodiment, two or more second elements 12 are provided.
  • one element 11 is a light receiving element
  • the second element 12 is a light emitting element
  • the array substrate 50 is used as an imaging device, for example.
  • the first element 11 is a light emitting element
  • the second element 12 is a light receiving element
  • the array substrate 50 is used as a display device, for example.
  • An example of the light receiving element is a photodiode.
  • the light emitting element include LED (Light Emitting Diode), LD (Laser Diode), and organic EL (Electro-Luminescence).
  • An array structure array is typically a matrix array along two orthogonal axes (xy axes).
  • the array structure includes, in addition to this matrix-like arrangement, a staggered arrangement, an arrangement along a straight line or a curve in two dimensions, and an arrangement having an arrangement having regularity or geometric characteristics.
  • the number of second elements 12 is smaller than the number of first elements 11.
  • the ratio of the number of the second elements 12 to the number of the first elements 11 is 1 ppm to 30%, and more practically 0.01% to 15%. .
  • the plurality of second elements 12 may be arranged adjacently and continuously in a predetermined region on the array substrate 50.
  • FIG. 2A to 2E are diagrams showing a method of manufacturing the array substrate 50.
  • a transfer source substrate 60 such as a semiconductor wafer on which a plurality of first elements 11 are formed is prepared.
  • FIG. 2B a mounting substrate 10 which is an unmounted transfer destination substrate is prepared.
  • the first elements 11 are formed in an array structure at a pitch substantially the same as the mounting pitch on the mounting substrate 10 or a suitable pitch.
  • a UBM UnderUBump Metalization
  • Lands (not shown here) configured as are formed respectively.
  • Corresponding solder bumps (not shown here) are formed on the lands of the first element 11.
  • the solder bump is simply referred to as “bump”.
  • the first element 11 is transferred from the transfer source substrate 60 to the mounting substrate 10.
  • the first elements 11 are collectively transferred to the mounting substrate 10 over the entire surface of a predetermined mounting area.
  • this transfer method for example, the transfer source substrate 60 and the mounting substrate 10 are aligned, superposed, and the first element 11 is mounted on the mounting substrate 10 by heat treatment such as reflow (of the first element 11). Bump joins to land).
  • one or more first elements 11 arranged at predetermined positions on the mounting substrate 10 are removed from the mounting substrate 10.
  • the plurality of first elements 11 are removed.
  • Examples of the removal method include known methods described in JP 2001-007508, 2010-36232, 2004-260053, 2013-21325, and the like.
  • one or more second elements 12 are mounted on the removal region 14 on the mounting substrate 10 after the first element 11 is removed.
  • the plurality of second elements 12 are mounted in the plurality of removal regions 14, respectively. Thereby, the array substrate 50 is completed.
  • a mounting method of the second element 12 for example, transfer by laser ablation may be used, or a component mounting machine may be used.
  • FIG. 3 shows a state where the array substrate 50 manufactured as described above is cut and divided at a position indicated by a broken line to form a plurality of array substrates 50 ′. In this figure, it is divided into four, but it may be divided into five or more. Thereby, a plurality of array substrates 50 ′ are formed from one array substrate 50.
  • the plurality of first elements 11 are mounted on the mounting substrate 10 simultaneously by transfer, and the second elements 12 are mounted in the removal region 14 where the first elements 11 are removed.
  • This manufacturing method does not include a complicated process, and can easily manufacture the array substrate 50 including the first element 11 and the second element 12.
  • cost reduction is realizable. Further, no extra material such as a release member is left on the completed array substrate 50.
  • a repair element having the same function as the first element 11 may be used. That is, when a specific first element 11 is defective among the plurality of first elements 11, a repair element is mounted as the second element 12 instead of the first element 11 having the defect. That is, the removal of the first element 11 and the repair process can be performed, the number of manufacturing processes of the array substrate 50 including the repair process can be reduced, and the manufacture of the array substrate 50 can be realized with a high yield.
  • the repair element is configured so that the size of the repair element (the length of one side of the main body) is different from that of the first element 11, for example.
  • FIG. 4 is a diagram showing a device using the array substrate 50. As shown in FIG. In this device 100, the flexible wiring board 13 is connected to two sides of the array substrate 50. The number of elements 15 shown in this figure is different from the number of elements 15 on the array substrate 50 shown in FIG. In FIGS. 1 to 4, the number of elements is illustrated to be easy to understand, but the actual number of elements may be several thousand to several tens of thousands or even larger.
  • Examples of devices using the array substrate 50 include the following devices in addition to the light emitting and receiving devices as in the present embodiment.
  • a mirror array device For example, a MEMS (Micro Electro Mechanical Systems) device, another sensor array device, or a device composed of a combination of at least two of them.
  • MEMS Micro Electro Mechanical Systems
  • a device composed of a combination of at least two of them By using this manufacturing method, it is possible to significantly reduce the number of steps of a device on which a large number of types of elements such as sensor array devices are mounted, and it becomes easy to manufacture a device having specific characteristics.
  • FIG. 5 is a diagram for showing the sizes of the first element 11 and the second element 12.
  • the first element 11 includes a main body 11a and bumps 11b (plural) provided on the main body 11a.
  • the second element 12 includes a main body 12a and bumps 12b (plural).
  • the main bodies 11a and 12a have a rectangular shape.
  • the length of one side of the main body 12 a of the second element 12 is shorter than that of the first element 11. In this case, the length of one side is set to the extent that there is no adverse effect on the function of the second element 12.
  • the size of one side of the main body 11a, 12a of the element 15 is not less than 50 ⁇ m and not more than 2000 ⁇ m, and a narrower range is not less than 90 ⁇ m and not more than 400 ⁇ m.
  • the length of one side of the main body 11a of the first element 11 is 60 ⁇ m or more and 2000 ⁇ m or less, 70 ⁇ m or more and 1500 ⁇ m or less as a narrower range, and 80 ⁇ m or more and 1000 ⁇ m or less as a narrower range.
  • the length of one side of the main body 12a of the second element 12 is 50 ⁇ m or more and 1990 ⁇ m or less, a narrower range is 50 ⁇ m or more and 1490 ⁇ m or less, and a narrower range is 60 ⁇ m or more and 600 ⁇ m or less.
  • each bump 12b of the second element 12 is formed on the land (the plurality of lands 16 in one removal region 14 and the residual solder 11c thereon) on the removal region 14 (see FIG. 2D) of the mounting substrate 10.
  • the second elements 12 can be mounted on the mounting substrate 10 so as to be connected to each other.
  • the number of bumps that one element 15 has is several to several tens, depending on the element size.
  • the diameters of the bumps 11a and 12b are 15 ⁇ m or more and 40 ⁇ m or less, and more narrowly 20 ⁇ m or more and 30 ⁇ m or less.
  • 6A to 6C are sectional views showing the manufacturing process of the array substrate 50 shown in FIGS. 2C to 2E.
  • the bumps 11b of the first element 11 are bonded to the lands 16 of the mounting board 10, whereby the first element 11 is mounted on the mounting board 10.
  • the bump 12b of the second element 12 is bonded to the land 16, but may be mounted in a shifted manner.
  • the length of one side of the main body 12a is short, so that the second element 12 does not contact the adjacent first element 11. Yes (easy to implement)
  • the elements 15 are arranged at a high density, the merit is great.
  • FIG. 8 is a diagram for explaining the shift amount of the second element 12, and is an enlarged view of a portion surrounded by a one-dot chain line in FIG. 6C. Since the first element 11 was originally mounted in the removal region 14, the distance between the adjacent first elements 11 (distance a in FIG. 6B) in this removal region 14 is one side of the main body 11 a of the first element 11. It is set slightly larger than the length. Since the second element 12 is smaller than the first element 11, if the second element is mounted at an exact position, the second element 12 can be accommodated in the removal region 14. Needless to say.
  • the distance d between the adjacent main bodies 11a is, for example, 10 ⁇ m or more and 30 ⁇ m or less, and more narrowly 10 ⁇ m or more and 20 ⁇ m or less, 15 ⁇ m or more and 25 ⁇ m or less, or 15 ⁇ m or more and 20 ⁇ m or less.
  • the difference between the length of one side of the main body 12a of the second element 12 and that of the first element 11 may be set to be twice or more the sum b of the radius of the land 16 (residual solder 11c) and the radius of the bump 12b. desirable.
  • the radii of the land 16 and the bump 12b are substantially the same. According to such conditions, even if the second element 12 is arranged with a deviation from the intended position in a state where the land 16 and the bump 12b are joined (electrical connection is possible), the main bodies 11a and 12a There is no contact between them.
  • “double” means that the second element 12 may be shifted to the left or right in FIG. 8 with respect to the position of the land 16.
  • the second element 12 is mounted so that the maximum deviation from the intended position occurs in a state where the land 16 and the bump 12b are bonded, the second element 12 and the adjacent element Contact with the first element 11 can be prevented.
  • the size of the second element 12 is smaller than that of the first element 11, but the size of the first element may be smaller than the size of the second element.
  • FIGS. 9A to 9D are diagrams respectively showing various forms of the arrangement of bumps (bump groups) of the element 15.
  • the uppermost drawing shows the arrangement form of the bumps (first bump group 110) of the first element 11 respectively.
  • the second drawing from the top shows the arrangement of the bumps (second bump group 120) of the second element 12, respectively.
  • the first element 11 is removed, and a part of the solder of the first bump group 110 remains in the removal region 14 (see FIG. 6B), and the second element 12 is mounted on the mounting board.
  • FIG. The lowermost figure shows a cross section taken along the broken line in the third stage.
  • FIG. 9D shows a form in which the size of the first element 11 is smaller than the size of the second element 12.
  • FIG. 9A shows a form in which the arrangement of the first bump group 110 is completely the same as the arrangement of the second bump group 120.
  • the second element 12 is mounted on the removal region 14 of the mounting substrate 10
  • the residual solder 11 c (see FIG. 6B) of the first bump group 110 remaining in the removal region 14 and the bump 12 b of the second element 12. And everything is joined.
  • An electrode in a state where the residual solder 11c and the bump 12b are fused is denoted by reference numeral 17 in FIGS. 9A and 9B.
  • FIG. 9B shows a form in which the arrangement of the second bump group 120 matches a part of the arrangement of the first bump group 110, and the arrangement of the first bump group 110 includes the arrangement of the second bump group 120. In this case, all of the second bump group 120 is bonded to a part of the residual solder 11c of the first bump group 110 remaining in the removal region 14.
  • FIG. 9C shows a form in which the arrangement of the first bump group 110 and the arrangement of the second bump group 120 do not all match, that is, all differ. Also in this case, all of the second bump group 120 is not bonded to the residual solder 11c of the first bump group 110, but is bonded to a land (not shown here) of the mounting substrate 10.
  • FIG. 9D is a diagram having the same purpose as FIG. 9C.
  • FIG. 10 shows a form in which the arrangement of the second bump group 120 is not included in the arrangement of the first bump group 110. That is, a part of the second bump group 120 overlaps with a part of the first bump group 110, but the other part does not overlap. In such a bump arrangement, mounting of the second element 12 results in an error. In this case, the non-overlapping bumps 12b of the second bump group 120 may not be joined to lands (not shown here) on the mounting substrate 10. This is because the overlapping second bump group 120 is joined to the residual solder at a position higher by the height of the residual solder of the first bump group 110.
  • the arrangement of the first bump group 110 completely matches the arrangement of the second bump group 120, or the arrangement of the first bump group 110 includes the arrangement of the second bump group 120. Occurrence of a connection failure when the element 12 is mounted can be prevented.
  • FIG. 11 is a cross-sectional view showing the mounting substrate 10 having the residual solder 11c. As described above, after removing the first element 11, a part of the solder of the bump 11 b remains on the land 16 on the mounting substrate 10.
  • 12A and 12B are cross-sectional views showing the first element 11 and the second element 12, respectively.
  • the bumps 12b of the second bump group 120 are designed so that the height (which may be a diameter or volume) is lower than the height of the bumps 11b of the first bump group 110.
  • 12A and 12B the diameter of the bump 11b of the first element 11 is X
  • the diameter of the bump 12b of the second element 12 is X- ⁇ .
  • the volume of the bump 12b is designed so that the sum of the volume of the residual solder 11c and the volume of the bump 12b of the second element 12 is substantially equal to the volume of the bump 11b of the first element 11. Specifically, in the manufacturing process of the second element 12, the diameter of the solder material forming the bump 12b is controlled using a mask (in this case, the height (thickness) is constant). The volume of the bump 12b can be controlled.
  • FIG. 13A and 13B show a mounting process (for example, a reflow process) when the height of the bump 11b of the first element 11 is the same as that of the second element 12.
  • FIG. 13B a difference occurs between the height of the main body 12a of the second element 12 after mounting (including the residual solder 11c) and the height of the main body 11a of the other first element 11.
  • the height of the bump 12b of the second element 12 when the height of the bump 12b of the second element 12 is set in advance lower than that of the first element 11, it becomes as shown in FIG. 14B. That is, the height of the bump 12b (including the residual solder 11c) after mounting the second element 12 is the same as the height of the bump 11b of the other first element 11. Thereby, the height of the main body 12a of the mounted second element 12 can be made the same as the height of the main body 11a of the first element 11. As a result, for example, the height of the entire surface of the elements 15 can be made uniform.
  • the design of the bumps 11b and 12b as shown in FIGS. 13A and 13B may be used.
  • the bumps 11b and 12b may be designed so as to make the second element 12 lower than the height of the main body 11a of the first element 11 in consideration of the amount of the residual solder 11c.
  • the height of the element 15 can be adjusted, and the process of removing the residual solder 11c can be omitted.
  • FIG. 15 shows a form in which the amount of the residual solder 11c on the land 16 is different in one removal region.
  • the second element 12 is mounted in an inclined state.
  • a second element 12 having a bump 12b having at least two different heights (which may be a diameter or a volume) is used.
  • the diameter of one bump 12b is X- ⁇
  • the diameter of the other bump 12b is X- ⁇ .
  • ⁇ ⁇ is joined to the residual solder 11c having a small residual amount
  • the bump 12b having the smaller diameter X- ⁇ is joined to the residual solder 11c having a large residual amount.
  • the second element 12 having at least two bumps 12b having different heights is mounted.
  • the main body 12 a is disposed so as to be inclined with respect to the mounting substrate 10.
  • the inclination angle of the main body 12a of the second element 12 after mounting can be controlled by controlling the diameter of the bump 12b of the second element 12 at the time of design. That is, the second element 12 that is inclined at an arbitrary angle with respect to the mounting substrate 10 can be realized by controlling only the diameter of the bump 12b.
  • first element 11 and the second element 12 have been described, but the same applies to three or more types of elements. That is, in addition to the second elements smaller than the number of the first elements 11, third elements smaller than the number of the first elements 11 may be mounted in the removed region where the first elements are removed.
  • this technique can also take the following structures.
  • a mounting board An array substrate comprising: two or more first elements; and a plurality of elements mounted to be arranged in an array structure on the mounting substrate, including one or more second elements different from the first elements .
  • Each of the plurality of elements has a main body and one or more bumps provided on the main body.
  • the array substrate according to (2) above, The length of one side of the main body of the second element is shorter than that of the first element.
  • the array substrate according to (2) or (3) The mounting substrate has lands to which bumps of the plurality of elements are connected, The difference between the length of one side of the main body of the second element and that of the first element is at least twice the sum of the radius of the land and the radius of the bump of the second element.
  • the array substrate according to any one of (2) to (4) The length of one side of the main body of the first element is 60 ⁇ m or more and 2000 ⁇ m or less, The length of one side of the main body of the second element is 50 ⁇ m or more and 1990 ⁇ m or less.
  • the array substrate according to any one of (2) to (8), The height of the bump of the second element is lower than the height of the bump of the first element.
  • the array substrate according to any one of (2) to (8), The bump of the second element has at least two different heights.
  • the second element mounted on a mounting substrate of an array substrate comprising a plurality of elements including two or more first elements and one or more second elements, The plurality of elements are arranged in an array structure on the mounting substrate, A main body configured such that the length of one side is shorter than the length of one side of the main body of the first element; A mounting element comprising one or more bumps provided on the main body.
  • the mounting element according to (11), The bump of the second element has at least two different heights.
  • a mounting board comprising: two or more first elements; and a plurality of elements mounted on the mounting substrate so as to be arranged in an array structure, including at least one second element different from the first element.
  • Device provided.
  • a plurality of first elements arranged in an array structure are transferred and mounted on a mounting substrate, Removing one or more first elements of the plurality of first elements from the mounting substrate;
  • the method of manufacturing an array substrate according to (14) Each of the plurality of elements has a main body and one or more bumps provided on the main body.
  • the mounting substrate has a land to which bumps of the plurality of elements are connected.
  • the method for manufacturing an array substrate according to (15) The height of the bump of the second element before mounting the second element is set so that the height of the main body of the first element from the mounting substrate is the same as that of the second element.
  • An array substrate manufacturing method configured to be lower than the bump height of the element.
  • the method for manufacturing an array substrate according to (15) When the lands remaining in one removal region have at least two different heights, the mounting substrate and the main body of the second element after mounting the second element are parallel to each other.
  • the method of manufacturing an array substrate, wherein the bumps of the second element before the two elements are mounted have at least two different heights.

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Abstract

Un mode de réalisation de l'invention concerne un substrat de réseau comprenant un substrat de montage ainsi qu'une pluralité d'éléments. La pluralité d'éléments comprend au moins deux premiers éléments ainsi qu'un ou plusieurs seconds éléments, différents du premier élément, qui sont montés sur le substrat de montage de façon à être agencés dans une structure de réseau.
PCT/JP2018/000747 2017-02-17 2018-01-15 Substrat de réseau, élément monté, dispositif comprenant un substrat de réseau et procédé de production d'un substrat de réseau Ceased WO2018150776A1 (fr)

Priority Applications (1)

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CN201880010798.4A CN110268459A (zh) 2017-02-17 2018-01-15 阵列基板、安装元件、包括阵列基板的装置以及制造阵列基板的方法

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JP2017027631A JP2018132715A (ja) 2017-02-17 2017-02-17 アレイ基板、実装素子、アレイ基板を備えたデバイス、アレイ基板の製造方法
JP2017-027631 2017-02-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023508014A (ja) * 2019-12-17 2023-02-28 ソウル バイオシス カンパニー リミテッド 発光素子の復元方法および復元された発光素子を含むディスプレイパネル

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12318870B2 (en) * 2022-12-22 2025-06-03 Samsung Electronics Co., Ltd. Ball attachment apparatus

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH09162545A (ja) * 1995-12-11 1997-06-20 Nec Corp ボールグリッドアレイ実装構造及び実装方法
JP2005123381A (ja) * 2003-10-16 2005-05-12 Seiko Epson Corp 素子チップの実装方法、実装基板、電気光学装置及び電子機器
WO2005067062A1 (fr) * 2003-12-26 2005-07-21 Nec Corporation Substrat a entree de lumiere, substrat a sortie de lumiere, substrat a entree/sortie de lumiere, et circuit integre a semi-conducteurs equipe d'un element optique
WO2005067061A1 (fr) * 2003-12-26 2005-07-21 Nec Corporation Circuit integre a semi-conducteurs equipe d'un element optique
US20060148281A1 (en) * 2004-12-30 2006-07-06 Horine Bryce D Connection of package, board, and flex cable

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162545A (ja) * 1995-12-11 1997-06-20 Nec Corp ボールグリッドアレイ実装構造及び実装方法
JP2005123381A (ja) * 2003-10-16 2005-05-12 Seiko Epson Corp 素子チップの実装方法、実装基板、電気光学装置及び電子機器
WO2005067062A1 (fr) * 2003-12-26 2005-07-21 Nec Corporation Substrat a entree de lumiere, substrat a sortie de lumiere, substrat a entree/sortie de lumiere, et circuit integre a semi-conducteurs equipe d'un element optique
WO2005067061A1 (fr) * 2003-12-26 2005-07-21 Nec Corporation Circuit integre a semi-conducteurs equipe d'un element optique
US20060148281A1 (en) * 2004-12-30 2006-07-06 Horine Bryce D Connection of package, board, and flex cable

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023508014A (ja) * 2019-12-17 2023-02-28 ソウル バイオシス カンパニー リミテッド 発光素子の復元方法および復元された発光素子を含むディスプレイパネル
JP7670719B2 (ja) 2019-12-17 2025-04-30 ソウル バイオシス カンパニー リミテッド 発光素子の復元方法および復元された発光素子を含むディスプレイパネル

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CN110268459A (zh) 2019-09-20

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