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WO2018142707A1 - Système d'imagerie et dispositif d'imagerie - Google Patents

Système d'imagerie et dispositif d'imagerie Download PDF

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Publication number
WO2018142707A1
WO2018142707A1 PCT/JP2017/040155 JP2017040155W WO2018142707A1 WO 2018142707 A1 WO2018142707 A1 WO 2018142707A1 JP 2017040155 W JP2017040155 W JP 2017040155W WO 2018142707 A1 WO2018142707 A1 WO 2018142707A1
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WIPO (PCT)
Prior art keywords
pixel
period
pixels
test
imaging device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2017/040155
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English (en)
Japanese (ja)
Inventor
直樹 河津
敦史 鈴木
純一郎 薊
裕一 本橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2017206335A external-priority patent/JP6953274B2/ja
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to DE112017006977.7T priority Critical patent/DE112017006977T5/de
Priority to CN201780084589.XA priority patent/CN110226325B/zh
Priority to US16/471,406 priority patent/US10819928B2/en
Publication of WO2018142707A1 publication Critical patent/WO2018142707A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/002—Diagnosis, testing or measuring for television systems or their details for television cameras
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/68—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/74—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R2300/00—Details of viewing arrangements using cameras and displays, specially adapted for use in a vehicle
    • B60R2300/30—Details of viewing arrangements using cameras and displays, specially adapted for use in a vehicle characterised by the type of image processing

Definitions

  • the present disclosure relates to an imaging system and an imaging apparatus.
  • amplification-type solid-state imaging devices represented by MOS type image sensors such as CMOS (Complementary Metal Oxide Semiconductor) are known.
  • MOS type image sensors such as CMOS (Complementary Metal Oxide Semiconductor)
  • CCD Charge Coupled Device
  • CCD Charge Coupled Device
  • a unit pixel is formed by a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors, and a pixel array (pixel region) in which the plurality of unit pixels are arranged in a two-dimensional array, And having a peripheral circuit region.
  • the plurality of pixel transistors are formed of MOS transistors, and include transfer transistors, reset transistors, three transistors of amplification and transistors, or four transistors including a selection transistor.
  • Patent Document 1 discloses an example of a mechanism for detecting a failure of a solid-state imaging device using a failure detection circuit.
  • Patent Document 1 since various tests are performed using a failure detection circuit when the image detection chip is powered on or a signal is received from an external inspection device, for example, a failure that occurs during imaging is detected at run-time. Difficult to do.
  • the present disclosure proposes an imaging system and an imaging apparatus capable of more efficiently executing various tests for detecting an abnormality.
  • an imaging device that is mounted on a vehicle and images a peripheral region of the vehicle to generate an image
  • a processing device that is mounted on the vehicle and executes processing related to a function of controlling the vehicle
  • the imaging apparatus includes a plurality of pixels, a control unit that controls exposure by each of the plurality of pixels, and a processing unit that executes a predetermined test, and the control unit includes the plurality of pixels. Reading of the pixel signal is started in the second period in which one or more exposures are executed after the reading of the pixel signal is completed in the first period in which one or more exposures are performed on at least some of the pixels.
  • Exposure is controlled so that the processing unit performs the predetermined test in a third period between the readout of the pixel signal in the first period and the readout of the pixel signal in the second period.
  • Run The processor, based on the predetermined test result, limits the function of controlling the vehicle, the imaging system is provided.
  • the present disclosure further includes a plurality of pixels, a control unit that controls exposure by each of the plurality of pixels, and a processing unit that executes a predetermined test, and the control unit includes the plurality of pixels.
  • the control unit After reading of the pixel signal is completed in the first period in which at least one exposure is performed on at least some of the pixels, reading out of the pixel signal is started in the second period in which at least one exposure is performed. Exposure is controlled so that the processing unit performs the predetermined test in a third period between the readout of the pixel signal in the first period and the readout of the pixel signal in the second period.
  • An imaging device is provided for execution.
  • a plurality of pixels, a control unit that controls exposure by each of the plurality of pixels, and at least one exposure by at least some of the plurality of pixels are executed.
  • An imaging apparatus includes a processing unit that executes a predetermined test in a third period until the first time.
  • an imaging system and an imaging apparatus capable of more efficiently executing various tests for detecting an abnormality.
  • FIG. 6 is a block diagram illustrating another example of a functional configuration of a solid-state imaging device according to an embodiment of the present disclosure. It is a figure showing other examples of composition of a solid imaging device concerning one embodiment of this indication. It is a figure showing an example of circuit composition of a unit pixel concerning one embodiment of this indication.
  • 5 is a schematic timing chart illustrating an example of drive control of a solid-state imaging device according to an embodiment of the present disclosure.
  • 5 is a schematic timing chart illustrating an example of drive control of a solid-state imaging device according to an embodiment of the present disclosure.
  • 1 is a block diagram illustrating an example of a schematic configuration of a solid-state imaging device according to a first embodiment of the present disclosure. It is the block diagram which showed an example of the schematic structure of the solid-state imaging device concerning the embodiment.
  • 3 is a schematic timing chart showing an example of drive control of the solid-state imaging device according to the embodiment. It is explanatory drawing for demonstrating an example of the drive control of the solid-state imaging device concerning the embodiment.
  • FIG. 6 is an explanatory diagram for describing an example of an operation related to pixel signal correction in the solid-state imaging device according to the embodiment. It is the figure which showed an example of the circuit structure of the unit pixel in the solid-state imaging device which concerns on the modification of the embodiment. 6 is a schematic timing chart illustrating an example of drive control of a solid-state imaging device according to a modification of the embodiment. It is explanatory drawing for demonstrating an example of the drive control of the solid-state imaging device which concerns on the modification of the embodiment.
  • FIG. 6 is an explanatory diagram for describing an example of an operation related to pixel signal correction in the solid-state imaging device according to the embodiment.
  • FIG. 6 is an explanatory diagram for describing an example of an operation related to pixel signal correction in the solid-state imaging device according to the embodiment.
  • 3 is a schematic timing chart showing an example of drive control of the solid-state imaging device according to the embodiment.
  • FIG. 6 is an explanatory diagram for describing an example of schematic control related to readout of a pixel signal from each pixel in the solid-state imaging device according to the embodiment.
  • FIG. 6 is an explanatory diagram for describing an example of schematic control related to readout of a pixel signal from each pixel in the solid-state imaging device according to the embodiment.
  • 6 is a timing chart for explaining a relationship between an exposure time constraint and a vertical blank period in the solid-state imaging device according to the embodiment. It is explanatory drawing for demonstrating the structure of the hardware of a front camera ECU and an image pick-up element. It is explanatory drawing for demonstrating the structure of the hardware of a front camera ECU and an image pick-up element.
  • FIG. 1 illustrates a schematic configuration of a CMOS solid-state imaging device as an example of a configuration of a solid-state imaging device according to an embodiment of the present disclosure. This CMOS solid-state imaging device is applied to the solid-state imaging device of each embodiment.
  • the solid-state imaging device 1 of the present example includes a pixel array unit 3, an address recorder 4, a pixel timing driving circuit 5, a column signal processing circuit 6, a sensor controller 7, and an analog potential generation circuit 8.
  • each pixel 2 is connected to the pixel timing drive circuit 5 via a horizontal signal line and also via a vertical signal line VSL. It is connected to the column signal processing circuit 6.
  • the plurality of pixels 2 each output a pixel signal corresponding to the amount of light irradiated through an optical system (not shown), and an image of the subject imaged on the pixel array unit 3 is constructed from these pixel signals. .
  • the pixel 2 includes, for example, a photodiode serving as a photoelectric conversion unit and a plurality of pixel transistors (so-called MOS transistors).
  • the plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplification transistor.
  • a selection transistor may be added to configure the transistor with four transistors.
  • An example of an equivalent circuit of the unit pixel will be described later separately.
  • the pixel 2 can be configured as one unit pixel. Further, the pixel 2 may have a shared pixel structure. This shared pixel structure includes a plurality of photodiodes, a plurality of transfer transistors, a shared floating diffusion, and a shared other pixel transistor. That is, in the shared pixel, a photodiode and a transfer transistor that constitute a plurality of unit pixels are configured by sharing each other pixel transistor.
  • a dummy pixel 2a that does not contribute to display may be arranged in a part of the pixel array unit 3 (for example, a non-display area).
  • the dummy pixel 2 a is used for acquiring various information related to the solid-state imaging device 1. For example, a voltage corresponding to white luminance is applied to the dummy pixel 2a during a period in which the pixel 2 contributing to display is driven. At this time, for example, the current flowing in the dummy pixel 2a is converted into a voltage, and the voltage obtained by this conversion is measured, so that the deterioration of the pixel 2 contributing to display can be predicted. That is, the dummy pixel 2 a can correspond to a sensor that can detect the electrical characteristics of the solid-state imaging device 1.
  • the address recorder 4 controls the vertical access of the pixel array unit 3, and the pixel timing drive circuit 5 drives the pixel 2 according to the logical sum of the control signal from the address recorder 4 and the pixel drive pulse.
  • the column signal processing circuit 6 performs AD conversion of the pixel signal by performing CDS (Correlated Double Sampling) processing on the pixel signal output from the plurality of pixels 2 through the vertical signal line VSL. And reset noise.
  • the column signal processing circuit 6 includes a plurality of AD converters corresponding to the number of columns of the pixels 2, and can perform CDS processing in parallel for each column of the pixels 2.
  • the column signal processing circuit 6 includes a constant current circuit forming a load MOS portion of the source follower circuit, and a single slope type DA converter for analog-digital conversion of the potential of the vertical signal line VSL.
  • the sensor controller 7 controls the overall driving of the solid-state imaging device 1. For example, the sensor controller 7 generates a clock signal according to the driving cycle of each block constituting the solid-state imaging device 1 and supplies the clock signal to each block.
  • the analog potential generation circuit 8 generates an analog potential for driving the dummy pixels 2a in a desired manner in order to acquire various information related to the solid-state imaging device 1. For example, when the pixel timing drive circuit 5 drives the dummy pixel 2a based on the analog potential generated by the analog potential generation circuit 8, various information regarding the solid-state imaging device 1 is obtained based on the output signal from the dummy pixel 2a. To be acquired.
  • the solid-state imaging device 330 illustrated in the upper part of FIG. 2 includes a pixel region 332, a control circuit 333, and a logic circuit 334 including the above-described signal processing circuit in one semiconductor chip 331. Is done.
  • the solid-state imaging device 340 shown in the middle of FIG. 2 includes a first semiconductor chip unit 341 and a second semiconductor chip unit 342.
  • a pixel region 343 and a control circuit 344 are mounted on the first semiconductor chip portion 341, and a logic circuit 345 including the signal processing circuit described above is mounted on the second semiconductor chip portion 342.
  • the first semiconductor chip unit 341 and the second semiconductor chip unit 342 are electrically connected to each other, so that a solid-state imaging device 340 as one semiconductor chip is configured.
  • the solid-state imaging device 350 shown in the lower part of FIG. 2 includes a first semiconductor chip part 351 and a second semiconductor chip part 352.
  • a pixel region 353 is mounted on the first semiconductor chip portion 351, and a control circuit 354 and a logic circuit 355 including the signal processing circuit described above are mounted on the second semiconductor chip portion 352.
  • the first semiconductor chip unit 351 and the second semiconductor chip unit 352 are electrically connected to each other, so that a solid-state imaging device 350 as one semiconductor chip is configured.
  • FIG. 3 is a block diagram illustrating an example of a partial functional configuration of the solid-state imaging device according to an embodiment of the present disclosure.
  • the solid-state imaging device 1 shown in FIG. 3 is an imaging element that captures a subject and obtains digital data of the captured image, such as a complementary metal oxide semiconductor (CMOS) image sensor or a charge coupled device (CCD) image sensor. .
  • CMOS complementary metal oxide semiconductor
  • CCD charge coupled device
  • the solid-state imaging device 1 includes a control unit 101, a pixel array unit 111, a selection unit 112, an A / D conversion unit (ADC (Analog Digital Converter)) 113, and a constant current circuit unit 114. .
  • ADC Analog Digital Converter
  • the control unit 101 controls each unit of the solid-state imaging device 1 to execute processing related to reading of image data (pixel signal).
  • the pixel array unit 111 is a pixel region in which pixel configurations having photoelectric conversion elements such as photodiodes are arranged in a matrix (array).
  • the pixel array unit 111 is controlled by the control unit 101 to receive the light of the subject at each pixel, photoelectrically convert the incident light to accumulate charges, and store the charges accumulated in each pixel at a predetermined timing. Output as a pixel signal.
  • the pixel 121 and the pixel 122 indicate two pixels that are adjacent in the vertical direction in the pixel group arranged in the pixel array unit 111.
  • the pixel 121 and the pixel 122 are pixels in consecutive rows in the same column.
  • a photoelectric conversion element and four transistors are used in the circuit of each pixel. Note that the circuit configuration of each pixel is arbitrary and may be other than the example shown in FIG.
  • output lines for pixel signals are provided for each column.
  • two (two systems) output lines are provided for each column.
  • the circuit of the pixel in one column is alternately connected to these two output lines every other row.
  • the circuit of the pixel 121 is connected to the first output line (VSL1)
  • the circuit of the pixel 122 is connected to the second output line (VSL2).
  • FIG. 3 for convenience of explanation, only an output line for one column is shown, but actually, two output lines are provided for each column in the same manner. Each output line is connected to every other row of pixel circuits in that column.
  • the selection unit 112 includes a switch that connects each output line of the pixel array unit 111 to the input of the ADC 113, and is controlled by the control unit 101 to control connection between the pixel array unit 111 and the ADC 113. That is, the pixel signal read from the pixel array unit 111 is supplied to the ADC 113 via the selection unit 112.
  • the selection unit 112 includes a switch 131, a switch 132, and a switch 133.
  • the switch 131 (selection SW) controls connection of two output lines corresponding to the same column. For example, the first output line (VSL1) and the second output line (VSL2) are connected when the switch 131 is turned on (ON), and disconnected when the switch 131 is turned off (OFF).
  • one ADC is provided for each output line (column ADC). Therefore, if both the switch 132 and the switch 133 are in the on state, when the switch 131 is in the on state, the two output lines of the same column are connected, so that the circuit of one pixel is connected to the two ADCs. Will be. Conversely, when the switch 131 is turned off, the two output lines in the same column are disconnected, and the circuit of one pixel is connected to one ADC. That is, the switch 131 selects the number of ADCs (column ADCs) that are output destinations of signals of one pixel.
  • the switch 131 controls the number of ADCs to which pixel signals are output, so that the solid-state imaging device 1 can output more various pixel signals according to the number of ADCs. That is, the solid-state imaging device 1 can realize more various data outputs.
  • the switch 132 controls the connection between the first output line (VSL1) corresponding to the pixel 121 and the ADC corresponding to the output line.
  • VSL1 first output line
  • ADC ADC corresponding to the output line.
  • the switch 133 controls the connection between the second output line (VSL2) corresponding to the pixel 122 and the ADC corresponding to the output line.
  • VSL2 the second output line
  • ADC the ADC corresponding to the output line.
  • the selection unit 112 can control the number of ADCs (column ADCs) that are output destinations of signals of one pixel by switching the states of the switches 131 to 133 according to the control of the control unit 101. .
  • each output line may be always connected to the ADC corresponding to the output line.
  • the selection of the number of ADCs (column ADCs) that are the output destinations of signals of one pixel is expanded by enabling these switches to control connection / disconnection of these pixels. That is, by providing these switches, the solid-state imaging device 1 can output more various pixel signals.
  • the selection unit 112 has the same configuration as that shown in FIG. 133). That is, the selection unit 112 performs connection control similar to that described above for each column according to the control of the control unit 101.
  • the ADC 113 A / D converts each pixel signal supplied from the pixel array unit 111 via each output line, and outputs it as digital data.
  • the ADC 113 includes an ADC (column ADC) for each output line from the pixel array unit 111. That is, the ADC 113 has a plurality of column ADCs.
  • a column ADC corresponding to one output line is a single slope type ADC having a comparator, a D / A converter (DAC), and a counter.
  • the comparator compares the signal value (potential) of the pixel signal supplied via the vertical signal line VSL with the potential of the ramp wave supplied from the DAC and inverts the signal at the timing when these potentials intersect. Output a pulse.
  • the counter counts an AD period corresponding to the timing at which the potential of the pixel signal and the potential of the ramp wave intersect in order to convert the analog value into a digital value.
  • the counter increments the count value (digital value) until the signal value of the pixel signal is equal to the ramp wave potential supplied from the DAC.
  • the comparator stops the counter when the DAC output reaches the signal value. Thereafter, the signals digitized by the counters 1 and 2 are output to the outside of the solid-state imaging device 1 from DATA1 and DATA2.
  • the counter returns the count value to the initial value (for example, 0) after outputting the data for the next A / D conversion.
  • the ADC 113 has two column ADCs for each column. For example, a comparator 141 (COMP1), a DAC 142 (DAC1), and a counter 143 (counter 1) are provided for the first output line (VSL1), and a comparison is made for the second output line (VSL2). A device 151 (COMP2), a DAC 152 (DAC2), and a counter 153 (counter 2) are provided. Although not shown, the ADC 113 has the same configuration for output lines of other columns.
  • the DAC can be shared among these configurations. DAC sharing is performed for each system. That is, DACs of the same system in each column are shared. In the example of FIG. 3, the DAC corresponding to the first output line (VSL1) of each column is shared as the DAC 142, and the DAC corresponding to the second output line (VSL2) of each column is shared as the DAC 152. ing. Note that a comparator and a counter are provided for each output line system.
  • the constant current circuit unit 114 is a constant current circuit connected to each output line, and is driven by being controlled by the control unit 101.
  • the circuit of the constant current circuit unit 114 includes, for example, a MOS (Metal Oxide Semiconductor) transistor or the like.
  • MOS Metal Oxide Semiconductor
  • FIG. 3 for convenience of explanation, a MOS transistor 161 (LOAD1) is provided for the first output line (VSL1), and for the second output line (VSL2).
  • LOAD2 MOS transistor 162
  • the control unit 101 receives a request from the outside such as a user, selects a read mode, controls the selection unit 112, and controls connection to the output line. Further, the control unit 101 controls driving of the column ADC according to the selected read mode. Further, in addition to the column ADC, the control unit 101 controls driving of the constant current circuit unit 114 as necessary, and controls driving of the pixel array unit 111 such as a reading rate and timing. .
  • control unit 101 can operate not only the selection unit 112 but also each unit other than the selection unit 112 in more various modes. Therefore, the solid-state imaging device 1 can output more various pixel signals.
  • the pixels 121 and 122 shown in FIG. 3 correspond to the pixel 2 in FIG.
  • the selection unit 112, the ADC 113, and the constant current circuit unit 114 correspond to the column signal processing circuit 6 described with reference to FIG.
  • the control unit 101 shown in FIG. 3 corresponds to the sensor controller 7 described with reference to FIG.
  • each part shown in FIG. 3 is arbitrary as long as there is no shortage.
  • three or more output lines may be provided for each column.
  • the number of pixel signals output in parallel may be increased by increasing the number of parallel pixel signals output from the switch 132 and the number of switches 132 themselves shown in FIG.
  • FIG. 4 is a block diagram illustrating another example of the functional configuration of the solid-state imaging device according to an embodiment of the present disclosure.
  • reference numerals 6a and 6b respectively indicate configurations corresponding to the column signal processing circuit 6 described with reference to FIG. That is, in the example shown in FIG. 4, a plurality of systems corresponding to the column signal processing circuit 6 (for example, the comparators 141 and 151, the counters 143 and 153, and the constant current circuit unit 114) are provided. Further, as shown in FIG. 4, the DACs 142 and 152 may be shared between the column signal processing circuits 6a and 6b.
  • FIG. 5 is a diagram illustrating another example of the configuration of the solid-state imaging device according to an embodiment of the present disclosure.
  • a pixel array unit 111 in which a plurality of pixels 2 are arranged is provided on an upper semiconductor chip and an ADC 113 is provided on a lower chip is shown.
  • the pixel array unit 111 is divided into a plurality of areas 1111 each including a plurality of pixels 2, and an ADC 1131 is provided for each area 1111.
  • the pixel array unit 111 is divided into a plurality of areas 1111 using 10 pixels ⁇ 16 pixels as a unit of the area 1111.
  • each pixel 2 included in the area 1111 and the ADC 1131 provided corresponding to the area 1111 are electrically connected by stacking semiconductor chips.
  • a direct connection between a wiring connected to each pixel 2 included in the area 1111 and a wiring connected to the ADC 1131 provided corresponding to the area is based on a so-called Cu—Cu bonding. They may be connected by a so-called TSV (Through-Silicon Via).
  • the ADC 1131 for each area 1111 As described above, by providing the ADC 1131 for each area 1111, for example, compared to the case where the ADC 113 is provided for each column, the pixel signal from each pixel 2 is A / D converted and output as digital data. It becomes possible to increase the parallel number. Therefore, for example, it is possible to further reduce the time required for reading out the pixel signal from each pixel 2.
  • the ADC 1131 for each area 1111 can be individually driven independently. Therefore, for example, pixel signals can be read from each pixel 2 more flexibly, for example, pixel signals from pixels 2 included in some areas 1111 can be individually read at a desired timing. It becomes possible.
  • some configurations may be provided outside the solid-state imaging device 1.
  • the configuration that bears at least part of the function of the control unit 101 illustrated in FIG. 3 transmits a control signal to each component in the solid-state imaging device 1 from the outside of the solid-state imaging device 1. You may control the operation
  • the configuration corresponding to the control unit 101 corresponds to an example of a “control device”.
  • FIG. 6 is a diagram illustrating an example of a circuit configuration of a unit pixel according to an embodiment of the present disclosure.
  • the unit pixel 2 includes a photoelectric conversion element (for example, a photodiode) PD and four pixel transistors.
  • the four pixel transistors are, for example, a transfer transistor Tr11, a reset transistor Tr12, an amplification transistor Tr13, and a selection transistor Tr14.
  • These pixel transistors can be composed of, for example, n-channel MOS transistors.
  • the transfer transistor Tr11 is connected between the cathode of the photoelectric conversion element PD and the floating diffusion portion FD.
  • Signal charges here, electrons
  • TRG transfer pulse
  • the reset transistor Tr12 has a drain connected to the power supply VDD and a source connected to the floating diffusion portion FD. Prior to the transfer of signal charges from the photoelectric conversion element PD to the floating diffusion portion FD, the potential of the floating diffusion portion FD is reset by applying a reset pulse RST to the gate.
  • the amplification transistor Tr13 has a gate connected to the floating diffusion portion FD, a drain connected to the power supply VDD, and a source connected to the drain of the selection transistor Tr14.
  • the amplification transistor Tr13 outputs the potential of the floating diffusion portion FD after being reset by the reset transistor Tr12 to the selection transistor Tr14 as a reset level. Further, the amplification transistor Tr13 outputs the potential of the floating diffusion portion FD after the signal charge is transferred by the transfer transistor Tr11 as a signal level to the selection transistor Tr14.
  • the selection transistor Tr14 has a drain connected to the source of the amplification transistor Tr13 and a source connected to the vertical signal line VSL.
  • the selection pulse SEL is applied to the gate of the selection transistor Tr14, the selection transistor Tr14 is turned on, and the signal output from the amplification transistor Tr13 is output to the vertical signal line VSL.
  • the selection transistor Tr14 may be configured to be connected between the power supply VDD and the drain of the amplification transistor Tr13.
  • the solid-state imaging device 1 is configured as a stacked solid-state imaging device
  • elements such as photodiodes and a plurality of MOS transistors are included in the first semiconductor chip in the middle or lower stage of FIG. Formed in part 341.
  • the transfer pulse, the reset pulse, the selection pulse, and the power supply voltage are supplied from the second semiconductor chip unit 342 in the middle stage or the lower stage of FIG.
  • the elements subsequent to the vertical signal line VSL connected to the drain of the selection transistor are configured in the logic circuit 345, and the elements subsequent to the vertical signal line VSL connected to the drain of the selection transistor are configured in the second circuit. It is formed in the semiconductor chip part 342.
  • FIG. 7 is a schematic timing chart illustrating an example of drive control of the solid-state imaging device 1 according to an embodiment of the present disclosure, and illustrates an example of drive control of the pixel 2.
  • FIG. 7 shows a horizontal synchronization signal (XHS) indicating one horizontal synchronization period, a TRG drive pulse for driving the transfer transistor Tr11 (transfer pulse for reading and transfer pulse for electronic shutter), and an RST drive pulse for driving the reset transistor Tr12 ( An electronic shutter reset pulse and a readout reset pulse), and a SEL drive pulse (readout selection pulse) for driving the selection transistor Tr14 are shown.
  • XHS horizontal synchronization signal
  • the potential of the photoelectric conversion element PD is reset by turning on the electronic shutter transfer pulse and the electronic shutter reset pulse. Thereafter, charges are accumulated in the photoelectric conversion element PD during the accumulation time, and a read pulse is issued from the sensor controller 7.
  • the potential of the floating diffusion part FD is reset by turning on a reset pulse at the time of reading, and then the potential of the pre-data phase (P phase) is AD converted. Thereafter, the charge of the photoelectric conversion element PD is transferred to the floating diffusion portion FD by a transfer pulse at the time of reading, and the data phase (D phase) is AD converted.
  • the selection pulse at the time of reading is in an on state.
  • the above is merely an example, and at least a part of the drive timing may be changed according to the electronic shutter and the reading operation.
  • the transfer pulse at the electronic shutter and the reset pulse at the electronic shutter are changed.
  • the potential of the photoelectric conversion element PD may be reset by turning it on.
  • FIG. 8 is a schematic timing chart showing an example of drive control of the solid-state imaging device 1 according to an embodiment of the present disclosure, and shows an example of drive control of the ADC 113.
  • the driving of the ADC 113 will be described by focusing on the operations of the DAC 142, the comparator 141, and the counter 143 in the ADC 113 illustrated in FIG.
  • the horizontal synchronization signal (XHS) indicating one horizontal synchronization period
  • the potential of the ramp signal output from the DAC 142 (solid line)
  • the potential of the pixel signal output from the vertical signal line VSL (broken line)
  • the comparator 141 the comparator 141.
  • the inversion pulse output from the counter 143 and the operation image of the counter 143 are shown.
  • the DAC 142 has a first slope in which the potential sequentially drops at a constant gradient in the P phase for reading the reset level of the pixel signal, and is constant in the D phase for reading the data level of the pixel signal.
  • a ramp wave having a second slope in which the potential drops sequentially with a gradient is generated.
  • the comparator 141 compares the potential of the pixel signal with the potential of the ramp wave, and outputs an inversion pulse that is inverted at the timing when the potential of the pixel signal and the potential of the ramp wave intersect.
  • the counter 143 counts (P-phase count value) from the timing when the ramp wave starts to drop in the P phase to the timing when the potential of the ramp wave becomes equal to or lower than the potential of the pixel signal, and then the ramp wave in the D phase. Is counted from the timing when the voltage starts to fall to the timing when the potential of the ramp wave becomes equal to or lower than the potential of the pixel signal (D-phase count value). Thereby, the difference between the P-phase count value and the D-phase count value is acquired as a pixel signal from which reset noise has been removed. As described above, AD conversion of the pixel signal is performed using the ramp wave.
  • FIGS. 9 and 10 are block diagrams illustrating an example of a schematic configuration of the solid-state imaging device 1a according to the present embodiment.
  • the configuration of the solid-state imaging device 1a will be described by focusing on the difference from the solid-state imaging device 1 described with reference to FIGS. 1 to 8, and substantially the same as the solid-state imaging device 1. Detailed description of this part is omitted.
  • FIG. 9 shows an example of the power supply configuration of the solid-state imaging device 1 according to this embodiment.
  • the configuration of the portion where the pixel timing drive circuit 5 supplies the drive signal to the pixel 2 is mainly shown, and the other configurations are not shown.
  • a power source that supplies a power source voltage to the pixel 2 and a pixel timing driving circuit 5 that supplies a driving signal to the pixel 2 A power supply for supplying a power supply voltage to the pixel timing drive circuit 5 is provided individually. Therefore, hereinafter, the power supply that supplies the power supply voltage to the pixel 2 is also referred to as “power supply VDDHPX”, and the power supply voltage to the pixel timing drive circuit 5 (that is, the power supply for supplying the drive signal to the pixel 2).
  • the power supply for supplying the voltage is also referred to as “power supply VDDHVS”.
  • the power supplies VDDHPX and VDDHVS may be provided on different semiconductor chips.
  • the power supply VDDHPX may be provided in a semiconductor chip in which the pixels 2 are arranged (for example, the first semiconductor chip unit 341 shown in FIG. 2).
  • the power supply VDDHVS may be provided in a semiconductor chip (for example, the second semiconductor chip unit 342 shown in FIG. 2) provided with the pixel timing driving circuit 5.
  • the semiconductor chip on which the pixels 2 are arranged and the semiconductor chip on which the pixel timing driving circuit 5 is provided are connected via a connection part (for example, TSV (Through-Silicon Via)).
  • FIG. 10 shows an example of the configuration of a part related to reading of a pixel signal from the pixel 2 in the configuration of the solid-state imaging device 1a according to the present embodiment. That is, in the example shown in FIG. 10, the parts corresponding to the constant current circuit unit 114 and the ADC 113 are mainly shown, and the other components are not shown.
  • the MOS transistor 161, the comparator 141, the DAC 142, and the counter 143 are substantially the same as the MOS transistor 161, the comparator 141, the DAC 142, and the counter 143 shown in FIG. Omitted.
  • the comparator 141, the DAC 142, and the counter 143 correspond to the ADC 113 shown in FIG.
  • the MOS transistor 161 corresponds to the constant current circuit portion 114 shown in FIG.
  • the solid-state imaging device 1 a includes a sensor data unit 211.
  • the sensor data unit 211 recognizes the state of the pixel 2 based on a signal output from the counter 143, that is, a digital signal obtained by converting the pixel signal supplied from the pixel 2, and performs various processing using the recognition result. Execute.
  • the sensor data unit 211 may perform various processes related to so-called failure detection by using the recognition result of the state of the pixel 2.
  • the failure of the photoelectric conversion element PD is individually determined for each pixel 2. Can be recognized. Note that details of a mechanism for detecting a failure of the photoelectric conversion element PD included in the pixel 2 for each pixel 2 will be described later together with an example of drive control for recognizing the state of the pixel 2.
  • a part related to recognition of the pixel 2 corresponds to an example of a “recognition unit”.
  • the sensor data unit 211 may notify the detection result of the abnormality to the outside of the solid-state imaging device 1a.
  • the sensor data unit 211 may output a predetermined signal indicating that an abnormality has been detected to the outside of the solid-state imaging device 1a via a predetermined output terminal (that is, an Error pin).
  • a predetermined DSP (Digital Signal Processor) 401 provided outside the solid-state imaging device 1a may be notified that an abnormality has been detected.
  • the DSP 401 can notify the user that an abnormality has occurred in the solid-state imaging device 1a, for example, via a predetermined output unit.
  • the DSP 401 may perform control so as to limit all or a part of the vehicle safety function (ADAS function).
  • ADAS function vehicle safety function
  • the DSP 401 can correct the output of the pixel 2 in which an abnormality is detected using the output of another pixel 2 (for example, an adjacent pixel) different from the pixel 2.
  • a predetermined output destination for example, the DSP 401 or the like
  • the sensor data unit 211 itself may correct the output of the pixel 2 in which an abnormality is detected by using the result of failure detection.
  • the correction method is the same as that when the DSP 401 performs correction.
  • a portion of the sensor data unit 211 that corrects the output of the pixel 2 in which an abnormality has been detected corresponds to an example of a “correction processing unit”.
  • FIG. 6 is a schematic timing chart showing an example of drive control of the solid-state imaging device 1a according to the present embodiment, and an example of control for recognizing the state of the photoelectric conversion element PD included in the pixel 2. Shows about.
  • VDDHPX indicates a power supply voltage applied to the pixel 2 from the power supply VDDHPX.
  • INCK indicates a synchronization signal
  • one pulse of the synchronization signal is a minimum unit of various processing periods executed in the solid-state imaging device 1a.
  • XVS and XHS indicate a vertical synchronization signal and a horizontal synchronization signal. That is, 1XVS corresponds to one frame period.
  • TRG, RST, and SEL indicate drive signals (that is, TRG drive pulse, RST drive pulse, and SEL drive pulse) supplied to the transfer transistor Tr11, the reset transistor Tr12, and the selection transistor Tr14, respectively.
  • the control related to the recognition of the state of the photoelectric conversion element PD is mainly the first control for accumulating charges in the photoelectric conversion element PD of the target pixel 2, Second control for reading out the electric charge accumulated in the photoelectric conversion element PD.
  • first control for accumulating charges in the photoelectric conversion element PD of the target pixel 2
  • Second control for reading out the electric charge accumulated in the photoelectric conversion element PD.
  • one frame period is assigned to each of the first control and the second control. Therefore, in this description, as shown in FIG. 11, the frame period to which the first control is assigned is also referred to as an “accumulated frame”, and the frame period to which the second control is assigned is also referred to as a “read frame”.
  • the accumulation frame will be described. As shown in FIG. 11, in the accumulation frame, first, the power supply voltage applied to the pixel 2 from the power supply VDDHPX is controlled to 0 V, and then the power supply voltage is controlled to the predetermined voltage VDD. The voltage VDD is applied to the pixel 2.
  • FIG. 12 is an explanatory diagram for explaining an example of drive control of the solid-state imaging device 1a according to the present embodiment, and schematically shows the state of the pixel 2 in the period T11 in FIG.
  • the TRG drive pulse and the RST drive pulse are controlled to be on, the SEL drive pulse is controlled to be off, and the voltage applied to the pixel 2 from the power supply VDDHPX is controlled to 0V. Is done.
  • the potential of the floating diffusion portion FD is controlled to 0 V, a potential difference is generated between the anode and the cathode of the photoelectric conversion element PD, and charges are injected into the photoelectric conversion element PD.
  • the amount of charge held in the photoelectric conversion element PD as a result of the control shown in FIG. 12 is determined by the saturation characteristics of the photoelectric conversion element PD regardless of the light receiving state of the photoelectric conversion element PD.
  • the control for injecting charges into the photoelectric conversion element PD may be executed for all the pixels 2 at a predetermined timing (so-called global reset), or time division for each pixel 2. May be executed individually.
  • FIG. 13 is an explanatory diagram for explaining an example of drive control of the solid-state imaging device 1a according to the present embodiment, and schematically shows the state of the pixel 2 in the period T13 in FIG.
  • the RST drive pulse is kept in the on state, and the TRG drive pulse is controlled in the off state.
  • the SEL drive pulse is kept off.
  • the voltage applied to the pixel 2 from the power supply VDDHPX is controlled to VDD.
  • the floating diffusion portion FD and the photoelectric conversion element PD are brought into a non-conductive state, and the potential of the floating diffusion portion FD is controlled to VDD.
  • the readout frame will be described.
  • the target pixel 2 is driven at a predetermined timing, and a pixel signal corresponding to the charge accumulated in the photoelectric conversion element PD of the pixel 2 is read out.
  • the pixel 2 is driven in the period indicated by the reference symbol T ⁇ b> 15, and a pixel signal corresponding to the charge accumulated in the photoelectric conversion element PD of the pixel 2 is read.
  • FIG. 14 is an explanatory diagram for explaining an example of drive control of the solid-state imaging device 1a according to the present embodiment, and schematically shows the state of the pixel 2 in the period T15 in FIG.
  • each of the TRG drive pulse, the RST drive pulse, and the SEL drive pulse is controlled to be in an off state.
  • the state where the voltage VDD is applied to the pixel 2 is maintained.
  • each of the TRG drive pulse, the RST drive pulse, and the SEL drive pulse is controlled to be in an on state.
  • the transfer transistor Tr11 and the reset transistor Tr12 are turned on, and the charge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion portion FD. Accumulated in the floating diffusion portion FD.
  • the selection transistor Tr14 is controlled to be conductive.
  • a voltage corresponding to the charge accumulated in the floating diffusion portion FD (in other words, charge leaked from the photoelectric conversion element PD) is applied to the gate of the amplification transistor Tr13, and the amplification transistor Tr13 is controlled to be in a conductive state.
  • a pixel signal corresponding to the voltage applied to the gate of the amplification transistor Tr13 is output from the pixel 2 via the vertical signal line VSL. That is, a charge corresponding to the saturation characteristic of the photoelectric conversion element PD is read from the photoelectric conversion element PD, and a pixel signal corresponding to the charge read result is output from the pixel 2 via the vertical signal line VSL. It will be.
  • the pixel signal output from the pixel 2 via the vertical signal line VSL is converted into a digital signal by the ADC 113 and output to, for example, the sensor data unit 211 described with reference to FIG.
  • the digital signal output to the sensor data unit 211 indicates a potential corresponding to the saturation characteristic of the photoelectric conversion element PD included in the pixel 2. That is, the sensor data unit 211 can individually recognize the state of the pixel 2 (and thus the state of the photoelectric conversion element PD included in the pixel 2) for each pixel 2 based on the digital signal. Therefore, for example, when an abnormality occurs in the pixel 2, the sensor data unit 211 can detect the abnormality for each pixel 2 individually. Based on such a configuration, for example, the sensor data unit 211 can output information regarding the pixel 2 in which an abnormality has occurred to a predetermined output destination.
  • the sensor data unit 211 may correct the pixel signal output from the pixel 2 in which an abnormality has occurred based on the pixel signal output from the other pixel 2.
  • FIG. 15 is an explanatory diagram for explaining an example of an operation related to pixel signal correction in the solid-state imaging device 1a according to the present embodiment. In the example illustrated in FIG. 15, an example in which the pixel signal output from the pixel 2 in which an abnormality has occurred is corrected based on the pixel signal output from another pixel 2 adjacent to the pixel 2 is illustrated.
  • the sensor data unit 211 for example, based on the timing at which the pixel signal from the pixel 2 in which an abnormality has occurred is read, and the position of the pixel 2 and the other pixel 2 adjacent to the pixel 2 What is necessary is just to recognize a position.
  • control related to the recognition of the state of the photoelectric conversion element PD included in each pixel 2 described above for example, control for detecting abnormality of the photoelectric conversion element PD
  • the target pixel 2 It may be executed at a timing when normal driving is not performed.
  • the above control may be executed when the solid-state imaging device 1 is activated.
  • the above control may be executed for other pixels 2 that are not used for capturing the image.
  • FIG. 16 is a diagram illustrating an example of a circuit configuration of a unit pixel in a solid-state imaging device according to a modification of the present embodiment.
  • a high-sensitivity photodiode (PD1) and a low-sensitivity for one pixel 1 shows an example of a seven-transistor configuration in which a photodiode (PD2) and a pixel internal capacitance (FC) are arranged.
  • the solid-state imaging device according to the modification of the present embodiment may be referred to as “solid-state imaging device 1c” in order to distinguish it from the solid-state imaging device 1a according to the above-described embodiment.
  • the pixel of the solid-state imaging device 1c according to the modification of the present embodiment that is, the pixel constituting the shared pixel structure from the pixel 2 of the solid-state imaging device 1a according to the above-described embodiment, “pixel 2c Or “unit pixel 2c”.
  • the unit pixel 2c includes a photoelectric conversion element PD1, a first transfer gate unit Tr21, a photoelectric conversion element PD2, a second transfer gate unit Tr22, a third transfer gate unit Tr23, a fourth transfer gate unit Tr25,
  • the charge storage unit FC, the reset gate unit Tr24, the floating diffusion unit FD, the amplification transistor Tr26, and the selection transistor Tr27 are included.
  • a plurality of drive lines for supplying various drive signals to the unit pixel 2c are wired for each pixel row, for example.
  • Various drive signals TG1, TG2, FCG, RST, and SEL are supplied from the pixel timing drive circuit 5 shown in FIG. 1 via a plurality of drive lines.
  • these drive signals are in an active state at a high level (for example, the power supply voltage VDD) and are in a non-low state (for example, a negative potential). This is a pulse signal that becomes active.
  • the photoelectric conversion element PD1 is composed of, for example, a PN junction photodiode.
  • the photoelectric conversion element PD1 generates and accumulates charges corresponding to the received light quantity.
  • the first transfer gate portion Tr21 is connected between the photoelectric conversion element PD1 and the floating diffusion portion FD.
  • a drive signal TG1 is applied to the gate electrode of the first transfer gate portion Tr21.
  • the drive signal TG1 becomes active, the first transfer gate portion Tr21 becomes conductive, and the charges accumulated in the photoelectric conversion element PD1 are transferred to the floating diffusion portion FD via the first transfer gate portion Tr21. .
  • the photoelectric conversion element PD2 is composed of, for example, a PN junction photodiode, similarly to the photoelectric conversion element PD1.
  • the photoelectric conversion element PD2 generates and accumulates charges corresponding to the received light quantity.
  • the photoelectric conversion element PD1 has a larger light receiving surface area and higher sensitivity
  • the photoelectric conversion element PD2 has a smaller light receiving surface area and lower sensitivity.
  • the second transfer gate portion Tr22 is connected between the charge storage portion FC and the floating diffusion portion FD.
  • a drive signal FCG is applied to the gate electrode of the second transfer gate portion Tr22.
  • the drive signal FCG becomes active, the second transfer gate portion Tr22 becomes conductive, and the potentials of the charge storage portion FC and the floating diffusion portion FD are coupled.
  • the third transfer gate portion Tr23 is connected between the photoelectric conversion element PD2 and the charge storage portion FC.
  • the drive signal TG2 is applied to the gate electrode of the third transfer gate portion Tr23.
  • the third transfer gate portion Tr23 becomes conductive, and the charge accumulated in the photoelectric conversion element PD2 passes through the third transfer gate portion Tr23, or the charge accumulation portion FC or It is transferred to a region where the potentials of the charge storage unit FC and the floating diffusion unit FD are combined.
  • the lower portion of the gate electrode of the third transfer gate portion Tr23 has a slightly deep potential, and exceeds the saturation charge amount of the photoelectric conversion element PD2, and transfers the charges overflowing from the photoelectric conversion element PD2 to the charge storage portion FC.
  • An overflow path is formed.
  • the overflow path formed below the gate electrode of the third transfer gate portion Tr23 is simply referred to as the overflow path of the third transfer gate portion Tr23.
  • the fourth transfer gate portion Tr25 is connected between the second transfer gate portion Tr22 and the reset gate portion Tr24, and the floating diffusion portion FD.
  • a drive signal FDG is applied to the gate electrode of the fourth transfer gate portion Tr25.
  • the fourth transfer gate portion Tr25 becomes conductive, the node 152 between the second transfer gate portion Tr22, the reset gate portion Tr24, and the fourth transfer gate portion Tr25, and the floating diffusion
  • the potential with the part FD is coupled.
  • the charge storage unit FC includes, for example, a capacitor, and is connected between the second transfer gate unit Tr22 and the third transfer gate unit Tr23.
  • the counter electrode of the charge storage unit FC is connected between the power supply VDD that supplies the power supply voltage VDD.
  • the charge storage unit FC stores the charge transferred from the photoelectric conversion element PD2.
  • the reset gate portion Tr24 is connected between the power supply VDD and the floating diffusion portion FD.
  • a drive signal RST is applied to the gate electrode of the reset gate portion Tr24.
  • the reset gate portion Tr24 becomes conductive and the potential of the floating diffusion portion FD is reset to the level of the power supply voltage VDD.
  • the floating diffusion unit FD converts the charge into a voltage signal and outputs it.
  • the amplification transistor Tr26 has a gate electrode connected to the floating diffusion portion FD, a drain electrode connected to the power supply VDD, and a readout circuit for reading out the electric charge held in the floating diffusion portion FD, a so-called source follower circuit input portion and Become. That is, the amplifying transistor Tr26 forms a constant current source and a source follower circuit connected to one end of the vertical signal line VSL by connecting the source electrode to the vertical signal line VSL via the selection transistor Tr27.
  • the selection transistor Tr27 is connected between the source electrode of the amplification transistor Tr26 and the vertical signal line VSL.
  • a drive signal SEL is applied to the gate electrode of the selection transistor Tr27.
  • the selection transistor Tr27 becomes conductive and the unit pixel 2c becomes selected.
  • the pixel signal output from the amplification transistor Tr26 is output to the vertical signal line VSL via the selection transistor Tr27.
  • each drive signal is in an active state, each drive signal is turned on, or each drive signal is controlled to be in an on state, and each drive signal is in an inactive state.
  • Each drive signal is turned off or each drive signal is controlled to be turned off.
  • each gate portion or each transistor is turned on, each gate portion or each transistor may be turned on, and each gate portion or each transistor is turned off. It is also said that the transistor is turned off.
  • FIG. 17 is a schematic timing chart showing an example of drive control of the solid-state imaging device 1c according to the modification of the present embodiment, and recognizes the states of the photoelectric conversion elements PD1 and PD2 included in the pixel 2c. An example of control for this is shown.
  • VDDHPX indicates a power supply voltage applied to the pixel 2c from the power supply VDDHPX.
  • INCK indicates a synchronization signal
  • one pulse of the synchronization signal is a minimum unit of various processing periods executed in the solid-state imaging device 1c.
  • XVS and XHS indicate a vertical synchronization signal and a horizontal synchronization signal. That is, 1XVS corresponds to one frame period.
  • TG1, FCG, TG2, and FDG are drive signals (hereinafter referred to as “drive signals”) supplied to the first transfer gate unit Tr21, the second transfer gate unit Tr22, the third transfer gate unit Tr23, and the fourth transfer gate unit Tr25, respectively.
  • RST and SEL indicate drive signals (ie, RST drive pulse and SEL drive pulse) supplied to the reset gate unit Tr24 and the selection transistor Tr27, respectively.
  • the control related to the recognition of the state of the photoelectric conversion elements PD1 and PD2 is the first control for accumulating charges in the photoelectric conversion elements PD1 and PD2 of the target pixel 2c.
  • second control for reading out the electric charge accumulated in the photoelectric conversion element PD.
  • one frame period is assigned to each of the first control and the second control. That is, the frame period to which the first control is assigned corresponds to an “accumulated frame”, and the frame period to which the second control is assigned corresponds to a “read frame”.
  • the accumulation frame will be described. As shown in FIG. 17, in the accumulation frame, first, the power supply voltage applied to the pixel 2c from the power supply VDDHPX is controlled to 0V, and then the power supply voltage is controlled to the predetermined voltage VDD. The voltage VDD is applied to the pixel 2c.
  • FIG. 18 is an explanatory diagram for explaining an example of drive control of the solid-state imaging device 1c according to the modification of the present embodiment, and schematically shows the state of the pixel 2c in the period T21 in FIG.
  • the TG1 drive pulse, the FCG drive pulse, the TG2 drive pulse, the FDG drive pulse, and the RST drive pulse are controlled to be in the on state, and the SEL drive pulse is controlled to be in the off state.
  • the voltage applied to the pixel 2 from the power supply VDDHPX is controlled to 0V.
  • the potentials of the floating diffusion portion FD and the charge storage portion FC are controlled to 0 V, a potential difference is generated between the anode and the cathode of each of the photoelectric conversion elements PD1 and PD2, and charges are injected into the photoelectric conversion element PD. Note that, as a result of the control shown in FIG.
  • the amount of charge held in each of the photoelectric conversion elements PD1 and PD2 is the saturation of each of the photoelectric conversion elements PD1 and PD2 regardless of the light receiving state of the photoelectric conversion elements PD1 and PD2. It will be determined by the characteristics. That is, when some abnormality occurs in the photoelectric conversion element PD1, the amount of charge held in the photoelectric conversion element PD1 changes (for example, decreases) compared to the normal time. The same applies to the photoelectric conversion element PD2. As shown in FIG. 18, the control for injecting charges into each of the photoelectric conversion elements PD1 and PD2 may be executed for all the pixels 2c at a predetermined timing (that is, global reset), or each pixel. 2c may be individually executed in a time division manner.
  • FIG. 19 is an explanatory diagram for explaining an example of drive control of the solid-state imaging device 1c according to the application example of the present embodiment, and schematically shows the state of the pixel 2c in the period T23 of FIG.
  • each of the FDG drive pulse and the RST drive pulse is kept in the on state, and each of the TG1 drive pulse, the FCG drive pulse, and the TG2 drive pulse is controlled to be in the off state. .
  • the SEL drive pulse is kept off.
  • the voltage applied to the pixel 2c from the power supply VDDHPX is controlled to VDD.
  • FIG. 20 is a schematic timing chart showing an example of drive control of the solid-state imaging device 1c according to the present embodiment, and control related to readout of charges accumulated in the photoelectric conversion elements PD1 and PD2 of the pixel 2c. An example is shown.
  • VSL indicates the potential of a signal output via the vertical signal line (that is, a pixel signal output from the pixel 2c).
  • the signal shown as VSL is individually shown for each of the dark state and the bright state.
  • RAMP indicates the potential of the ramp wave output from the DAC in the ADC to the comparator.
  • a pulse indicating a change in potential of a signal output via the vertical signal line is superimposed on a pulse indicating a change in potential of the ramp wave.
  • VCO represents a voltage signal output from a counter in the ADC.
  • the P phase indicates a pre-data phase for reading the reset level of the pixel signal output from the pixel 2c.
  • the D phase indicates a data phase for reading the data level of the pixel signal.
  • the solid-state imaging device 1c As shown in FIG. 20, in the solid-state imaging device 1c according to the modified example of the present embodiment, first the first pixel signal corresponding to the electric charge accumulated in the photoelectric conversion element PD1 is read, and then accumulated in the photoelectric conversion element PD2. A second pixel signal corresponding to the generated charge is read out. At this time, for reading the first pixel signal, the P phase is read first, and then the D phase is read. On the other hand, regarding the reading of the second pixel signal, the charge accumulated in the charge accumulation unit FC is reset with the reading of the P phase, so the D phase is read first and then the P phase is read. Read phase. In the following, the operation of the solid-state imaging device 1c related to the reading of each of the first pixel signal and the second pixel signal is divided into an operation related to the P-phase reading and an operation related to the D-phase reading. explain.
  • the FDG drive pulse and the RST drive pulse are controlled to be in an off state. That is, at the start of the readout frame, each of the TG1 drive pulse, the FCG drive pulse, the TG2 drive pulse, the FDG drive pulse, the RST drive pulse, and the SEL drive pulse is in an OFF state. Thereafter, readout of the pixel signal from the target pixel 2c is started at a predetermined timing (a predetermined horizontal synchronization period) in the readout frame.
  • P-phase readout is performed on the first pixel signal corresponding to the electric charge accumulated in the photoelectric conversion element PD1.
  • the potential of the floating diffusion portion FD is set to the power supply voltage VDD by temporarily controlling the RST drive pulse to be in the on state. Reset to level.
  • the TG1 drive pulse, the FCG drive pulse, and the TG2 drive pulse are kept off. That is, between the photoelectric conversion element PD1 and the floating diffusion portion FD, and between the charge storage portion FC (and thus the photoelectric conversion element PD2) and the floating diffusion portion FD are in a non-conductive state. Therefore, the pixel signal read from the pixel 2c via the vertical signal line VSL at this time indicates the reset level of the pixel signal output from the pixel 2c.
  • D-phase reading is performed on the first pixel signal corresponding to the electric charge accumulated in the photoelectric conversion element PD1.
  • the TG1 drive pulse is temporarily controlled to be in an on state, and the photoelectric conversion element PD1 and the floating diffusion portion FD are in a conductive state during the period in which the TG1 drive pulse indicates the on state.
  • the electric charge accumulated in the photoelectric conversion element PD1 is transferred to the floating diffusion portion FD and accumulated in the floating diffusion portion FD.
  • a voltage corresponding to the charge accumulated in the floating diffusion portion FD (in other words, charge leaked from the photoelectric conversion element PD1) is applied to the gate of the amplification transistor Tr26, and the amplification transistor Tr26 is controlled to be in a conductive state.
  • a pixel signal (that is, a first pixel signal) corresponding to the voltage applied to the gate of the amplification transistor Tr26 is output from the pixel 2c via the vertical signal line VSL. That is, the charge corresponding to the saturation characteristic of the photoelectric conversion element PD1 is read from the photoelectric conversion element PD1, and the first pixel signal corresponding to the read result of the charge is read from the pixel 2c via the vertical signal line VSL. Will be output.
  • the SEL drive signal is controlled to the off state
  • the FDG drive signal is first temporarily controlled to the off state
  • the RST drive signal is temporarily The on state is controlled.
  • the potential of the floating diffusion portion FD is reset to the level of the power supply voltage VDD.
  • the FCG drive signal is controlled to be in an on state, and the floating diffusion unit FD and the charge storage unit FC are brought into conduction.
  • the SEL drive signal is controlled to be on, and reading of the second pixel signal corresponding to the charge accumulated in the photoelectric conversion element PD2 is started.
  • the D-phase reading is first performed as described above. Specifically, the TG1 drive pulse is temporarily controlled to be in an on state, and the photoelectric conversion element PD2 and the charge storage unit FC are in a conductive state during the period in which the TG2 drive pulse is in the on state. That is, during the period, the photoelectric conversion element PD2, the charge storage unit FC, and the floating diffusion unit FD are in a conductive state. As a result, the potentials of the charge storage unit FC and the floating diffusion unit FD are combined, and the charges stored in the photoelectric conversion element PD2 are transferred to the combined region and stored in the region.
  • a voltage corresponding to the charge accumulated in the region (in other words, the charge leaked from the photoelectric conversion element PD2) is applied to the gate of the amplification transistor Tr26, and the amplification transistor Tr26 is controlled to be conductive. Accordingly, a pixel signal (that is, a second pixel signal) corresponding to the voltage applied to the gate of the amplification transistor Tr26 is output from the pixel 2c through the vertical signal line VSL. That is, the charge corresponding to the saturation characteristic of the photoelectric conversion element PD2 is read from the photoelectric conversion element PD2, and the second pixel signal corresponding to the read result of the charge is transferred from the pixel 2c via the vertical signal line VSL. Will be output.
  • P-phase readout is performed on the second pixel signal corresponding to the charge accumulated in the photoelectric conversion element PD2.
  • the SEL drive signal is controlled to the off state, and then the RST drive signal is temporarily controlled to the on state.
  • the potential of the region where the potentials of the charge storage unit FC and the floating diffusion unit FD are combined is reset to the level of the power supply voltage VDD.
  • the SEL drive signal is controlled to be in an ON state, a voltage corresponding to the potential of the region is applied to the gate of the amplification transistor Tr26, and a pixel signal corresponding to the voltage (that is, the second pixel signal) is a vertical signal. It is output via the line VSL.
  • the TG1 drive pulse, the FCG drive pulse, and the TG2 drive pulse are kept off.
  • each between the photoelectric conversion element PD1 and the floating diffusion part FD and between the charge storage part FC and the floating diffusion part FD (and thus between the photoelectric conversion element PD2 and the floating diffusion part FD) is non-existent. It becomes conductive. Therefore, the pixel signal read from the pixel 2c via the vertical signal line VSL at this time indicates the reset level of the pixel signal output from the pixel 2c.
  • the first pixel signal and the second pixel signal sequentially output from the pixel 2c via the vertical signal line VSL are converted into digital signals by the ADC 113, for example, the sensor data unit described with reference to FIG. 211 is output.
  • the digital signal sequentially output to the sensor data unit 211 indicates a potential corresponding to the saturation characteristics of the photoelectric conversion elements PD1 and PD2 included in the pixel 2c. That is, the sensor data unit 211 can individually recognize the state of the pixel 2c (and thus the state of each of the photoelectric conversion elements PD1 and PD2 included in the pixel 2c) based on the digital signal. It becomes.
  • the application of the power supply voltage to the pixels is controlled so that charges are injected into the photoelectric conversion elements of at least some of the plurality of pixels, After that, supply of a drive signal to the pixel is controlled so that a pixel signal corresponding to the charge injected from the photoelectric conversion element is read out.
  • the solid-state imaging device according to the present embodiment recognizes the state of the pixel according to the readout result of the pixel signal corresponding to the charge from the photoelectric conversion element of the at least some pixels.
  • the state of the pixel (and thus the photoelectric conversion element included in the pixel) is individually recognized based on the pixel signal output from each pixel. Is possible. Therefore, in the solid-state imaging device, for example, when a failure occurs in some pixels, the abnormality can be detected for each pixel. Further, by using such a mechanism, for example, when an abnormality occurs in some pixels, it is possible to output information about the pixels to a predetermined output destination. As another example, since it is possible to specify the position of a pixel in which a failure has occurred, a pixel signal output from the pixel when an image is captured is output from another pixel (for example, an adjacent pixel). It is also possible to correct based on the pixel signal.
  • the application of power supply voltage to each pixel is controlled to inject charges into the photoelectric conversion element of the pixel. That is, the amount of charge held in the photoelectric conversion element as a result of the control is determined by the saturation characteristics of the photoelectric conversion elements PD1 and PD2, regardless of the light receiving state of the photoelectric conversion element. Due to such characteristics, according to the solid-state imaging device according to the present embodiment, control related to recognition of the state of each pixel (for example, a test for detecting a defective pixel) is executed regardless of the amount of light in the external environment. Is possible. That is, according to the solid-state imaging device according to the present embodiment, for example, a test for detecting a failure of each pixel 2 can be performed even in an environment where the amount of light in the external environment is smaller.
  • Solid-state imaging device 1d an example of a mechanism for the solid-state imaging device 1 to more efficiently execute various tests such as failure detection during an image (particularly, moving image) imaging period will be described.
  • the solid-state imaging device 1 may be referred to as “solid-state imaging device 1d”.
  • FIG. 21 is a block diagram illustrating an example of a schematic configuration of the solid-state imaging device 1d according to the present embodiment.
  • the configuration of the solid-state imaging device 1a will be described by focusing on the difference from the solid-state imaging device 1 described with reference to FIGS. 1 to 8, and substantially the same as the solid-state imaging device 1. Detailed description of this part is omitted.
  • FIG. 21 illustrates an example of a configuration of a portion related to reading of a pixel signal from the pixel 2 in the configuration of the solid-state imaging device 1d according to the present embodiment. That is, in the example shown in FIG. 21, the parts corresponding to the constant current circuit unit 114 and the ADC 113 are mainly shown, and the other components are not shown.
  • the MOS transistor 161, the comparator 141, the DAC 142, and the counter 143 are substantially the same as the MOS transistor 161, the comparator 141, the DAC 142, and the counter 143 shown in FIG. Omitted.
  • the comparator 141, the DAC 142, and the counter 143 correspond to the ADC 113 shown in FIG.
  • the MOS transistor 161 corresponds to the constant current circuit unit 114 shown in FIG.
  • the solid-state imaging device 1d includes a sensor data unit 221.
  • the sensor data unit 221 corresponds to the sensor data unit 211 in the solid-state imaging device 1a according to the first embodiment described with reference to FIG.
  • the control unit 101 illustrated in FIG. 3 controls the timing of exposure by each pixel 2 and the timing of reading a pixel signal based on the exposure result from the pixel 2. Further, the control unit 101 performs exposure by the pixel 2 and reading of a pixel signal based on the exposure result during a unit frame period corresponding to a predetermined frame rate in at least some of the pixels 2.
  • the operation of a predetermined configuration (for example, the sensor data unit 221) in the solid-state imaging device 1d is controlled so that a predetermined test such as failure detection is executed using a period that is not.
  • the timing at which the control unit 101 causes the predetermined configuration such as the sensor data unit 221 to execute the predetermined test will be described later in detail along with an example of drive control of the solid-state imaging device 1d.
  • the sensor data unit 221 executes a predetermined test such as failure detection based on the control from the control unit 101. Specifically, the sensor data unit 221 determines a state of a predetermined configuration in the solid-state imaging device 1d based on a signal output from the counter 143, that is, a digital signal obtained by converting the pixel signal supplied from the pixel 2. By recognizing, when an abnormality occurs in the configuration, the abnormality is detected.
  • the sensor data unit 221 is configured to supply a driving signal to at least some of the pixels 2 and each pixel 2 based on the digital signal output from the counter 143 (for example, the pixel timing driving circuit 5 and the address decoder 4). Etc.) and an abnormality occurring in at least one of the ADCs 111 can be detected.
  • the sensor data unit 221 may specify the ADC 113 that is the output source of the digital signal and the pixel 2 in which an abnormality has occurred according to the output timing of the digital signal.
  • the configuration related to the output of the pixel signal from each of the plurality of pixels 2 for example, the address decoder 4, the pixel timing drive circuit 5, the ADC 113, etc. It is possible to recognize that an abnormality has occurred.
  • the sensor data unit 221 includes a wiring connected to at least some of the pixels 2, a configuration for supplying a driving signal to each pixel 2, and the ADC 113 according to the output state of the digital signal from the counter 143. It is possible to detect an abnormality occurring in at least one of them.
  • the vertical signal line corresponding to the column or the column corresponds to the column. It can be recognized that an abnormality has occurred in the ADC 113.
  • an abnormality occurs in the output state of a digital signal for some rows, it can be recognized that an abnormality has occurred in the horizontal signal line corresponding to the row.
  • the subject of the detection Is not limited to the sensor data unit 221 and the detection method is not limited.
  • a unit for detecting an abnormality occurring in the configuration may be additionally provided separately from the sensor data unit 221 depending on the configuration to be tested.
  • a predetermined filter for example, LPF
  • LPF predetermined filter
  • the sensor data unit 221 may execute a predetermined process according to the detection result.
  • the sensor data unit 221 may notify the outside of the solid-state imaging device 1d of a detection result of an abnormality that has occurred in at least a part of the configuration.
  • the sensor data unit 211 may output a predetermined signal indicating that an abnormality has been detected to the outside of the solid-state imaging device 1d via a predetermined output terminal (that is, an Error pin).
  • a predetermined DSP (Digital Signal Processor) 401 provided outside the solid-state imaging device 1d may be notified that an abnormality has been detected.
  • a part of the sensor data unit 221 that controls the detection result of an abnormality occurring in at least a part of the configuration to a predetermined output destination is an example of the “output control unit”. It corresponds to.
  • the pixel The output from 2 may be corrected based on the output from other pixels 2.
  • FIGS. 22 and 23 are explanatory diagrams for explaining an example of an operation related to pixel signal correction in the solid-state imaging device 1d according to the present embodiment.
  • FIG. 22 shows an example when abnormality occurs in the output of pixel signals corresponding to some columns.
  • an example in which the pixel signal corresponding to the column in which the abnormality has occurred is corrected based on the pixel signal corresponding to another column adjacent to the column.
  • the sensor data unit 221 specifies the ADC 113 in which the abnormality is detected in the output of the digital signal, thereby specifying the column in which the abnormality has occurred and another column adjacent to the column. Good.
  • FIG. 23 shows an example where an abnormality occurs in the output of pixel signals corresponding to some rows.
  • an example in which the pixel signal corresponding to the row in which the abnormality has occurred is corrected based on the pixel signal corresponding to another row adjacent to the row.
  • the sensor data unit 221 may identify a row in which an abnormality has occurred and another row adjacent to the row based on the timing at which the pixel signal in which the abnormality has occurred is read.
  • the pixel signal output from the pixel 2 in which an abnormality has occurred is corrected based on the pixel signal output from another pixel 2 adjacent to the pixel 2. Is also possible.
  • a portion of the sensor data unit 221 that corrects an output from at least some of the pixels 2 corresponds to an example of a “correction processing unit”.
  • FIG. 24 is a schematic timing chart showing an example of drive control of the solid-state imaging device 1d according to the present embodiment, and an example of timing control at which a predetermined test of the solid-state imaging device 1d is executed. Show.
  • the horizontal axis indicates the time direction
  • the vertical axis indicates the position in the row direction of the two-dimensionally arranged pixels 2.
  • each pixel 2 is exposed during the unit frame period (that is, one vertical synchronization period) and the exposure result.
  • the drive control of the solid-state imaging device 1d will be described by paying attention to the case where reading is executed a plurality of times.
  • the solid-state imaging device 1 d includes a first exposure (Long exposure), a second exposure (Middle exposure), and a third exposure (Short exposure) having different exposure times during a unit frame period. exposure) is executed sequentially in a time-sharing manner.
  • reference symbols T111 and T112 indicate an exposure period (Long Shutter) in the first exposure
  • reference symbols T121 and T122 indicate pixel signals based on the result of the first exposure. Indicates the read period (Long Read).
  • Reference symbols T131 and T132 indicate an exposure period (Middle Shutter) in the second exposure
  • reference symbols T141 and T142 indicate a pixel signal readout period (Middle Read) based on the result of the second exposure.
  • Reference symbols T151 and T152 indicate an exposure period (Short Shutter) in the third exposure
  • reference symbols T161 and T162 indicate a pixel signal readout period (Short Read) based on the result of the third exposure. Show.
  • reference symbol VBLK indicates a vertical blank (V blank) period.
  • V blank vertical blank
  • a predetermined test such as column signal line failure detection or TSV failure detection is performed, and pixel signals are read from any of the pixels 2 during the period.
  • the vertical blank period VBLK is a period from the completion of reading pixel signals from a series of pixels 2 in a certain frame period to the start of reading pixel signals from the series of pixels 2 in the next frame period. It corresponds to a period.
  • Reference numerals T171 and T172 indicate that pixel 2 in each row is subjected to exposure by the pixel 2 (for example, first exposure to third exposure) and readout of a pixel signal based on the exposure result. Corresponds to no period.
  • the solid-state imaging device 1d according to the present embodiment performs a predetermined test (for example, BIST: Built-In Self-Test) using the periods T171 and T172. Specific examples of the predetermined test include failure detection for each pixel.
  • the periods indicated by reference numerals T171 and T172 are also referred to as “BIST periods”.
  • the BIST periods T171 and T172 are also referred to as “BIST period T170” unless otherwise distinguished.
  • the BIST period T170 is the last in the unit frame period in which one or more exposures (for example, the first exposure to the third exposure) are performed by pixels in a certain row. This is started after the reading of the pixel signal based on the result of the exposure (for example, the third exposure) is completed. Further, the BIST period T170 ends before the first exposure (for example, the first exposure) in the next frame period after the unit frame period is started. As a more specific example, the BIST period T171 shown in FIG. 24 starts from the exposure period T112 of the first exposure in the next unit frame period after the end of the pixel signal readout period T161 based on the third exposure result. It is a period until. The BIST period T170 may be set between the first exposure and the second exposure, or between the second exposure and the third exposure. Although details will be described later, the BIST period T170 is generated by setting the vertical blank period VBLK.
  • FIG. 25 and FIG. 26 are explanatory diagrams for explaining an example of schematic control related to readout of pixel signals from each pixel 2 in the solid-state imaging device 1d according to the present embodiment.
  • the vertical axis schematically shows the vertical synchronization period XVS
  • the horizontal axis schematically shows the horizontal synchronization period XHS.
  • square regions indicated by reference characters L, M, and S schematically show the readout timing of the exposure result from each of the two-dimensionally arranged plurality of pixels 2. This corresponds to each of the exposure, the second exposure, and the third exposure.
  • the horizontal direction corresponds to the column direction of the plurality of pixels 2 that are two-dimensionally arranged
  • the vertical direction corresponds to the row direction of the plurality of pixels 2. It corresponds.
  • pixel signals are read from the pixels 2 included in the row for each horizontal synchronization period.
  • pixel signals are sequentially read out based on each exposure result in the order of the first exposure, the second exposure, and the third exposure every horizontal synchronization period.
  • reference numeral R111 in FIG. 25 schematically illustrates a part of the vertical synchronization period. That is, in the example shown in FIG. 25, in the period R111, the pixel signals based on the results of the first exposure, the second exposure, and the third exposure are the pixel 2 in the ⁇ row and the pixel in the ⁇ row, respectively. 2 and the pixel 2 in the ⁇ -th row.
  • FIG. 26 shows a schematic timing chart relating to readout of the pixel signal from each pixel 2 in the example shown in FIG.
  • the pixel signal is read based on the first exposure result from the pixel 2 in the ⁇ row, and the pixel signal based on the second exposure result from the pixel 2 in the ⁇ row.
  • Readout and readout of pixel signals based on the third exposure result from the pixels 2 in the ⁇ -th row are sequentially executed.
  • readout of a pixel signal based on the first exposure result from the pixel 2 in the ⁇ + 1 row readout of a pixel signal based on the second exposure result from the pixel 2 in the ⁇ + 1 row, and ⁇ + 1 row.
  • the readout of pixel signals based on the third exposure result from the pixel 2 of the eye is sequentially executed.
  • the drive control described above is merely an example, and at least the BIST period T170 is provided, and if a predetermined test can be performed during the BIST period T170, the drive control of the solid-state imaging device 1d according to the present embodiment is
  • the example described with reference to FIGS. 24 to 26 is not necessarily limited.
  • the solid-state imaging device 1d according to the present embodiment may be configured such that each pixel 2 executes exposure and reading of the exposure result only once during a unit frame period. Good.
  • the BIST period T170 is started after the reading of the pixel signal based on the exposure result in a certain unit frame period, and is ended until the exposure in the next unit frame period is started.
  • FIG. 27 is a timing chart for explaining the relationship between the exposure time constraint and the vertical blank period in the solid-state imaging device 1d according to the present embodiment.
  • the first exposure Long exposure
  • the second exposure Middle exposure
  • the third exposure having different exposure times during the unit frame period.
  • An example in which exposure (Short exposure) is sequentially performed is shown.
  • the horizontal axis and the vertical axis in FIG. 27 are the same as the horizontal axis and the vertical axis in FIG.
  • the unit frame period (that is, one vertical synchronization period) is 25 ms.
  • the ratio of the exposure period (in other words, the charge accumulation period in the pixel 2) between each of the first exposure to the third exposure (hereinafter also referred to as “exposure ratio”) is 16 times, Assuming that the first exposure period (Long Shutter) is A, the second exposure period (Middle Shutter) is A / 16, and the third exposure period (Short Shutter) is 1/256.
  • the solid-state imaging device performs exposure by at least some pixels and reading of pixel signals based on the exposure result during a unit frame period corresponding to a predetermined frame rate.
  • a predetermined test is executed during a BIST period that is not performed.
  • the BIST period is started after the reading of the pixel signal based on the result of the last exposure in the unit frame period in which one or more exposures are performed by at least some pixels (for example, pixels in a certain row) is completed. . Further, the BIST period ends before the first exposure in the next frame period after the unit frame period is started.
  • a test for detecting a failure of the pixel 2 included in each row is executed in a BIST period defined corresponding to the row. It becomes possible.
  • the conventional solid-state imaging device when fault detection is executed for all rows, it takes a period of at least one frame to execute the test, and a dedicated image is not taken for the test. It was necessary to provide a frame.
  • the solid-state imaging device according to the present embodiment it is possible to execute a test for failure detection for each row in parallel with the imaging of the image, compared with the conventional solid-state imaging device. Therefore, there is no need to provide a dedicated frame in which no image is taken for testing.
  • the solid-state imaging device According to the solid-state imaging device according to the present embodiment, at least a part of the tests performed in the vertical blank period can be performed in the BIST period. With such a configuration, the vertical blank period can be further shortened, and as a result, the frame rate can be further improved.
  • failure detection for TSV, column signal line failure detection, and the like may be executed in the vertical blank period. With such a configuration, it is possible to execute each failure detection while maintaining a sufficient exposure time while maintaining the frame rate.
  • the solid-state imaging device by performing a predetermined test using the BIST period, various tests such as failure detection during the imaging period can be performed. It becomes possible to execute efficiently.
  • the hardware of the front camera ECU and the imaging device has a configuration in which a lower chip 1091 and an upper chip 1092 are stacked.
  • the right part of FIG. 28 represents a floor plan that is the hardware configuration of the lower chip 1091, and the left part of FIG. 28 represents the floor plan that is the hardware structure of the upper chip 1092.
  • the lower chip 1091 and the upper chip 1092 are provided with TCVs (Through Chip Vias) 1093-1 and 1093-2 at the left and right ends in the respective drawings, and the lower chip 1091 and the upper chip 1092 penetrate therethrough. Are electrically connected.
  • a row driving unit 1102 (FIG. 29) is arranged on the right side of the TCV 1093-1 in the drawing and is electrically connected.
  • a control line gate 1143 (FIG. 29) of the front camera ECU 73 is arranged on the left side of the TCV 1093-2 in the drawing and is electrically connected. Details of the row driver 1102 and the control line gate 1143 will be described later with reference to FIG. In this specification, TCV and TSV are treated as synonymous.
  • the lower chip 1091 and the upper chip 1092 are provided with TCV 1093-11 and 1093-12 at the upper and lower ends in the respective drawings, and the lower chip 1091 and the upper chip 1092 are penetrated and electrically connected. Yes.
  • a column ADC (Analog to Digital Converter) 1111-1 is arranged and electrically connected to the lower part of the TCV 1093-11 in the figure, and the upper part of the TCV 1093-12 in the figure is A column ADC (Analog to Digital Converter) 111-2 is disposed and electrically connected.
  • a DAC (Digital to Analog Converter) 1112 is provided between the right end portions of the column ADCs 1111-1 and 111-2 in the drawing and on the left side of the control line gate 1143, and arrows C1 and C2 in the drawing. As shown, the ramp voltage is output to the column ADCs 1111-1 and 111-2. Note that the column ADCs 1111-1 and 111-2 and the DAC 1112 have a configuration corresponding to the image signal output unit 1103 in FIG. Since the DAC 1112 preferably outputs ramp voltages having the same characteristics to the column ADCs 1111-1 and 111-2, it is desirable that the DAC 1112 be equidistant from both the column ADCs 1111-1 and 111-2. Further, although one example is shown in the example of FIG. 28, two DACs 1112 having the same characteristics are provided for each of the column ADCs 1111-1 and 111-2. May be. Details of the image signal output unit 1103 will be described later with reference to FIG.
  • a signal processing circuit 1113 is provided between the upper and lower columns ADC 1111-1 and 111-2 and between the row driving unit 1102 and the DAC 1112.
  • the control unit 1121 and the image processing unit 1122 in FIG. Functions corresponding to the output unit 1123 and the failure detection unit 1124 are realized.
  • the pixel array 1101 substantially forms the entire surface of a rectangular area surrounded by TCVs 1093-1, 1093-2, 1093-11, and 1093-12 provided at the top, bottom, left and right ends. Yes.
  • the pixel array 1101 is based on a control signal supplied from the row driver 1102 from the TCV 1093-1 via the pixel control line L (FIG. 29), and among the pixel signals, the pixel signal of the upper half pixel in the figure. Is output to the lower chip 1091 via the TCV 1093-11, and the pixel signal of the lower half pixel in the figure is output to the lower chip 1091 via the TCV 1093-12.
  • the control signal is sent from the signal processing circuit 1113 that implements the row driving unit 1102 via the TCV 1093-1 via the pixel control line L of the pixel array of the upper chip 1092, as indicated by an arrow B1 in the figure. It is output to the gate 1143 (FIG. 29).
  • the control line gate 1143 controls the control line according to the control signal via the pixel control line L from the row driving unit 1102 (FIG. 29) for the row address which is the command information from the control unit 1121 (FIG. 29).
  • the control line gate 1143 By comparing the signal output from the gate 1143 with the detection pulse of the control signal corresponding to the row address supplied from the control unit 1121, the presence or absence of a failure due to the disconnection of the pixel control line L and TCV 1093-1 and 1093-2 is determined. To detect. Then, the control line gate 1143 outputs information on the presence / absence of a failure to the failure detection unit 1124 realized by the signal processing circuit 1113, as indicated by an arrow B2 in the figure.
  • the column ADC 11111-1 converts the pixel signal of the upper half pixel in the figure of the pixel array 1101 supplied via the TCV 1093-11 into a digital signal in units of columns, as indicated by an arrow A 1 in the figure. And output to the signal processing circuit 1113. Further, the column ADC 111-2, as indicated by an arrow A2 in the figure, converts the pixel signal of the lower half pixel in the figure of the pixel array 1101 supplied via the TCV 1093-12 into a digital signal in units of columns. And output to the signal processing circuit 1113.
  • the upper chip 1092 becomes only the pixel array 1101, so that it is possible to introduce a semiconductor process specialized for pixels. For example, since there is no circuit transistor in the upper chip 1092, it is not necessary to pay attention to characteristic fluctuations caused by an annealing process at 1000 ° C., etc. The characteristics can be improved.
  • the failure detection unit 1124 in the lower chip 1091, it is possible to detect signals after passing through the TCVs 1093-1 and 1093-2 in the lower chip 1091 through the upper chip 1092 and the upper chip 1092 through the lower chip 1091. Therefore, it becomes possible to detect a failure appropriately.
  • the upper chip 1092 corresponds to an example of a “first substrate”
  • the lower chip 1091 corresponds to an example of a “second substrate”.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.
  • FIG. 30 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp.
  • the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted.
  • the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image.
  • the vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light.
  • the imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
  • the vehicle interior information detection unit 12040 detects vehicle interior information.
  • a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
  • the microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010.
  • the microcomputer 12051 realizes an ADAS (Advanced Driver Assistance System) function including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintaining traveling, vehicle collision warning, or vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
  • the sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 31 is a diagram illustrating an example of an installation position of the imaging unit 12031.
  • the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100.
  • the imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100.
  • the forward images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 31 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100).
  • a predetermined speed for example, 0 km / h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
  • the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles.
  • the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining.
  • the audio image output unit 12052 When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to be superimposed and displayed.
  • voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the solid-state imaging device 1 illustrated in FIG. 1 can be applied to the imaging unit 12031.
  • the technology according to the present disclosure to the imaging unit 12031, for example, when an abnormality occurs in at least some of the pixels of the solid-state imaging device that configures the imaging unit 12031, the abnormality is determined. It becomes possible to detect.
  • information indicating that the abnormality has occurred can be notified to the user via a predetermined output unit. It becomes possible.
  • the function which controls a vehicle can be restrict
  • Specific examples of the function of controlling the vehicle include a collision avoidance or impact mitigation function of the vehicle, a following traveling function based on the inter-vehicle distance, a vehicle speed maintaining traveling function, a vehicle collision warning function, or a vehicle lane departure warning function. .
  • the function of controlling the vehicle can be restricted or prohibited. Thereby, it is possible to prevent an accident caused by erroneous detection based on the malfunction of the imaging unit 7410.
  • FIG. 32 is a block diagram showing an example of a schematic configuration of an imaging apparatus applied to a moving body.
  • the imaging apparatus 800 illustrated in FIG. 32 corresponds to, for example, the imaging unit 12031 illustrated in FIG.
  • the imaging apparatus 800 includes an optical system 801, a solid-state imaging device 803, a control unit 805, and a communication unit 807.
  • the solid-state imaging device 803 may correspond to, for example, the imaging unit 12031 illustrated in FIG. That is, light that has entered the imaging device 800 via the optical system 801 such as a lens is photoelectrically converted into an electric signal by the solid-state imaging device 803, and an image corresponding to the electric signal or an electric signal corresponding to the electric signal is obtained. Ranging information is output to the control unit 805.
  • the control unit 805 is configured as an ECU (Electronic Control Unit), for example, and executes various processes based on an image output from the solid-state image sensor 803 and distance measurement information. As a specific example, the control unit 805 performs various kinds of analysis processing on the image output from the solid-state image sensor 803, so that an external person, a vehicle, an obstacle, a sign, or a character on the road surface is based on the analysis result. Etc., and the distance to the object is measured.
  • ECU Electronic Control Unit
  • control unit 805 is connected to a vehicle-mounted network (CAN: Controller Area Network) via the communication unit 807.
  • the communication unit 807 corresponds to an interface with so-called CAN communication. Based on such a configuration, for example, the control unit 805 transmits / receives various information to / from other control units (for example, the integrated control unit 12050 shown in FIG. 30) connected to the in-vehicle network.
  • control unit 805 can provide various functions by using, for example, the recognition result of the object and the measurement result of the distance to the object as described above.
  • FCW Pedestrian Detection for Forward Collision Warning
  • AEB Automatic Emergency Braking
  • Vehicle Detection for FCW / AEB LDW (Lane Departure Warning)
  • TJP Traffic Jam Pilot
  • LKA Lane Keeping Aid
  • VO ACC Vision Only Adaptive Cruise Control
  • VO TSR Traffic Sign Recognition
  • IHC Intelligent Head Ramp Control
  • control unit 805 can calculate the time until the vehicle collides with an external object such as a person or another vehicle in a situation where the vehicle is likely to collide with the object. is there. Therefore, for example, when the calculation result of such time is notified to the integrated control unit 12050, the integrated control unit 12050 can use the notified information for realizing the FCW.
  • an external object such as a person or another vehicle in a situation where the vehicle is likely to collide with the object. is there. Therefore, for example, when the calculation result of such time is notified to the integrated control unit 12050, the integrated control unit 12050 can use the notified information for realizing the FCW.
  • control unit 805 can detect the brake lamp of the preceding vehicle based on the analysis result of the image ahead of the vehicle. That is, when the detection result is notified to the integrated control unit 12050, the integrated control unit 12050 can use the notified information for realizing the AEB.
  • control unit 805 can recognize a lane in which the vehicle is traveling, an edge of the lane, a curb, and the like based on an analysis result of an image in front of the vehicle. Therefore, when the recognition result is notified to the integrated control unit 12050, the integrated control unit 12050 can use the notified information for realizing the LDW.
  • control unit 805 may recognize the presence or absence of a preceding vehicle based on the analysis result of the image ahead of the vehicle, and notify the integrated control unit 12050 of the recognition result.
  • the integrated control unit 12050 can control the vehicle speed according to the presence or absence of a preceding vehicle, for example, when the TJP is executed.
  • the control unit 805 may recognize the sign based on the analysis result of the image ahead of the vehicle, and notify the integrated control unit 12050 of the recognition result.
  • the integrated control unit 12050 can recognize the speed limit according to the recognition result of the sign and control the vehicle speed according to the speed limit, for example, when the TJP is executed.
  • the control unit 805 can also recognize the entrance and exit of the expressway, recognize whether or not the traveling vehicle has reached a curve, and the recognition result is obtained by the integrated control unit 12050. It can be used for vehicle control.
  • the control unit 805 can also recognize the light source located in front of the vehicle based on the analysis result of the image in front of the vehicle. That is, the integrated control unit 12050 is notified of the recognition result of the light source, so that the integrated control unit 12050 can use the notified information for realizing the IHC. As a specific example, the integrated control unit 12050 can control the light amount of the headlamp according to the recognized light amount of the light source. As another example, the integrated control unit 12050 can limit the amount of light of either the left or right headlamp according to the recognized position of the light source.
  • the control unit 805 when an abnormality occurs in the solid-state imaging device 803, the control unit 805 outputs information to be output from the solid-state imaging device 803. Based on this, it is possible to detect the abnormality. Therefore, for example, the control unit 805 notifies the integrated control unit 12050 of the abnormality detection result of the solid-state imaging device 803, so that the integrated control unit 12050 performs various controls for ensuring safety. It becomes possible to execute.
  • the integrated control unit 12050 may notify the user that an abnormality has occurred in the solid-state imaging device 803 via various output devices.
  • the output device include an audio speaker 12061, a display unit 12062, an instrument panel 12063, and the like shown in FIG.
  • the integrated control unit 12050 may control the operation of the vehicle according to the recognition result.
  • the integrated control unit 12050 may limit a so-called automatic control function such as TJP or LKA described above. Further, the integrated control unit 12050 may execute control for ensuring safety, such as limiting the vehicle speed.
  • an abnormality occurs in the solid-state imaging device 803, and it is difficult to operate various recognition processes normally.
  • the abnormality can be detected. Therefore, for example, in accordance with the detection result of the abnormality, execution of various measures for ensuring safety, such as notifying the user of notification information regarding the abnormality or controlling the operation of the configuration related to various recognition processes Can be realized.
  • a plurality of pixels A control unit for controlling exposure by each of the plurality of pixels; From the completion of the readout of the pixel signal based on the final exposure result in the first period in which at least one exposure is performed by at least some of the plurality of pixels, than in the first period.
  • a processing unit that executes a predetermined test in a third period until the first exposure in the second period in which the one or more exposures are performed later;
  • An imaging apparatus comprising: (2) The imaging apparatus according to (1), wherein the first period and the second period are unit frame periods corresponding to a predetermined frame rate. (3) The imaging apparatus according to (2), wherein the third period is set according to a vertical blanking period in the unit frame period.
  • the control unit controls the exposure start timing for each of the plurality of pixels arranged in a two-dimensional matrix, for each row, For each row, the processing unit performs the first in the second period after the completion of reading out the pixel signal based on the last exposure result in the first period by the pixels included in the row. Performing the test in the third period until the exposure of The imaging apparatus according to any one of (1) to (5).
  • the imaging apparatus according to any one of (1) to (6), wherein the processing unit executes a test for the some pixels as the test.
  • a drive circuit for supplying a drive signal to each of the plurality of pixels;
  • the imaging apparatus according to any one of (1) to (7), wherein the processing unit executes a test for the drive circuit as the test.
  • An AD converter that converts the analog pixel signal read from the pixel into a digital signal;
  • the imaging apparatus according to any one of (1) to (9), wherein the processing unit executes a test for wiring connected to the some pixels as the test.
  • the imaging apparatus according to any one of (1) to (10), further including an output control unit configured to control information according to a result of the test to be output to a predetermined output destination.
  • the imaging apparatus according to any one of (1) to (11), further including a correction processing unit that corrects the pixel signals output from at least some of the pixels in accordance with a result of the test.
  • a control unit for controlling exposure by each of a plurality of pixels; From the completion of the readout of the pixel signal based on the final exposure result in the first period in which at least one exposure is performed by at least some of the plurality of pixels, than in the first period.
  • a processing unit that performs a test on the partial pixels in a third period until the first exposure in the second period in which the one or more exposures are performed later;
  • a control device comprising: (14) The control device according to (13), further including an output control unit that performs control so that information according to the result of the test is presented to a predetermined output unit. (15) The control device according to (13) or (14), further including a correction processing unit that corrects an image based on a readout result of the pixel signal from the plurality of pixels according to the result of the test.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

Le problème décrit par la présente invention est de permettre de réaliser de manière plus efficace divers tests de détection d'anomalies. À cet effet, l'invention concerne un système d'imagerie comprenant : un dispositif d'imagerie qui est monté sur un véhicule et qui génère des images au moyen de la capture d'images de la zone autour du véhicule; et un dispositif de traitement qui est monté sur le véhicule et qui effectue un traitement relatif à une fonction de commande du véhicule. Le dispositif d'imagerie comprend une pluralité de pixels, une unité de commande destinée à commander l'exposition au moyen de chacun de la pluralité de pixels, et une unité de traitement destinée à effectuer un test prédéterminé. L'unité de commande commande l'exposition de sorte que, après que la lecture de signaux de pixels est achevée dans une première période dans laquelle une exposition est effectuée au moins une fois par au moins une partie des pixels de la pluralité de pixels, la lecture des signaux de pixels est démarrée dans une seconde période dans laquelle une exposition est effectuée au moins une fois. L'unité de traitement effectue un test prédéterminé dans une troisième période qui se trouve entre la lecture de signaux de pixels dans la première période et la lecture de signaux de pixels dans la seconde période. Le dispositif de traitement limite la fonction de commande du véhicule sur la base des résultats du test prédéterminé.
PCT/JP2017/040155 2017-02-01 2017-11-07 Système d'imagerie et dispositif d'imagerie Ceased WO2018142707A1 (fr)

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DE112017006977.7T DE112017006977T5 (de) 2017-02-01 2017-11-07 Abbildungssystem und abbildungseinrichtung
CN201780084589.XA CN110226325B (zh) 2017-02-01 2017-11-07 摄像系统和摄像装置
US16/471,406 US10819928B2 (en) 2017-02-01 2017-11-07 Imaging system and imaging apparatus for detection of abnormalities associated with the imaging system

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