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WO2018038133A1 - Dispositif semi-conducteur en carbure de silicium - Google Patents

Dispositif semi-conducteur en carbure de silicium Download PDF

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Publication number
WO2018038133A1
WO2018038133A1 PCT/JP2017/030039 JP2017030039W WO2018038133A1 WO 2018038133 A1 WO2018038133 A1 WO 2018038133A1 JP 2017030039 W JP2017030039 W JP 2017030039W WO 2018038133 A1 WO2018038133 A1 WO 2018038133A1
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Prior art keywords
well region
insulating film
gate
region
well
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English (en)
Japanese (ja)
Inventor
愛 赤木
史郎 日野
勝俊 菅原
須賀原　和之
正尚 伊藤
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2018535720A priority Critical patent/JP6580270B2/ja
Publication of WO2018038133A1 publication Critical patent/WO2018038133A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/143—VDMOS having built-in components the built-in components being PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers

Definitions

  • the present invention relates to a silicon carbide semiconductor device.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the n-channel MOSFET has an n-type drift layer and a p-type well provided thereon.
  • the drain voltage of the MOSFET that is, the drain electrode voltage
  • the drain electrode voltage abruptly rises and changes from approximately 0V to several hundred volts.
  • a displacement current is generated through a parasitic capacitance that exists between the p-type well and the n-type drift layer. Displacement current generated on the drain electrode side flows to the drain electrode, and displacement current generated on the source electrode side flows to the source electrode via the p-type well.
  • the vertical n-channel MOSFET is typically provided with another p-type well on the outermost periphery of the chip in addition to the p-type well constituting the MOSFET cell that actually functions as a MOSFET.
  • these other p-type wells are those located directly under the gate pad.
  • These outermost p-type wells usually have a much larger cross-sectional area (area in a planar layout) than the p-type well of a MOSFET cell. For this reason, in the outermost p-type well, the displacement current described above needs to flow through a long path before reaching the source electrode. Therefore, this p-type well has a high electric resistance as a current path for displacement current.
  • silicon carbide semiconductor devices particularly n-channel MOSFETs, that use silicon carbide having a band gap approximately three times larger than the band gap of silicon, which is the most common semiconductor material, as a semiconductor material, are switching inverter circuits. It has begun to be applied as an element. Thereby, the loss of an inverter circuit can be reduced. In order to further reduce the loss, it is required to drive the switching element at a higher speed. In other words, in order to reduce the loss, it is required to further increase dV / dt, which is the fluctuation of the drain voltage V with respect to time t. In that case, the displacement current flowing into the p-type well via the parasitic capacitance also increases.
  • silicon carbide which is a semiconductor material having a large band gap, is less likely to reduce electrical resistance by doping than silicon. For this reason, the parasitic resistance of the p-type well is likely to be increased by using silicon carbide. As a result, the potential drop in the p-type well tends to be larger. From the above, when silicon carbide is used, the above-described fear of dielectric breakdown is further increased.
  • a p-type semiconductor layer having a low resistance is provided entirely or partially on the upper surface of the outermost p-type well located below the gate pad.
  • a p-type semiconductor layer having a low resistance is provided on a p-type well in order to prevent element destruction during switching. Therefore, in manufacturing a silicon carbide semiconductor device, a step of depositing a low-resistance p-type semiconductor layer on the p-type well is required. Thereby, manufacture of a silicon carbide semiconductor device will become more difficult. Therefore, a new technology different from this technology has been demanded.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a silicon carbide semiconductor device capable of preventing element destruction during switching.
  • a silicon carbide semiconductor device of the present invention includes a semiconductor substrate, a drain electrode, a drift layer, a plurality of first well regions, a source region, a second well region, a gate insulating film, a field insulating film, and a gate An electrode, an interlayer insulating film, a source electrode, an insulator layer, and a conductor layer are included.
  • the semiconductor substrate has a first surface and a second surface opposite to the first surface.
  • the drain electrode is provided on the first surface of the semiconductor substrate.
  • the drift layer is provided on the second surface of the semiconductor substrate, is made of silicon carbide, and has the first conductivity type.
  • the plurality of first well regions are provided on the drift layer and have a second conductivity type different from the first conductivity type.
  • the source region is provided on the first well region, has the first conductivity type, and is separated from the drift layer by the first well region.
  • the second well region is provided on the drift layer, has an end adjacent to the first well region via the drift layer, and has the second conductivity type.
  • the gate insulating film is provided on the first well region and on the end of the second well region.
  • the field insulating film is provided on the second well region and is thicker than the gate insulating film.
  • the gate electrode has a portion on the gate insulating film and a portion on the field insulating film.
  • the interlayer insulating film has a source contact hole on the source region and a first well contact hole on the second well region.
  • the source electrode is connected to the source region through the source contact hole, and is connected to the second well region through the first well contact hole.
  • the insulator layer is provided on the second well region and is thinner than the field insulating film.
  • the conductor layer has a portion disposed on the second well region through only the insulator layer.
  • the insulator layer and the conductor layer are provided on the second well region.
  • a capacitor is provided on the second well region.
  • This capacitance can have a large value per unit area because the insulator layer is thinner than the field insulating film.
  • FIG. 1 is a plan view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention.
  • FIG. 2 is a partial cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a partial cross-sectional view taken along line III-III in FIG.
  • FIG. 5 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention in a field of view corresponding to FIG. 2.
  • FIG. 4 is a partial cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention in a field of view corresponding to FIG. 3.
  • FIG. 3 is a partial cross-sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention in a field of view corresponding to FIG. 3.
  • FIG. 3 is a partial cross-sectional view schematic
  • FIG. 11 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 2.
  • FIG. 4 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 3.
  • FIG. 11 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 2.
  • FIG. 4 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 3.
  • FIG. 11 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a
  • FIG. 4 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 3.
  • FIG. 10 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 2.
  • FIG. 4 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 3.
  • FIG. 10 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention with a field of view corresponding to FIG. 3.
  • FIG. 3 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a second embodiment of the present invention in the same field of view as FIG. 2.
  • FIG. 4 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a second embodiment of the present invention in the same field of view as FIG. 3.
  • FIG. 13 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention with a field of view corresponding to FIG. 12.
  • FIG. 14 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention with a field of view corresponding to FIG. 13.
  • FIG. 13 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention with a field of view corresponding to FIG. 13.
  • FIG. 13 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention with a field of view corresponding to FIG. 12.
  • FIG. 14 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention with a field of view corresponding to FIG. 13.
  • FIG. 13 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in the second embodiment of the present invention with a field of view corresponding to FIG. 12.
  • FIG. 14 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device in Embodiment 2 of the present invention in a field of view corresponding to FIG. 13.
  • FIG. 4 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a third embodiment of the present invention in the same field of view as FIG. 2. It is a top view which shows roughly the structure of the silicon carbide semiconductor device in Embodiment 4 of this invention.
  • FIG. 22 is a partial cross-sectional view taken along line XXII-XXII in FIG. 21.
  • FIG. 22 is a partial cross-sectional view taken along line XXIII-XXIII in FIG. 21.
  • FIG. 23 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a fifth embodiment of the present invention with a view similar to FIG.
  • FIG. 24 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a fifth embodiment of the present invention in the same field of view as FIG. 23.
  • FIG. 12 is a plan view schematically showing a configuration of a silicon carbide semiconductor device in a sixth embodiment of the present invention.
  • FIG. 27 is a partial cross-sectional view taken along line XXVII-XXVII in FIG. 26. It is a top view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 7 of this invention.
  • FIG. 24 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a fifth embodiment of the present invention in the same field of view as FIG. 23.
  • FIG. 12 is a plan view schematically showing a configuration of a silicon carbide semiconductor
  • FIG. 29 is an enlarged view of a broken line part XXIX in FIG. 28.
  • FIG. 30 is a partial cross-sectional view taken along line XXX-XXX in FIG. 29.
  • FIG. 30 is a partial cross-sectional view taken along line XXXI-XXXI in FIG. 29. It is a fragmentary sectional view which shows schematically the structure of the silicon carbide semiconductor device in Embodiment 8 of this invention.
  • MOSFET 101 silicon carbide semiconductor device
  • the MOSFET 101 includes a semiconductor substrate 20, a drain electrode 13, a drift layer 21, a plurality of first well regions 41, a source region 80, a second well region 42, a gate insulating film 30, and a field insulating film 31.
  • the semiconductor substrate 20 has a lower surface (first surface) and an upper surface (second surface opposite to the first surface).
  • Semiconductor substrate 20 is made of silicon carbide.
  • the semiconductor substrate 20 has an n type (first conductivity type).
  • the semiconductor substrate 20 has a higher impurity concentration than the impurity concentration of the drift layer 21.
  • the drain electrode 13 is provided on the lower surface of the semiconductor substrate 20.
  • the drain electrode 13 includes a back surface ohmic electrode 13 m that contacts the lower surface of the semiconductor substrate 20.
  • the drain electrode 13 is ohmically connected to the lower surface of the semiconductor substrate 20.
  • the drift layer 21 is provided on the upper surface of the semiconductor substrate 20.
  • the drift layer 21 has an n-type.
  • Drift layer 21 is made of silicon carbide.
  • the first well region 41 is selectively provided on the surface of the drift layer 21.
  • the first well region 41 has a p-type (a second conductivity type different from the first conductivity type).
  • First well region 41 is made of silicon carbide.
  • the source region 80 is selectively provided on each surface of the first well region 41.
  • the source region 80 is separated from the drift layer 21 by the first well region 41.
  • Source region 80 has n-type.
  • Source region 80 is made of silicon carbide.
  • a portion sandwiched between the source region 80 and the drift layer 21 can function as a channel region.
  • the second well region 42 is provided on the drift layer 21. Specifically, the second well region 42 is provided in a region different from the first well region 41 on the surface layer of the drift layer 21. The second well region 42 has an end adjacent to the first well region 41 through the drift layer 21. Therefore, the second well region 42 is disposed at a distance from the first well region 41.
  • the second well region 42 has a p-type.
  • Second well region 42 is made of silicon carbide.
  • the second well region 42 includes a well body region 42L (first portion) and a well contact region 42H (second portion).
  • the well contact region 42H has an impurity concentration higher than that of the well body region 42L.
  • the gate insulating film 30 is provided on the first well region 41 and its periphery, and on the end portion of the second well region 42.
  • the gate insulating film 30 may have a portion located on the drift layer 21 between the first well region 41 and the second well region 42.
  • the gate insulating film 30 may have a portion located on the source region 80.
  • the field insulating film 31 is provided on a part of the second well region 42.
  • the field insulating film 31 is disposed on the second well region 42 on the side opposite to the first well region 41 side (left side in FIG. 3).
  • the field insulating film 31 is provided on the end portion (the right end portion in FIGS. 2 and 3) of the second well region 42 that is adjacent to the first well region 41 via the drift layer 21. It is provided on the other end, particularly on the outer peripheral end (the left end in FIG. 3).
  • the field insulating film 31 is thicker than the gate insulating film 30.
  • the gate electrode 50 has a portion on the gate insulating film 30 and a portion on the field insulating film 31.
  • the gate electrode 50 has a portion disposed on the channel region via the gate insulating film 30.
  • the interlayer insulating film 32 has a source contact hole HS on the source region 80 and the well contact region 46, and a well contact hole HW1 (first well contact hole) on the second well region 42.
  • the source contact hole HS is disposed in the opening of the gate insulating film 30.
  • the well contact hole HW1 further reaches the second well region 42 by penetrating the field insulating film 31 and the gate insulating film 30.
  • the source electrode 10 is connected to the well contact region 42H of the second well region 42 through the well contact hole HW1.
  • the interlayer insulating film 32 has a gate contact hole HG disposed on the field insulating film 31 with the gate electrode 50 interposed therebetween.
  • Interlayer insulating film 32 is made of an oxide, for example.
  • the gate pad 11 is connected to the gate electrode 50 through the gate contact hole HG of the interlayer insulating film 32.
  • the gate pad 11 is typically disposed on one side (the upper side in FIG. 1) of the source electrode 10 in the planar layout.
  • the interface between the gate electrode 50 and the gate pad 11 is silicided in the gate contact hole HG of the interlayer insulating film 32.
  • a gate wiring portion 11w extending from the gate pad 11 may be provided.
  • the gate wiring portion 11 w is connected to the gate electrode 50 through the gate contact hole HG of the interlayer insulating film 32.
  • the gate wiring portion 11w may surround the source electrode 10 in the planar layout (FIG. 1).
  • the gate pad 11 and the gate wiring portion 11w are electrically connected to the gate electrode 50 of the unit cell, thereby applying a gate voltage supplied from an external control circuit to the gate electrode 50.
  • the gate contact hole HG of the interlayer insulating film 32 is disposed on the field insulating film 31. Therefore, the gate pad 11 or the gate wiring portion 11 w and the gate electrode 50 are connected on the field insulating film 31. This is because the position of the gate contact hole HG, that is, the position of the contact between the gate electrode 50 and the gate pad 11 or the gate wiring portion 11 w is disposed on the field insulating film 31, so Alternatively, when the material of the gate wiring portion 11w, that is, the dissimilar material, reacts between the portion where this reaction occurs and the silicon carbide region (specifically, the second well region 42 in FIGS. 2 and 3), It is blocked by the field insulating film 31.
  • field insulating film 31 is thicker than gate insulating film 30, the above reaction is effectively prevented from reaching the silicon carbide region. Thereby, generation
  • the material of the gate electrode 50 is polycrystalline silicon and the material of the gate pad 11 and the gate wiring portion 11w is aluminum
  • a silicidation reaction of aluminum occurs at a contact portion of different materials.
  • the relatively thick field insulating film 31 instead of the relatively thin gate insulating film 30 exists in the lower layer of the reaction site, so that the aluminum silicide and carbonized carbon generated by the reaction exist. Contact with the silicon region is prevented. Therefore, it is possible to reduce the probability of occurrence of a gate leak defect due to this contact.
  • the source electrode 10 is connected to the source region 80 and the well contact region 46 through the source contact hole HS.
  • the source electrode 10 is connected to the second well region 42 through the well contact hole HW1.
  • the source electrode 10 is typically disposed at the center of the planar layout of the MOSFET 101 as shown in FIG.
  • the source electrode 10 includes an ohmic electrode 10m.
  • the ohmic electrode 10m is in contact with the source region 80 and the well contact region 46 in the source contact hole HS, and is in contact with the second well region 42 in the well contact hole HW1.
  • the well contact region 46 is provided on the first well region 41. Specifically, the well contact region 46 is provided in a portion surrounded by the source region 80 in the surface layer of the first well region 41. The well contact region 46 connects between the source electrode 10 and the first well region 41.
  • Well contact region 46 has a p-type. The well contact region 46 has a higher impurity concentration than the impurity concentration of the first well region 41.
  • Well contact region 46 is made of silicon carbide.
  • a JTE (Junction Termination Extension) region 43 may be provided on the drift layer 21 in contact with the outer peripheral end of the second well region 42.
  • the JTE region 43 is p-type and has a lower impurity concentration than the impurity concentration of the second well region 42.
  • the field stopper region 81 may be provided on the drift layer 21 on the outer peripheral side of the second well region 42 and spaced from the second well region 42. Field stopper region 81 has an n-type and has an impurity concentration higher than that of drift layer 21.
  • the insulator layer 90 is provided on the second well region 42.
  • the insulator layer 90 is thinner than the field insulating film 31.
  • the insulator layer 90 is a silicon oxide layer having a thickness of 10 nm to 0.2 ⁇ m.
  • the insulator layer 90 and the gate insulating film 30 are preferably made of the same material and have the same thickness. Note that “the same thickness” may mean a thickness within a range of process variation, in other words, a thickness within about ⁇ 10% from one value.
  • the field insulating film 31 is not provided at the place where the insulator layer 90 is disposed.
  • the conductor layer 99 has a portion disposed on the second well region 42 through only the insulator layer 90.
  • the conductor layer 99 may have a portion disposed on the field insulating film 31 in addition to the above portion.
  • the conductor layer 99 is electrically insulated from the gate electrode 50. Therefore, even if the insulator layer 90 is broken down, a short circuit between the gate and the source does not occur.
  • conductor layer 99 is in an electrically floating state.
  • the conductor layer 99 has a sheet resistance lower than that of the second well region 42.
  • the conductor layer 99 extends continuously on the insulator layer 90.
  • the conductor layer 99 is disposed outside a region sandwiched between the gate pad 11 and the second well region 42.
  • the conductor layer 99 is disposed in a region (see FIG. 2) disposed in a region sandwiched between the gate pad 11 and the second well region 42 and disposed outside the region. Part (see FIG. 3).
  • the material of the conductor layer 99 is preferably a material that can easily obtain high electrical conductivity, and therefore, is preferably a material that is not silicon carbide.
  • the material of the conductor layer 99 the same material as that of the gate electrode 50 can be used. In that case, the manufacturing process can be further simplified while ensuring high conductivity.
  • a silicon carbide semiconductor substrate 20 is prepared.
  • the polytype of silicon carbide and the plane orientation of the semiconductor substrate 20 can be arbitrarily selected according to the characteristics required for the MOSFET 101.
  • the drift layer 21 is formed on the upper surface of the semiconductor substrate 20 by epitaxial growth.
  • epitaxial growth for example, a chemical vapor deposition (CVD) method is used.
  • the impurity concentration of the drift layer 21 is, for example, about 1 ⁇ 10 13 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of the drift layer 21 is, for example, about 4 ⁇ m or more and 200 ⁇ m or less.
  • the semiconductor substrate 20 may not be positively heated, or may be heated to about 200 ° C. or higher and 800 ° C. or lower.
  • ions used for ion implantation Al (aluminum) or B (boron) is preferable for imparting p-type, and N (nitrogen) or P (phosphorus) is suitable for imparting n-type. It is.
  • the depths of the first well region 41 and the second well region 42 need to be set so as not to be deeper than the bottom surface of the drift layer 21, and are set within a range of, for example, about 0.3 ⁇ m to 2.0 ⁇ m. Is done.
  • the p-type impurity concentration (acceptor concentration) of the first well region 41 and the second well region 42 exceeds the n-type impurity concentration (donor concentration) of the drift layer 21 and is 1 ⁇ 10 15 cm ⁇ . It is set to 3 or more 1 ⁇ 10 19 cm -3 in the range of lower than about.
  • the p-type impurity concentration may be lower than the n-type impurity concentration in order to increase conductivity.
  • the depth of the source region 80 needs to be set so that the bottom surface thereof does not become deeper than the bottom surface of the first well region 41. Further, the n-type impurity concentration of the source region 80 exceeds the p-type impurity concentration of the first well region 41 and is in the range of about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3. Is set.
  • the field stopper region 81 can be formed under the same conditions as the source region 80.
  • each of the well contact region 46 and the well contact region 42H is provided so that the first well region 41 and the second well region 42 are in good electrical contact with the source electrode 10. Therefore, the impurity concentrations of the well contact region 46 and the well contact region 42H are preferably set higher than the impurity concentrations of the first well region 41 and the second well region 42. In order to greatly reduce the electrical resistance using a high impurity concentration, it is desirable to heat the semiconductor substrate 20 to 150 ° C. or higher during ion implantation.
  • the temperature is about 1500 ° C. or more and 2200 ° C. or less and the time is about 0.5 to 60 minutes.
  • a heat treatment is performed. Thereby, the ion-implanted impurity is electrically activated.
  • This heat treatment may be performed with the drift layer 21 formed on the upper surface of the semiconductor substrate 20 and the back surface of the semiconductor substrate 20 covered with a carbon film. Thereby, it is possible to prevent the occurrence of surface roughness of the silicon carbide due to residual moisture or residual oxygen in the apparatus during the heat treatment.
  • a thermal oxide film is formed by sacrificing the surface of the drift layer 21 implanted with ions.
  • the thermal oxide film By removing the thermal oxide film with hydrofluoric acid, the surface-modified region of the drift layer 21 into which ions have been implanted is removed. This exposes a clean surface.
  • an oxide film such as a silicon dioxide film is deposited as field insulating film 31 by a CVD method or the like.
  • the thickness of the oxide film is, for example, about 0.5 ⁇ m to 2.0 ⁇ m.
  • the deposited oxide film is patterned using etching. Specifically, the deposited oxide film is removed on the place to be the MOSFET cell region and on a part of the second well region 42.
  • gate insulating film 30 is formed by, eg, thermal oxidation or deposition.
  • Thermal oxidation is performed in an oxidizing gas atmosphere such as a wet atmosphere, an oxygen (O 2 ) atmosphere, or a nitrogen oxide (NO or N 2 O) atmosphere.
  • the deposition method may be performed using a high dielectric constant material (so-called “high-k material”).
  • the insulator layer 90 may be formed at the same time.
  • the film thicknesses of both are usually within ⁇ 10% from one value. Both materials are the same.
  • the insulator layer 90 is formed by selectively etching a region to be the insulator layer 90 after forming an insulating film including a region to be the field insulating film 31 and a region to be the insulator layer 90. You may form by reducing the film thickness of this area
  • a gate electrode 50 is formed at a predetermined location on the gate insulating film 30 and the field insulating film 31.
  • film formation by a CVD method and patterning using a photolithography technique are performed.
  • a polycrystalline silicon material is used. It is desirable that the polycrystalline silicon used has a low resistance due to the inclusion of P atoms or B atoms.
  • the sheet resistance of the gate electrode 50 is preferably about 10 ⁇ / ⁇ for n-type polycrystalline silicon and about 30 ⁇ / ⁇ for p-type polycrystalline silicon.
  • Impurities such as P or B may be introduced during the deposition of the polycrystalline silicon, or may be introduced after the deposition by an ion implantation method or the like.
  • the gate electrode 50 may be a multi-region film made of polycrystalline silicon and metal, a multi-region film made of polycrystalline silicon and metal silicide, or a metal film.
  • the outermost end surface of the gate electrode 50 is preferably disposed on the field insulating film 31 instead of on the gate insulating film 30. Thereby, quality deterioration due to the gate insulating film 30 being etched in the vicinity of the outermost end surface of the gate electrode 50 by over-etching in the dry etching process for patterning the gate electrode 50 can be prevented.
  • the conductor layer 99 may be formed at the same time.
  • the film thicknesses of both are usually within ⁇ 10% from one value. Both materials are the same.
  • the conductor layer 99 has a function of lowering the effective sheet resistance of the second well region 42 by causing a displacement current flowing through the insulator layer 90 to flow. For this reason, it is desirable that the sheet resistance of the conductor layer 99 is lower than the sheet resistance of the second well region 42.
  • Doped polycrystalline silicon used for the gate electrode 50 is suitable as a material for the conductor layer 99 because it has a low resistance.
  • insulating film 30 it is desirable not to use a photolithography process between the manufacturing process of the gate insulating film 30 and the film forming process of the gate electrode 50. This is to prevent deterioration of the insulating properties of the gate insulating film 30 due to adhesion or mixing of impurities such as carbon, which is a constituent material of the photoresist, into the gate insulating film 30 that requires high reliability. is there. Therefore, when the gate electrode 50 and the conductor layer 99 are formed at the same time, an insulating film (insulator layer) formed in the manufacturing process of the gate insulating film 30 exists below the conductor layer 99.
  • interlayer insulating film 32 made of, for example, a silicon dioxide film is formed on gate electrode 50 and the like by a deposition method such as a CVD method. Subsequently, the source contact hole HS and the well contact hole HW1 are formed by using a photolithography technique and a dry etching technique.
  • a metal film containing Ni as a main component is formed by sputtering or the like. Subsequently, a heat treatment at about 600 ° C. or higher and about 1100 ° C. or lower is performed. As a result, the metal film containing Ni as a main component and the silicon carbide region react to form silicide between them. Next, the metal film remaining on the interlayer insulating film 32 without being silicided is removed by wet etching.
  • the etchant for example, any one of sulfuric acid, nitric acid and hydrochloric acid, or a mixed solution of these and hydrogen peroxide water can be used.
  • a silicide region as the ohmic electrode 10m is formed in the source contact hole HS and the well contact hole HW1.
  • a back ohmic electrode 13m is formed on the back surface of the semiconductor substrate 20 by a substantially similar method.
  • the source electrode 10, the gate pad 11, and the gate wiring portion 11w are formed on the semiconductor substrate 20 that has been processed so far.
  • a wiring metal such as Al is deposited by sputtering or vapor deposition, patterning into a predetermined shape is performed using a photolithography technique.
  • the gate wiring portion 11w may be omitted.
  • a metal film is formed on the back ohmic electrode 13 m on the back surface of the semiconductor substrate 20. Thereby, the drain electrode 13 is formed.
  • MOSFET 101 is completed.
  • Capacitor structure with insulator layer 90 and conductor layer 99 By providing the insulator layer 90 and the conductor layer 99 on the second well region 42, a capacitor structure is formed on the second well region 42.
  • the capacitor behaves like a resistor against alternating current. This is called capacitive reactance and is represented by Xc.
  • the capacitive reactance Xc becomes smaller as the AC frequency f is higher and the capacitance C is larger, and as a result, the AC current is more likely to flow. Therefore, in the present embodiment, if the AC frequency f as the switching frequency is the same, the displacement current is more likely to pass between the second well region 42 and the conductor layer 99 as the capacitance C is larger. .
  • the thickness d is reduced by using the thin insulator layer 90, a dielectric having a high relative dielectric constant ⁇ r is used as the material of the insulator layer 90, or It is effective to increase the area S by widely opposing the second well region 42 and the conductor layer 99 with the insulator layer 90 interposed therebetween.
  • the thickness of the insulator layer 90 is desirably sufficiently small from the above viewpoint. Specifically, the thickness of the insulator layer 90 is smaller than the thickness of the field insulating film 31, preferably about the thickness of the gate insulating film 30, and is set within a range of about 10 nm to 0.2 ⁇ m, for example.
  • the dielectric layer 90 has a high relative dielectric constant, and so a so-called high-k material may be used.
  • the high-k material include metal oxides HfO 2 , ZrO 2 , and silicates thereof (HfSi X O y , ZrSi X O y ), and Al 2 O 3 and composite oxides (Hf 1-X). Al X O y, Zr 1- X Al X O y) is.
  • the conductor layer 99 has a function of lowering the effective sheet resistance of the second well region 42 by flowing a displacement current flowing through the insulator layer 90. For this reason, it is desirable that the sheet resistance of the conductor layer 99 is lower than the sheet resistance of the second well region 42.
  • the voltage of the drain electrode 13 rapidly increases, from about 0 V to several hundreds. Change to V. Then, the displacement current flows in both the p-type and n-type regions via the parasitic capacitance between the p-type first well region 41 or the second well region 42 and the n-type drift layer 21.
  • a displacement current flows from the first well region 41, the second well region 42, and the like toward the source electrode 10 through the ohmic electrode 10m.
  • a displacement current flows from the drift layer 21 to the drain electrode 13 through the semiconductor substrate 20 and the back surface ohmic electrode 13m.
  • the area of the second well region 42 is very large compared to the area of the first well region 41. Therefore, the resistance value of the displacement current path in the second well region 42 is very large as compared with the resistance value of the displacement current path in the first well region 41.
  • the magnitude of the displacement current flowing through the second well region 42 is larger than the magnitude of the displacement current flowing through the first well region 41.
  • the displacement current that has flowed into the second well region 42 during switching flows to the source electrode 10 via the well contact region 42H of the second well region 42 and the ohmic electrode 10m in the well contact hole HW1.
  • a potential drop of a magnitude that cannot be ignored occurs in the second well region 42.
  • the portion of the second well region 42 that has a large horizontal distance from the portion that is electrically connected to the source electrode 10 via the well contact hole HW1 (the portion immediately below the well contact hole HW1) It has a relatively large potential difference with respect to the source potential. This potential difference increases as the fluctuation dV / dt of the drain voltage V with respect to time t increases.
  • the gate electrode 50 and the gate pad 11 having the gate potential are provided on the second well region 42 where a relatively large voltage can be generated via the gate insulating film 30, the field insulating film 31, and the interlayer insulating film 32. It has been. For this reason, immediately after the MOSFET cell is switched from the on state to the off state, between the gate electrode 50 or the gate pad 11 having a voltage value close to 0 V and the second well region 42 where a high voltage is generated. A large voltage is applied to the gate insulating film 30, the field insulating film 31, or the interlayer insulating film 32. If dielectric breakdown due to this occurs, the gate and the source are short-circuited.
  • the capacitor structure described above can flow a displacement current that is an alternating current.
  • the second well region 42 and the conductor layer 99 are connected to each other by the capacitive reactance represented by the above-described equation (1).
  • the sheet resistance of the conductor layer 99 is lower than that of the second well region 42, much of the displacement current flows from the second well region 42 into the conductor layer 99 via the capacitive reactance, and the conductor layer 99 is conducted in the planar direction, and flows out to the second well region 42 again through the capacitive reactance. Since the displacement current mainly passes through such a conduction path, the effective sheet resistance of the second well region 42 against the displacement current that is an alternating current is reduced.
  • the insulator layer 90 and the conductor layer 99 are provided on the second well region 42.
  • a capacitor having a capacitor structure is provided on the second well region 42.
  • This capacity can have a large value per unit area because the insulator layer 90 is thinner than the field insulating film 31.
  • the displacement current flowing along the second well region 42 at the time of high-speed switching of the MOSFET 101 is sufficiently branched to the conductor layer 99 through the capacitance. Therefore, the effective sheet resistance in the region where the displacement current flows along the second well region 42 is reduced. Therefore, the magnitude of the potential drop along the second well region 42 is suppressed. Therefore, an increase in voltage between the second well region 42 and the region having the gate potential, which is caused by this potential drop, is suppressed. Therefore, dielectric breakdown between these regions is prevented. From the above, it is possible to prevent element destruction during switching.
  • the second well region 42 includes a well contact region 42H having an impurity concentration higher than that of the well body region 42L. Thereby, the electrical contact between the second well region 42 and the source electrode 10 can be improved.
  • the conductor layer 99 has a sheet resistance lower than the sheet resistance of the second well region 42. Thereby, the effective sheet resistance of the second well region 42 can be further reduced.
  • the insulator layer 90 is a silicon oxide layer having a thickness of 10 nm to 0.2 ⁇ m.
  • the capacitance between the second well region 42 and the conductor layer 99 can be increased. Therefore, the displacement current along the second well region 42 is easily branched to the conductor layer 99.
  • the insulator layer 90 and the gate insulating film 30 are made of the same material and have the same thickness. Thereby, the insulator layer 90 can be formed simultaneously with the gate insulating film 30. Therefore, the manufacturing process is simplified.
  • the gate contact hole HG of the interlayer insulating film 32 is disposed on the field insulating film 31 via the gate electrode 50. This prevents the gate electrode 50 and the second well region 42 from being unintentionally short-circuited at the position of the gate contact hole HG. In particular, the silicidation reaction at the interface between the gate electrode 50 and the gate pad 11 tends to cause the short circuit.
  • At least a part of the conductor layer 99 is disposed outside a region sandwiched between the gate pad 11 and the second well region 42.
  • the magnitude of the potential drop along the second well region 42 is suppressed, thereby preventing dielectric breakdown.
  • FIGS. 12 and 13 are partial cross-sectional view schematically showing the configuration of MOSFET 102 (silicon carbide semiconductor device) in the second embodiment in the same field of view as in FIGS. 2 and 3.
  • field insulating film 31 includes a portion sandwiched between insulator layers 90 on second well region 42.
  • the field insulating film 31 includes a plurality of portions sandwiching the insulator layer 90 in a cross-sectional view along the thickness direction.
  • the plurality of portions may have different dimensions on the second well region 42 as shown, or may have equal dimensions.
  • steps similar to those in FIGS. 6 and 7 of the first embodiment are performed.
  • steps similar to those in FIGS. 8 and 9 of the first embodiment are performed.
  • steps similar to those in FIGS. 10 and 11 of the first embodiment are performed. Thereafter, substantially the same process as in the first embodiment is further performed, whereby the MOSFET 102 is completed.
  • the field insulating film 31 includes a portion sandwiched between the insulating layers 90 on the second well region 42. Thereby, the stress applied to the insulator layer 90 from the outside is effectively relieved by the field insulating film 31. Therefore, it is possible to prevent the insulator layer 90 from being broken due to external stress.
  • the gate pad 11 when the gate pad 11 is disposed above the insulator layer 90, in other words, when the insulator layer 90 and the gate pad 11 overlap in a planar layout, the gate A particularly large stress can be applied to the insulator layer 90 during wire bonding to the pad 11.
  • the above range is simply increased in the structure of FIG. 2 of the first embodiment, the area where the insulator layer 90 and the conductor layer 99 can be disposed is reduced.
  • the field insulating film 31 is divided into more portions on the second well region 42.
  • FIG. 20 is a partial cross-sectional view schematically showing the configuration of MOSFET 103 (silicon carbide semiconductor device) in the present embodiment in the same field of view as FIG.
  • MOSFET 103 silicon carbide semiconductor device
  • the conductor layer 99 extends discontinuously on the insulator layer 90.
  • the portions of the conductor layer 99 that are separated by the discontinuous portions may have different dimensions as shown, or may have equal dimensions.
  • the discontinuous portion of the conductor layer 99 is disposed on the field insulating film 31, but the discontinuous portion of the conductor layer 99 may be disposed on the insulator layer 90. In that case, a part of the insulator layer 90 is not covered with the conductor layer 99.
  • the conductor layer 99 extends discontinuously on the insulator layer 90, the area of the conductor layer 99 is suppressed. Therefore, when the gate pad 11 is disposed on the conductor layer 99 via the interlayer insulating film 32, the probability that the conductor layer 99 and the gate pad 11 are short-circuited can be suppressed. Further, even if the gate pad 11 is short-circuited with a part of the conductor layer 99, the gate pad 11 can be prevented from being short-circuited with the whole conductor layer 99. As a result, the probability of a short circuit between the gate and the source can be suppressed.
  • source electrode 10 includes source pad portion 10p having the same configuration as in the first embodiment, A source wiring portion 10w connected to the source pad portion 10p is provided. There may be at least one connection point between the source pad portion 10p and the source wiring portion 10w.
  • the source wiring portion 10w is disposed outside the source pad portion 10p disposed in the center portion in the planar layout (see FIG. 21).
  • the gate wiring portion 11w is provided, the source wiring portion 10w can be disposed outside the gate wiring portion 11w (that is, near the outer edge of the MOSFET 104).
  • the gate wiring portion 11w can be disposed between the source pad portion 10p and the source wiring portion 10w in the planar layout.
  • the source wiring portion 10w is electrically insulated from the gate pad 11 and the gate wiring portion 11w. Accordingly, in FIG. 21, the gate wiring portion 11w is not provided at a location where the source pad portion 10p and the source wiring portion 10w are electrically connected. Note that the gate wiring portion 11w may be omitted as in the first embodiment.
  • the interlayer insulating film 32 has a conductor contact hole HC on the conductor layer 99.
  • the conductor layer 99 is electrically connected to the source wiring portion 10w through the conductor contact hole HC. Thereby, the conductor layer 99 is short-circuited with the source electrode 10. Therefore, in MOSFET 104, conductor layer 99 is not in a floating state.
  • the conductor layer 99 is short-circuited to the source electrode 10 by being electrically connected to the source wiring portion 10w.
  • the displacement current flowing through the conductor layer 99 when the MOSFET 104 is switched can be directly extracted by the source wiring portion 10w. Therefore, the magnitude of the potential drop along the second well region 42 is further suppressed. Therefore, element destruction at the time of switching can be prevented more reliably.
  • FIG. 24 and FIG. 25 are a partial cross-sectional view schematically showing the configuration of MOSFET 105 (silicon carbide semiconductor device) in the present embodiment in the same field of view as FIG. 22 and FIG.
  • the interlayer insulating film 32 has a well contact hole HW2 (second well contact hole) on the second well region.
  • the source wiring portion 10w of the source electrode 10 is connected to the second well region 42 through the well contact hole HW2.
  • the source wiring portion 10w of the source electrode 10 includes an ohmic electrode 10m that is in contact with the second well region 42 in the well contact hole HW2.
  • an insulator layer 90 is disposed between the well contact hole HW1 and the well contact hole HW2.
  • the displacement current is distributed to the well contact hole HW1 and the well contact hole HW2.
  • the magnitude of the potential drop along the second well region 42 is further suppressed. Therefore, element destruction at the time of switching can be prevented more reliably.
  • FIG. 26 shows a planar layout of MOSFET 106 (silicon carbide semiconductor device) in the present embodiment.
  • MOSFET 106 silicon carbide semiconductor device
  • a sand pattern is attached to the portion made of the conductor.
  • 27 is a partial sectional view taken along line XXVII-XXVII in FIG.
  • MOSFET 106 includes temperature sense diode 59 (built-in temperature sensor), sense pad 19, and interlayer insulating film 33.
  • the “built-in temperature sensor” is a temperature sensor formed directly or indirectly on the semiconductor substrate 20, and is typically disposed between the semiconductor substrate 20 and the interlayer insulating film 32. .
  • temperature sensing diode 59 is arranged between interlayer insulating film 32 and interlayer insulating film 33 in the thickness direction (vertical direction in FIG. 27).
  • the interlayer insulating film 33 is provided on the conductor layer 99, the gate electrode 50, and the field insulating film 31 not covered with them.
  • the temperature sense diode 59 has a p-type sense anode region 55 and an n-type sense cathode region 56.
  • the sense anode region 55 and the sense cathode region 56 are adjacent to each other in the in-plane direction (lateral direction in FIG. 27) on the interlayer insulating film 33, and form a pn junction by being in direct contact with each other. In other words, a pn diode is configured.
  • the temperature sensing diode 59 is disposed on the second well region 42 via the insulator layer 90, the conductor layer 99, and the interlayer insulating film 33.
  • the temperature sensing diode 59 is included in the second well region 42.
  • the temperature sensing diode 59 is disposed on the conductor layer 99 with the interlayer insulating film 33 interposed therebetween.
  • the temperature sensing diode 59 is at least partially contained in the conductor layer 99, preferably mostly contained, more preferably. The whole is included.
  • the sense pad 19 has a sense anode pad 15 and a sense cathode pad 16. Each of sense anode pad 15 and sense cathode pad 16 is connected to sense anode region 55 and sense cathode region 56 through sense contact hole HT formed in interlayer insulating film 32.
  • the sense pad 19, that is, the sense anode pad 15 and the sense cathode pad 16 includes the insulator layer 90, the conductor layer 99, the interlayer insulating film 33, the temperature sense diode 59, and the interlayer insulating film 32. It is arranged on the second well region 42 through the included structure.
  • the sense pad 19 is included in the second well region 42.
  • the sense pad 19, that is, the sense anode pad 15 and the sense cathode pad 16 are electrically connected to each other through a structure including the interlayer insulating film 33, the temperature sense diode 59, and the interlayer insulating film 32.
  • the sense pad 19 is at least partially included in the conductor layer 99, preferably most of it is included, and more preferably the whole is included. Is included.
  • the sense anode pad 15 and the sense cathode pad 16 are for connecting the temperature sense diode 59 and an external circuit (not shown) that is a control circuit of the temperature sense diode 59 to each other. It is necessary to apply different potentials to the sense anode pad 15 and the sense cathode pad 16. Therefore, the sense anode pad 15 and the sense cathode pad 16 are arranged apart from each other. In addition, at least one of the sense anode pad 15 and the sense cathode pad 16 is electrically insulated from the source electrode 10 so that the two are not short-circuited.
  • both the sense anode pad 15 and the sense cathode pad 16 are electrically insulated from the source electrode 10.
  • the control circuit for the temperature sense diode 59 and the drive circuit for the gate electrode 50 need to be electrically separated. Therefore, the sense anode pad 15 and the sense cathode pad 16 are electrically insulated from the gate pad 11. . Therefore, the sense anode pad 15 and the sense cathode pad 16 are separated from the gate pad 11.
  • the sense anode pad 15 and the sense cathode pad 16 are arranged in a region where the source electrode 10 is removed in the outer edge of the source electrode 10. In the planar layout, the sense anode pad 15 and the sense cathode pad 16 are separated from each other, and are separated from the gate pad 11 and the source electrode 10.
  • the method for manufacturing MOSFET 106 only needs to add a step of forming temperature sensing diode 59, sense pad 19, and interlayer insulating film 33 to the manufacturing method of MOSFET 101 (Embodiment 1).
  • the interlayer insulating film 33 is formed as a silicon dioxide film by a deposition method such as a CVD method.
  • the temperature sense diode 59 can be formed by patterning a semiconductor film formed by a deposition method.
  • a CVD method may be used. For example, polycrystalline silicon is deposited.
  • Addition of an acceptor and a donor so that each of the sense anode region 55 and the sense cathode region 56 constituting the temperature sense diode 59 has p-type and n-type is performed at the time of deposition by selecting a source gas used in CVD. It may be performed by ion implantation after material deposition.
  • the sense anode pad 15 and the sense cathode pad 16 may be formed by patterning a metal film formed by a deposition method. As the deposition method, a sputtering method or an evaporation method may be used, for example, aluminum is deposited. Patterning is performed by photolithography and etching.
  • the sense anode pad 15 and the sense cathode pad 16 may be formed simultaneously with the source electrode 10 and the gate pad 11.
  • the portion facing the sense pad 19 and the temperature sense diode 59 via the insulator layer 90 is not the drift layer 21 but the second well region 42.
  • the sense anode pad 15 and the sense cathode pad 16 require a certain large area in order to facilitate electrical connection with the outside.
  • a large area of, for example, about 100 um square is required.
  • the second well region 42 including these in the planar layout also requires a large area. In the switching of the MOSFET 106, a large displacement current flows from the wide second well region 42.
  • the second well region 42 having a large sheet resistance is large.
  • a large voltage is generated in the second well region 42. Accordingly, a large voltage is applied to the interlayer insulating film 33 or the stacked body of the interlayer insulating film 32 and the interlayer insulating film 33 between the configuration having the sense pad 19 and the temperature sense diode 59 and the second well region 42. Applied. As a result, the temperature sensing diode 59 can be destroyed.
  • FIG. 28 shows a planar layout of MOSFET 107 (silicon carbide semiconductor device) in the present embodiment.
  • MOSFET 107 silicon carbide semiconductor device
  • FIG. 29 is an enlarged view of a broken line part XXIX in FIG.
  • FIG. 30 and FIG. 31 is a partial cross-sectional view taken along line XXX-XXX and line XXXI-XXXI in FIG.
  • the MOSFET 107 of this embodiment has at least one built-in gate resistor 51 (two built-in gate resistors 51 in FIG. 29) and the monitor pad 17.
  • the “built-in gate resistance” is a gate resistance formed directly or indirectly on the semiconductor substrate 20 and is typically disposed between the semiconductor substrate 20 and the interlayer insulating film 32.
  • the “gate resistance” is an electrical resistance provided between the gate electrode and its drive circuit in order to optimize the switching speed of the switching element (here, the MOSFET 107) having the gate electrode.
  • the overall size of the MOSFET provided with the gate resistance can be suppressed, and the manufacturing cost can be reduced. Since the built-in gate resistance is formed in the switching element during the manufacturing process of the semiconductor switching element, the gate resistance value varies due to variations in the semiconductor manufacturing process. For this reason, it is necessary to inspect the resistance value after forming the gate resistance.
  • the monitor pad 17 is an electrode pad used for this inspection.
  • the built-in gate resistor 51 is disposed between the field insulating film 31 and the interlayer insulating film 32 in the thickness direction (vertical direction in FIG. 30). Further, in the present embodiment, unlike the first embodiment, the gate pad 11 and the gate wiring portion 11w are separated from each other, and the built-in gate resistor 51 is electrically connected with a desired resistance value therebetween. ing. Specifically, in the planar layout, the gate pad 11 and the gate wiring portion 11w are separated from each other, and a built-in gate resistor 51 is provided so as to connect them.
  • the electrical connection between the gate wiring portion 11 w and the built-in gate resistor 51 is obtained by connecting the gate wiring portion 11 w to the monitor pad 17 connected to the built-in gate resistor 51.
  • the gate wiring portion 11w and the monitor pad 17 are connected in a planar layout and are in contact with each other.
  • the gate wiring part 11w and the monitor pad 17 may be integrally formed.
  • the gate pad 11 is connected to one end (the right end in FIG. 30) of the built-in gate resistor 51 through the gate resistance contact hole HRa formed in the interlayer insulating film 32.
  • the monitor pad 17 is connected to the other end (the left end in FIG. 30) of the built-in gate resistor 51 through the gate resistance contact hole HRb formed in the interlayer insulating film 32.
  • the monitor pad 17 has dimensions larger than the dimension D0 in the width direction (vertical direction in FIG. 29) of the gate wiring portion 11w in two different directions.
  • the monitor pad 17 has a dimension D1 and a dimension D2 larger than the dimension D0.
  • the dimension D1 is a dimension in a direction parallel to the direction of the dimension D0
  • the dimension D2 is a dimension in a direction orthogonal to the direction of the dimension D0.
  • the dimension D1 and the dimension D2 are preferably 50 ⁇ m or more.
  • the built-in gate resistor 51 is disposed on the second well region 42 via the field insulating film 31.
  • the monitor pad 17 is formed on the second well region 42 through a configuration including the field insulating film 31, the built-in gate resistor 51, the insulating layer 90, the conductive layer 99, and the interlayer insulating film 32. Has been placed.
  • the built-in gate resistor 51 and the monitor pad 17 are included in the second well region 42.
  • the monitor pad 17 is disposed on the conductor layer 99 via the interlayer insulating film 32.
  • a part, preferably most, of the sense pad 19 is included in the conductor layer 99.
  • the entire monitor pad 17 may be disposed on the conductor layer 99 with the interlayer insulating film 32 interposed therebetween.
  • the entire monitor pad 17 may be included in the conductor layer 99.
  • a source wiring portion 10w passing between the gate pad 11 and the monitor pad 17 is provided.
  • One end and the other end of the source wiring portion 10 w are connected to different positions of the source electrode 10.
  • FIG. 31 Another cross-sectional view (FIG. 31) spans the gate pad 11, the source wiring portion 10w, and the monitor pad 17 as shown in FIG. 29, and the built-in gate resistor 51 is arranged. There are no areas.
  • the source wiring portion 10w is in contact with the second well region 42 through the well contact hole HW2.
  • the voltage generated in the second well region 42 in the vicinity of the well contact hole HW2 is reduced by the presence of the conductor layer 99 described above.
  • the main difference between the manufacturing method of the MOSFET 107 and the manufacturing method of the MOSFET 101 (Embodiment 1) is that a step of forming the built-in gate resistor 51 is required.
  • the built-in gate resistor 51 may be formed by patterning a film formed by a deposition method. For example, polycrystalline silicon is deposited by CVD. Patterning is performed by photolithography and etching. When the material of the built-in gate resistor 51 and the material of the gate electrode 50 are the same, the deposition process and the patterning process can be performed collectively, thereby reducing the manufacturing cost.
  • the stacked body of the conductor layer 99 and the insulator layer 90 is disposed between the monitor pad 17 and the second well region 42 in a cross-sectional view (FIG. 30).
  • any of the MOSFETs 102 to 106 may be provided with the built-in gate resistor 51 and the monitor pad 17 described in the present embodiment and the configuration related thereto.
  • FIG. 32 is a partial cross sectional view schematically showing a configuration of MOSFET 108 (silicon carbide semiconductor device) in the present embodiment, in the same field of view as FIG. 2 (Embodiment 1).
  • MOSFET 108 silicon carbide semiconductor device
  • the conductor layer 99 is provided under the interlayer insulating film 32 (in other words, below).
  • the insulator layer 90 is not provided, and the conductor layer 99 does not pass through the insulator layer 90 (FIG. 2: embodiment 1), and the second well region. 42 is provided.
  • the conductor layer 99 is in Schottky contact with the second well region 42.
  • the interface between the conductor layer 99 and the second well region 42 forms a Schottky junction.
  • most of the second well region 42 is in Schottky contact with the conductor layer 99.
  • the entire portion of the second well region 42 not covered with the field insulating film 31 may be in Schottky contact with the conductor layer 99.
  • the process of forming the conductor layer 99 in the method for manufacturing the MOSFET 108 will be described below.
  • the field insulating film 31 and the gate insulating film 30 on the region where the Schottky contact described above is to be formed are removed by wet etching.
  • a film to be the conductor layer 99 is deposited by sputtering or the like, and this film is patterned by photolithography and etching. Thereby, the conductor layer 99 having the Schottky contact described above is formed.
  • the material of the conductor layer 99 may be selected so that a Schottky contact can be obtained. For example, Ti, Mo, W, Ni, Ta, or polycrystalline silicon is used. Since steps other than those described above in the method for manufacturing MOSFET 108 are substantially the same as those in the first embodiment, description thereof will be omitted.
  • a Schottky junction a rectifying property in which a current flows when a forward voltage is applied is widely used. Specifically, the characteristic is used for a Schottky diode. In such applications, it is generally considered that no current flows when a reverse voltage is applied. As an actual phenomenon, when a reverse voltage is applied to the Schottky junction, a depletion layer extends from the Schottky interface to the semiconductor side. As a result, a capacitance determined by the thickness of the depletion layer is formed. Therefore, when a reverse voltage is applied between the semiconductor and the Schottky electrode, a steady forward current cannot flow, but a displacement current can flow through the capacitor. In the present embodiment, by using this displacement current, the current flowing in the second well region 42 (semiconductor) is branched to the conductor layer 99 (Schottky electrode). This will be further described below.
  • the depletion layer formed by applying a reverse voltage to the Schottky junction formed by the conductor layer 99 and the second well region 42 is the insulator layer 90 (see FIG. It plays the role of 2).
  • the second well region 42 is a p-type semiconductor
  • the displacement current that flows from the drift layer 21 into the second well region 42 immediately after the MOSFET 108 is switched from the on state to the off state is formed at the Schottky interface. It flows into the conductor layer 99 through the capacity of the depletion layer.
  • This current flows through the conductor layer 99 having a low sheet resistance along the in-plane direction (lateral direction in FIG. 32), and again flows into the second well region 42 in the vicinity of the well contact hole HW1.
  • the current flowing in the second well region 42 is branched to the conductor layer 99 (Schottky electrode).
  • the conductor layer 99 as a Schottky electrode may be provided in any of the MOSFETs 102 to 107 while omitting the insulator layer 90.
  • the case where the first conductivity type is n-type and the second conductivity type is p-type has been described, but these conductivity types may be reversed. In that case, the names of the electrodes excluding the gate electrode are also reversed.
  • a silicon carbide semiconductor device that is a semiconductor device using silicon carbide, which is one of the wide band gap semiconductor materials, has been described.
  • a wide band gap semiconductor material other than silicon carbide is used.
  • gallium nitride, diamond, or gallium oxide may be used.
  • the present invention can be freely combined with each other, or can be appropriately modified or omitted.
  • HC conductor contact hole HG gate contact hole, HRa, HRb gate resistance contact hole, HS source contact hole, HT sense contact hole, HW1 well contact hole (first well contact hole), HW2 well contact hole (second well contact) Hole), 10 source electrode, 10 m ohmic electrode, 10 p source pad part, 10 w source wiring part, 11 gate pad, 11 w gate wiring part, 13 drain electrode, 13 m back ohmic electrode, 15 sense anode pad, 16 sense cathode pad, 17 Monitor pad, 19 sense pads, 20 semiconductor substrate, 21 drift layer, 30 gate insulating film, 31 field insulating film, 32, 33 interlayer insulating film 41 First well region, 42 Second well region, 42H Well contact region (second portion), 42L Well body region (first portion), 43 JTE region, 46 well contact region, 50 gate electrode, 51 built-in gate resistance, 55 sense anode region, 56 sense cathode region, 59 temperature sense diode (built-in temperature sensor), 80 source region, 81 field stopper region

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  • Electrodes Of Semiconductors (AREA)

Abstract

Des premières régions de puits (41) et une seconde région de puits (42), toutes deux d'un second type de conductivité, sont disposées sur une couche de dérive (21) d'un premier type de conductivité. Une région de source (80) du premier type de conductivité est disposée sur chaque première région de puits (41). Un film d'isolation de champ (31) plus épais qu'un film d'isolation de grille (30) est disposé sur la seconde région de puits (42). Un film isolant intercouche (32) comporte un trou de contact de source (HS) sur chaque région de source (80) et un premier trou de contact de puits (HW1) sur la seconde région de puits (42). Une électrode de source (10) est connectée à chaque région de source (80) à travers chaque trou de contact de source (HS) et à la seconde région de puits (42) à travers le premier trou de contact de puits (HW1) Une couche isolante (90) plus mince que le film d'isolation de champ (31) est disposée sur la seconde région de puits (42). Une couche conductrice (99) a une portion disposée sur la seconde région de puits (42), avec seulement la couche isolante (90) entre celles-ci.
PCT/JP2017/030039 2016-08-25 2017-08-23 Dispositif semi-conducteur en carbure de silicium Ceased WO2018038133A1 (fr)

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JP2020155704A (ja) * 2019-03-22 2020-09-24 三菱電機株式会社 半導体装置
JP2021002620A (ja) * 2019-06-24 2021-01-07 富士電機株式会社 半導体装置
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JP2024510130A (ja) * 2021-03-15 2024-03-06 ウルフスピード インコーポレイテッド センサ素子を備えたワイド・バンドギャップ半導体デバイス
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