WO2018012654A1 - Introduction device for manuf+acturing silicon semiconductor ingot, and doping method - Google Patents
Introduction device for manuf+acturing silicon semiconductor ingot, and doping method Download PDFInfo
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- WO2018012654A1 WO2018012654A1 PCT/KR2016/007677 KR2016007677W WO2018012654A1 WO 2018012654 A1 WO2018012654 A1 WO 2018012654A1 KR 2016007677 W KR2016007677 W KR 2016007677W WO 2018012654 A1 WO2018012654 A1 WO 2018012654A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- the present invention relates to an input device and a doping method for manufacturing a silicon semiconductor ingot, and more particularly, to an input device and a doping method for manufacturing a silicon semiconductor ingot capable of minimizing volatilization of a dopant and greatly shortening a process time.
- Silicon semiconductors are widely used in various industrial fields, and their importance is increasing. Such a silicon semiconductor is doped with an additive material called a dopant, and the electrical properties are determined by the type and amount thereof.
- Fig. 1 a conventional doping process is shown.
- the semiconductor raw material S is melted in the crucible 10, and then a dopant input device in which the dopant d is accommodated is placed on the top of the crucible 10.
- the dopant input device is composed of a seating portion (5) on which the dopant is seated, and a shielding portion (7) for shielding the upper portion of the seating portion (5),
- the play is formed between the side plates.
- As dopants ascenic (As) and the like are generally used, and since they have high volatility, they are easily vaporized. Therefore, the dopant seated on the seating portion 5 is moved through the gap formed between the side plate of the seating portion 5 and the side plate of the shielding portion 7 in the vaporized state, by the air curtain formed around the dopant input device The semiconductor raw material S contained in the crucible 10 is reached and gradually doped.
- Ascenic (As) and the like are generally used, and since they have high volatility, they are easily vaporized. Therefore, the dopant seated on the seating portion 5 is moved through the gap formed between the side plate of the seating portion 5 and the side plate of the shielding portion 7 in the vaporized state, by the air curtain formed around the dopant input device The semiconductor raw material S contained in the crucible 10 is reached and gradually doped.
- the doping efficiency is not only greatly reduced, but also a long process time, there is a problem that the yield is low.
- a large amount of vaporized dopant is adsorbed on the inner surface of the dopant input device, the amount of loss is considerable, and accordingly maintenance is required.
- the present invention has been made to solve the above-mentioned problems of the prior art, and has an object to provide a doping method capable of quickly doping semiconductor raw materials.
- the lower portion is opened, the body portion to form a receiving space therein and the lower portion is provided in the opened lower portion of the body portion, and optionally includes a door portion that can be opened and closed
- a stain resistant coating is formed on at least a portion of the inner surface of the body portion and the inner surface of the door portion exposed to the receiving space.
- the fouling resistant coating may be formed of a Ti coating.
- the door portion may be formed thicker than the body portion.
- the doping method of the present invention for achieving the above object, the lower portion is opened, the body portion to form a receiving space therein, and the lower portion is provided in the opened lower portion of the body portion, the input including a selectively openable door portion Laminating a dopant layer made of a dopant in the receiving space of the device, laminating a cover layer made of a solid semiconductor raw material on the dopant layer, and placing the input device on a molten semiconductor raw material at a predetermined height. And opening the door of the dosing device so that the dopant layer and the cover layer are placed on the molten semiconductor raw material while maintaining the stacked state.
- the step of laminating the dopant layer laminating the dopant layer on the bottom layer It can be done.
- the cover layer may be formed thicker than the bottom layer.
- the solid semiconductor raw material constituting the cover layer may have a second particle size larger than the first particle size of the solid semiconductor raw material constituting the bottom layer.
- the cover layer may be a mixture of a solid semiconductor raw material having a first particle size and a solid semiconductor raw material having a second particle size.
- a solid semiconductor raw material may be disposed at the periphery of the dopant forming the dopant layer.
- the dosing device and the doping method for manufacturing a silicon semiconductor ingot of the present invention have the following effects.
- the dopant is directly injected into the molten semiconductor raw material, there is an advantage that can greatly increase the doping efficiency, as well as significantly reduce the process time.
- FIG. 2 is a view showing the structure of an input device for manufacturing a silicon semiconductor ingot according to a first embodiment of the present invention
- FIG. 3 is a view showing a lamination of a dopant layer and a cover layer in the doping method according to the first embodiment of the present invention
- FIG. 4 is a view showing a state in which a dosing method for manufacturing a silicon semiconductor ingot is placed on a crucible in the doping method according to the first embodiment of the present invention
- FIG. 5 is a view showing a state in which a dopant layer and a cover layer are introduced into a molten semiconductor raw material by opening a door of a dosing device for manufacturing a silicon semiconductor ingot in the doping method according to the first embodiment of the present invention
- FIG. 6 is a view showing a dopant layer doped in a molten semiconductor raw material in the doping method according to the first embodiment of the present invention
- FIG. 7 is a view showing a stacking of a bottom layer, a dopant layer and a cover layer in the doping method according to the second embodiment of the present invention.
- FIG. 8 is a view showing a lamination of a bottom layer, a dopant layer and a cover layer in the doping method according to the third embodiment of the present invention.
- FIG. 9 is a view showing a stacking of a bottom layer, a dopant layer and a cover layer in the doping method according to the fourth embodiment of the present invention.
- FIG. 10 is a view showing a stacking of a bottom layer, a dopant layer and a cover layer in the doping method according to the fifth embodiment of the present invention.
- FIG. 2 is a view showing the structure of an input device 100 for manufacturing a silicon semiconductor ingot according to a first embodiment of the present invention.
- the input device 100 for manufacturing a silicon semiconductor ingot according to the first embodiment of the present invention includes a body portion 102 and a door portion 110.
- the body portion 102 has a lower opening and is a component forming an accommodation space 105 therein.
- the accommodating space 105 may then contain a solid semiconductor raw material including a dopant. This will be described later.
- the door part 110 is provided at an opened lower portion of the body part 102 and is formed to be selectively opened and closed. Therefore, the door 110 may open or shield the lower portion of the receiving space 105 in accordance with the opening and closing. When the door part 110 is opened, the dopant and the solid semiconductor raw material contained in the accommodation space 105 fall.
- the reason for forming the fouling resistant coating 120a on the inner surface of the body portion 102 and the inner surface of the door portion 110 is that the body portion 102 as the dopant contained in the accommodating space 105 is vaporized. This is to prevent adsorption on the inner surface and the inner surface of the door unit 110.
- the material of the pollution-resistant coating (120a), in the present embodiment was to be Ti coating.
- an asnic (As) is used as a dopant, and in the case of Ti coating, the reactivity with the acenic is low, so that the vaporized acenic may be effectively prevented from being adsorbed.
- the door part 110 may be formed thicker than the body part 102. The reason for doing this is to minimize the transfer of heat into the receiving space 105 when the silicon semiconductor ingot manufacturing input device 100 is placed on the crucible in which the semiconductor raw materials are melted. That is, the door part 110 blocks heat transfer to prevent the dopant from easily evaporating.
- FIG. 3 is a view illustrating a dopant layer L 1 and a cover layer L 2 stacked in the doping method according to the first embodiment of the present invention.
- a dopant layer (L 1 ) made of a dopant (d) is deposited in a receiving space of the silicon semiconductor ingot manufacturing device 100, and the solid on the dopant layer (L 1 ).
- the step of laminating a cover layer (L 2 ) made of the semiconductor raw material (s) is performed.
- the dopant layer L 1 includes a dopant d having a predetermined particle size and is provided under the cover layer L 2 .
- the cover layer L 2 includes a solid semiconductor raw material s having a predetermined particle size.
- the dopant (d) is considered to be acenic, and the semiconductor raw material is silicon. That is, the raw material s of the solid semiconductor forming the cover layer L 2 is obtained by solidifying silicon and covering the dopant d.
- the dopant layer (L 1) is further disposed a semiconductor raw material (s) of the solid in the rim portion of the dopant (d) forming the dopant layer (L 1). This is for the dopant d to be completely surrounded by the solid semiconductor raw material s.
- the reason for doing this is to minimize vaporization of the dopant d, and the solid semiconductor raw material s can block both the upper and side portions of the dopant d so as not to be exposed to the outside.
- FIG. 4 is a view showing a state in which the dosing method 100 for manufacturing a silicon semiconductor ingot is placed on the crucible 10 in the doping method according to the first embodiment of the present invention
- FIG. 5 is a first embodiment of the present invention.
- the crucible 10 is accommodated in the molten state the raw material (S) of the semiconductor.
- the molten semiconductor raw material S in this state is non-conductive and may be conductive through the addition of the dopant d.
- the dosing device 100 is placed at a predetermined height on the top of the crucible 10, and then the door part 110 of the dosing device 100. ), The dopant layer L 1 and the cover layer L 2 are introduced into the molten semiconductor raw material S.
- the dopant layer (L 1 ) and the cover layer (L 2 ) fall on the molten semiconductor raw material (S) while maintaining a laminated state, the molten semiconductor raw material (S) has a viscosity and thus The dopant layer L 1 and the cover layer L 2 gradually sink from the surface of the molten semiconductor raw material S as shown in FIG. 6.
- the dopant (d) is melted by high temperature so that the molten semiconductor raw material (S) is doped.
- the solid semiconductor raw material s included in the dopant layer L 1 and the cover layer L 2 is substantially the same material as the semiconductor raw material S melted in the crucible 10 and thus melted by high temperature. And mixed.
- the dopant d is mixed in the molten semiconductor raw material S, the solid semiconductor raw material s included in the dopant layer L 1 and the cover layer L 2 is a dopant d. ), And the dopant (d) is injected into the semiconductor raw material (S) directly melted in a solid state, thereby greatly improving the doping efficiency as compared with the related art.
- FIG. 7 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the dopant doping method according to the second embodiment of the present invention.
- FIG case of the second embodiment of the present invention in Figure 7 the first embodiment and likewise the dopant layer (L 1) and a cover layer that the (L 2) is laminated is equal to one, and the dopant layer (L 1) The difference is that the bottom layer (L 3 ) is further laminated to the bottom of the.
- the bottom layer (L 3 ) includes a solid semiconductor raw material (s), and is provided in the form of surrounding the dopant (d) together with the cover layer (L 2 ).
- the bottom layer (L 3 ) can block the transfer of heat to the dopant (d) can significantly reduce the amount of vaporization of the dopant (d).
- FIG. 8 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the doping method according to the third embodiment of the present invention.
- the bottom layer L 3 , the dopant layer L 1 , and the cover layer L 2 are stacked in the same manner as in the second embodiment.
- the present embodiment is different in that the cover layer (L 2 ) is formed thicker than the bottom layer (L 3 ).
- the thickness of the cover layer (L 2 ) is made thicker, thereby minimizing the possibility that the cover layer (L 2 ) may be dispersed due to the impact falling on the crucible and the dopant (d) may be exposed. have.
- the cover layer (L 2 ) is because the solid semiconductor raw material (s) forms a plurality of layers, because even if slightly dispersed, the layer formed on top can fill the gap.
- FIG. 9 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the doping method according to the fourth embodiment of the present invention.
- the bottom layer L 3 , the dopant layer L 1 , and the cover layer L 2 are stacked as in the second and third embodiments. .
- the solid semiconductor raw material s 1 constituting the cover layer L 2 has a particle size larger than the first particle size of the solid semiconductor raw material s 2 constituting the bottom layer L 3 .
- the difference is that it has two granularities.
- the particle size of the solid semiconductor raw material s 1 constituting the cover layer L 2 is formed to be larger, thereby more effectively preventing the dopant d from being exposed.
- the solid semiconductor raw material s 2 constituting the bottom layer L 3 is formed with a relatively small particle size, and thus may be rapidly melted when it is introduced into the crucible.
- FIG. 10 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the doping method according to the fifth embodiment of the present invention.
- the bottom layer L 3 , the dopant layer L 1 , and the cover layer L 2 are laminated in the same manner as in the second to fourth embodiments. .
- the present embodiment differs in that the cover layer L 2 is mixed with a solid semiconductor raw material s 1 having a first particle size and a solid semiconductor raw material s 2 having a second particle size.
- the cover layer (L 2) is the first size to a second size for having the semiconductor raw material (s 2) of the solid in between the solid semiconductor raw material (s 1) having location, the first granularity
- the eggplant can effectively fill the voids of the solid semiconductor raw material s 1 , thereby more effectively preventing the dopant d from being exposed.
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Abstract
Description
본 발명은 실리콘 반도체 잉곳 제조용 투입장치 및 도핑방법에 관한 것으로서, 보다 상세하게는 도펀트의 휘발량을 최소화하고, 공정 소요시간을 크게 단축시킬 수 있는 실리콘 반도체 잉곳 제조용 투입장치 및 도핑방법에 관한 것이다.The present invention relates to an input device and a doping method for manufacturing a silicon semiconductor ingot, and more particularly, to an input device and a doping method for manufacturing a silicon semiconductor ingot capable of minimizing volatilization of a dopant and greatly shortening a process time.
실리콘 반도체는 다양한 산업 분야에 널리 사용되고 있으며, 그 중요도는 갈수록 증가하고 있다. 이와 같은 실리콘 반도체는 도펀트(Dopant)라 불리는 첨가 물질을 도핑하게 되며, 이때 그 종류와 양에 의해 전기적 특성이 결정된다.Silicon semiconductors are widely used in various industrial fields, and their importance is increasing. Such a silicon semiconductor is doped with an additive material called a dopant, and the electrical properties are determined by the type and amount thereof.
도 1에는, 종래의 도핑 과정이 도시된다.In Fig. 1, a conventional doping process is shown.
도 1에 도시된 바와 같이, 종래의 도핑 과정은 도가니(10) 내에 반도체 원재료(S)를 용융시킨 뒤, 도가니(10)의 상부에 도펀트(d)가 수용된 도펀트 투입장치를 위치시킨다.As shown in FIG. 1, in the conventional doping process, the semiconductor raw material S is melted in the
이때 도펀트 투입장치는, 도펀트가 안착된 안착부(5)와, 안착부(5)의 상부를 차폐하는 차폐부(7)로 이루어지며, 안착부(5)의 측판과 차폐부(7)의 측판 사이에는 유격이 형성된다.At this time, the dopant input device is composed of a seating portion (5) on which the dopant is seated, and a shielding portion (7) for shielding the upper portion of the seating portion (5), The play is formed between the side plates.
그리고 도펀트로는 일반적으로 아세닉(As) 등이 사용되며, 이는 고휘발성을 가지기 때문에 쉽게 기화된다. 따라서 안착부(5)에 안착된 도펀트는 기화된 상태로 안착부(5)의 측판과 차폐부(7)의 측판 사이에 형성된 유격을 통해 이동하게 되며, 도펀트 투입장치 둘레에 형성된 에어커튼에 의해 도가니(10)에 수용된 반도체 원재료(S)에 도달하여 서서히 도핑된다.As dopants, ascenic (As) and the like are generally used, and since they have high volatility, they are easily vaporized. Therefore, the dopant seated on the
하지만, 이와 같은 종래의 도핑 과정은, 도핑 효율이 크게 떨어질 뿐 아니라 공정 소요시간이 길어 수율이 떨어지는 문제가 있다. 뿐만 아니라, 기화된 도펀트가 도펀트 투입장치의 내면에 다량 흡착되어 소실량이 상당하며, 이에 따라 유지 보수에도 큰 노력이 소요된다.However, in the conventional doping process, the doping efficiency is not only greatly reduced, but also a long process time, there is a problem that the yield is low. In addition, a large amount of vaporized dopant is adsorbed on the inner surface of the dopant input device, the amount of loss is considerable, and accordingly maintenance is required.
또한 유해 성분의 흡착에 의해 작업자의 건강을 해칠 수 있는 등 여러 가지 문제점이 지적되고 있다.In addition, a number of problems have been pointed out, such as damage to the health of workers by the adsorption of harmful components.
따라서 이와 같은 문제점들을 해결하기 위한 방법이 요구된다.Therefore, there is a need for a method for solving such problems.
본 발명은 상술한 종래 기술의 문제점을 해결하기 위하여 안출된 발명으로서, 반도체 원재료를 신속하게 도핑시킬 수 있는 도핑방법을 제공하기 위한 목적을 가진다.The present invention has been made to solve the above-mentioned problems of the prior art, and has an object to provide a doping method capable of quickly doping semiconductor raw materials.
그리고 도펀트의 소실량을 최소화하고, 도핑 효율을 향상시킬 수 있는 도핑방법을 제공하기 위한 목적을 가진다.And it has a purpose to provide a doping method that can minimize the loss of dopant, and improve the doping efficiency.
본 발명의 과제들은 이상에서 언급한 과제들로 제한되지 않으며, 언급되지 않은 또 다른 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.
상기한 목적을 달성하기 위한 본 발명의 실리콘 반도체 잉곳 제조용 투입장치는, 하부가 개구되고, 내부에 수용공간을 형성하는 몸체부 및 상기 몸체부의 개구된 하부에 구비되며, 선택적으로 개폐 가능한 도어부를 포함하며, 상기 수용공간 측으로 노출된 상기 몸체부 내면의 적어도 일부 및 상기 도어부의 내면에는 내오염성코팅이 형성된다.The silicon semiconductor ingot production device of the present invention for achieving the above object, the lower portion is opened, the body portion to form a receiving space therein and the lower portion is provided in the opened lower portion of the body portion, and optionally includes a door portion that can be opened and closed A stain resistant coating is formed on at least a portion of the inner surface of the body portion and the inner surface of the door portion exposed to the receiving space.
그리고 상기 내오염성코팅은 Ti코팅으로 형성될 수 있다.The fouling resistant coating may be formed of a Ti coating.
또한 상기 도어부는 상기 몸체부보다 두껍게 형성될 수 있다.In addition, the door portion may be formed thicker than the body portion.
그리고 상기한 목적을 달성하기 위한 본 발명의 도핑방법은, 하부가 개구되고, 내부에 수용공간을 형성하는 몸체부와, 상기 몸체부의 개구된 하부에 구비되며, 선택적으로 개폐 가능한 도어부를 포함하는 투입장치의 상기 수용공간에 도펀트로 이루어진 도펀트층을 적층하는 단계, 상기 도펀트층 상에 고형의 반도체 원재료로 이루어진 커버층을 적층하는 단계, 용융된 반도체 원재료 상에 상기 투입장치를 기 설정된 높이로 위치시키는 단계 및 상기 투입장치의 도어부를 개방하여 상기 도펀트층과 상기 커버층이 적층 상태를 유지한 상태로 상기 용융된 반도체 원재료 상에 투입되도록 하는 단계를 포함한다.In addition, the doping method of the present invention for achieving the above object, the lower portion is opened, the body portion to form a receiving space therein, and the lower portion is provided in the opened lower portion of the body portion, the input including a selectively openable door portion Laminating a dopant layer made of a dopant in the receiving space of the device, laminating a cover layer made of a solid semiconductor raw material on the dopant layer, and placing the input device on a molten semiconductor raw material at a predetermined height. And opening the door of the dosing device so that the dopant layer and the cover layer are placed on the molten semiconductor raw material while maintaining the stacked state.
또한 상기 도펀트층을 적층하는 단계 이전에는, 상기 수용공간에 고형의 반도체 원재료로 이루어진 바닥층을 적층하는 단계가 더 포함되며, 상기 도펀트층을 적층하는 단계는, 상기 도펀트층을 상기 바닥층 상에 적층하는 것으로 할 수 있다.In addition, before the step of stacking the dopant layer, further comprising the step of laminating a bottom layer of a solid semiconductor raw material in the receiving space, the step of laminating the dopant layer, laminating the dopant layer on the bottom layer It can be done.
그리고 상기 커버층이 상기 바닥층보다 두껍게 형성되도록 할 수 있다.The cover layer may be formed thicker than the bottom layer.
또한 상기 커버층을 이루는 고형의 반도체 원재료는, 상기 바닥층을 이루는 고형의 반도체 원재료의 제1입도보다 입도가 큰 제2입도를 가지는 것으로 할 수 있다.In addition, the solid semiconductor raw material constituting the cover layer may have a second particle size larger than the first particle size of the solid semiconductor raw material constituting the bottom layer.
그리고 상기 커버층은, 제1입도를 가지는 고형의 반도체 원재료와 제2입도를 가지는 고형의 반도체 원재료가 혼합된 것으로 할 수 있다.The cover layer may be a mixture of a solid semiconductor raw material having a first particle size and a solid semiconductor raw material having a second particle size.
또한 상기 도펀트층은, 상기 도펀트층을 이루는 도펀트의 둘레부에 고형의 반도체 원재료가 배치되는 것으로 할 수 있다.In the dopant layer, a solid semiconductor raw material may be disposed at the periphery of the dopant forming the dopant layer.
상기한 과제를 해결하기 위한 본 발명의 실리콘 반도체 잉곳 제조용 투입장치 및 도핑방법은 다음과 같은 효과가 있다.In order to solve the above problems, the dosing device and the doping method for manufacturing a silicon semiconductor ingot of the present invention have the following effects.
첫째, 도펀트가 직접적으로 용융된 반도체 원재료에 투입되므로, 도핑 효율을 크게 증대시킴은 물론, 공정 소요시간을 크게 단축시킬 수 있는 장점이 있다.First, since the dopant is directly injected into the molten semiconductor raw material, there is an advantage that can greatly increase the doping efficiency, as well as significantly reduce the process time.
둘째, 도펀트의 휘발에 의한 소실량을 최소화시킬 수 있는 장점이 있다.Second, there is an advantage that can minimize the loss due to the volatilization of the dopant.
셋째, 투입장치의 내부에 도펀트가 흡착되는 것을 최소화할 수 있으므로, 유지 보수에 소요되는 노력을 절감할 수 있으며 작업자의 건강이 손상되는 것을 방지할 수 있다.Third, it is possible to minimize the absorption of the dopant in the input device, it is possible to reduce the effort required for maintenance and to prevent the health of the worker is impaired.
본 발명의 효과들은 이상에서 언급한 효과들로 제한되지 않으며, 언급되지 않은 또 다른 효과들은 청구범위의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.
도 1은 종래의 도핑 과정을 나타낸 도면;1 illustrates a conventional doping process;
도 2는 본 발명의 제1실시예에 따른 실리콘 반도체 잉곳 제조용 투입장치의 구조를 나타낸 도면;2 is a view showing the structure of an input device for manufacturing a silicon semiconductor ingot according to a first embodiment of the present invention;
도 3은 본 발명의 제1실시예에 따른 도핑방법에 있어서, 도펀트층 및 커버층을 적층한 모습을 나타낸 도면;3 is a view showing a lamination of a dopant layer and a cover layer in the doping method according to the first embodiment of the present invention;
도 4는 본 발명의 제1실시예에 따른 도핑방법에 있어서, 실리콘 반도체 잉곳 제조용 투입장치를 도가니 상에 위치시킨 모습을 나타낸 도면;4 is a view showing a state in which a dosing method for manufacturing a silicon semiconductor ingot is placed on a crucible in the doping method according to the first embodiment of the present invention;
도 5는 본 발명의 제1실시예에 따른 도핑방법에 있어서, 실리콘 반도체 잉곳 제조용 투입장치의 도어부를 개방하여 도펀트층 및 커버층을 용융된 반도체 원재료에 투입시킨 모습을 나타낸 도면;FIG. 5 is a view showing a state in which a dopant layer and a cover layer are introduced into a molten semiconductor raw material by opening a door of a dosing device for manufacturing a silicon semiconductor ingot in the doping method according to the first embodiment of the present invention; FIG.
도 6은 본 발명의 제1실시예에 따른 도핑방법에 있어서, 도펀트층이 용융된 반도체 원재료 내에 도핑되는 모습을 나타낸 도면;6 is a view showing a dopant layer doped in a molten semiconductor raw material in the doping method according to the first embodiment of the present invention;
도 7은 본 발명의 제2실시예에 따른 도핑방법에 있어서, 바닥층, 도펀트층 및 커버층을 적층한 모습을 나타낸 도면;7 is a view showing a stacking of a bottom layer, a dopant layer and a cover layer in the doping method according to the second embodiment of the present invention;
도 8은 본 발명의 제3실시예에 따른 도핑방법에 있어서, 바닥층, 도펀트층 및 커버층을 적층한 모습을 나타낸 도면;8 is a view showing a lamination of a bottom layer, a dopant layer and a cover layer in the doping method according to the third embodiment of the present invention;
도 9는 본 발명의 제4실시예에 따른 도핑방법에 있어서, 바닥층, 도펀트층 및 커버층을 적층한 모습을 나타낸 도면; 및9 is a view showing a stacking of a bottom layer, a dopant layer and a cover layer in the doping method according to the fourth embodiment of the present invention; And
도 10은 본 발명의 제5실시예에 따른 도핑방법에 있어서, 바닥층, 도펀트층 및 커버층을 적층한 모습을 나타낸 도면이다.10 is a view showing a stacking of a bottom layer, a dopant layer and a cover layer in the doping method according to the fifth embodiment of the present invention.
이하 본 발명의 목적이 구체적으로 실현될 수 있는 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 본 실시예를 설명함에 있어서, 동일 구성에 대해서는 동일 명칭 및 동일 부호가 사용되며 이에 따른 부가적인 설명은 생략하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of this embodiment, the same name and the same reference numerals are used for the same configuration and additional description thereof will be omitted.
도 2는 본 발명의 제1실시예에 따른 실리콘 반도체 잉곳 제조용 투입장치(100)의 구조를 나타낸 도면이다.2 is a view showing the structure of an
도 2에 도시된 바와 같이, 본 발명의 제1실시예에 따른 실리콘 반도체 잉곳 제조용 투입장치(100)는 몸체부(102)와, 도어부(110)를 포함한다.As shown in FIG. 2, the
상기 몸체부(102)는 하부가 개구되며, 내부에 수용공간(105)을 형성하는 구성요소이다. 상기 수용공간(105)에는 이후 도펀트를 비롯한 고형의 반도체 원재료가 수용될 수 있다. 이에 대해서는 후술하도록 한다.The
상기 도어부(110)는 상기 몸체부(102)의 개구된 하부에 구비되며, 선택적으로 개폐 가능하게 형성된다. 따라서 상기 도어부(110)는 개폐에 따라 상기 수용공간(105)의 하부를 개방 또는 차폐시킬 수 있다. 상기 도어부(110)가 개방된 경우, 상기 수용공간(105)에 수용된 도펀트 및 고형의 반도체 원재료가 낙하하게 된다.The
이때 본 실시예의 경우, 상기 수용공간(105) 측으로 노출된 상기 몸체부(102) 내면의 적어도 일부와, 상기 도어부(110)의 내면에는 내오염성코팅(120a)이 형성될 수 있다.At this time, in the present embodiment, at least a portion of the inner surface of the
이와 같이 상기 몸체부(102) 내면과 상기 도어부(110)의 내면에 내오염성코팅(120a)을 형성하는 이유는, 상기 수용공간(105)에 수용된 도펀트가 기화됨에 따라 상기 몸체부(102) 내면과 상기 도어부(110)의 내면에 흡착되는 것을 방지하기 위해서이다.As such, the reason for forming the fouling
또한 도펀트와 함께 상기 수용공간(105)에 실리콘 원재료를 투입할 경우, 이에 의한 투입장치(100) 내부의 마모로 인해 발생할 수 있는 원재료의 금속불순물 오염을 방지하기 위해서이다.In addition, when the silicon raw material is introduced into the
상기 내오염성코팅(120a)의 재료로는 다양한 물질이 사용될 수 있으며, 본 실시예의 경우 Ti코팅인 것으로 하였다. 본 실시예에서는 도펀트로 아세닉(As)을 사용하며, Ti코팅의 경우 아세닉과의 반응성이 낮아 기화된 아세닉이 흡착되는 것을 효과적으로 방지할 수 있다.Various materials may be used as the material of the pollution-resistant coating (120a), in the present embodiment was to be Ti coating. In the present exemplary embodiment, an asnic (As) is used as a dopant, and in the case of Ti coating, the reactivity with the acenic is low, so that the vaporized acenic may be effectively prevented from being adsorbed.
그리고 본 실시예에서 상기 도어부(110)는 상기 몸체부(102)보다 두껍게 형성될 수 있다. 이와 같이 하는 이유는 이후 실리콘 반도체 잉곳 제조용 투입장치(100)가 반도체 원재료가 용융된 도가니 상에 위치될 경우, 열이 수용공간(105) 내측으로 전달되는 것을 최소화하기 위해서이다. 즉 상기 도어부(110)는 열 전달을 차단하여 도펀트가 쉽게 기화되는 것을 방지하게 된다.In this embodiment, the
이하에서는, 이와 같은 실리콘 반도체 잉곳 제조용 투입장치(100)를 이용한 반도체 원재료의 도핑방법에 대해 설명하도록 한다.Hereinafter, a method of doping a semiconductor raw material using such a silicon semiconductor ingot
도 3은 본 발명의 제1실시예에 따른 도핑방법에 있어서, 도펀트층(L1) 및 커버층(L2)을 적층한 모습을 나타낸 도면이다.FIG. 3 is a view illustrating a dopant layer L 1 and a cover layer L 2 stacked in the doping method according to the first embodiment of the present invention.
도 3에 도시된 바와 같이, 먼저 실리콘 반도체 잉곳 제조용 투입장치(100)의 수용공간에 도펀트(d)로 이루어진 도펀트층(L1)을 적층하는 단계와, 상기 도펀트층(L1) 상에 고형의 반도체 원재료(s)로 이루어진 커버층(L2)을 적층하는 단계가 수행된다.As shown in FIG. 3, first, a dopant layer (L 1 ) made of a dopant (d) is deposited in a receiving space of the silicon semiconductor
상기 도펀트층(L1)은 소정 입도를 가지는 도펀트(d)를 포함하며, 상기 커버층(L2)의 하부에 구비된다. 그리고 상기 커버층(L2)은 소정 입도를 가지는 고형의 반도체 원재료(s)를 포함한다.The dopant layer L 1 includes a dopant d having a predetermined particle size and is provided under the cover layer L 2 . The cover layer L 2 includes a solid semiconductor raw material s having a predetermined particle size.
본 실시예에서 상기 도펀트(d)는 아세닉인 것으로 하였으며, 반도체 원재료는 실리콘인 것으로 하였다. 즉 상기 커버층(L2)을 형성하는 고형의 반도체의 원재료(s)는 실리콘이 고형화된 것이며, 상기 도펀트(d)를 덮어 감싸는 형태로 구비된다.In this embodiment, the dopant (d) is considered to be acenic, and the semiconductor raw material is silicon. That is, the raw material s of the solid semiconductor forming the cover layer L 2 is obtained by solidifying silicon and covering the dopant d.
그리고 본 실시예의 경우 상기 도펀트층(L1)은, 상기 도펀트층(L1)을 이루는 도펀트(d)의 둘레부에 고형의 반도체 원재료(s)를 더 배치하는 것으로 하였다. 이는 도펀트(d)가 고형의 반도체 원재료(s)에 의해 완전히 둘러싸이도록 하기 위한 것이다.And was that in this embodiment the dopant layer (L 1) is further disposed a semiconductor raw material (s) of the solid in the rim portion of the dopant (d) forming the dopant layer (L 1). This is for the dopant d to be completely surrounded by the solid semiconductor raw material s.
이와 같이 하는 이유는, 도펀트(d)의 기화를 최소화하기 위한 것으로, 고형의 반도체 원재료(s)는 도펀트(d)의 상부 및 측부를 모두 막아 외부에 노출되지 않도록 할 수 있다.The reason for doing this is to minimize vaporization of the dopant d, and the solid semiconductor raw material s can block both the upper and side portions of the dopant d so as not to be exposed to the outside.
도 4는 본 발명의 제1실시예에 따른 도핑방법에 있어서, 실리콘 반도체 잉곳 제조용 투입장치(100)를 도가니(10) 상에 위치시킨 모습을 나타낸 도면이며, 도 5는 본 발명의 제1실시예에 따른 반도체 원재료의 도펀트 도핑방법에 있어서, 실리콘 반도체 잉곳 제조용 투입장치(100)의 도어부(110)를 개방하여 도펀트층(L1) 및 커버층(L2)을 용융된 반도체 원재료(S)에 투입시킨 모습을 나타낸 도면이다.4 is a view showing a state in which the
도 4 및 도 5에 도시된 바와 같이 도펀트층(L1)을 적층하는 단계와 커버층(L2)을 적층하는 단계 이후에는, 상기 도가니(10)에 수용된 용융된 반도체 원재료(S) 상에 상기 투입장치(100)를 기 설정된 높이로 위치시키는 단계와, 상기 투입장치(100)의 도어부(110)를 개방하여 도펀트층(L1) 및 커버층(L2)이 적층 상태를 유지한 상태로 상기 용융된 반도체 원재료(S) 상에 투입되도록 하는 단계가 각각 수행된다.4 and 5, after laminating the dopant layer L 1 and laminating the cover layer L 2 , on the molten semiconductor raw material S accommodated in the
구체적으로 상기 도가니(10)에는, 반도체의 원재료(S)가 용융된 상태로 수용된다. 이와 같은 상태의 용융된 반도체 원재료(S)는 비전도성을 가지며, 도펀트(d)의 첨가를 통해 전도성을 가지게 될 수 있다.Specifically, the
따라서 도펀트층(L1) 및 커버층(L2)이 각각 적층된 투입장치(100)를 도가니(10)의 상부에 기 설정된 높이로 위치시킨 뒤, 상기 투입장치(100)의 도어부(110)를 개방하여 도펀트층(L1) 및 커버층(L2)을 용융된 반도체 원재료(S)에 투입하게 된다.Therefore, after the dopant layer L 1 and the cover layer L 2 are stacked, the
이때 상기 도펀트층(L1) 및 상기 커버층(L2)은 적층 상태를 유지한 상태로 용융된 반도체 원재료(S) 상에 낙하하며, 상기 용융된 반도체 원재료(S)는 점성을 가지므로 상기 도펀트층(L1) 및 상기 커버층(L2)은 도 6과 같이 상기 용융된 반도체 원재료(S)의 표면으로부터 서서히 가라앉게 된다.At this time, the dopant layer (L 1 ) and the cover layer (L 2 ) fall on the molten semiconductor raw material (S) while maintaining a laminated state, the molten semiconductor raw material (S) has a viscosity and thus The dopant layer L 1 and the cover layer L 2 gradually sink from the surface of the molten semiconductor raw material S as shown in FIG. 6.
이 과정에서 도펀트(d)는 고온에 의해 용융되어 상기 용융된 반도체 원재료(S)가 도핑된다. 그리고 상기 도펀트층(L1) 및 상기 커버층(L2)에 포함된 고형의 반도체 원재료(s)는, 실질적으로 도가니(10) 내에 용융된 반도체 원재료(S)와 동일한 물질이므로 고온에 의해 용융되어 혼합된다.In this process, the dopant (d) is melted by high temperature so that the molten semiconductor raw material (S) is doped. The solid semiconductor raw material s included in the dopant layer L 1 and the cover layer L 2 is substantially the same material as the semiconductor raw material S melted in the
즉 본 발명은 용융된 반도체 원재료(S) 내에 도펀트(d)가 혼합되기까지, 상기 도펀트층(L1) 및 상기 커버층(L2)에 포함된 고형의 반도체 원재료(s)가 도펀트(d)의 기화를 최소화하게 되며, 도펀트(d)는 고형의 상태에서 직접적으로 용융된 반도체 원재료(S)에 투입되므로 종래에 비해 도핑 효율을 크게 향상시킬 수 있다.That is, in the present invention, until the dopant d is mixed in the molten semiconductor raw material S, the solid semiconductor raw material s included in the dopant layer L 1 and the cover layer L 2 is a dopant d. ), And the dopant (d) is injected into the semiconductor raw material (S) directly melted in a solid state, thereby greatly improving the doping efficiency as compared with the related art.
종래의 경우, 도펀트(d)를 기화시킨 상태로 도핑을 수행하기 때문에 공정 소요 시간이 길어질 뿐 아니라 소실량이 많아 비효율적이나, 본 발명은 이와 같은 종래의 문제점들을 해결할 수 있게 된다.In the related art, since the doping is performed while the dopant (d) is vaporized, the process takes a long time and a large amount of loss, which is inefficient, but the present invention can solve these problems.
이하에서는, 본 발명의 다른 실시예들에 대해 설명하도록 한다.Hereinafter, other embodiments of the present invention will be described.
도 7은 본 발명의 제2실시예에 따른 도펀트 도핑방법에 있어서, 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층한 모습을 나타낸 도면이다.FIG. 7 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the dopant doping method according to the second embodiment of the present invention.
도 7에 도시된 본 발명의 제2실시예의 경우, 전술한 제1실시예와 마찬가지로 도펀트층(L1) 및 커버층(L2)이 적층된다는 점은 동일하나, 상기 도펀트층(L1)의 하부에 바닥층(L3)이 더 적층된다는 점이 다르다.FIG case of the second embodiment of the present invention in Figure 7, the first embodiment and likewise the dopant layer (L 1) and a cover layer that the (L 2) is laminated is equal to one, and the dopant layer (L 1) The difference is that the bottom layer (L 3 ) is further laminated to the bottom of the.
상기 바닥층(L3)은 상기 커버층(L2)과 마찬가지로 고형의 반도체 원재료(s)를 포함하며, 상기 커버층(L2)과 함께 도펀트(d)를 감싸는 형태로 구비된다.Like the cover layer (L 2 ), the bottom layer (L 3 ) includes a solid semiconductor raw material (s), and is provided in the form of surrounding the dopant (d) together with the cover layer (L 2 ).
이와 같이 본 실시예에서 바닥층(L3)을 더 형성하는 이유는, 이후 투입장치(100)가 도가니 상에 위치될 경우, 하부에서부터 도펀트(d)에 열이 직접적으로 전달되는 것을 방지하기 위해서이다.The reason for further forming a bottom layer (L 3) in the present embodiment, if after the
즉 상기 바닥층(L3)은 도펀트(d)에 열이 전달되는 것을 차단하여 도펀트(d)의 기화량을 현저하게 줄일 수 있다.That is, the bottom layer (L 3 ) can block the transfer of heat to the dopant (d) can significantly reduce the amount of vaporization of the dopant (d).
도 8은 본 발명의 제3실시예에 따른 도핑방법에 있어서, 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층한 모습을 나타낸 도면이다.FIG. 8 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the doping method according to the third embodiment of the present invention.
도 8에 도시된 본 발명의 제3실시예의 경우, 전술한 제2실시예와 마찬가지로 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층하게 된다. 다만, 본 실시예의 경우 상기 커버층(L2)이 상기 바닥층(L3)보다 두껍게 형성된다는 점이 다르다.In the third embodiment of the present invention illustrated in FIG. 8, the bottom layer L 3 , the dopant layer L 1 , and the cover layer L 2 are stacked in the same manner as in the second embodiment. However, the present embodiment is different in that the cover layer (L 2 ) is formed thicker than the bottom layer (L 3 ).
즉 본 실시예의 경우 상기 커버층(L2)의 두께를 보다 두껍게 하여, 이후 커버층(L2)이 도가니에 낙하하는 충격으로 인해 분산되어 도펀트(d)가 노출될 수 있는 가능성을 최소화할 수 있다. 상기 커버층(L2)은 고형의 반도체 원재료(s)가 복수 층을 형성하므로, 다소 분산되더라도 상부에 형성된 층이 빈틈을 메꿀 수 있기 때문이다.That is, in the present embodiment, the thickness of the cover layer (L 2 ) is made thicker, thereby minimizing the possibility that the cover layer (L 2 ) may be dispersed due to the impact falling on the crucible and the dopant (d) may be exposed. have. The cover layer (L 2 ) is because the solid semiconductor raw material (s) forms a plurality of layers, because even if slightly dispersed, the layer formed on top can fill the gap.
도 9는 본 발명의 제4실시예에 따른 도핑방법에 있어서, 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층한 모습을 나타낸 도면이다.FIG. 9 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the doping method according to the fourth embodiment of the present invention.
도 9에 도시된 본 발명의 제4실시예의 경우, 전술한 제2실시예 및 제3실시예와 마찬가지로 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층하게 된다.In the fourth embodiment of the present invention illustrated in FIG. 9, the bottom layer L 3 , the dopant layer L 1 , and the cover layer L 2 are stacked as in the second and third embodiments. .
다만, 본 실시예의 경우 상기 커버층(L2)을 이루는 고형의 반도체 원재료(s1)는, 상기 바닥층(L3)을 이루는 고형의 반도체 원재료(s2)의 제1입도보다 입도가 큰 제2입도를 가진다는 점이 다르다.However, in the present exemplary embodiment, the solid semiconductor raw material s 1 constituting the cover layer L 2 has a particle size larger than the first particle size of the solid semiconductor raw material s 2 constituting the bottom layer L 3 . The difference is that it has two granularities.
즉 본 실시예의 경우 상기 커버층(L2)을 이루는 고형의 반도체 원재료(s1)의 입도가 보다 크게 형성되어, 도펀트(d)의 노출을 보다 효과적으로 방지할 수 있다.That is, in the present exemplary embodiment, the particle size of the solid semiconductor raw material s 1 constituting the cover layer L 2 is formed to be larger, thereby more effectively preventing the dopant d from being exposed.
그리고 상기 바닥층(L3)을 이루는 고형의 반도체 원재료(s2)는 상대적으로 입도가 작게 형성되어, 도가니 내에 투입 시 빠르게 용융될 수 있다.In addition, the solid semiconductor raw material s 2 constituting the bottom layer L 3 is formed with a relatively small particle size, and thus may be rapidly melted when it is introduced into the crucible.
도 10은 본 발명의 제5실시예에 따른 도핑방법에 있어서, 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층한 모습을 나타낸 도면이다.FIG. 10 is a view illustrating a lamination of a bottom layer L 3 , a dopant layer L 1 , and a cover layer L 2 in the doping method according to the fifth embodiment of the present invention.
도 10에 도시된 본 발명의 제5실시예의 경우, 전술한 제2실시예 내지 제4실시예와 마찬가지로 바닥층(L3), 도펀트층(L1) 및 커버층(L2)을 적층하게 된다.In the case of the fifth embodiment of the present invention shown in FIG. 10, the bottom layer L 3 , the dopant layer L 1 , and the cover layer L 2 are laminated in the same manner as in the second to fourth embodiments. .
다만, 본 실시예의 경우 상기 커버층(L2)이 제1입도를 가지는 고형의 반도체 원재료(s1)와, 제2입도를 가지는 고형의 반도체 원재료(s2)가 혼합된다는 점이 다르다.However, the present embodiment differs in that the cover layer L 2 is mixed with a solid semiconductor raw material s 1 having a first particle size and a solid semiconductor raw material s 2 having a second particle size.
즉 본 실시예의 경우 상기 커버층(L2)이 제1입도를 가지는 고형의 반도체 원재료(s1) 사이사이에 제2입도를 가지는 고형의 반도체 원재료(s2)가 위치되므로, 제1입도를 가지는 고형의 반도체 원재료(s1)의 공극을 효과적으로 채울 수 있어 도펀트(d)의 노출을 보다 효과적으로 방지할 수 있다.That is the case of this embodiment, because the cover layer (L 2) is the first size to a second size for having the semiconductor raw material (s 2) of the solid in between the solid semiconductor raw material (s 1) having location, the first granularity The eggplant can effectively fill the voids of the solid semiconductor raw material s 1 , thereby more effectively preventing the dopant d from being exposed.
이상과 같이 본 발명에 따른 바람직한 실시예를 살펴보았으며, 앞서 설명된 실시예 이외에도 본 발명이 그 취지나 범주에서 벗어남이 없이 다른 특정 형태로 구체화될 수 있다는 사실은 해당 기술에 통상의 지식을 가진 이들에게는 자명한 것이다. 그러므로, 상술된 실시예는 제한적인 것이 아니라 예시적인 것으로 여겨져야 하고, 이에 따라 본 발명은 상술한 설명에 한정되지 않고 첨부된 청구항의 범주 및 그 동등 범위 내에서 변경될 수도 있다.As described above, a preferred embodiment according to the present invention has been described, and the fact that the present invention can be embodied in other specific forms in addition to the above-described embodiments without departing from the spirit or scope thereof has ordinary skill in the art. It is obvious to them. Therefore, the above-described embodiments should be regarded as illustrative rather than restrictive, and thus, the present invention is not limited to the above description and may be modified within the scope of the appended claims and their equivalents.
Claims (9)
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