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WO2018004668A2 - Techniques de formation de dispositifs résonateurs à ondes acoustiques de volume sur couches minces - Google Patents

Techniques de formation de dispositifs résonateurs à ondes acoustiques de volume sur couches minces Download PDF

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Publication number
WO2018004668A2
WO2018004668A2 PCT/US2016/040766 US2016040766W WO2018004668A2 WO 2018004668 A2 WO2018004668 A2 WO 2018004668A2 US 2016040766 W US2016040766 W US 2016040766W WO 2018004668 A2 WO2018004668 A2 WO 2018004668A2
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Prior art keywords
iii
layer
semiconductor
superlattice structure
electrode
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WO2018004668A3 (fr
Inventor
Han Wui Then
Sansaptak DASGUPTA
Marko Radosavljevic
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Intel Corp
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Intel Corp
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Priority to PCT/US2016/040766 priority Critical patent/WO2018004668A2/fr
Publication of WO2018004668A2 publication Critical patent/WO2018004668A2/fr
Publication of WO2018004668A3 publication Critical patent/WO2018004668A3/fr
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02015—Characteristics of piezoelectric layers, e.g. cutting angles

Definitions

  • RF filters employ thin-film bulk acoustic resonators (TFBARs, also called FBARs).
  • TFBARs thin-film bulk acoustic resonators
  • Typical RF front-end technologies employing second-generation (2G), third-generation (3G), fourth-generation (4G), and long-term evolution (LTE) wireless standards utilize multiple RF filters, each with one or more constituent TFBARs.
  • FIGS. 1-9 illustrate a process flow for forming an integrated circuit (IC) in accordance with an embodiment of the present disclosure.
  • Figure 10 illustrates a computing system implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (A1N), and any one, or combination, of other III-N semiconductor materials.
  • A1N aluminum nitride
  • aluminum indium nitride Al x Ini -x N
  • aluminum gallium nitride Al x Gai -x N
  • aluminum indium gallium nitride Al x In y Gai -x-y N
  • the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers.
  • individual constituent layers may be selectively removed from the superlattice with no (or otherwise negligible) impact on other layers, in accordance with some embodiments.
  • the superlattice structure may be thinned down, in nanometer-range increments, to achieve a given target resonance frequency for the host resonator device, in accordance with some embodiments. Numerous configurations and variations will be apparent in light of this disclosure.
  • TFBAR thin-film bulk acoustic resonator
  • AlN aluminum nitride
  • sputtered AIN is generally of poorer quality than AIN layers formed, for example, by epitaxial deposition.
  • a sputtered AIN film of 2 ⁇ thickness which typically is characterized by X-ray diffraction (XRD) to have a full width at half maximum (FWFDVI) (002) of 2 degrees.
  • XRD X-ray diffraction
  • FWFDVI full width at half maximum
  • epitaxial AIN films can achieve thicknesses of about 0.5 ⁇ or less (e.g., 0.2 ⁇ ), which are characterized by XRD to have a FWHM (002) of 0.4 degrees or less.
  • film quality improvements may be obtained even in cases of epitaxial growth, for example, from a silicon (Si) substrate, which has a 41% lattice mismatch with AIN.
  • a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AIN), and any one, or combination, of other III- N semiconductor materials.
  • AIN aluminum nitride
  • aluminum indium nitride Al x Ini -x N
  • aluminum gallium nitride Al x Gai -x N
  • aluminum indium gallium nitride Al x In y Gai -x-y N
  • the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers.
  • individual constituent layers may be selectively removed from the superlattice with no (or otherwise negligible) impact on other layers, in accordance with some embodiments.
  • the superlattice structure may be thinned down, in nanometer-range increments, to achieve a given target resonance frequency for the host resonator device, in accordance with some embodiments.
  • use of the disclosed techniques may realize improvements in controlled formation of layer thicknesses to nanometer-range precision as compared to existing sputter deposition and timed etch approaches, at least in some instances.
  • use of the disclosed techniques may provide for very precise control over the thickness of the constituent epitaxial layers of a superlattice structure and in thinning that structure to produce multiple TFBARs of different resonance frequencies over a commonly shared semiconductor substrate.
  • the disclosed techniques may be used in fabricating multiple TFBARs on a commonly shared semiconductor substrate, thus allowing for fabrication of multi-band, multi-mode communication filters integrated on the same die. More generally, the techniques described herein may be used, in accordance with some embodiments, to produce any desired quantity of resonator devices with as many different resonance frequencies as desired for a given target application or end-use.
  • use of techniques described herein may result in III-N semiconductor superlattice structures including higher quality piezoelectric layer(s) that provide for higher electromechanical coupling and Q-factor RF devices.
  • these improvements may realize bandwidth increases, reductions in signal losses, and increases in the ability of the host RF filter to reject out-of-band signals.
  • TFBAR devices fabricated via the disclosed techniques may be utilized in RF filters and other RF devices that may be used in communication technologies that employ any one, or combination, of second-generation (2G), third-generation (3G), fourth-generation (4G), or long- term evolution (LTE) wireless standards, among others.
  • use of such devices may realize lower losses and higher signal integrity, from which host wireless communication platforms may benefit.
  • structures provided as variously described herein may be configured for use, for example, in RF front-end modules in computing devices, mobile or otherwise, and various communication systems, although numerous other applications will be apparent in light of this disclosure.
  • structures provided as variously described herein may be configured for use, for example, in base stations, cellular communication towers, and the like.
  • FIGS 1-9 illustrate a process flow for forming an IC 100 in accordance with an embodiment of the present disclosure.
  • this process flow may be used, for example, to fabricate an IC 100 including one or more resonator devices (e.g., TFBARs) 101a, 101b, and so forth, of different resonance frequencies from a superlattice structure comprised of one or more piezoelectric III-N semiconductor materials, in accordance with some embodiments.
  • resonator devices e.g., TFBARs
  • IC 100 may include a semiconductor substrate 102, which may have any of a wide range of configurations.
  • semiconductor substrate 102 may be configured as any one, or combination, of a bulk semiconductor substrate, a silicon-on-insulator (SOI) structure or other semiconductor-on-insulator structure (XOI, where X represents a semiconductor material, such as silicon, germanium, germanium-enriched silicon, and so forth), a semiconductor wafer, and a multi-layered semiconductor structure.
  • semiconductor substrate 102 may be configured as a silicon-on-sapphire (SOS) structure.
  • SOS silicon-on-sapphire
  • Semiconductor substrate 102 may be comprised of any of a wide range of semiconductor materials.
  • semiconductor substrate 102 may be comprised of any one, or combination, of Group IV semiconductor materials, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe).
  • semiconductor substrate 102 may be comprised of Si having a crystallographic orientation of (111), (110), or (100), optionally with an offcut towards (110) in the range of about 1-10° (e.g., about 1-4°, about 4-7°, about 7-10°, or any other sub-range in the range of about 1-10°).
  • semiconductor substrate 102 may be comprised of any one, or combination, of Group III-V compound semiconductor materials, such as gallium arsenide (GaAs) or indium phosphide (InP), among others.
  • semiconductor substrate 102 may be comprised of silicon carbide (SiC) or sapphire ( ⁇ - ⁇ 1 2 0 3 ).
  • the particular material composition of semiconductor substrate 102 may be chosen, at least in part, based on a target electrical resistivity range suitable for one or more resonator devices formed there over, as described herein.
  • semiconductor substrate 102 may have an electrical resistivity of about 1,000 ⁇ -cm or greater (e.g., about 1,200 ⁇ -cm or greater, about 1,500 ⁇ -cm or greater, and so forth).
  • semiconductor substrate 102 is not intended to be limited only to configurations and implementations as a substrate for a given host architecture, as in accordance with some other embodiments, semiconductor substrate 102 may be configured or otherwise implemented as an intermediate layer disposed in a given host architecture.
  • Other suitable materials, configurations, and resistivity ranges for semiconductor substrate 102 will depend on a given application and will be apparent in light of this disclosure.
  • Electrode layer 104 may be comprised of any of a wide range of electrically conductive materials.
  • electrode layer 104 may be comprised of any one, or combination, of electrically conductive refractory materials, such as tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), or an alloy of any thereof, to name a few.
  • electrode layer 104 may be comprised of highly n-doped (e.g., n + ) indium gallium nitride (In x Gai -x N), where x is in the range of about 0.05-0.2.
  • n-type dopants include silicon (Si) and germanium (Ge), to name a few.
  • Electrode layer 104 may be formed via any suitable standard, custom, or proprietary techniques, as will be apparent in light of this disclosure.
  • electrode layer 104 may be formed via any one, or combination, of a physical vapor deposition (PVD) process (e.g., sputtering), a chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process, among others.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the dimensions (e.g., z-thickness in the z-direction) of electrode layer 104 may be customized, as desired for a given target application or end-use.
  • electrode layer 104 may have a z-thickness in the range of about 200 nm or less (e.g., about 150 nm or less, about 100 nm or less, about 50 nm or less, or any other sub-range in the range of about 200 nm or less).
  • IC 100 may include a III-N semiconductor layer 106 disposed over a topography provided, in part or in whole, by electrode layer 104.
  • III-N semiconductor layer 106 may be configured as a superlattice structure (e.g., bi-layer, tri-layer, or other multi-layer) including alternating layers of III-N semiconductor materials.
  • III-N semiconductor layer 106 may include: (1) a first constituent layer 106(i) comprised of a first III-N semiconductor material; and (2) an immediately adjacent second constituent layer 106(ii) (e.g., immediately superjacent and/or immediately subjacent) comprised of a different second III-N semiconductor material.
  • first and second layers 106(i) and 106(ii) may be repeated in an alternating manner (e.g., as generally can be seen in the portion of Figure 1 enclosed in the dashed box) or other given desired order. Additional third, fourth, and further constituent layers, each being comprised of a given III-N semiconductor material, optionally may be provided, in accordance with some embodiments.
  • constituent layers 106(i), 106(ii), and so forth hereinafter may be collectively referred to generally as constituent layers 106( «), except where separately referenced.
  • a given constituent layer 106( «) of III-N semiconductor layer 106 may be comprised of any one, or combination, of III-N semiconductor materials, including gallium nitride (GaN), aluminum nitride (A1N), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), and aluminum indium gallium nitride (AlInGaN).
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • AlInN aluminum indium nitride
  • AlInGaN aluminum indium gallium nitride
  • III-N semiconductor layer 106 may be a superlattice structure including alternating layers of an A1N layer 106(i) and an Al x Ini -x N layer 106(ii), where x is in the range of about 0.7-0.99.
  • x 0.9
  • III-N semiconductor layer 106 includes alternating layers of A1N layer 106(i) and Alo.9Ino.1N layer 106(ii).
  • x 0.83
  • III-N semiconductor layer 106 includes alternating layers of A1N layer 106(i) and Alo.83Ino.17N layer 106(ii).
  • III-N semiconductor layer 106 may be a superlattice structure including alternating layers of an A1N layer 106(i) and an Al x Gai -x N layer 106(ii), where x is in the range of about 0.01-0.5.
  • III-N semiconductor layer 106 may be a superlattice structure including alternating layers of an A1N layer 106(i) and an Al x In y Gai -x-y N layer 106(ii), where x is in the range of about 0.01-0.3 and y is in the range of about 0.01-0.1.
  • III-N semiconductor layer 106 includes alternating layers of A1N layer 106(i) and Alo.9Ino.05Gao.05N layer 106(ii).
  • III-N semiconductor layer 106 may be formed via any suitable standard, custom, or proprietary techniques, as will be apparent in light of this disclosure.
  • a given constituent layer 106( «) of III-N semiconductor layer 106 may be formed via any one, or combination, of a chemical vapor deposition (CVD) process, such as metal- organic CVD (MOCVD), an epitaxy process, such as molecular beam epitaxy (MBE), or an atomic layer deposition (ALD) process, among others.
  • CVD chemical vapor deposition
  • MOCVD metal- organic CVD
  • MBE molecular beam epitaxy
  • ALD atomic layer deposition
  • the dimensions (e.g., z-thickness in the z-direction) of a given constituent layer 106( «) of III-N semiconductor layer 106 may be customized, as desired for a given target application or end-use.
  • a given constituent layer 106( «) of III-N semiconductor layer 106 may have a z-thickness in the range of about 1-10 nm (e.g., about 1-2.5 nm, about 2.5-5 nm, about 7-10 nm, or any other range in the sub-range of about 1-10 nm).
  • III-N semiconductor layer 106 may have a z- thickness in the range of about 0.5-3 ⁇ (e.g., about 0.5-1.75 ⁇ , about 1.75-3 ⁇ , or any other sub-range in the range of about 0.5-3 ⁇ ).
  • the particular z-thickness of a given constituent layer 106( «) of III-N semiconductor layer 106 may be tuned depending on how tightly spaced the target resonance frequencies are for a given target application or end-use.
  • precision control of such thickness may allow for very fine control in thinning a given III-N semiconductor layer 106 to provide one or multiple TFBARs of different resonance frequencies over the same semiconductor substrate 102, in accordance with some embodiments.
  • Other suitable materials, formation techniques, configurations, and dimensions for III-N semiconductor layer 106 will depend on a given application and will be apparent in light of this disclosure.
  • IC 100 may include a hardmask layer 108 disposed over a topography provided, in part or in whole, by III-N semiconductor layer 106.
  • Hardmask layer 108 may be comprised of any suitable hardmask material(s), as will be apparent in light of this disclosure.
  • hardmask layer 108 may be comprised of any one, or combination, of silicon nitride (Si 3 N 4 ), silicon dioxide (Si0 2 ), and silicon oxynitride (SiO x N y ), to name a few.
  • Hardmask layer 108 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • hardmask layer 108 may be formed via any one, or combination, of a physical vapor deposition (PVD) process (e.g., sputtering) and a chemical vapor deposition (CVD) process, among others.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the dimensions (e.g., z-thickness in the z-direction) of hardmask layer 108 may be customized, as desired for a given target application or end-use.
  • hardmask layer 108 may have a z-thickness in the range of about 100-350 nm (e.g., about 100-225 nm, about 225-350 nm, or any other subrange in the range of about 100-350 nm).
  • Hardmask layer 108 may depend on a given application and will be apparent in light of this disclosure.
  • the process flow may continue as in Figure 2, which illustrates a cross-sectional view of the IC 100 of Figure 1 after patterning with one or more features 110, in accordance with an embodiment of the present disclosure.
  • a given feature 110 may be, for example, a trench, through-hole, or other opening or recess that extends through a full thickness (e.g., z-thickness in the z-direction) of hardmask layer 108, III-N semiconductor layer 106, and electrode layer 104, and into semiconductor substrate 102.
  • a given feature 110 may be formed via any suitable standard, custom, or proprietary lithography, etch, and clean technique(s), as will be apparent in light of this disclosure.
  • a given feature 110 may be formed via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use.
  • the dimensions e.g., x-width in the x-direction; z-depth in the z-direction
  • geometry of a given feature 110, as well as the pitch or other spacing of neighboring features 110 may be customized, as desired for a given target application or end-use.
  • a given feature 110 may have an x-width in the range of about 200-800 ⁇ (e.g., about 200-400 ⁇ , about 400-600 ⁇ , about 600-800 ⁇ , or any other sub-range in the range of about 200-800 ⁇ ).
  • the z-depth of a given feature 110 may be tuned, for example, so as to extend down through one or more intervening layers and into semiconductor layer 102, in accordance with some embodiments.
  • Other suitable formation techniques, configurations, and dimensions for feature(s) 110 will depend on a given application and will be apparent in light of this disclosure.
  • a first stacked arrangement (e.g., a first mesa portion) including a first electrode layer portion 104a, a first III-N semiconductor layer portion 106a, and a first hardmask layer portion 108a may remain over a first portion of semiconductor substrate 102.
  • a second stacked arrangement (e.g., a second mesa portion) including a second electrode layer portion 104b, a second III-N semiconductor layer portion 106b, and a second hardmask layer portion 108b may remain over a second portion of semiconductor substrate 102.
  • the remaining mesa portions may serve as initial defining points for what ultimately may become resonator devices 101a and 101b for IC 100 as they undergo additional processing, as described herein.
  • the initial dimensions of a given mesa portion of either (or both) resonator device 101a or 101b may be customized, as desired for a given target application or end-use, and may depend, at least in part, on the dimensions of feature(s) 110 of IC 100.
  • either (or both) mesa portions of resonator devices 101a and 101b may have an x-width in the range of about 50-400 ⁇ (e.g., about 50-250 ⁇ , about 250-400 ⁇ , or any other sub-range in the range of about 50-400 ⁇ ). In some cases, either (or both) mesa portions of resonator devices 101a and 101b may have a z-height in the range of about 1-3 ⁇ (e.g., about 1-2 ⁇ , about 2-3 ⁇ , or any other sub-range in the range of about 1-3 ⁇ ).
  • Dielectric layer 112 may be disposed over a topography provided, in part or in whole, by hardmask layer portions 108a, 108b, III-N semiconductor layer portions 106a, 106b, electrode layer portions 104a, 104b, and semiconductor substrate 102.
  • Dielectric layer 112 may be comprised of any one, or combination, of a wide range of dielectric materials.
  • dielectric layer 112 may be comprised of an oxide, such as silicon oxide (Si0 2 ), aluminum oxide (A1 2 0 3 ), hafnium oxide (Hf0 2 ), zirconium oxide (Zr0 2 ), tantalum oxide (Ta 2 0 5 ), titanium oxide (Ti0 2 ), lanthanum oxide (La 2 0 3 ), or carbon (C)-doped oxide (CDO), among others.
  • oxide such as silicon oxide (Si0 2 ), aluminum oxide (A1 2 0 3 ), hafnium oxide (Hf0 2 ), zirconium oxide (Zr0 2 ), tantalum oxide (Ta 2 0 5 ), titanium oxide (Ti0 2 ), lanthanum oxide (La 2 0 3 ), or carbon (C)-doped oxide (CDO), among others.
  • oxide such as silicon oxide (Si0 2 ), aluminum oxide (A1 2 0 3 ), hafnium oxide (Hf0 2 ), zirconium oxide
  • dielectric layer 112 may be comprised of a nitride, such as silicon mononitride (SiN) or silicon nitride (Si 3 N 4 ), or an oxynitride, such as silicon oxynitride (SiON) or C-doped SiON, a carbide, such as silicon carbide (SiC), or an oxycarbonitride, such as silicon oxycarbonitride (SiOCN), among others.
  • dielectric layer 112 may be comprised of an organosilicate glass (SiCOH).
  • dielectric layer 112 may be comprised of an inorganic compound, such as hydrogen silsesquioxane (HSQ).
  • Dielectric layer 112 may be formed via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • dielectric layer 112 may be formed via any one, or combination, of a physical vapor deposition (PVD) process, such as sputter deposition, a spin-on deposition (SOD) process, a chemical vapor deposition (CVD) process, such as plasma-enhanced CVD (PECVD), and an atomic layer deposition (ALD) process, to name a few.
  • PVD physical vapor deposition
  • SOD spin-on deposition
  • CVD chemical vapor deposition
  • PECVD plasma-enhanced CVD
  • ALD atomic layer deposition
  • the thickness (e.g., x-thickness in the x- direction; z-thickness in the z-direction) of dielectric layer 112 may be customized, as desired for a given target application or end-use. In some cases, dielectric layer 112 may have a z-thickness, for example, sufficient to fill a given feature 110. Any overburden of dielectric layer 112 may be removed, for example, via a chemical-mechanical planarization (CMP) process or other suitable planarization process.
  • CMP chemical-mechanical planarization
  • hardmask layer portions 108a, 108b may serve as a stop point in overburden removal, and thus a surface of hardmask layer portions 108a, 108b may be substantially co-planar with a surface of dielectric layer 112 (e.g., as generally can be seen in Figure 3).
  • dielectric layer 112 may be configured to serve as a shallow trench isolation (STI) layer for IC 100.
  • STI shallow trench isolation
  • FIG 4 illustrates a cross-sectional view of the IC 100 of Figure 3 after removing hardmask layer portion 108b and partially removing III-N semiconductor layer 106, in accordance with an embodiment of the present disclosure.
  • hardmask layer portion 108b may be removed from IC 100, exposing the surface of underlying III-N semiconductor layer portion 106b. Removal of hardmask layer portion 108b may be provided via any suitable standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure.
  • hardmask layer portion 108b may be removed via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use.
  • the particular etch process(es) employed may be selective to removal of the material of hardmask layer portion 108b as compared to the material of dielectric layer 112, for example, in accordance with some embodiments.
  • III-N semiconductor layer portion 106b may be thinned down in z-thickness, in accordance with some embodiments.
  • III-N semiconductor layer portion 106b may undergo selective removal of one or more of its constituent layers 106( «).
  • removal of individual constituent layers 106( «) of III-N semiconductor layer portion 106b may be provided via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use.
  • the applied etch chemistry may be comprised of sulfur hexafluoride (SF 6 ).
  • III-N semiconductor layer portion 106b may include, at least in some embodiments, an alternating stack of a first constituent layer 106(i) and a second constituent layer 106(ii) which differ from one another in material composition.
  • a given constituent layer 106(«) having a first material composition may be selectively removed with no, or otherwise negligible, impact on a vertically adjacent constituent layer 106( «) having a second, different material composition.
  • a second constituent layer 106(ii) may be removed, in part or in whole, without removing a first constituent layer 106(i) vertically adjacent thereto.
  • a first constituent layer 106(i) may be removed, in part or in whole, without removing a second constituent layer 106(ii) vertically adjacent thereto.
  • Selective removal on a layer-by- layer basis may be possible, at least in part, because of the different material composition (and thus etch or other removal process selectivity) of vertically adjacent constituent layers 106( «) of III-N semiconductor layer portion 106b.
  • resonator device 101b may differ in z-thickness from resonator device 101a by a distance (D), which may depend on the quantity and z-thicknesses of the one or more constituent layers 106( «) removed from III-N semiconductor layer portion 106b.
  • resonator device 101a may have a lower resonance frequency than resonator device 101b because III-N semiconductor layer portion 106a is of greater z- thickness than III-N semiconductor layer portion 106b.
  • FIG. 5 illustrates a cross-sectional view of the IC 100 of Figure 4 after removing hardmask layer portion 108a and partially removing dielectric layer 112, in accordance with an embodiment of the present disclosure.
  • hardmask layer portion 108a may be removed from IC 100, exposing the surface of underlying III-N semiconductor layer portion 106a. Removal of hardmask layer portion 108a may be provided via any of the example techniques discussed above, for instance, with respect to removal of hardmask layer portion 108b, in accordance with some embodiments.
  • dielectric layer 112 may be reduced in z-thickness, for example, to a point where it is substantially co-planar with or recessed below an uppermost surface of either (or both) III-N semiconductor layer portion 106a and III-N semiconductor layer portion 106b, in accordance with some embodiments. In some cases, dielectric layer 112 may be reduced in z-thickness such that it is substantially co-planar with or recessed below the uppermost surface of whichever III-N semiconductor layer portion 106a, 106b, or other has the lowest z-thickness (e.g., partial removal of dielectric layer 112 may stop at a point which coincides with the thinnest of the superlattice structures of IC 100). Partial removal of dielectric layer 112 may be provided via any standard, custom, or proprietary lithography, etch, and clean processes, as will be apparent in light of this disclosure.
  • a given feature 114 may be, for example, a trench, through-hole, or other opening or recess that extends through a full thickness (e.g., z-thickness in the z-direction) of either III-N semiconductor layer portion 106a or 106b and lands on or otherwise extends into either electrode layer portion 104a or 104b.
  • III-N semiconductor layer portion 106a and electrode layer portion 104a or III-N semiconductor layer portion 106b and electrode layer portion 104b may be provided via any of the example techniques discussed above, for instance, with respect to feature(s) 110, in accordance with some embodiments.
  • one or more sidewalls of a portion of dielectric layer 112 may be exposed (e.g., such as generally can be seen in Figure 6).
  • the particular dimensions and geometry of a given feature 114 may be customized, as desired for a given target application or end-use. Other suitable formation techniques, configurations, and dimensions for feature(s) 114 will depend on a given application and will be apparent in light of this disclosure.
  • Figure 7 illustrates a cross-sectional view of the IC 100 of Figure 6 after forming contact portions 116a and 116b and electrode layers 118a and 118b, in accordance with an embodiment of the present disclosure.
  • a first contact portion 116a may be disposed within a feature 114 so as to contact (or otherwise be configured for electrical communication with) electrode layer portion 104a of resonator device 101a.
  • a second contact portion 116b may be disposed within a feature 114 so as to contact (or otherwise be configured for electrical communication with) electrode layer portion 104b of resonator device 101b.
  • a first electrode layer 118a may be disposed over a topography provided, in part or in whole, by III-N semiconductor layer portion 106a and dielectric layer 112.
  • a second electrode layer 118b may be disposed over a topography provided, in part or in whole, by III-N semiconductor layer portion 106b and dielectric layer 112.
  • first contact portion 116a, second contact portion 116b, first electrode layer 118a, and second electrode layer 118b may be provided with any of the example materials and formation techniques discussed above, for instance, with respect to electrode layer 104 (e.g., here in Figure 7, electrode layer portions 104a and 104b), in accordance with some embodiments.
  • the dimensions and geometry of first contact portion 116a and second contact portion 116b may be customized, as desired for a given target application or end-use, and may depend, at least in part, on the particular dimensions and geometry of a given host feature 114, in accordance with some embodiments.
  • first contact portion 116a and second contact portion 116b may extend along one or more sidewalls of a portion of dielectric layer 112 (e.g., such as generally can be seen in Figure 7). In some instances, either (or both) of first contact portion 116a and second contact portion 116b may have a portion that extends over an upper surface of a portion of dielectric layer 112 (e.g., such as generally can be seen in Figure 7).
  • first electrode layer 118a and second electrode layer 118b may be customized, as desired for a given target application or end-use, and at least in some instances may be of any of the example dimensions and geometries discussed above, for instance, with respect to electrode layer 104 (e.g., here in Figure 7, electrode layer portions 104a and 104b), in accordance with some embodiments.
  • electrode layer 104 e.g., here in Figure 7, electrode layer portions 104a and 104b
  • Other suitable materials, formation techniques, configurations, and dimensions for first contact portion 116a, second contact portion 116b, first electrode layer 118a, and second electrode layer 118b will depend on a given application and will be apparent in light of this disclosure.
  • a gap 120 may be provided there between, for example, to prevent electrical shorting.
  • a gap 120 may be provided there between for a similar purpose.
  • a given gap 120 may be formed via any standard, custom, or proprietary technique(s), as will be apparent in light of this disclosure. In accordance with some embodiments, a masking and metallization process may be used to such ends. The particular dimensions and geometry of a given gap 120 may be customized, as desired for a given target application or end-use.
  • a given feature 122 may be, for example, a trench, through-hole, or other opening or recess that extends through a full thickness (e.g., z-thickness in the z-direction) of a portion of dielectric layer 112 to a surface of underlying semiconductor substrate 102.
  • a given feature 122 may be disposed between a first contact portion 116a and a second contact portion 116b neighboring therewith (e.g., as generally can be seen in Figure 8).
  • partial removal of dielectric layer 112 may be provided via any standard, custom, or proprietary lithography, etch, and clean processes, as will be apparent in light of this disclosure.
  • the particular dimensions and geometry of a given feature 122 may be customized, as desired for a given target application or end-use. Other suitable formation techniques, configurations, and dimensions for a given feature 122 will depend on a given application and will be apparent in light of this disclosure.
  • FIG. 9 illustrates a cross-sectional view of the IC 100 of Figure 8 after forming a cavity 124 in semiconductor substrate 102, in accordance with an embodiment of the present disclosure.
  • Partial removal of semiconductor substrate 102 to form a cavity 124 therein may be provided via any one, or combination, of a dry etch process and a wet etch process, the etch chemistry of which may be customized, as desired for a given target application or end-use.
  • the particular etch chemistry employed in forming cavity 124 may depend on the particular material composition of semiconductor substrate 102.
  • semiconductor substrate 102 is a Si substrate or a Si-on-insulator (SOI) of Si-on-sapphire (SOS) substrate
  • an etchant comprised of potassium hydroxide (KOH) or tetra-methyl ammonium hydroxide (TMAH) ((CH 3 ) 4 NOH) may be utilized in removing Si material to form cavity 124, in accordance with some embodiments.
  • KOH potassium hydroxide
  • TMAH tetra-methyl ammonium hydroxide
  • semiconductor substrate 102 is comprised of a Group III-V semiconductor material, such as GaAs or InP, for example, then an etchant comprised of phosphoric acid (H 3 P0 4 ) containing hydrogen peroxide (H 2 0 2 ) or comprised of a concentrated hydrochloric acid (HQ) or sulfuric acid (H 2 S0 4 ) may be utilized in removing III-V material to form cavity 124, in accordance with some embodiments.
  • phosphoric acid H 3 P0 4
  • HQ concentrated hydrochloric acid
  • sulfuric acid H 2 S0 4
  • Numerous other suitable etchants and etch schemes for various configurations of semiconductor substrate 102 will be apparent in light of this disclosure. Further note that the particular etch scheme employed may include either (or both) anisotropic and isotropic etching. In accordance with some embodiments, anisotropic etching may be utilized in forming feature 122, followed by isotropic etching to form cavity 124.
  • the etchant(s) employed in forming cavity 124 may be delivered to semiconductor substrate 102 through a given feature 122, which may serve as a sort of passageway that channels the etchant(s) to the exposed surface and, eventually, interior of semiconductor substrate 102.
  • semiconductor substrate 102 may be considered, in part or in whole, a sacrificial layer (e.g., in that at least a portion thereof may be intentionally removed from IC 100).
  • a first cavity portion 124a may form under electrode layer portion 104a of resonator device 101a
  • a second cavity 124b may form under electrode layer portion 104b of resonator device 101b, in accordance with some embodiments.
  • cavities 124 may be customized, as desired for a given target application or end-use, and at least in some instances may be made to correspond with the particular quantity of resonator devices native to IC 100.
  • the particular dimensions and geometry of cavity 124 may be customized, as desired for a given target application or end-use.
  • either (or both) of resonator devices 101a and 101b may extend over cavity 124 in a generally cantilevered manner over semiconductor substrate 102, in accordance with some embodiments.
  • One or more electrical interconnection layers optionally may be formed over IC 100 to make any desired electrical connections for either (or both) of resonator devices 101a and 101b, in accordance with some embodiments.
  • the various constituent layers of IC 100 may have any of a wide range of thicknesses (e.g., z-thicknesses in the z-direction, x-thicknesses in the x-direction, or other designated thickness), as desired for a given target application or end-use.
  • a given layer may be provided as a monolayer over an underlying topography.
  • a given constituent layer thereof may have a substantially uniform thickness over an underlying topography.
  • a given constituent layer may be provided as a substantially conformal layer over an underlying topography.
  • a given constituent layer may be provided with a non -uniform or otherwise varying thickness over an underlying topography.
  • a first portion of a given layer may have a thickness within a first range
  • a second portion thereof may have a thickness within a second, different range.
  • a given layer may have first and second portions having average thicknesses that are different from one another by about 20% or less, about 15% or less, about 10% or less, or about 5% or less. Numerous configurations and variations will be apparent in light of this disclosure.
  • the various constituent layers of IC 100 may be disposed over one or more other constituent layers.
  • a first constituent layer may be disposed directly on a second constituent layer with no layers intervening.
  • one or more intervening layers may be disposed between a first constituent layer and a second constituent layer underlying.
  • a given constituent layer may be disposed superjacent to another given constituent layer, optionally with one or more intervening layers, in accordance with some embodiments.
  • FIG 10 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • the computing system 1000 houses a motherboard 1002.
  • the motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein.
  • the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.
  • computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • graphics processor e.g., a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
  • the communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 1000 may include a plurality of communication chips 1006.
  • a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004.
  • the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006.
  • the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein.
  • multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips).
  • processor 1004 may be a chip set having such wireless capability.
  • any number of processor 1004 and/or communication chips 1006 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • PDA personal digital assistant
  • Example 1 is an integrated circuit including: a semiconductor substrate having a cavity formed therein; a first resonator device of a first resonance frequency, the first resonator device disposed over a first region of the cavity in the semiconductor substrate and including a first III- N semiconductor superlattice structure including at least one epitaxial piezoelectric layer; and a second resonator device of a second resonance frequency that differs from the first resonance frequency, the second resonator device disposed over a second region of the cavity in the semiconductor substrate and including a second III-N semiconductor superlattice structure including at least one epitaxial piezoelectric layer.
  • Example 2 includes the subject matter of any of Examples 1, 3-4, and 8-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum indium nitride (Al x Ini -x N) layer disposed over the AIN layer, wherein x is in the range of about 0.7-0.99.
  • AIN aluminum nitride
  • Al x Ini -x N aluminum indium nitride
  • Example 3 includes the subject matter of Example 2, wherein the Al x Ini -x N layer includes
  • Example 4 includes the subject matter of Example 2, wherein the Al x Ini -x N layer includes Alo.83Ino.17N.
  • Example 5 includes the subject matter of any of Examples 1 and 8-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (A1N) layer; and an aluminum gallium nitride (Al x Gai -x N) layer disposed over the A1N layer, wherein x is in the range of about 0.01- 0.5.
  • A1N aluminum nitride
  • Al x Gai -x N aluminum gallium nitride
  • Example 6 includes the subject matter of any of Examples 1 and 7-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (A1N) layer; and an aluminum indium gallium nitride (Al x In y Gai -x-y N) layer disposed over the A1N layer, wherein x is in the range of about 0.01-0.3 and y is in the range of about 0.01-0.1.
  • A1N aluminum nitride
  • Al x In y Gai -x-y N aluminum indium gallium nitride
  • Example 7 includes the subject matter of Example 6, wherein the Al x In y Gai -x-y N layer includes Alo.9Ino.05Gao.05N.
  • Example 8 includes the subject matter of any of Examples 1-7 and 9-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes at least one III-N semiconductor layer having a z-thickness in the range of about 1-10 nm.
  • Example 9 includes the subject matter of any of Examples 1-8 and 10-13, wherein the second III-N semiconductor superlattice structure is of a different z-thickness than the first III-N semiconductor superlattice structure.
  • Example 10 includes the subject matter of any of Examples 1-9 and 11-13, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes a plurality of epitaxial piezoelectric layers.
  • Example 11 includes the subject matter of any of Examples 1-10 and 12-13 and further includes at least one of: a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; a third electrode disposed on a first side of the second III-N semiconductor superlattice structure; and a fourth electrode disposed on a second side of the second III-N semiconductor superlattice structure.
  • Example 12 includes the subject matter of Example 11, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes at least one of tungsten (W), molybdenum (Mo), tantalum nitride (TaN), titanium nitride (TiN), and an alloy of any thereof.
  • Example 13 includes the subject matter of Example 11, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes n-doped indium gallium nitride (In x Gai -x N), wherein x is in the range of about 0.05-0.2.
  • n-doped indium gallium nitride In x Gai -x N
  • Example 14 is a method of fabricating an integrated circuit, the method including: forming a first resonator device over a first region of a semiconductor substrate, the first resonator device of a first resonance frequency and including a first III-N semiconductor superlattice structure including at least one epitaxial piezoelectric layer; forming a second resonator device over a second region of a semiconductor substrate, the second resonator device of a second resonance frequency that differs from the first resonance frequency and including a second III-N semiconductor superlattice structure including at least one epitaxial piezoelectric layer; and forming a cavity within the semiconductor substrate, wherein the cavity extends under at least one of the first resonator device and the second resonator device.
  • Example 15 includes the subject matter of any of Examples 14, 16-17, and 21-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum indium nitride (Al x Ini -x N) layer disposed over the AIN layer, wherein x is in the range of about 0.7-0.99.
  • AIN aluminum nitride
  • Al x Ini -x N aluminum indium nitride
  • Example 16 includes the subject matter of Example 15, wherein the Al x Ini -x N layer includes Alo.9Ino.1N.
  • Example 17 includes the subject matter of Example 15, wherein the Al x Ini -x N layer includes Alo.83Ino.17N.
  • Example 18 includes the subject matter of any of Examples 14 and 21-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum gallium nitride (Al x Gai -x N) layer disposed over the AIN layer, wherein x is in the range of about 0.01-0.5.
  • AIN aluminum nitride
  • Al x Gai -x N aluminum gallium nitride
  • Example 19 includes the subject matter of any of Examples 14 and 20-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes: an aluminum nitride (AIN) layer; and an aluminum indium gallium nitride (Al x In y Gai -x-y N) layer disposed over the AIN layer, wherein x is in the range of about 0.01-0.3 and y is in the range of about 0.01-0.1.
  • AIN aluminum nitride
  • Al x In y Gai -x-y N aluminum indium gallium nitride
  • Example 20 includes the subject matter of Example 19, wherein the Al x In y Gai -x-y N layer includes Alo.9Ino.05Gao.05N.
  • Example 21 includes the subject matter of any of Examples 14-20 and 22-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes at least one III-N semiconductor layer having a z- thickness in the range of about 1-10 nm.
  • Example 22 includes the subject matter of any of Examples 14-21 and 23-26, wherein the second III-N semiconductor superlattice structure is of a different z-thickness than the first III-N semiconductor superlattice structure.
  • Example 23 includes the subject matter of any of Examples 14-22 and 24-26, wherein at least one of the first III-N semiconductor superlattice structure and the second III-N semiconductor superlattice structure includes a plurality of epitaxial piezoelectric layers.
  • Example 24 includes the subject matter of any of Examples 14-23 and 25-26 and further includes at least one of: forming a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; forming a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; forming a third electrode disposed on a first side of the second III-N semiconductor superlattice structure; and forming a fourth electrode disposed on a second side of the second III-N semiconductor superlattice structure.
  • Example 26 includes the subject matter of Example 24, wherein at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode includes n-doped indium gallium nitride (In x Gai -x N), wherein x is in the range of about 0.05-0.2.
  • n-doped indium gallium nitride In x Gai -x N
  • Example 27 is an integrated circuit including: a semiconductor substrate; a first thin-film bulk acoustic resonator (TFBAR) device of a first resonance frequency, the first TFBAR device disposed over a first region of the semiconductor substrate and including a first III-N semiconductor superlattice structure including alternating layers of epitaxial aluminum nitride (A1N) and at least one other III-N semiconductor layer; and a second TFBAR device of a second resonance frequency that differs from the first resonance frequency, the second TFBAR device disposed over a second region of the semiconductor substrate and including a second III-N semiconductor superlattice structure including alternating layers of epitaxial A1N and at least one other III-N semiconductor layer.
  • TFBAR thin-film bulk acoustic resonator
  • Example 28 includes the subject matter of any of Examples 27 and 29-34, wherein the first TFBAR device further includes: a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; and a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; wherein at least one of the first electrode and the second electrode includes at least one of an electrically conductive refractory material and indium gallium nitride (InGaN) doped with at least one of silicon and germanium.
  • the first TFBAR device further includes: a first electrode disposed on a first side of the first III-N semiconductor superlattice structure; and a second electrode disposed on a second side of the first III-N semiconductor superlattice structure; wherein at least one of the first electrode and the second electrode includes at least one of an electrically conductive refractory material and indium gallium nitride (InGaN) doped with at least one of silicon and germanium.
  • InGaN
  • Example 29 includes the subject matter of any of Examples 27-28 and 30-34, wherein the second TFBAR device further includes: a first electrode disposed on a first side of the second III-N semiconductor superlattice structure; and a second electrode disposed on a second side of the second III-N semiconductor superlattice structure; wherein at least one of the first electrode and the second electrode includes at least one of an electrically conductive refractory material and indium gallium nitride (InGaN) doped with at least one of silicon and germanium.
  • InGaN indium gallium nitride
  • Example 30 includes the subject matter of any of Examples 27-29 and 31-34, wherein the semiconductor substrate includes a Group IV semiconductor material.
  • Example 31 includes the subject matter of any of Examples 27-30 and 32-34, wherein the semiconductor substrate includes a Group III-V compound semiconductor material.
  • Example 32 includes the subject matter of any of Examples 27-31 and 33-34 and further includes a third TFBAR device of a third resonance frequency that differs from both the first resonance frequency and the second resonance frequency, the third TFBAR device disposed over a third region of the semiconductor substrate and including a third III-N semiconductor superlattice structure including alternating layers of epitaxial A1N and at least one other III-N semiconductor layer.
  • Example 33 includes a radio frequency (RF) filter including an integrated circuit including the subject matter of any of Examples 27-32 and 34.
  • RF radio frequency
  • Example 34 includes a mobile computing device including the RF filter including the subj ect matter of Example 33.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

L'invention concerne des techniques de fabrication d'un circuit intégré comprenant un ou plusieurs dispositifs résonateurs à ondes acoustiques de volume sur couches minces (TFBAR, également appelés FBAR). Un dispositif TFBAR donné peut comprendre une structure de super-réseau comprenant des couches alternées d'un matériau piézoélectrique épitaxial, tel que du nitrure d'aluminium (AlN), et l'un quelconque parmi ou une combinaison de nitrure d'aluminium-indium (A1xIn1-xN), de nitrure d'aluminium-gallium (A1xGa1-xN), ou de nitrure d'aluminium-indium-gallium (A1xInyGa1-x-yN), dont les rapports de composition particuliers peuvent être ajustés pour personnaliser les performances du résonateur. Les couches de super-réseau peuvent être formées par un procédé de dépôt épitaxial, ce qui permet de maîtriser avec précision l'épaisseur. En exploitant les différences de composition des matériaux et à l'aide de compositions chimiques et de techniques de gravure sélective appropriées, des couches constitutives individuelles peuvent être retirées sélectivement du super-réseau sans impact (ou sinon avec un impact négligeable) sur d'autres couches. De cette manière, la structure de super-réseau peut être amincie, selon des incréments de l'ordre du nanomètre, afin d'obtenir une fréquence de résonance cible donnée pour le dispositif résonateur hôte.
PCT/US2016/040766 2016-07-01 2016-07-01 Techniques de formation de dispositifs résonateurs à ondes acoustiques de volume sur couches minces Ceased WO2018004668A2 (fr)

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EP3982537A4 (fr) * 2019-06-06 2022-07-06 Tianjin University Résonateur acoustique de volume avec concentration en dopage variable, filtre, et dispositif électronique
EP4191878A1 (fr) * 2021-12-06 2023-06-07 Commissariat à l'énergie atomique et aux énergies alternatives Dispositif à onde acoustique de volume et procédé de réalisation d'un tel dispositif

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US5883575A (en) * 1997-08-12 1999-03-16 Hewlett-Packard Company RF-tags utilizing thin film bulk wave acoustic resonators
US6965128B2 (en) * 2003-02-03 2005-11-15 Freescale Semiconductor, Inc. Structure and method for fabricating semiconductor microresonator devices
WO2005034301A1 (fr) * 2003-09-25 2005-04-14 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur en nitrure et procede de fabrication de celui-ci
US7564316B2 (en) * 2005-12-23 2009-07-21 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Variable-frequency oscillator incorporating thin-film bulk acoustic resonators
DE102008025691B4 (de) * 2007-05-31 2011-08-25 National Institute Of Advanced Industrial Science And Technology Piezoelektrischer Dünnfilm, piezoelektrisches Material und Herstellungsverfahren für piezoelektrischen Dünnfilm

Cited By (3)

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Publication number Priority date Publication date Assignee Title
EP3982537A4 (fr) * 2019-06-06 2022-07-06 Tianjin University Résonateur acoustique de volume avec concentration en dopage variable, filtre, et dispositif électronique
EP4191878A1 (fr) * 2021-12-06 2023-06-07 Commissariat à l'énergie atomique et aux énergies alternatives Dispositif à onde acoustique de volume et procédé de réalisation d'un tel dispositif
FR3130102A1 (fr) * 2021-12-06 2023-06-09 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif à onde acoustique de volume et procédé de réalisation d’un tel dispositif

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