WO2018068255A1 - Neuron-synapsis circuit and neuron circuit - Google Patents

Abstract

A neuron-synapsis circuit and a neuron circuit, wherein the neuron-synapsis circuit comprises: a charging circuit, a discharging circuit and a MOS capacitor connected to the charging circuit and the discharging circuit respectively. Both the charging circuit and the discharging circuit are composed of a plurality of MOS devices, and access a pulse sequence generated by a pre-synaptic neuron and a pulse sequence generated by a post-synaptic neuron; the charging circuit is configured to output an analogue voltage that increases the weight of the synapsis by charging the MOS capacitor when the pulse sequence generated by the pre-synaptic neuron arrives earlier than the pulse sequence generated by the post-synaptic neuron; and the discharging circuit is configured to output an analogue voltage that decreases the weight of the synapsis by discharging the MOS capacitor when the pulse sequence generated by the pre-synaptic neuron arrives later than the pulse sequence generated by the post-synaptic neuron. The power consumption of the circuit can be reduced and the integration degree can be increased.

Description

Neuronal synapse circuit and neuron circuit Technical field

The invention relates to the field of artificial neural network technology, in particular to a neuron synapse circuit and a neuron circuit.

Background technique

There are hundreds of millions of neurons in the human brain, and the number of synapses is even larger. Therefore, power consumption and integration are two of the most important factors for brain-like nerve chips. Brain-like nerve chips, whether from computing speed, learning mechanism or power consumption, are considered by scientists to be the most promising technology of the next generation. Because digital storage technology is very mature, its storage weight accuracy is high, data is reliable, technology is mature, design specifications, so in many programs synapse and neuron circuits are implemented digitally. However, with the deep research of artificial neural networks, the shortcomings of traditional digital neural network algorithms are becoming more and more obvious. At this stage, the neuron synapse circuits required to achieve the required multiplication and addition operations and nonlinear transformations are large in scale, power consumption and bulky, and the synaptic weights need to be digital and analog in the simulated neural network. Constant conversion between them requires a large number of D/A and A/D converters, which greatly increases the power consumption of the circuit and is difficult to adapt to the needs of development.

Summary of the invention

Embodiments of the present invention provide a neuron synapse circuit for reducing power consumption of a neuron synapse circuit and improving integration. The neuron synapse circuit includes:

a charging circuit, a discharging circuit, and a MOS capacitor respectively connected to the charging circuit and the discharging circuit;

The charging circuit and the discharging circuit are each composed of a plurality of MOS devices, and are connected to a pulse sequence generated by a presynaptic neuron and a pulse sequence generated by a post-synaptic neuron;

The charging circuit is configured to simulate an analog voltage that increases synaptic weight by charging the MOS capacitor when a pulse sequence generated by a presynaptic neuron arrives earlier than a pulse sequence generated by a post-synaptic neuron;

The discharge circuit is configured to simulate an analog voltage that reduces synaptic weight by discharging a discharge of the MOS capacitor when a pulse sequence generated by a presynaptic neuron arrives later than a pulse sequence generated by a post-synaptic neuron .

The embodiment of the present invention further provides a neuron circuit for reducing power consumption of a neuron circuit and improving integration. The neuron circuit includes:

Presynaptic neurons, postsynaptic neurons, neuronal synapse circuits, voltage-current conversion modules;

The presynaptic neuron output is coupled to the first input of the neuronal synapse circuit and the first input of the voltage-current conversion module; the post-synaptic neuron output is synaptic with the neuron The second input end of the circuit is connected; the output end of the neuron synapse circuit is connected to the second input end of the voltage current conversion module; the output end of the voltage current conversion module is connected to the input end of the post-synaptic neuron;

The voltage-current conversion module is configured to convert an analog voltage output by the neuron synapse circuit into a corresponding current stimulus to be injected into the post-synaptic neuron.

The embodiment of the present invention implements a neuron synapse circuit by using an analog circuit. Compared with the existing digital circuit mode, the structure is simple, the power consumption is low, and the operation speed is fast, and the operation efficiency of the neural network can be significantly improved. The nerve of the embodiment of the present invention The metasynaptic circuit can compare the pulse of presynaptic neuron with the pulse of post-synaptic neuron to realize the nerve conduction learning mechanism based on Spike-Timing-Dependent Plasticity (STDP). The neuron circuit of the embodiment of the invention also reduces the power consumption of the circuit and improves the integration degree by using the above-mentioned neuron synapse circuit.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work. In the drawing:

1 is a view showing a specific example of a neuron synapse circuit according to an embodiment of the present invention;

2 is a schematic structural view of a neuron circuit according to an embodiment of the present invention.

detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The illustrative embodiments of the present invention and the description thereof are intended to explain the present invention, but are not intended to limit the invention.

The inventors have considered that if the analog circuit is used to implement the neuron synapse circuit, the structure is simple, the power consumption is low, and the operation speed is fast, which can significantly improve the computational efficiency of the neural network. Therefore, the analog synapse circuit is one of the basic units of the analog neural network in the embodiment of the present invention. In an embodiment of the invention, the two neurons connected by the same synapse are referred to as presynaptic neurons and postsynaptic neurons, respectively. Neuronal synaptic circuits determine the relationship between presynaptic neurons and postsynaptic neurons The signal transmission mechanism, the neuron synapse circuit of the embodiment of the present invention uses an analog circuit to implement an STDP conduction mechanism between presynaptic neurons and postsynaptic neurons. The STDP conduction mechanism means that if a neuron generates activity itself after receiving information transmitted by other neurons, the connection between the two neurons will be strengthened, that is, the synaptic weight will increase; if the neuron receives other nerves If the meta-information itself has generated activity, the connection between the two neurons will be weakened, that is, the synaptic weight will decrease.

The neuron synapse circuit in the embodiment of the present invention may include: a charging circuit, a discharging circuit, and a MOS capacitor respectively connected to the charging circuit and the discharging circuit; the charging circuit and the discharging circuit are both composed of a plurality of MOS devices, and the access is sudden a pulse sequence generated by a pre-neural neuron and a pulse sequence generated by a post-synaptic neuron; the charging circuit is configured to pass a pulse sequence generated by the presynaptic neuron before the pulse sequence generated by the post-synaptic neuron The MOS capacitor charges the analog voltage that increases the synaptic weight; the discharge circuit is configured to discharge the MOS capacitor when the pulse sequence generated by the presynaptic neuron arrives later than the pulse sequence generated by the post-synaptic neuron Outputs an analog voltage that reduces the synaptic weight.

It can be seen from the above embodiments that the neuron synaptic circuit of the embodiment of the present invention can be used to implement weight storage in a neuron brain chip. The neuron synaptic circuit can compare the pulse sequence of the presynaptic neuron with the pulse sequence of the post-synaptic neuron to implement a STDP-based neural conduction learning mechanism. The neuron synapse circuit is implemented by an analog MOS (Metal Oxide Semiconductor) device.

In a specific example, the plurality of MOS devices operate in a sub-threshold region, which can reduce the on current and the operating voltage, further reducing power consumption. In terms of power consumption, when the transistor operates in the subthreshold region, the transistor operating in this region has a small operating current and a small operating voltage. For example, the operating voltage of the neuron synapse circuit can be as low as 0.6V, which greatly reduces power consumption. .

In a specific example, the MOS capacitor may be formed by shorting the drain and source of the NMOS device. Of course, those skilled in the art will readily understand that the above MOS capacitors may be formed in other manners according to actual needs.

In a specific example, the charging circuit can include at least one pair of current mirrors composed of two MOS devices for controlling the magnitude of current charging the MOS capacitors; and/or, the discharging circuit can include at least one pair of two MOS devices A current mirror is formed to control the amount of current discharged for the MOS capacitor.

The specific implementation of the neuron synapse circuit of the embodiment of the present invention will be described below with reference to the example of FIG. Of course, those skilled in the art can easily understand that the specific circuit structure shown in FIG. 1 is only one specific example of the implementation of the neuron synapse circuit of the embodiment of the present invention. In the specific implementation, some or all of the structural units in the circuit can be completely implemented. Deformation The same function can be realized by adding or adding transistors, and further, for example, a current redesign of a current mirror or a MOS capacitor in a charging circuit or a discharging circuit, and the implementation principle of the holding circuit is the same.

As shown in FIG. 1, the neuron synapse circuit of this example is composed of a MOS device, wherein the charging circuit includes: a first MOS device M1, a second MOS device M2, a third MOS device M3, a fourth MOS device M4, and a Five MOS device M5; the discharge circuit comprises: a sixth MOS device M6, a seventh MOS device M7, an eighth MOS device M8, a ninth MOS device M9 and a tenth MOS device M10; these MOS devices all operate in a subthreshold region, Reduce the on current and operating voltage.

The first MOS device M1, the fourth MOS device M4, the fifth MOS device M5, the eighth MOS device M8, and the ninth MOS device M9 are PMOS devices, and are turned on at a low level; the second MOS device M2, the third MOS The device M3, the sixth MOS device M6, the seventh MOS device M7, and the tenth MOS device M10 are NMOS devices, and are turned on at a high level;

The source of the first MOS device M1 is connected to the input voltage VDD, and is respectively connected to the source of the fourth MOS device M4 and the source of the eighth MOS device M8; the drain of the first MOS device M1 is connected to the drain of the second MOS device M2, and The gate of the first MOS device M1 is shorted; the gate of the first MOS device M1 is also connected to the gate of the fourth MOS device M4; in a specific example, the input voltage VDD can be powered by ultra-low voltage DC, further enabling the neuron synapse circuit to realize Low power consumption, high integration and so on. For example, the neuronal synapse circuit can implement an STDP conduction mechanism between neurons under ultra-low voltage (0.6V) power.

The second MOS device M2 source is connected to the third MOS device M3 drain; the second MOS device M2 gate is connected to the pulse sequence Vpre generated by the pre-synaptic neuron, and is connected to the sixth MOS device M6 gate;

The gate of the third MOS device M3 is connected to the first voltage Vd for determining the static working current of the charging circuit; the source of the third MOS device M3 is grounded, and is connected to the source of the seventh MOS device M7 and the source of the tenth MOS device M10, respectively. ;

The fourth MOS device M4 source is also connected to the eighth MOS device M8 source; the fourth MOS device M4 drain is connected to the fifth MOS device M5 source;

The gate of the fifth MOS device M5 is connected to the pulse sequence Vpost generated by the post-synaptic neuron, and is connected to the gate of the ninth MOS device M9; the drain of the fifth MOS device M5 outputs the analog voltage Vw, and is respectively connected to the sixth MOS device M6. a drain and a gate of an NMOS device forming a MOS capacitor;

The sixth MOS device M6 source is connected to the drain of the seventh MOS device M7;

The drain of the seventh MOS device M7 is short-circuited with the gate of the seventh MOS device M7; the gate of the seventh MOS device M7 is also connected to the gate of the tenth MOS device M10; the source of the seventh MOS device M7 is grounded, and the tenth MOS device is connected M10 source;

The eighth MOS device M8 source is connected to the input voltage VDD; the eighth MOS device M8 gate is connected to the second voltage Vp for determining the static working current of the discharge circuit; the eighth MOS device M8 is connected to the ninth MOS device M9 source pole;

The drain of the ninth MOS device M9 is connected to the drain of the tenth MOS device M10;

The NMOS device forming the MOS capacitor is short-circuited to the drain and grounded. This MOS capacitor is labeled Mcw in Figure 1.

Further, in this example, the gates of the fifth MOS device M5 and the gate of the ninth MOS device M9 can also be connected to the pulse sequence generated by the postsynaptic neurons via an inverter IN1. The inverter IN1 changes the low level of the pulse sequence to a high level and the high level to a low level.

The analog voltage Vw determines the strength of the synaptic weight. The magnitude of Vw is determined by the pulse sequence generated by the presynaptic neurons and the relative time of the pulse sequence generated by the postsynaptic neurons: when the presynaptic neurons produce pulses The sequence arrives earlier than the pulse sequence produced by the postsynaptic neuron (indicating that the postsynaptic neuron is the activity produced by the stimulation of the presynaptic neurons, the relationship between the two should be strengthened), the neuron synapse circuit a MOS device M1, the second MOS device M2, a third MOS device M3, the fourth MOS devices M4 and the fifth MOS devices M5 work presynaptic neuron MOS device pulse sequences generated by the second generating currents I ₁ through M2 After the first MOS device M1, the fourth MOS device M4, and the fifth MOS device M5 are activated, the current is converted into a current I _A to charge the MOS capacitor Mcw, so that Vw rises, that is, the synaptic weight increases; when the postsynaptic neuron The generated pulse sequence arrives earlier than the pulse sequence generated by the presynaptic neurons (indicating that the postsynaptic neuron has its own activity before the information transmitted by the presynaptic neurons arrives, the relationship between the two should be weakened) Sixth in the neuron synaptic circuit The MOS device M6, the seventh MOS device M7, the eighth MOS device M8, the ninth MOS device M9, and the tenth MOS device M10 work, and the pulse sequence generated by the post-synaptic neuron passes through the inverter IN1 and passes through the ninth MOS device M9. The current I _{2 is} generated, and after being acted by the sixth MOS device M6, the seventh MOS device M7, and the tenth MOS device M10, it is converted into I _B to discharge the MOS capacitor Mcw, so that Vw is lowered, that is, the synaptic weight is decreased.

The first MOS device M1 and the fourth MOS device M4 are a pair of current mirrors, and the current I _{A is} controlled to be charged by Mcw (in a certain ratio with I ₁ ); similarly, the seventh MOS device M7 and the tenth MOS device M10 are also A pair of current mirrors, controlled to the magnitude of the current I _B of the Mcw discharge (proportional to I ₂ ). The first voltage Vd and the second voltage Vp determine the static working current of the circuit through the third MOS device M3 and the eighth MOS device M8, respectively; the pulse sequence generated by the pre-synaptic neurons and the postsynaptic neurons is turned on or off. The MOS device M5 and the sixth MOS device M6 allow the currents I _A and I _B to flow through the MOS capacitor Mcw to increase or decrease the value of the analog voltage Vw.

The embodiment of the present invention further provides a neuron circuit. FIG. 2 is a schematic structural diagram of a neuron circuit according to an embodiment of the present invention. As shown in FIG. 2, the neuron circuit may include:

Presynaptic neuron 201, post-synaptic neuron 202, neuron synapse circuit 203, voltage-current conversion module 204;

The output of the presynaptic neuron 201 is connected to the first input of the neuron synapse circuit 203 and the first input of the voltage-current conversion module 204; the output of the post-synaptic neuron 202 and the second input of the neuron synapse circuit 203 Connecting; the output of the neuron synapse circuit 203 is connected to the second input end of the voltage-current conversion module 204; the output end of the voltage-current conversion module 204 is connected to the input end of the post-synaptic neuron 203;

The voltage-current conversion module 204 is configured to convert the analog voltage output by the neuron synapse circuit 203 into a corresponding current stimulus for injection into the postsynaptic neuron 202.

As shown in FIG. 2, the pulse sequences Vpre and Vpost generated by the presynaptic neuron 201 and the postsynaptic neuron 202 enter the neuronal synapse circuit 203 of the embodiment of the present invention. The neuron synapse circuit 203 compares the two pulse sequences and outputs the synaptic weight values obtained after the comparison. After the output synaptic weight passes through the voltage-current conversion module 204, the corresponding current stimulus is injected into the postsynaptic neuron 202. The greater the synaptic weight, the greater the current stimulation, and the effect on the postsynaptic neuron 203. The larger, the closer the relationship between the two neurons; the less the opposite.

In summary, the embodiment of the present invention implements a neuron synapse circuit by using an analog circuit. Compared with the existing digital circuit method, the structure is simple, the number of transistors used is small, and the transistor capacitance is used to store the synaptic weight. The chip area occupied by the circuit is greatly reduced, and the integration degree is improved; and the neuron synapse circuit of the embodiment of the invention has low power consumption and fast calculation speed, and can significantly improve the operation efficiency of the neural network; the neuron of the embodiment of the invention The synaptic circuit can compare the pulse of presynaptic neurons with the pulse of post-synaptic neurons to achieve a STDP-based neural conduction learning mechanism. The neuron circuit of the embodiment of the invention also reduces the power consumption of the circuit and improves the integration degree by using the above-mentioned neuron synapse circuit.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

The above described specific embodiments of the present invention are further described in detail, and are intended to be illustrative of the embodiments of the present invention. All modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (7)

A neuron synapse circuit, comprising: a charging circuit, a discharging circuit, and a MOS capacitor respectively connected to the charging circuit and the discharging circuit; The charging circuit and the discharging circuit are each composed of a plurality of MOS devices, and are connected to a pulse sequence generated by a presynaptic neuron and a pulse sequence generated by a post-synaptic neuron; The charging circuit is configured to simulate an analog voltage that increases synaptic weight by charging the MOS capacitor when a pulse sequence generated by a presynaptic neuron arrives earlier than a pulse sequence generated by a post-synaptic neuron; The discharge circuit is configured to simulate an analog voltage that reduces synaptic weight by discharging a discharge of the MOS capacitor when a pulse sequence generated by a presynaptic neuron arrives later than a pulse sequence generated by a post-synaptic neuron . The neuronal synapse circuit of claim 1 wherein said plurality of MOS devices operate in a subthreshold region. The neuronal synapse circuit of claim 1 wherein said MOS capacitor is formed by shorting the drain and source of the NMOS device. A neuron synapse circuit according to claim 1, wherein said charging circuit comprises at least one pair of current mirrors composed of two MOS devices for controlling the magnitude of current charged for said MOS capacitor; and / Alternatively, the discharge circuit includes at least one pair of current mirrors composed of two MOS devices for controlling the magnitude of current discharged for the MOS capacitors. The neuron synapse circuit according to claim 1, wherein said charging circuit comprises: first MOS device M1, second MOS device M2, third MOS device M3, fourth MOS device M4, and fifth MOS Device M5; The discharge circuit includes: a sixth MOS device M6, a seventh MOS device M7, an eighth MOS device M8, a ninth MOS device M9, and a tenth MOS device M10; The first MOS device M1, the fourth MOS device M4, the fifth MOS device M5, the eighth MOS device M8, and the ninth MOS device M9 are PMOS devices; the second MOS device M2, the third MOS device M3, and the sixth MOS device M6, seventh MOS device M7 and tenth MOS device M10 are NMOS devices; The source of the first MOS device M1 is connected to the input voltage VDD, and is respectively connected to the source of the fourth MOS device M4 and the source of the eighth MOS device M8; the drain of the first MOS device M1 is connected to the drain of the second MOS device M2, and The gate of the first MOS device M1 is shorted; the gate of the first MOS device M1 is also connected to the gate of the fourth MOS device M4; The second MOS device M2 source is connected to the third MOS device M3 drain; the second MOS device M2 gate is connected to the pulse sequence generated by the pre-synaptic neuron, and is connected to the sixth MOS device M6 gate; The gate of the third MOS device M3 is connected to the first voltage Vd for determining the static working current of the charging circuit; the source of the third MOS device M3 is grounded, and is connected to the source of the seventh MOS device M7 and the source of the tenth MOS device M10, respectively. ; The fourth MOS device M4 source is also connected to the eighth MOS device M8 source; the fourth MOS device M4 drain is connected to the fifth MOS device M5 source; The gate of the fifth MOS device M5 is connected to the pulse sequence generated by the post-synaptic neuron, and is connected to the gate of the ninth MOS device M9; the drain of the fifth MOS device M5 outputs the analog voltage Vw, and is respectively connected to the sixth MOS device M6 drain a gate of the NMOS device forming a MOS capacitor; The sixth MOS device M6 source is connected to the drain of the seventh MOS device M7; The drain of the seventh MOS device M7 is short-circuited with the gate of the seventh MOS device M7; the gate of the seventh MOS device M7 is also connected to the gate of the tenth MOS device M10; the source of the seventh MOS device M7 is grounded, and the tenth MOS device is connected M10 source; The eighth MOS device M8 source is connected to the input voltage VDD; the eighth MOS device M8 gate is connected to the second voltage Vp for determining the static working current of the discharge circuit; the eighth MOS device M8 is connected to the ninth MOS device M9 source pole; The drain of the ninth MOS device M9 is connected to the drain of the tenth MOS device M10; The NMOS device forming the MOS capacitor is short-circuited to the drain and grounded. The neuron synapse circuit according to claim 5, wherein the gate of the fifth MOS device M5 and the gate of the ninth MOS device M9 are connected to a pulse sequence generated by the post-synaptic neuron via an inverter IN1. A neuron circuit, comprising: Presynaptic neuron, post-synaptic neuron, neuronal synapse circuit of claim 1, voltage-current conversion module; The presynaptic neuron output is coupled to the first input of the neuronal synapse circuit and the first input of the voltage-current conversion module; the post-synaptic neuron output is synaptic with the neuron The second input end of the circuit is connected; the output end of the neuron synapse circuit is connected to the second input end of the voltage current conversion module; the output end of the voltage current conversion module is connected to the input end of the post-synaptic neuron; The voltage-current conversion module is configured to convert an analog voltage output by the neuron synapse circuit into a corresponding current stimulus to be injected into the post-synaptic neuron.

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