WO2018059697A1

WO2018059697A1 - Optoelectronic semiconductor chip package and manufacturing method thereof

Info

Publication number: WO2018059697A1
Application number: PCT/EP2016/073301
Authority: WO
Inventors: Choo Kean LIM; Siang Min NENG; Choon Keat OR; Seong Tak KOAY
Original assignee: Osram Opto Semiconductors GmbH
Current assignee: Ams Osram International GmbH
Priority date: 2016-09-29
Filing date: 2016-09-29
Publication date: 2018-04-05
Anticipated expiration: 2019-03-29

Abstract

The scope of the invention is an optoelectronic semiconductor package, comprising an optoelectronic semiconductor chip, which comprises a first contact pad and a second contact pad for applying an electric voltage to the optoelectronic semiconductor chip and a light emitting face. The optoelectronic package further comprises an isolating material adjacent to the optoelectronic semiconductor chip forming a housing of the optoelectronic semiconductor chip. The housing comprises walls. The light emitting face of the optoelectronic semiconductor chip is uncovered by the isolating material. A part of the first contact pad and a part of the second contact pad are free from the isolating material. The first contact pad is arranged at a first wall of the housing, which is opposite to the emitting face. The optoelectronic package further comprises a first contact layer in electrical contact with the first contact pad, which is arranged at the first wall and at a second wall of the housing, extending over a first edge between the first and the second wall of the housing. A second contact layer is in electrical contact with the second contact pad and arranged at a wall of the housing.

Description

OPTOELECTRONIC SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD

THEREOF

DESCRIPTION The invention refers to an optoelectronic semiconductor chip package. Optoelectronic semiconductor chip packages may be implemented with small dimensions of the package compared to the semiconductor chip size. For electrical connection of the semiconductor chip, usually lead frames are used. A main dis- advantage of the approach of using lead frames in such optoe^¬ lectronic semiconductor chip packages is that these packages only allow for a bottom soldering, but not side soldering.

An assignment of the invention is to provide an improved op- toelectronic semiconductor chip package. Another assignment of the invention is to provide a fabrication method of such an optoelectronic semiconductor chip package.

The solution of these assignments is disclosed in the inde- pendent claims of this invention. Preferred embodiments are disclosed in the dependent claims.

An optoelectronic semiconductor package comprises an optoe^¬ lectronic semiconductor chip. The optoelectronic semiconduc- tor chip comprises a first contact pad and a second contact pad for applying an electric voltage to the optoelectronic semiconductor chip. Additionally, the optoelectronic semicon^¬ ductor chip comprises a light emitting face. The optoelec^¬ tronic semiconductor package further comprises an isolating material adjacent to the optoelectronic semiconductor chip forming a housing of the optoelectronic semiconductor chip. The housing comprises walls. The light emitting face of the optoelectronic semiconductor chip is uncovered by the isolat^¬ ing material. A part of the first contact pad and a part of the second contact pad are free from the isolating material to allow for electrical contacting of the contact pads. The first contact pad is arranged at a first wall of the housing opposite to the emitting face of the optoelectronic semicon- ductor chip. The optoelectronic semiconductor package further comprises a first contact layer in electrical contact with the first contact pad. The first contact layer is arranged at the first wall and at a second wall of the housing and ex- tends over a first edge between the first wall and the second wall of the housing. Additionally, the optoelectronic semi^¬ conductor package comprises a second contact layer in elec^¬ trical contact with the second contact pad, which is arranged on a wall of the housing. The second contact layer may be ar- ranged at the first wall of the housing or at another wall of the housing. As the first contact layer of the optoelectronic semiconductor package extends over the first edge between the first and the second wall of the housing, the first contact layer extends to a side wall of the housing. Therefore, side soldering of said optoelectronic semiconductor package is possible. This allows for a greater variety of applications of such an optoelectronic semiconductor package.

In one embodiment of the invention, the housing comprises a first lug extending from the second wall of the housing. The first lug may be adjacent to the light emitting face of the optoelectronic semiconductor chip or at another place of the second wall. The first contact layer is arranged on the first lug and extends over a second edge between the first lug and the second wall. Therefore, the first contact layer extends over the first edge and the second edge, thus forming a shape which allows for easy aligning of the optoelectronic semicon^¬ ductor package. In one embodiment of the invention, the second contact pad is arranged at the first wall of the housing and the second con^¬ tact layer is arranged on the first and a third wall of the housing. The second contact layer extends over a third edge between the first and the third wall of the housing. This al- lows for side soldering of the second contact layer as well.

In one embodiment, the housing comprises a second lug extend^¬ ing from the third wall of the housing. The second contact layer is arranged on the second lug and extends over a fourth edge between the second lug and the third wall.

In one embodiment, the second wall and the third wall are on opposite sides of the housing. If the second wall and the third wall are on opposite sides of the housing, the side soldering parts of the first contact layer and the second contact layer are on opposite sides of the housing as well. Therefore, several such optoelectronic semiconductor packages can be arranged right next to each other and can be connected from the side.

In one embodiment of the invention, the first contact layer and/or the second contact layer comprise galvanically depos- ited metal. Galvanic deposition of metal is suitable for forming contact layers, which can easily be extended over edges, as during the galvanic deposition the deposited metal follows the shape of the underlying housing. In one embodiment of the invention, the first contact layer and/or the second contact layer comprise copper. Copper is a metal, which can be easily galvanically deposited and which allows for good electrical connectivity. Therefore, copper is a very suitable material for an optoelectronic semiconductor package with contact layers that are suited for side solder^¬ ing .

In one embodiment of the invention, the housing is formed by a mold process. Mold processes are easily performed. There- fore, the forming of the housing using a mold process allows for easy implementation and cheap production of the chip scaled optoelectronic semiconductor package.

In one embodiment of the invention, the isolating material forming the housing comprises a silicone compound and/or ti^¬ tan dioxide. Silicone compounds can be easily molded and are therefore suitable for the housing. Titan dioxide, in the form of titan dioxide powder, can be applied to the silicone compound or to another mold material and therefore lead to a white appearance of the housing, which is favorable for opto^¬ electronic semiconductor devices. A method of producing the optoelectronic semiconductor package comprises the steps:

- Providing a light emitting optoelectronic semiconductor chip with a light emitting face, a first contact pad and a second contact pad;

- Embedding the optoelectronic semiconductor chip in an isolating material. The isolating material forms a housing with walls. The first contact pad is arranged at a first wall of the housing. The light emitting face of the optoelectronic semiconductor chip is uncovered by the isolating material; - Deposition of a first contact layer, which is in electrical contact with the first contact pad and arranged on the first wall and a second wall of the housing. The first contact lay^¬ er extends over a first edge between the first and the second wall of the housing;

- Deposition of a second contact layer, which is in electrical contact with the second contact pad.

In one embodiment, the deposition of the contact layers com^¬ prises the steps:

- Sputtering of a first metal layer on the contact pads and the isolating material, covering at least two external walls of the housing extending over an edge between two external walls of the housing. The first metal layer may extend over the first edge between the first and the second wall of the housing;

- Structuration of the first metal layer to electrically dis^¬ connect the contact pads from each other;

- Galvanic deposition of a second metal layer on top of the first metal layer, forming two contact layers.

As the first metal layer extends over an edge of the housing, the galvanically deposited second metal layer on top of the first metal layer extends over said edge as well. In one embodiment of the invention, the structuration of the first metal layer is performed before the galvanic deposition of the second metal layer is performed and comprises the steps:

- depositing of a photo-resist on top of the first metal lay^¬ er;

- partially illuminating of the photo-resist;

- developing of the photo-resist, forming dissolvable and non-dissolvable parts of the photo-resist regarding a first solvent ;

- dissolving the dissolvable parts of the photo-resist using the first solvent;

- applying of an etchant to the first metal layer at loca- tions where the photo-resist has been dissolved;

- removing of the remaining photo-resist using a second sol^¬ vent .

With these intermediate steps, the first metal layer can be structured in at least two parts, therefore breaking the con^¬ nection between the first and the second contact pad and thus allowing for electric isolation of the two contact pads from each other. Afterwards, the galvanic deposition is performed in a way that the contact layers remain isolated from each other as well.

In one embodiment of the invention, the deposition of the second metal layer is performed in between the process steps leading to the structuration of the first metal layer. The galvanic deposition and the structuration comprise the steps:

- depositing of a photo-resist on top of the first metal lay^¬ er;

- partially illuminating of the photo-resist;

- dissolving the dissolvable parts of the photo-resist using the first solvent; - galvanic deposition of the second metal layer, wherein are^¬ as of the first metal layer covered with remaining photo^¬ resist are kept free from the second metal layer. The thick^¬ ness of the second metal layer is larger than the thickness of the first metal layer;

- removing of the remaining photo-resist using a second sol^¬ vent ;

- applying of an etchant to the first metal layer and the second metal layer in a way, that the first metal layer is completely removed in the areas previously covered with the non-dissolvable parts of the photo-resist regarding the first solvent .

With this approach, the remaining photo-resist after dissolv- ing the dissolvable parts of the photo-resist functions as a barrier for the second metal layer during the galvanic pro^¬ cess. After the galvanic process the first contact layer and the second contact layer are still in electrical contact with each other through the first metal layer. With a subsequently performed etching process, the connection of the first con^¬ tact layer and the second contact layer can be removed by re^¬ moving the first contact layer in the areas previously cov^¬ ered with the non-dissolvable parts of the photo-resist. Dur^¬ ing this process, parts of the second metal layer are also removed, but as the second metal layer has a larger thickness as the first metal layer, the contact layers stay intact.

In one embodiment, the contact pads of the optoelectronic semiconductor chip are covered by the isolating material dur- ing the embedding process. Afterwards, in an additional step, parts of the isolating material are removed to expose the contact pads .

In one embodiment of the invention, the embedding of the op- toelectronic semiconductor chip within the isolating material is performed as mold process. The above described properties, features and advantages of this invention as well as the method of obtaining them, will be more clearly and obviously understandable in the context of the following description of the embodiments, which are explained in more detail in the context of the figures.

In schematic illustration show

Figs. 1 - 8 cross sections and top views of different em- bodiments an optoelectronic semiconductor chip package; and

Figs. 9 - 20 intermediate steps during the fabrication pro^¬ cess.

Fig. 1 shows a cross section of an optoelectronic semiconduc^¬ tor package 100. The optoelectronic semiconductor package 100 comprises an optoelectronic semiconductor chip 110. The opto^¬ electronic semiconductor chip 110 comprises a first contact pad 111 and a second contact pad 112, wherein both contact pads 111, 112 are located on a bottom face 115 of the optoe^¬ lectronic semiconductor chip 110. Opposite to the bottom face 115, the optoelectronic semiconductor chip 110 comprises a light emitting face 113. Thus, the light emitting face 113 is a top face of the optoelectronic semiconductor chip 110. A voltage applied to the contact pads 111, 112 leads to light emitting through the light emitting face 113 of the optoelec^¬ tronic semiconductor chip 110. Adjacent to the optoelectronic semiconductor chip 110 an isolating material 120 forms a housing 121. The housing 121 is located at side faces 114 of the optoelectronic semiconductor chip 110 and in between the contact pads 111, 112 on the bottom face 115 of the optoelec^¬ tronic semiconductor chip 110. The side faces 114 of the op^¬ toelectronic semiconductor chip 110 are the faces that are neither the light emitting face 113 nor the bottom face 115. The light emitting face 113 is uncovered by the isolating ma^¬ terial 120. The contact pads 111, 112 are free from the iso^¬ lating material 120 on the bottom face 115. Therefore, the contact pads 111, 112 are freely accessible from the bottom of the optoelectronic semiconductor chip package 100. The first contact pad 111 is arranged at a first wall 131 of the housing 121. The first wall 131 is a bottom wall of the hous- ing 121, located at the same side of the optoelectronic semi^¬ conductor chip 110 than the bottom face 115. The optoelec^¬ tronic semiconductor package 100 further comprises a first contact layer 151 that is in electrical contact with the first contact pad 111. The first contact layer 151 is ar- ranged at the first wall 131 and at a second wall 132 of the housing 121. In between the first wall 131 and the second wall 132, the housing 121 comprises a first edge 141. The first contact layer 151 comprises a first section 153 located at the first wall 131 and a second section 154 located at the second wall 132, thus extending over the first edge 141 be^¬ tween the first wall 131 and the second wall 132 of the hous^¬ ing 121. The second section 154 of the first contact layer 151 covers the second wall 132 completely. It is also possi^¬ ble to arrange the second section 154 of the first contact layer 151 in a way that only a part of the second wall 133 is covered. The first section 153 and the second section 154 of the first contact layer 151 are perpendicular to each other in the embodiment of fig. 1. Other angles between the first section 153 and the second section 154 of the first contact layer 151 are also possible though.

A second contact layer 152 is in electrical contact with the second contact pad 112 and arranged on the first wall 131 of the housing 121. The second contact pad 112 and the second contact layer 152 may be arranged at another location of the optoelectronic semiconductor chip 110, for example at a side face 114 of the optoelectronic semiconductor chip 110.

Fig. 2 shows a top view of the optoelectronic semiconductor chip package 100 of fig. 1. The rectangular light emitting face 113 of the optoelectronic semiconductor chip 110 is en^¬ circled by the isolating material 120 forming the housing 121 adjacent to the side faces 114 of the optoelectronic semicon- ductor chip 110. At the second wall 132 of the housing facing one of the side faces 114, the second section 154 of the first contact layer 151 is arranged and visible from the top. The first wall 131 of the housing 121 with the first section 153 of the first contact layer 151 is located on the in fig. 2 not visible bottom side of the optoelectronic semiconductor chip package 100.

Fig. 3 shows a cross section of an optoelectronic semiconduc^¬ tor package 100, which essentially corresponds to the optoe^¬ lectronic semiconductor package 100 of Fig. 1. The housing 121 further comprises a first lug 161 extending from the sec^¬ ond wall 132. The first lug 161 is in line with the light emitting face 113 of the optoelectronic semiconductor chip 110. A second edge 142 is arranged between the second wall 132 and the first lug 161. The first contact layer 151 ex^¬ tends over the first edge 141 and the second edge 142, thus the first section 153 of the first contact layer 151 touches the first contact pad 111 and the first wall 131. The second section 154 of the first contact layer 151 touches the second wall 132. A third section 155 of the first contact layer 151 touches the first lug 161. The first section 153 and the third section 155 are parallel to each other, the second sec^¬ tion 154 is perpendicular to the first section 153 and the third section 155. Other angles between the sections 153, 154, 155 of the first contact layer 151 are also possible though .

Fig. 4 shows a top view of the optoelectronic semiconductor package 100 of fig. 3. The first lug 161 extends the housing 121 over the (not visible) second wall 132 of the housing 121. The partial area of the light emitting face 113 compared to the total area of the optoelectronic semiconductor package is thus smaller than in fig. 2. The first lug 161 exhibits the same width than the second wall 132. It is also possible, that the first lug 161 has a lower width. The width of the first lug 161 may be similar to the size of the light emit^¬ ting face 113 of the optoelectronic semiconductor chip. Fig. 5 shows another cross section through an optoelectronic semiconductor package 100 which is essentially similar to the previous described embodiments. The housing 121 comprises a first lug 161 as described in Fig. 3. A third edge 143 is lo^¬ cated between the first wall 131 and a third wall 133, where^¬ in the third wall 133 is opposite to the second wall 132 of the housing 121. The second contact layer 152 extends over the third edge 143, thus touching the second contact pad 112, the first wall 131 and the third wall 133. A first section

153 of the second contact layer 152 is arranged at the first wall 131, whereas a second section 154 of the second contact layer 152 is arranged at the third wall 133. The first sec^¬ tion 153 and the second section 154 are perpendicular, other angles are possible as well though.

The second wall 132 and the third wall 133 may be walls of the housing 121 that are not on opposite sides of the housing 121 as well.

Fig. 6 shows another embodiment of an optoelectronic semicon^¬ ductor package 100 with essentially the same features as the optoelectronic semiconductor package of Fig. 5. The housing 121 comprises a second lug 162 extending from the third wall 133 of the housing. In between the third wall 133 and the second lug 162, the housing 121 comprises a fourth edge 144. The second contact layer 152 extends over the third edge 143 and the fourth edge 144, thus touching the second contact pad 112, the first wall 131, the third wall 133 and the second lug 162. The second contact layer 152 comprises three sec^¬ tion, a first section 153 touching the second contact pad 112 and the first wall 133, a second section 154 touching the third wall 133 and a third section 155 touching the second lug 162. The first section 153 of the second contact layer 152 and the third section 155 of the second contact layer 152 are parallel to each other, the second section 154 of the second contact layer 152 is perpendicular to the first sec^¬ tion 153 of the second contact layer 152 and the third sec- tion 155 of the second contact layer 152. Other angles be^¬ tween the sections 153, 154, 155 of the second contact layer 152 are also possible though. For the embodiments of the Figs. 3 to 6 the first lug 161 and/or the second lug 162 may be arranged at another position of the second wall 132 and the third wall 133 respectively. In the embodiments of figs. 5 or 6, the third wall 133 is ar^¬ ranged opposite to the second wall 132 of the housing 122. It is also possible, to arrange the third wall 133 at another side wall of the housing 121, not opposite to the second wall 132.

The optoelectronic semiconductor chip package 100 may com- prise a first contact layer 151 similar to fig. 1 and a sec^¬ ond contact layer 152 similar to fig. 5, thus omitting the first lug 161 in fig. 5.

The optoelectronic semiconductor chip 110 and the housing 121 are of a cuboid shape. Other shapes, particularly for the housing 121 are also possible, for example prisms like cylin^¬ ders or a prism with a hexagonal base.

Fig. 7 shows another cross section of an optoelectronic semi- conductor package 100. The optoelectronic semiconductor pack^¬ age 100 comprises an optoelectronic semiconductor chip 110 with a first contact pad 111, a second contact pad 112, both arranged at a bottom face 115 of the optoelectronic semicon^¬ ductor chip 110 and a light emitting face 113 opposite of the bottom face 115. An isolating material 120 forms a housing of the optoelectronic semiconductor chip 110. The housing 122 comprises a first lug 161 and a second lug 162. The bottom face 115 of the semiconductor chip 110 is above a bottom side 163 of the first lug 161 and a bottom side 163 of the second lug 162. Thus, the optoelectronic semiconductor chip 110 is embedded in the part of the housing 121 that is formed by the first lug 161 and the second lug 162. To allow for the embed^¬ ding, the thickness of the first lug 161 and the second lug 162 is larger than thickness of the optoelectronic semicon^¬ ductor chip 110, relatively to a direction parallel to a con^¬ necting line extending from the bottom face 115 to the light emitting face 113 of the optoelectronic semiconductor chip 110. In a middle part 127 of the housing 121, the housing 121 is thicker than in the outer parts of the housing 121, formed by the lugs 161, 162. A first wall 131 is arranged at the housing 121 in the middle part 127 of the housing 121, thus forming a protrusion with the first wall 131 as a bottom wall of the housing 121. The first wall and the bottom sides 163 of the lugs 161, 162 in parallel to each other. A first inner connector 123 is located within the housing 121 and adjacent to the first connector pad 111. A second inner connector 124 is also located within the housing 121 and electrically con- nected to the second contact pad 112. The inner connectors 123, 124 may be regarded as parts of the first contact pad 111 and the second contact pad 112 respectively. A second wall 132 is located in between the first wall 131 and the bottom side 163 of the first lug 161. In between the first wall 131 and the second wall 132 a first edge 141 is located. Between the second wall 132 and the first lug 161 a second edge 142 is located. The first contact layer 151 extends over the first edge 141 and the second edge 142. The first contact layer 151 comprises a first section 153 adjacent to the first wall 131, a second section 154 adjacent to the second wall 132 and a third section 155 adjacent to the bottom side 163 of the first lug 161. The second contact layer 152 is ar^¬ ranged extending over a third edge 143 in between the first wall 131 and a third wall 133 and a fourth edge 144 in be- tween the third wall 133 and the second lug 162, symmetrical^¬ ly arranged at an opposite side of the optoelectronic semi^¬ conductor device 100. The second contact layer 152 comprises a first section 153 adjacent to the first wall 131, a second section 154 adjacent to the third wall 133 and a third sec- tion 155 adjacent to the bottom side 163 of the second lug 162. The first section 153 and the third section 155 of both con^¬ tact layers 151, 152 are parallel to each other, the second section 154 is perpendicular to the first section 153 and the third section 155 of both contact layers 151, 152. Other an- gles between the sections 153, 154, 155 of the first contact layer 151 and the second contact layer 152 are also possible though .

Fig. 8 shows a top view of the optoelectronic semiconductor chip package 100 of fig. 7 with the housing 121 consisting of the isolating material 120. The isolating material is ar^¬ ranged circumventing the light emitting face 113 of the rec^¬ tangular optoelectronic semiconductor chip 110. In one embodiment of the invention, the first contact layer

151 and/or the second contact layer 152 comprise galvanically deposited metal.

The optoelectronic semiconductor chip 110 may be square with a side length of 1 mm. The optoelectronic package 100 can may be square with a side length of 1.4 mm. The thickness of the housing 121 thus is 0.2 mm. Another possibility for the optoelectronic semiconductor chip 110 is a rectangular shape of 0.2 x 1.2 mm, with a size of the rectangular optoelectronic semiconductor package of 0.3 x 1.8 mm. The second set of siz^¬ es is particularly applicable to the embodiment of Figs. 7 and 8.

In one embodiment, the first contact layer 151 and/or the second contact layer 152 comprise copper. In one embodiment, the housing 121 is formed by a mold process. In one embodi^¬ ment, the isolating material 120 forming the housing 121 comprises a silicone compound and/or titan dioxide. The titan dioxide may be applied in the form of a titan dioxide powder mixed into the isolating material 121.

Figs. 9 to 19 show intermediate products during a fabrication of an optoelectronic semiconductor package according to the invention. Figs. 9 to 15 relate to a first production method, whereas after the intermediate product of fig. 11 is

achieved, a second production method can be implemented as well. The further steps of the second production method ex- plained in figs. 16 to 19.

Fig. 9 shows a cross section of an optoelectronic semiconduc^¬ tor chip 110 with a first contact pad 111 and a second con^¬ tact pad 112 arranged at a bottom face 115 of the optoelec- tronic semiconductor chip 110. A light emitting face 113 is arranged opposite of the bottom face 115. The optoelectronic semiconductor chip 110 is comparable to one of the optoelec^¬ tronic semiconductor chips 110 of Figs. 1 to 8. The optoelec^¬ tronic semiconductor chip 110 is of cuboid shape, but may comprise another shape like a hexagonal prism as well.

After the optoelectronic semiconductor chip 110 is provided, it is embedded into an isolating material 120. The isolating material 120 forms a housing 121 of the optoelectronic semi- conductor chip. The housing is arranged at the bottom face

115 as well as side faces 114 of the optoelectronic semicon^¬ ductor chip 110. The contact pads 111, 112 are arranged at a first wall 131 of the housing 121 and at least partially free of the isolating material 120. The light emitting face 113 is also uncovered by the isolating material 120. On top of the side faces 114 of the optoelectronic semiconductor chip 100 the housing 121 forms a second wall 132 and a third wall 133. A first edge 141 is located in between the first wall 131 and the second wall 132. A third edge 143 is located in between the first wall 131 and the third wall 133. The isolating ma^¬ terial 121 comprises a cuboid shape, but may also be a cylin^¬ der or a hexagonal prism. The isolating material 120 in which the optoelectronic semiconductor chip 110 is embedded, may comprise first and/or second lugs 161, 162 according to the figs. 3 to 8.

In a subsequent process step, a first contact layer 151 is deposited in a way, that it is arranged on the first wall 131, the second wall 132 and in electrical contact with the first contact pad 111. Therefore, the first contact layer 151 extends over the first edge 141. A second contact layer 152 is deposited onto the first wall 131 and in electrical con- tact with the second contact pad 112. The optoelectronic sem^¬ iconductor package 100 then is similar to the package shown in figs. 1 to 6.

Fig. 11 shows a cross section of the optoelectronic semicon- ductor chip 110 with the housing 120 after a first metal lay^¬ er 170 has been sputtered on the contact pads 111, 112 and the housing 121. The first metal layer 170 covers the first wall 131, the second wall 132 and the third wall 133. The first metal layer 170 may cover just the first wall 131 and the second wall 132, not covering the third wall 133.

After the sputtering of the first metal layer 170 the first metal layer 170 is structured to electrically disconnect the first contact pad 111 from the second contact pad 112. Anoth- er process step is a galvanic deposition of a second metal layer on top of the first metal layer 170 thus forming the first contact layer 151 and the second contact layer 152. The first production method relates to the structuration of the first metal layer 170 before the galvanic deposition of the second metal layer takes place. The second production method relates to a structuration of the first metal layer 170 after the galvanic deposition of the second metal layer takes place . A possibility for the structuration of the first metal layer 170 is shown in Fig. 12, which shows a cross section of the optoelectronic semiconductor chip 110 after the subsequent process step of depositing a photo-resist 180 on top of the first metal layer 170 adjacent to the bottom face 113. The photo-resist 180 is then partially illuminated, shown in Fig. 12 by arrows representing the illuminating light and a mask 190 blocking part of the light illuminating the photo-resist 180. The photo-resist can therefore be separated in a first part 181 illuminated by the light and a second part 182, not illuminated by the light. After the illumination of the pho^¬ to-resist 180 the photo-resist 180 is developed, therefore forming dissolvable and non-dissolvable parts of the photo- resist 180 regarding a first solvent. In the example of Fig. 12, the second part 182 of the photo-resist, which is not il^¬ luminated by the light, is dissolvable regarding a first sol^¬ vent, whereas the first parts 181 are not dissolvable due to the illumination. The mask 190 and therefore the second part 182 of the photo-resist 180 is located in between the first contact pad 111 and the second contact pad 112.

After developing the photo-resist 180 and the removing of the second part 182 of the photo-resist 180, an intermediate product shown in Fig. 13 is achieved. The first parts 181 of the photo-resist 180 cover the first metal layer 170 in areas adjacent to the contact pads 111, 112. In between the contact pads 111, 112, the first metal layer 170 is not covered by the photo resist 180 anymore.

Fig. 14 shows the optoelectronic semiconductor chip 110 and the intermediate product after a next process step, in which the first metal layer 170 in between the first contact pad

111 and the second contact pad 112 has been etched using an etchant. Therefore the first contact pad 111 and the second contact pad 112 are not in electrical contact anymore as the first metal layer 170 connecting these two contact pads 111,

112 has been removed. Subsequently, the remaining first parts 181 of the photo-resist 180 are removed using a second sol^¬ vent which is capable of dissolving these first parts 181 of the photo-resist 180.

In a final process step, a second metal layer forming a first contact layer 151 and a second contact layer 152 is deposited galvanically on top of the remaining parts of the first metal layer 170 and thus forming the contact layers 151 and 152. The product after this final process step is shown in fig. 15. Using all these described process steps from Fig. 9 to Fig. 15, an optoelectronic semiconductor package 100 is achieved .

It is also possible to use a photo-resist 180 which is dis- solvable for the first solvent after illumination and non- dissolvable, if the photo-resist 180 has not been illuminated by light. For the process step described in Fig. 12, a dif^¬ ferent mask 190 may then be used, to achieve the dissolvable and non-dissolvable parts of the photo-resist 180 according to Fig. 13.

Figs. 16 to 19 describe another method of fabrication of an optoelectronic semiconductor package according to the invention. The first steps of this process are similar to the Figs. 9 to 11. After the deposition of the photo-resist 180 on top of the first metal layer 170, the photo-resist 180 is partially illuminated. In this CcL S Θ cL S shown in Fig. 16, the non-dissolvable first parts 181 of the photo-resist 180 are in between the first contact pad 111 and the second contact pad 112.

Fig. 17 shows an intermediate product after a next process step, in which a second metal layer has been galvanically de^¬ posited on top of the first metal layer 170, thus forming the first contact layer 151 and the second contact layer 152. In between the first contact pad 111 and the second contact pad 112 the photo-resist 180 has covered a first metal layer 170 thus not allowing for the galvanic deposition to take place in between the first contact pad 111 and the second contact pad 112, as the photo-resist 180 blocks the galvanic deposi^¬ tion.

Fig. 18 shows a cross section to an intermediate product af^¬ ter the next process step of removing the remaining photo- resist using a second solvent. The first metal layer 170 still connects the first contact pad 111 and the second con^¬ tact pad 112. The second metal layer forming the first con- tact layer 151 and the second contact layer 152 has a larger thickness than the first metal layer 170.

In a subsequent step, the optoelectronic semiconductor pack- age 100 is exposed to an etchant in a way that the first met^¬ al layer 170 is completely removed in the area previously covered with the non-dissolvable first part 181 of the photo^¬ resist 180. Some minor parts of the second metal layer are thereby removed by the etchant as well. Due to this etching step, the first contact pad and the second contact pad are electrically isolated from each other. The optoelectronic semiconductor chip package after the etching process is shown in fig. 19. In one embodiment of the invention, the isolating material

120 and thus the housing 121 is formed using a mold process.

The first metal layer 170 may be used as a seed layer for the subsequent galvanic deposition of the second metal layer. Both metal layers may consist of the same metal. Therefore, the first metal layer 170 and the first contact layer 151 as well as the second contact layer 152 consist of the same met^¬ al and the boundary between the first metal layer 170 and the first contact layer 151 as well as the second contact layer 152 may not be determinable.

Fig. 20 shows another intermediate product during the process step. In this intermediate step, the optoelectronic semicon^¬ ductor chip 110 has been embedded within an isolating materi- al 120 forming a housing 121. During the embedding process, the first contact pad 111 and the second contact pad 112 have been covered by the isolating material 120 as well. In a sub^¬ sequent step, lower parts 125 of the isolating material can be removed. Upper parts 126 of the isolating material 120 re- main adjacent to the optoelectronic semiconductor chip 110. With a dash line the boundary between the upper part 126 and the lower part 125 is indicated in Fig. 20. After removing the lower part 125 of the isolating material, the first con- tact pad 111 and the second contact pad 112 are exposed. Af^¬ ter the removal of the lower parts 125 of the isolating mate^¬ rial, the intermediate product looks similar to the one in Fig. 10.

With the process steps described in figs. 9 to 20, the vari^¬ ous embodiments shown in figs. 1 to 8 can be achieved.

The optoelectronic semiconductor chip 110 may be embodied as a light emitting diode or a laser diode.

Although the invention was described and illustrated in more detail using preferred embodiments, the invention is not lim^¬ ited to these. Variants of the invention may be derived by a person skilled in the art from the described embodiments without leaving the scope of the invention.

REFERENCE NUMERALS

100 optoelectronic semiconductor package

110 optoelectronic semiconductor chip

111 first contact pad

112 second contact pad

113 light emitting face

114 side face

115 bottom face

120 isolating material

121 housing

123 first inner connector

124 second inner connector

125 lower part

126 upper part

127 middle part

131 first wall

132 second wall

133 third wall

141 first edge

142 second edge

143 third edge

144 fourth edge

151 first contact layer

152 second contact layer

153 first section

154 second section

155 third section

161 first lug

162 second lug

163 bottom side

170 first metal layer

180 photo-resist

181 first part

182 second part

190 mask

Claims

An optoelectronic semiconductor package (100), compris^¬ ing : an optoelectronic semiconductor chip (110), wherein the optoelectronic semiconductor chip (110) comprises a first contact pad (111) and a second contact pad (112) for ap^¬ plying an electric voltage to the optoelectronic semicon^¬ ductor chip (110) and wherein the optoelectronic semicon^¬ ductor chip (110) comprises a light emitting face (113); an isolating material (120) adjacent to the optoelectron^¬ ic semiconductor chip (110) forming a housing (121) of the optoelectronic semiconductor chip (110), wherein the housing (121) comprises walls (131, 132, 133), wherein the light emitting face (113) of the optoelectronic semi^¬ conductor chip (110) is uncovered by the isolating mate^¬ rial (120), wherein a part of the first contact pad (111) and a part of the second contact pad (112) are free from the isolating material (120), wherein the first contact pad (111) is arranged at a first wall (131) of the hous^¬ ing (121), wherein the first wall (131) is opposite to the light emitting face (113); a first contact layer (151) in electrical contact with the first contact pad (111), wherein the first contact layer (151) is arranged at the first wall (131) and at a second wall (132) of the housing (121), wherein the first contact layer (151) extends over a first edge (141) be^¬ tween the first and the second wall (132) of the housing (121) and a second contact layer (152) in electrical contact with the second contact pad (112) and arranged at a wall of the housing (121) .

The optoelectronic semiconductor package (100) according to claim 1, wherein the housing (121) comprises a first lug (161) extending from the second wall (132) of the housing (121), wherein the first contact layer (151) is arranged on the first lug (161) and wherein the first contact layer (151) extends over a second edge (142) be^¬ tween the first lug (161) and the second wall (132) .

The optoelectronic semiconductor package (100) according to any of the claims 1 or 2, wherein the second contact pad (112) is arranged at the first wall (131) of the housing (121), wherein the second contact layer (152) is arranged on the first wall (131) and a third wall (133) of the housing (121), wherein the second contact layer (152) extends over a third edge (143) between the first and the third wall (133) of the housing (121) .

The optoelectronic semiconductor package (100) according to claim 3, wherein the housing (121) comprises a second lug (162) extending from the third wall (133) of the housing (121), wherein the second contact layer (152) is arranged on the second lug (162) and wherein the second contact layer (152) extends over a fourth edge (144) between the second lug (162) and the third wall (133) .

The optoelectronic semiconductor package (100) according to claims 3 or 4, wherein the second wall (132) and the third wall (133) are on opposite sides of the housing (121) .

The optoelectronic semiconductor package (100) according to any of the claims 1 to 5, wherein the first contact layer (151) and/or the second contact layer (152) comprise galvanically deposited metal.

The optoelectronic semiconductor package (100) according to any of the claims 1 to 6, wherein the first contact layer (151) and/or the second contact layer (152) comprise copper.

8. The optoelectronic semiconductor package (100) according to any of the claims 1 to 7, wherein the housing (121) is formed by a mold process.

9. The optoelectronic semiconductor package according (100) to any of the claims 1 to 8, wherein the isolating mate^¬ rial (120) comprises a silicone compound and/or titan di^¬ oxide .

10. A method of producing the optoelectronic semiconductor package according to any of the claims 1 to 9, with the steps :

- Embedding the optoelectronic semiconductor chip in an isolating material, wherein the light emitting face is uncovered by the isolating material, thus forming a housing composed of the isolating material with walls, wherein the first contact pad is ar^¬ ranged at a first wall of the housing;

- Deposition of a first contact layer, wherein the

first contact layer is in electrical contact with the first contact pad and wherein the first contact layer is arranged on the first wall and a second wall of the housing, wherein the first contact layer extends over a first edge between the first and the second wall of the housing;

- Deposition of a second contact layer, wherein the second contact layer is in electrical contact with the second contact pad.

11. The method according to claim 10, wherein the contact

pads are covered by the isolating material during the em^¬ bedding process and removing, with an additional step, parts of the isolating material to expose the contact pads .

The method according to any of the claims 10 or 11, wherein the embedding of the optoelectronic semiconductor chip within the isolating material is performed as a mold process .

The method according to any of the claims 10 to 12, wherein the deposition of the contact layers comprises the steps:

- Sputtering of a first metal layer on the contact

pads and the isolating material, covering at least two external walls of the housing extending over an edge between two external walls of the housing;

- Structuration of the first metal layer to electrically disconnect the contact pads from each other;

- Galvanic deposition of a second metal layer on top of the first metal layer, forming two contact lay^¬ ers .

The method according to claim 13, wherein the structu^¬ ration of the first metal layer is performed before the galvanic deposition of the second metal layer is per^¬ formed and comprises the steps:

- Depositing of a photo-resist on top of the first

metal layer;

- Partially illuminating of the photo-resist;

- Developing of the photo-resist, forming dissolvable and non-dissolvable parts of the photo-resist re^¬ garding a first solvent;

- Dissolving the dissolvable parts of the photo-resist using the first solvent;

- Applying of an etchant to the first metal layer at locations where the photo-resist has been dissolved;

- Removing the remaining photo-resist using a second solvent . The method according to claim 13, wherein the galvanic deposition of the second metal layer is performed in be^¬ tween process steps leading to the structuration of the first metal layer, wherein the galvanic deposition and the structuration comprise the steps:

- Depositing of a photo-resist on top of the first

metal layer;

- Partially illuminating of the photo-resist;

- Dissolving the dissolvable parts of the photo-resist using the first solvent;

- Galvanic deposition of the second metal layer,

wherein areas of the first metal layer covered with remaining photo-resist are kept free from the second metal layer, wherein the thickness of the second metal layer is larger than the thickness of the first metal layer;

- Removing of the remaining photo-resist using a second solvent;

- Applying of an etchant to the first metal layer and the second metal layer in a way that the first metal layer is completely removed in the areas previously covered with the non-dissolvable parts of the photo^¬ resist regarding the first solvent.