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WO2018049648A1 - Appareil, puce, procédé et dispositif de conversion de données, et système d'image - Google Patents

Appareil, puce, procédé et dispositif de conversion de données, et système d'image Download PDF

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Publication number
WO2018049648A1
WO2018049648A1 PCT/CN2016/099210 CN2016099210W WO2018049648A1 WO 2018049648 A1 WO2018049648 A1 WO 2018049648A1 CN 2016099210 W CN2016099210 W CN 2016099210W WO 2018049648 A1 WO2018049648 A1 WO 2018049648A1
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WO
WIPO (PCT)
Prior art keywords
data
interface
chip
nvme
format
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/099210
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English (en)
Chinese (zh)
Inventor
庹伟
张强
刘志伟
王珂
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SZ DJI Technology Co Ltd
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SZ DJI Technology Co Ltd
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Publication date
Application filed by SZ DJI Technology Co Ltd filed Critical SZ DJI Technology Co Ltd
Priority to PCT/CN2016/099210 priority Critical patent/WO2018049648A1/fr
Priority to CN201680002575.4A priority patent/CN107077304B/zh
Publication of WO2018049648A1 publication Critical patent/WO2018049648A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the present application relates to data conversion technologies, and more particularly to data conversion devices, chips, methods, devices, and imaging systems.
  • RAW original
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge-coupled Device
  • RAW files are files generated after lossless compression, files in formats such as JPEG (Joint Photographic Experts Group) will be much larger.
  • Storage of RAW files requires a larger capacity storage device, which is adopted by some camera manufacturers.
  • SSD Solid State Drives
  • SATA Serial Advanced Technology Attachment
  • NVME Non-Volatile Memory Express
  • the application provides a data conversion device, a chip, a method, a device, and an imaging system.
  • a data conversion device comprising a data processing device, the data processing device comprising a first interface and a second interface;
  • the first interface is configured to connect to an external host to transmit data in a first format to the external host in both directions;
  • the second interface is used to connect to an NVME solid state drive
  • the data processing device is configured to convert the data of the first format into data of an NVME protocol format and send the data to the NVME solid state hard disk when receiving the write command of the external host; and receive the external host When the command is read, the NVME protocol format data in the NVME solid state drive is converted into the data in the first format and sent to the external host.
  • a chip including: a second interface, a parallel interface, and a protocol conversion device;
  • the second interface is used to connect to an NVME solid state drive
  • the parallel interface is used to connect with an external device
  • the protocol conversion device is configured to convert parallel interface data into data of an NVME protocol format and send the data to the NVME solid state hard disk upon receiving a write instruction from the external device; receiving a read command of the external device
  • the NVME protocol format data in the NVME solid state hard disk is converted into parallel interface data and sent to the parallel interface.
  • a chip including: a second interface, a USB interface, and a protocol conversion device;
  • the USB interface is used to connect with an external host
  • the second interface is used to connect with an NVME solid state hard disk
  • the protocol conversion device is configured to convert USB data into data in an NVME protocol format and send the data to the second interface when receiving the write command from the external host; when receiving the read command from the external host,
  • the NVME protocol format data in the NVME solid state drive is converted into USB data and sent to the USB interface.
  • a data conversion method including the steps of:
  • the write command of the external host When receiving the write command of the external host, converting the format of the write data carried by the write command into the NVME protocol format, and then writing the address space corresponding to the NVME solid state hard disk; when receiving the external host read command, the read command
  • the data in the NVME protocol format is read in the address space corresponding to the instruction, and converted into the data in the first format and sent to the external host, where the first format corresponds to the interface type of the external host.
  • a data conversion apparatus including:
  • a first interface driving module configured to receive a write command or a read command of the external host, and notify the protocol conversion module; and interact with the external host in the first format data
  • a second interface driving module configured to exchange data with the NVME solid state hard disk
  • the protocol conversion module is configured to write the data carried by the write command when receiving the write command of the external host Converting the format to the NVME protocol format, and then notifying the second interface driver module to write the address space corresponding to the NVME solid state hard disk; when receiving the external host read command, reading the NVME protocol format from the address space corresponding to the read command After the data is converted into the data of the first format, the first interface driver module is notified to send to the external host.
  • an image system including: an image capturing device and a data conversion device;
  • the image capturing device includes a PCIE interface for detachably connecting the NVME solid state hard disk;
  • the data conversion device includes at least one chip, and the chip includes:
  • the chip is configured to convert USB data into NVME protocol format data and send the data to the NVME solid state hard disk when receiving the write instruction of the image processing device; when receiving the read instruction of the image processing device, The NVME protocol format data is converted into USB data and sent to the image processing device.
  • the data conversion device, the chip, the method, the device and the image system of the embodiments of the present application provide a solution for converting and bidirectionally transmitting data of the NVME solid state hard disk and the data of the external host, so that the external host can be utilized.
  • the external interface enables data transmission with the NVME SSD, which eliminates the need for complex data conversion functions for both NVME SSDs and external hosts, thereby increasing the convenience of NVME SSD data transmission.
  • FIG. 1 is a schematic structural diagram of a system in an embodiment of the present application.
  • FIG. 2 is a partial schematic structural diagram of a data processing apparatus according to an embodiment of the present application.
  • FIG. 3 is a partial structural diagram of a data processing apparatus according to another embodiment of the present application.
  • FIG. 4 is a partial structural schematic view of a second chip in the embodiment of the present application.
  • FIG. 5 is a schematic diagram of an application scenario in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a portion of a data processing apparatus according to an embodiment of the present application.
  • FIG. 7 is a partial structural diagram of a chip in an embodiment of the present application.
  • FIG. 8 is a partial schematic structural diagram of a protocol conversion device in the chip shown in FIG. 7;
  • FIG. 9 is another schematic diagram of a protocol conversion apparatus according to an embodiment of the present application.
  • FIG. 10 is a partial structural schematic view of another chip in the embodiment of the present application.
  • FIG. 11 is a partial flowchart of a data conversion method in an embodiment of the present application.
  • FIG. 12 is a logic block diagram of a data conversion apparatus according to an embodiment of the present application.
  • FIG. 13 is a logic block diagram of a data conversion apparatus according to another embodiment of the present application.
  • FIG. 14 is a logic block diagram of a second protocol conversion module according to an embodiment of the present application.
  • first, second, third, etc. may be used to describe various information in this application, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information without departing from the scope of the present application.
  • second information may also be referred to as the first information.
  • NVME SSDs As the demand for storage bandwidth increases, NVME SSDs have begun to gain popularity. Some manufacturers install NVME SSDs on some electronic devices as needed to store data as storage devices. For example, some shadows Image devices (such as cameras, video recorders, etc.) already have an interface that is compatible with NVME SSDs, and uses NVME SSDs to store image data such as video or pictures.
  • the data stored in the NVME SSD may need to be exported to an external host.
  • the image data in the image device may be exported to a PC or other device.
  • the data in the NVME SSD may need to be performed by an external host.
  • Write operation for example, adding or deleting data in the NVME solid state drive through a personal computer. Because the external interface on the external host is not the interface that is compatible with the NVME SSD, it is not convenient to read and write data in the NVME SSD.
  • the embodiment of the present application provides a solution for bidirectionally transmitting data in an NVME solid state hard disk to an external host.
  • the type of the external host is not limited in this embodiment, and may be various terminals with computing power, such as a mobile phone, a tablet computer, a notebook computer, a desktop computer, and the like.
  • FIG. 1 is a partial structural diagram of each device in a system architecture in an embodiment.
  • a data conversion device 10 is provided.
  • the data conversion device 10 can be independent of the NVME solid state disk 11 and the external host 12 for convenient portability, convenient use on different devices, and no increase in NVME.
  • the purpose of the size and power consumption of the solid state drive 11 is.
  • the data conversion device 10 can be embodied as a card reader.
  • data conversion device 10 includes a data processing device 110.
  • the data processing device 110 has a first interface 1101 and a second interface 1102; the external host 12 can be connected through the first interface 1101, and the NVME solid state hard disk 11 can be connected through the second interface 1102.
  • the first interface 1101 and the second interface 1102 may be hardware interfaces, and may be respectively connected to the external host 12 or the NVME solid state hard disk 11 by means of physical connection.
  • the first interface 1101 can match the interface type of an external interface 120 of the external host 12, and the format of the data transmitted bidirectionally between the first interface 1101 and the external host 12 can be referred to as a first format, for example, when an external host When the interface of 12 is a USB1.0, USB2.0, or USB3.0 interface, the first interface 1101 is a matched USB interface, and the data of the first format is USB data.
  • the interface type for the first interface 1101 is not enumerated here, and the data of the first format is not limited to USB data.
  • the second interface 1102 can be a hardware interface supporting the NVME protocol, such as a PCIE interface, a U.2 interface, or the like.
  • the data processing device 110 When the data processing device 110 receives data through one of the interfaces, it converts to a data format corresponding to another interface and transmits it through another interface.
  • the flow of the data format conversion can be triggered by the external host 12, for example, when the data processing device 110 receives the write command of the external host 12, the first interface 1101
  • the received data of the first format is converted into the data of the NVME protocol format, and when the read command of the external host 12 is received, the data of the NVME protocol format in the NVME solid state hard disk is converted into the data of the first format, and sent to the external Host.
  • the write command may refer to an instruction that the external host 12 performs a write operation to the NVME solid state drive 11
  • the read command may refer to an instruction of the external host 12 to read the data in the NVME solid state drive 11.
  • the information carried by the write command or the read command can be determined according to different design requirements. For example, in some occasions, the write command or the read command can carry information such as the data storage address and the length of the read/write data.
  • the data processing device 110 When receiving the write command of the external host 12, the data processing device 110 converts the format of the write data carried by the write command into the NVME protocol format, and then writes the address space corresponding to the NVME solid state hard disk 11; upon receiving the external host 12 When the command is read, the data of the NVME protocol format is read from the address space corresponding to the read command in the NVME solid state hard disk 11 and converted into the data of the first format and sent to the external host 12.
  • the dedicated chip may be an ASIC (Application Specific Integrated Circuit) chip or a programmable device such as an FPGA (Field-Programmable Gate Array).
  • the functions of the data processing device 110 can be implemented by one chip, and some of the functions can be separately performed by different chips.
  • the chip can realize the corresponding functions through a software program, and can also implement corresponding functions through hardware forms such as circuits.
  • the data processing device 110 of FIG. 2 includes a first chip 1103 and a second chip 1104.
  • the two chips are connected by at least one inter-chip interface 1105.
  • the type of inter-chip interface 1105 can be determined by the type of two chips.
  • the first chip 1103 may be a USB PHY chip
  • the second chip 1104 may be an FPGA chip.
  • a parallel interface may be used as an inter-chip interface between two chips.
  • the parallel interface may be a GPIF (general programmable). Interface) General programmable interface.
  • the first interface 1101 is located on the first chip 1103, and the second interface 1102 is located on the second chip 1104.
  • the conversion process of the data between the first format and the NVME format can be further refined into multiple conversions.
  • the first chip 1103 has a read command or a write command from the first device to the second chip, and data format conversion and data transfer between the external host 12 and the second chip 1104.
  • second core The slice 1104 has a function of data format conversion and data transfer between the first chip 1103 and the NVME solid state hard disk 11 based on a read command or a write command. So in this example, the data conversion process can include the following process:
  • the write command and the write data of the first format carried by the write command are converted into the data format corresponding to the inter-chip interface 1105 (for example, Parallel interface data), and the converted data is sent to the second chip 1104 through the inter-chip interface 1105; the second chip 1104 analyzes the received write command, and converts the received write data into data in the NVME protocol format.
  • the corresponding address space of the NVME solid state hard disk 11 is then written through the second interface 1102.
  • the read command is converted into a data format corresponding to the inter-chip interface 1105 (for example, parallel interface data), and is converted by the inter-chip interface 1105.
  • the subsequent read command is sent to the second chip 1104; the second chip 1104 analyzes the received read command, reads the data in the NVME protocol format from the corresponding address space of the NVME solid state hard disk 11 through the second interface 1102, and then reads the data.
  • the data is converted into a data format corresponding to the inter-chip interface 1105, and is sent to the first chip 1103 through the inter-chip interface 1105.
  • the first chip 1103 converts the data into the first format. And transmitted to the external host 12 through the first interface 1101.
  • data from the external host 12 or data from the NVME solid state hard disk 11 may be cached before the data format conversion is performed, and then the conversion operation is performed. This will be described with reference to FIG. 3.
  • the second chip 1104 may have an internal cache 1107 inside, which may buffer data from the inter-chip interface 1105 of the second chip 1104 and the NVME solid state drive 11 through the internal cache 1107.
  • the data processing device 110 may further include a cache chip 1106 located outside the second chip 1104 and connected to the second chip 1104.
  • the inter-chip interface 1105 and NVME from the second chip 1104 may be utilized by the cache chip 1106.
  • the data of the solid state drive 11 is buffered.
  • the second chip 1104 can implement data exchange with the cache chip 1106 through a cache chip control module (not shown in this figure).
  • the data processing device 110 may further include an independent power supply module that is independent of the power supply of the first interface 1101.
  • the maximum power input capability of the independent power supply module may be greater than The maximum power input capability of the first interface 1101
  • the data processing device 110 may further include a power interface for supplying power to the first chip 1103 or the second chip 1104 by connecting an external power source.
  • the second chip 1104 may have a plurality of software or hardware modules to implement some of the functions of the second chip 1104.
  • 4 is a schematic illustration of the internal structure of a second chip 1104.
  • a DDR (Double Data Rate) chip 1106a is used as the cache chip 1106 for description.
  • the second chip 1104 includes a DMA (Direct Memory Access) module 1104a, a processing module 1104b, and a second interface driver module 1104c connected to the second interface 1102.
  • DMA Direct Memory Access
  • processing module 1104b the processing module 1104b
  • second interface driver module 1104c connected to the second interface 1102.
  • the DMA module 1104a can store the read/write command of the external host 12 into the DDR chip 1106a, notify the processing module 1104b of the cache address, and read data from the DDR chip 1106a according to the cache address notified by the processing module 1104b, and pass the slice.
  • the inter-interface 1105 is transmitted to the first chip 1103; as an example, the DMA module can support the DMA data transfer mode.
  • the processing module 1104b may acquire a read instruction according to the cache address notified by the DMA module 1104a, and analyze the read instruction to determine an access parameter including a corresponding address space (eg, a source address, a destination address, an address length of the read/write data), according to the access.
  • the parameter accesses the NVME solid state hard disk by using the second interface driving module 1104c, caches the data returned by the NVME solid state hard disk in the DDR chip 1106a, and notifies the DMA module 1104a of the buffer address of the data; or
  • the DDR control module 1104d connects the DDR chip 1106a and the processing module 1104b.
  • the read and write operations of the internal data of the DDR chip 1106a can be completed by the processing module 1104b controlling the DDR control module 1104d.
  • FIG. 5 is a schematic diagram of the application scenario.
  • the application scenario of FIG. 5 includes an image capture system 50 and an image processing device 515.
  • the image capture system 50 primarily includes an image capture device 510 and a data conversion device 10, which may be referred to as a card reader.
  • the image capturing device 510 can include a cloud platform that can be detachably mounted on the drone, and the pan/tilt can be used to carry a camera and stabilize the camera.
  • the NVME SSD 11 is used as the data storage device of the image capturing device 510.
  • the image capturing device 510 includes a PCIE interface 511, which can be embodied as a PCIE interface slot, and can be detachably connected to the NVME SSD 11.
  • the image data is written into the NVME solid state hard disk 11 through the PCIE interface 511, and the NVME solid state hard disk 11 can be taken from the PCIE interface 511 when the user needs it.
  • the slot is taken out and inserted into the data conversion device 10 to exchange data with the image processing device 515, and the data conversion device 10 can be connected to the image processing device 515 via the USB connection line 514.
  • the data conversion device 10 includes at least one chip that provides a hardware interface and a data conversion function.
  • a PCIE interface 513 is provided, and the NVME solid state hard disk 11 is detachably connected.
  • the PCIE interface 513 can be a slot for the NVME solid state hard disk 11 to be inserted.
  • the chip further provides a USB interface 512 for connecting to an external image processing device 515.
  • the data conversion device 10 can also provide power status indication, read/write status indication and the like through the chip. Accordingly, the data conversion device 10 can also have an output interface such as a power indicator light and a read/write indicator.
  • the write command data format is USB data
  • the chip can convert the USB data into the NVME protocol format data and send it to the NVME solid state hard disk 11; after receiving the image processing
  • the NVME protocol format data is converted into USB data and sent to the image processing device 515.
  • the data conversion device 10 can be exemplified with reference to FIG. 6 and FIG. 2 to FIG. 5 .
  • the data conversion device 10 can also include the USB PHY chip 601 (corresponding to the first chip 1103 ). And an FPGA chip (equivalent to the second chip 1104).
  • the USB interface of the USB PHY chip is USB3.0 interface, and the model of the USB PHY chip can be CY3014.
  • the FPGA chip 602 has a PCIE interface.
  • the USB PHY chip 601 and the FPGA chip 602 are parallel interfaces, and a GPIF interface can be adopted.
  • the USB PHY chip 601 implements mutual conversion of the USB protocol to the parallel interface. Since the USB protocol-related functions are completed by the USB PHY chip 601, the FPGA chip 602 can simplify the FPGA chip 602 without considering a complicated USB protocol. The difficulty of implementing the internal functions, that is, although the introduction of the USB PHY chip will increase the hardware cost, the FPGA development cost can be greatly reduced, and the overall cost still has considerable advantages.
  • the FPGA chip 602 includes a USB_DMA module 6022, a CPU 6021, a PCIE driver module 6024, and a DDR control module 6023. These function modules can be implemented programmatically.
  • the USB_DMA module 6022 interacts with the USB PHY chip 601 through a parallel interface and other control signal interfaces, and can implement data transmission and reception of the FPGA chip 602 and the USB PHY chip 601. From the data writing direction, the USB_DMA module 6022 is buffered into the DDR chip 1106a after receiving the data from the USB PHY chip; from the data reading direction, the USB_DMA module 6022 can read data from the DDR chip 1106a. To the USB PHY chip 601, the USB_DMA module 6022 can improve the data transmission efficiency, reduce the CPU load inside the FPGA, avoid the read/write speed drop caused by the CPU bottleneck, and increase the read/write data bandwidth as much as possible.
  • the FPGA chip 602 is connected to the NVME solid state hard disk 11 through the PCIE interface to implement data transmission and reception of the FPGA chip 602 and the NVME solid state hard disk 11.
  • the processor CPU 6021 (equivalent to the processing module 1104b) on the FPGA chip 602 manages the transfer of data from the two interfaces of the FPGA chip 602 such that the external host 12 needs to access the NVME solid state drive 11 through the FPGA chip 602.
  • the CPU 6021 interacts with the USB_DMA module 6022, the PCIE driver module 6024, and the DDR control module 6023 via the AXI bus.
  • the external host 12 When the external host 12 needs to write data to the NVME solid state hard disk 11, the external host 12 sends USB data to the USB PHY chip 601 according to a customized command format through the USB interface, and the USB PHY chip 601 receives the data of the external host 12 and then USB.
  • the data is converted into parallel interface data and sent to the USB_DMA module 6022 inside the FPGA chip 602.
  • the USB_DMA module 6022 After receiving the data, the USB_DMA module 6022 writes the address of the preset DDR chip 1106a, and then generates an interrupt to notify the CPU 6021 inside the FPGA chip 602.
  • the CPU 6021 analyzes the notification message to obtain the destination address to be written to the NVME SSD 11, and then the CPU 6021 converts the data acquired from the DDR chip 1106a into data in the NVME protocol format, and transmits the NVME IO WRITE to the NVME solid state drive 11.
  • the command carries the data to be written in the NVME IO WRITE command and writes to the NVNE SSD 11.
  • the external host 12 When the external host 12 needs to read data from the NVME solid state hard disk 11, first, the external host 12 sends a read command to the USB PHY chip 601 according to a predefined format through the USB interface, and the USB PHY chip 601 receives the read command and converts it into parallel interface data. Forwarded to the USB_DMA module 6022 inside the FPGA chip 602, the USB_DMA module 6022 writes a predefined DDR address after receiving the read command, and then generates an interrupt, informing the CPU 6021 on the FPGA chip 602 that the CPU 6021 analyzes the read command and acquires the read.
  • the CPU 6021 controls the PCIE driver module 6024 to send an NVME IO READ command to the NVME solid state disk 11 according to the access parameters, and the NVME solid state disk 11 sends the NVME protocol format data to the DDR through the PCIE interface according to the access parameters.
  • the CPU 6021 then reads the data of the NVME protocol format from the DDR chip 1106a and converts it into parallel interface data, and the control DMA module 6023 transmits the converted parallel interface data to the external host 12.
  • a DDR chip 1106a is connected to the periphery of the FPGA for data buffering. Data from both the external host 12 and the NVME SSD 11 can be cached in the DDR chip 1106a, and the data is managed by the CPU 6021 on the FPGA chip 602. .
  • the data conversion device 10 can provide the FPGA chip 602, the USB PHY chip 601, and the NVME solid state disk 11 through the DC power supply of the DC power supply interface. power supply.
  • the image processing device 515 does not need to implement the NVME protocol, and the NVME protocol is implemented by the FPGA chip 602.
  • the image processing device 515 only needs to use the NVME solid state hard disk 11 as a general large-capacity storage device, so that the existing device is not required to be modified.
  • the embodiments provided are more versatile.
  • FIG. 7 is a partial schematic structural view of a chip 70 in another embodiment.
  • the chip 70 can be used as a component of the structure of the data conversion device 10 described above, or can provide corresponding functions for a part of other products.
  • the chip 70 includes a second interface 1102, a parallel interface 702, and a protocol conversion device 701;
  • the second interface 1102 can be connected to the NVME solid state hard disk 11 and can be, for example, a PCIE interface, a U.2 interface, or the like.
  • the parallel interface 702 is connected to an external device (such as the first chip 1103 in FIG. 2, but does not exclude the connection of other external devices).
  • the function of the protocol conversion device 701 can be similar to that of the second chip 1104 in FIGS. 2 and 3.
  • the format of the write data carried by the write command may be converted into an NVME protocol format, and then sent to the second interface 1102 to be written to the NVME solid state hard disk 11;
  • the NVME protocol format data in the NVME solid state hard disk is converted into parallel interface data and sent to the parallel interface 702 when a read command from the external device is received.
  • the type of the chip 70 may be a chip having a programming function, such as an FPGA chip or the like.
  • the function of the protocol conversion device 701 can be implemented by software or by hardware or a combination of hardware and software.
  • the protocol conversion device 701 may include a plurality of functional modules to cooperatively perform the functions of the protocol conversion device 701.
  • the function module may have a DMA module 1104a, a second interface driver module 1104c connected to the second interface 1102, and a processing module 1104b.
  • the functions of the modules and the principle of cooperative operation may refer to the description of the corresponding module in FIG. I will not repeat them here.
  • the chip 70 can also be connected to a cache chip.
  • the cache chip is exemplified by a DDR chip 1106a.
  • the chip can also include a DDR control module 1104d.
  • the chip can pass the DDR control module before performing data format conversion. 1104d first caches data from an external device or data from an NVME solid state drive into DDR chip 1106a.
  • FIG. 10 is a partial structural schematic view of an embodiment of another chip.
  • the chip 90 has more data conversion functions than the chip of FIG. 7.
  • the chip 90 can be used to implement some functions of the data conversion device 10, and can also achieve its functions on other products that require data conversion.
  • the chip 90 includes a second interface 1102, a USB interface 901, and a protocol conversion device 902;
  • the second interface 1102 is connected to the NVME solid state hard disk 11 through the USB interface 901.
  • the second interface 1102 may be an interface supporting the NVME protocol such as a PCIE interface.
  • the protocol conversion device 902 in the chip 90 may have a function of directly converting data of USB data and NVME protocol format to each other.
  • the process can be embodied as: converting the USB data into the NVME protocol format data, and sending the data to the second interface 1102; and when receiving the read command from the external host, converting the NVME protocol format data in the NVME solid state hard disk 11 into USB data, Give the USB interface 901.
  • Figure 11 provides a partial flow of an embodiment of a data conversion method.
  • the various steps of the flow can be performed by the data conversion device 10, but the method is not limited to being executable only by this device.
  • step S110 receiving a write command or a read command of an external host
  • the data conversion between the data of the first format and the data of the NVME protocol format can be performed in stages. For example, when the data of the first format is converted into the data of the NVME protocol format, the write command can be written first. The data is converted into parallel interface data, and the parallel interface data is converted into data of the NVME protocol format; when the data of the NVME protocol format needs to be converted into the data of the first format, the NVME protocol format data can be first converted into a parallel interface. Data, and then converting the parallel interface data into data in a first format.
  • data in the first format can be directly converted into data in the NVME protocol format, or data in the NVME protocol format can be converted into data in the first format (for example, USB data).
  • the method can also be performed by the data conversion device provided by the present application.
  • the embodiment of the data conversion device can be implemented by software, or the device can be loaded into the data conversion device 10 in FIG. 1 or the chip shown in FIG. 7 and FIG. 10 by a combination of software and hardware. Taking the software implementation as an example, as a logical device, it can be described by using FIG. 12-14.
  • the data conversion device 200 may include:
  • the first interface driving module 201 can receive a write command or a read command of the external host 12, and notify the protocol conversion module; and interact with the external host 12 to data in the first format;
  • the second interface driving module 203 can exchange data with the NVME solid state hard disk 11;
  • the protocol conversion module 202 can include a first protocol conversion module 2021 and a second protocol conversion module 2022;
  • the first protocol conversion module 2021 can convert the data of the first format into parallel interface data, and convert the parallel interface data into data of the first format;
  • the second protocol conversion module 2022 can convert the parallel interface data into data in the NVME protocol format; and convert the data in the NVME protocol format into parallel interface data.
  • the second protocol conversion module 2022 may include: a DMA module 2022a and a processing module 2022b;
  • the DMA module 2022a may store the read/write command of the external host 12 into the cache chip 1106, notify the processing module 2022b of the cache address, and transfer the read data from the cache chip 1106 to the first according to the cache address notified by the processing module 2022b.
  • the processing module 2022b may acquire a read command according to the cache address notified by the DMA module 2022a, analyze the read command to determine an access parameter including a corresponding address space, and access the NVME solid state hard disk by using the second interface driving module 203 according to the access parameter,
  • the data returned by the NVME solid state hard disk is cached in the cache chip 1106, and the DMA module 2022a is notified of the cache address of the data; or
  • the data conversion device 200 can be applied to various application scenarios, for example, can be connected to an external host having a USB interface, and thus, the data of the first format can include USB data.
  • each of the logic modules in data conversion device 200 may have similar functionality to the modules of FIG.

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Abstract

L'invention concerne un appareil, une puce, un procédé et un dispositif de conversion de données, et un système d'image. L'appareil de conversion de données comprend un dispositif de traitement de données. Le dispositif de traitement de données comprend une première interface et une seconde interface. La première interface est utilisée pour se connecter à un hôte externe de façon à échanger avec l'hôte externe des données dans un premier format dans les deux sens. La seconde interface est utilisée pour se connecter à un disque transistorisé NVME. A la réception d'une instruction d'écriture provenant de l'hôte externe, le dispositif de traitement de données convertit des données dans le premier format en données dans un format au protocole NVME, et les transmet au disque transistorisé NVME. A la réception d'une instruction de lecture provenant de l'hôte externe, le dispositif de traitement de données convertit des données dans le format au protocole NVME sur le disque transistorisé NVME en données dans le premier format, et les transmet à l'hôte externe.
PCT/CN2016/099210 2016-09-18 2016-09-18 Appareil, puce, procédé et dispositif de conversion de données, et système d'image Ceased WO2018049648A1 (fr)

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