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WO2017136984A1 - N型薄膜晶体管的制作方法 - Google Patents

N型薄膜晶体管的制作方法 Download PDF

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WO2017136984A1
WO2017136984A1 PCT/CN2016/083566 CN2016083566W WO2017136984A1 WO 2017136984 A1 WO2017136984 A1 WO 2017136984A1 CN 2016083566 W CN2016083566 W CN 2016083566W WO 2017136984 A1 WO2017136984 A1 WO 2017136984A1
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layer
temperature polysilicon
film transistor
low temperature
thin film
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French (fr)
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虞晓江
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/119,383 priority Critical patent/US20180069099A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an N-type thin film transistor.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • a Thin Film Transistor In a flat display device, a Thin Film Transistor (TFT) is generally used as a switching element to control a pixel or as a driving element to drive a pixel. Thin film transistors are generally classified into amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) depending on their silicon film properties.
  • a-Si amorphous silicon
  • poly-Si polycrystalline silicon
  • LTPS Low Temperature Poly-Silicon
  • Low-temperature polysilicon film has a high carrier mobility (10 to 300 cm 2 /Vs) due to its atomic arrangement and can be applied to electronic components such as thin film transistors, so that the thin film transistor has a higher driving current, and thus the thin film transistor
  • the LTPS film is widely used as the material of the active layer of one of the core structures of the thin film transistor in the fabrication process.
  • the flat display device using the LTPS thin film transistor has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, and the like, because the silicon crystal arrangement of the LTPS thin film transistor is more ordered than the amorphous silicon, the electron mobility is relatively high. More than double, the peripheral drive circuit can be fabricated on the glass substrate at the same time to achieve the goal of system integration, saving space and cost of driving the IC. At the same time, since the driver IC circuit is directly fabricated on the panel, the external contact of the component can be reduced, and the reliability can be increased. Degree, maintenance is simpler, assembly process time is shortened, and application system design time and design freedom are reduced. Generally, N-type thin film transistors (NTFTs) are often used on planar display devices.
  • NTFTs N-type thin film transistors
  • the threshold voltage of N-type thin film transistors needs to be adjusted (from 1.0V to 1.5).
  • the ion implantation method is generally used to adjust the threshold voltage of the N-type thin film transistor, that is, the low-dose boron ion implantation of the poly-Si of the channel region of the N-type thin film transistor is performed. The threshold voltage of the N-type thin film transistor is adjusted.
  • the existing N-type thin film transistor is manufactured as follows: First, referring to FIG. 1-2, a buffer layer 2 and a low temperature polysilicon layer 31 are sequentially prepared on the substrate 1 from bottom to top; a photoresist layer 5 is coated on the low temperature polysilicon layer 31; and then the photoresist is passed through the mask. The layer 5 is subjected to exposure development, and a channel region 32 is defined on the low temperature polysilicon layer 31; subsequently, a low dose of boron (B) ion implantation is performed on the channel region 32, and then the low temperature polysilicon layer 31 is removed. Next, referring to FIG.
  • the low temperature polysilicon layer 31 is etched and ion doped to form the active layer 3; finally, the active layer 3 is sequentially prepared from bottom to top.
  • the hole carrier concentration of the polysilicon in the channel region 32 is adjusted by implanting boron ions in the channel region 32, and the threshold voltage of the N-type thin film transistor is shifted in the positive direction. The method is carried out under a certain vacuum using an expensive ion implantation apparatus, and the production efficiency is low and the production cost is high.
  • An object of the present invention is to provide a method for fabricating an N-type thin film transistor, which can adjust a threshold voltage of an N-type thin film transistor, ensure that the obtained N-type thin film transistor can be turned off at a low voltage in time, and is simple to manufacture and has high production efficiency. High, low production costs.
  • the present invention provides a method of fabricating an N-type thin film transistor, comprising the following steps:
  • Step 1 Providing a base substrate on which a buffer layer, a low temperature polysilicon layer, and a silicon oxide layer are sequentially prepared from bottom to top, and a surface layer of the low temperature polysilicon layer is oxidized in the air to form a silicon oxide layer;
  • Step 2 coating a photoresist layer on the low-temperature polysilicon layer, and exposing and developing the same on the low-temperature polysilicon layer by using a photomask;
  • Step 3 etching a low temperature polysilicon layer of the channel region by using a chemical solution, removing a silicon oxide layer above the channel region, and etching low temperature polysilicon in the channel region to improve the channel region Surface roughness of low temperature polysilicon;
  • Step 4 performing patterning processing and N-type ion doping on the low temperature polysilicon layer to form an active layer
  • Step 5 sequentially preparing a gate insulating layer, a gate electrode, and an interlayer insulating layer on the active layer and the buffer layer from bottom to top, and insulating the gate insulating layer and the interlayer by using a photolithography process
  • the layer and the silicon oxide layer are patterned to obtain two via holes corresponding to both ends of the active layer;
  • Step 6 Form a source/drain on the interlayer insulating layer, and the source/drain contacts the two ends of the active layer through two via holes.
  • the low temperature polysilicon layer of the channel region is etched by using a tetramethylammonium hydroxide aqueous solution.
  • the low temperature polysilicon layer of the channel region is first oxidized by using hydrogen peroxide, and then the low temperature polysilicon layer of the channel region is etched by using an aqueous solution of ammonium fluoride.
  • the material of the buffer layer, the gate insulating layer, and the interlayer insulating layer is a stack combination of one or more of silicon oxide and silicon nitride.
  • the N-type ions doped in the step 4 are phosphorus ions.
  • the active layer includes a channel region in the middle and an N-type ion doped region at both ends of the channel region.
  • the specific fabrication process of the low-temperature polysilicon layer in the step 1 is: first depositing a layer of amorphous silicon on the buffer layer, and then crystallizing the amorphous silicon to obtain a low-temperature polysilicon layer.
  • the material of the gate and the source/drain is a stack combination of one or more of molybdenum, aluminum, and copper.
  • the invention also provides a method for fabricating an N-type thin film transistor, comprising the following steps:
  • Step 1 Providing a substrate on which a buffer layer and a low temperature polysilicon layer are sequentially prepared from bottom to top, and a surface layer of the low temperature polysilicon layer is oxidized in the air to form a silicon oxide layer;
  • Step 2 coating a photoresist layer on the low-temperature polysilicon layer, and exposing and developing the same on the low-temperature polysilicon layer by using a photomask;
  • Step 3 etching a low temperature polysilicon layer of the channel region by using a chemical solution, removing a silicon oxide layer above the channel region, and etching low temperature polysilicon in the channel region to improve the channel region Surface roughness of low temperature polysilicon;
  • Step 4 performing patterning processing and N-type ion doping on the low temperature polysilicon layer to form an active layer
  • Step 5 sequentially preparing a gate insulating layer, a gate electrode, and an interlayer insulating layer on the active layer and the buffer layer from bottom to top, and insulating the gate insulating layer and the interlayer by using a photolithography process
  • the layer and the silicon oxide layer are patterned to obtain two via holes corresponding to both ends of the active layer;
  • Step 6 forming a source/drain on the interlayer insulating layer, the source/drain being in contact with both ends of the active layer through two via holes;
  • the material of the buffer layer, the gate insulating layer, and the interlayer insulating layer is a stack combination of one or more of silicon oxide and silicon nitride;
  • the active layer includes a channel region located in the middle and an N-type ion doped region located at both ends of the channel region.
  • the present invention provides a method for fabricating an N-type thin film transistor in which a channel region of an N-type thin film transistor is etched using a chemical solution to improve a channel region of the N-type thin film transistor
  • the surface roughness of the low-temperature polysilicon thereby increasing the surface defect concentration of the low-temperature polysilicon in the channel region of the N-type thin film transistor, so that the N-type film is made thin
  • the threshold voltage of the membrane transistor is moved in the positive direction to ensure that the obtained N-type thin film transistor can be turned off at a low voltage in time.
  • the method uses a cheaper device and can simultaneously produce multiple substrates. It can reduce production costs and increase production efficiency.
  • FIG. 1 is a schematic view showing exposure of a photoresist layer in a process of fabricating a conventional N-type thin film transistor
  • FIG. 2 is a schematic view showing ion doping of a channel region in a process of fabricating a conventional N-type thin film transistor
  • FIG. 3 is a schematic structural view of a conventional N-type thin film transistor
  • FIG. 4 is a schematic flow chart of a method of fabricating an N-type thin film transistor of the present invention.
  • step 1 is a schematic diagram of step 1 of a method of fabricating an N-type thin film transistor of the present invention
  • step 2 is a schematic diagram of step 2 of a method of fabricating an N-type thin film transistor of the present invention
  • step 3 is a schematic view showing a first embodiment of step 3 of the method for fabricating an N-type thin film transistor of the present invention.
  • step 8 is a schematic view showing a second embodiment of step 3 of the method for fabricating an N-type thin film transistor of the present invention.
  • step 4 is a schematic diagram of step 4 of a method of fabricating an N-type thin film transistor of the present invention.
  • step 5 is a schematic diagram of step 5 of a method of fabricating an N-type thin film transistor of the present invention.
  • Figure 11 is a schematic view showing the sixth step of the method of fabricating the N-type thin film transistor of the present invention.
  • the present invention provides a method for fabricating an N-type thin film transistor, comprising the following steps:
  • Step 1 a substrate 10 is provided on which a buffer layer 20 and a low temperature polysilicon layer 310 are sequentially prepared.
  • the surface layer of the low temperature polysilicon layer 310 is oxidized in the air to form silicon oxide.
  • Layer 40 is oxidized in the air to form silicon oxide.
  • the material of the buffer layer 20 is a heap of one or more of silicon oxide and silicon nitride. Stack combination.
  • the low-temperature polysilicon layer 310 is specifically formed by depositing a layer of amorphous silicon on the buffer layer 20 and then crystallizing the amorphous silicon to obtain a low-temperature polysilicon layer 310.
  • Step 2 referring to FIG. 6, after the photoresist layer 50 is coated on the low temperature polysilicon layer 310, and exposed and developed by a photomask, a channel region 320 is defined on the low temperature polysilicon layer 310.
  • Step 3 referring to FIG. 7 and FIG. 8, etching the low temperature polysilicon layer 310 of the channel region 320 with a chemical solution, removing the silicon oxide layer 40 above the channel region 320, and the channel region 320 is removed.
  • the low temperature polysilicon is etched to increase the surface roughness of the low temperature polysilicon in the channel region 320.
  • the low temperature polysilicon layer 310 of the channel region 320 is etched by using an aqueous solution of Tetramethylammonium Hydroxide (TMAH).
  • TMAH Tetramethylammonium Hydroxide
  • the mass percentage of tetramethylammonium hydroxide in the aqueous solution of tetramethylammonium hydroxide is 5% to 30%.
  • the low temperature polysilicon layer 310 of the channel region 320 is further oxidized by using hydrogen peroxide to make the thickness of the silicon oxide layer 40 of the surface layer more uniform, and then fluorine is used.
  • An aqueous solution of ammonium (NH 4 F) etches the low temperature polysilicon layer 310 of the channel region 320.
  • hydrogen peroxide and NH 4 F solutions can be recycled multiple times.
  • the volume percentage of hydrogen peroxide (H 2 O 2 ) in the hydrogen peroxide is 20% to 80%; and the mass percentage of ammonium fluoride in the aqueous ammonium fluoride solution is 3% to 20%.
  • etching the channel region of the N-type thin film transistor with a chemical solution can improve the surface roughness of the low-temperature polysilicon in the channel region of the N-type thin film transistor, thereby improving the channel of the N-type thin film transistor.
  • the surface defect concentration of the low-temperature polysilicon in the region causes the threshold voltage of the obtained N-type thin film transistor to move in the positive direction, compared with the conventional method for adjusting the threshold voltage of the NTFT by boron ion implantation, which is used for chemical solution etching.
  • the equipment is cheaper, and it is also possible to simultaneously produce multiple substrates, thereby reducing production costs and improving production efficiency.
  • Step 4 referring to FIG. 9, the low temperature polysilicon layer 310 is patterned and N-type ion doped to form the active layer 30.
  • the N-type ion doped in the step 4 is a phosphorus ion.
  • the active layer 30 includes a channel region 320 in the middle and an N-type ion doping region 330 at both ends of the channel region 320.
  • the channel region 320 is a low temperature polysilicon that is not ion doped.
  • Step 5 referring to FIG. 10, the gate insulating layer 60, the gate electrode 70, and the interlayer insulating layer 80 are sequentially prepared from the bottom layer on the active layer 30 and the buffer layer 20, and a photolithography process is used.
  • the gate insulating layer 60, the interlayer insulating layer 80, and the silicon oxide layer 40 are patterned to obtain two via holes 81 corresponding to both ends of the active layer 30.
  • the material of the gate insulating layer 60 and the interlayer insulating layer 80 is a stack combination of one or more of silicon oxide and silicon nitride.
  • Step 6 a source/drain 90 is formed on the interlayer insulating layer 80.
  • the source/drain 90 is in contact with both ends of the active layer 30 through two via holes 81.
  • the material of the gate 70 and the source/drain 90 is a stack combination of one or more of molybdenum, aluminum, and copper.
  • the present invention provides a method for fabricating an N-type thin film transistor in which a channel region of an N-type thin film transistor is etched using a chemical solution to improve a channel region of the N-type thin film transistor.
  • the surface roughness of the low-temperature polysilicon thereby increasing the surface defect concentration of the low-temperature polysilicon in the channel region of the N-type thin film transistor, and moving the threshold voltage of the obtained N-type thin film transistor in the positive direction to ensure the obtained N-type
  • the thin film transistor can be turned off at a low voltage in time.
  • the method uses cheaper equipment and can simultaneously produce multiple substrates, which can reduce production cost and improve production efficiency.

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Abstract

一种N型薄膜晶体管的制作方法，在制作过程中采用化学溶液对N型薄膜晶体管的沟道区进行蚀刻，提高N型薄膜晶体管的沟道区内的低温多晶硅的表面粗糙度，从而提高N型薄膜晶体管的沟道区内的低温多晶硅的表面缺陷浓度，使制得的N型薄膜晶体管的阈值电压向正方向移动，保证制得的N型薄膜晶体管在低电压下能及时关闭，生产效率高，生产成本低。

Description

N型薄膜晶体管的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种N型薄膜晶体管的制作方法。
背景技术
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)。
在平面显示器件中，薄膜晶体管(Thin Film Transistor，TFT)一般是用作开关元件来控制像素的作业，或是用作驱动元件来驱动像素。薄膜晶体管依其硅薄膜性质通常可分成非晶硅(a-Si)与多晶硅(poly-Si)两种。
由于非晶硅本身自有的缺陷问题，如缺陷太多导致的开态电流低、迁移率低、稳定性差，使它在应用中受到限制，为了弥补非晶硅本身的缺陷，扩大其在相关领域的应用，低温多晶硅(Low Temperature Poly-Silicon，LTPS)技术应运而生。
低温多晶硅薄膜由于其原子排列规则，载流子迁移率高(10～300cm2/Vs)，应用于薄膜晶体管等电子元器件时，可使薄膜晶体管具有更高的驱动电流，因此在薄膜晶体管的制作工艺中广泛采用LTPS薄膜作为薄膜晶体管的核心结构之一的有源层的材料。
采用LTPS薄膜晶体管的平面显示器件具有高分辨率、反应速度快、高亮度、高开口率等优点，加上由于LTPS薄膜晶体管的硅结晶排列较非晶硅有次序，使得电子移动率相对高100倍以上，可以将外围驱动电路同时制作在玻璃基板上，达到系统整合的目标，节省空间及驱动IC的成本；同时，由于驱动IC线路直接制作于面板上，可以减少组件的对外接点，增加可靠度、维护更简单、缩短组装制程时间，进而减少应用系统设计时程及扩大设计自由度。通常平面显示器件上使用较多的为N型薄膜晶体管(NTFT)，为了使得N型薄膜晶体管在低电压下能及时关闭，需要对N型薄膜晶体管的阈值电压进行调整(从1.0V移动至1.5V左右)，现有技术中，通常采用离子植入的方法来调整N型薄膜晶体管的阈值电压，即对N型薄膜晶体管沟道区的多晶硅(Poly-si)进行低剂量硼离子植入来调整N型薄膜晶体管的阈值电压。
具体地，请参阅图1-图3，现有的N型薄膜晶体管的制作过程如下： 首先，请参阅图1-2，在基板1上自下而上依次制备缓冲层2和低温多晶硅层31；在所述低温多晶硅层31上涂布光阻层5；然后通过光罩对光阻层5进行曝光显影，在所述低温多晶硅层31上定义出沟道区32；随后，对沟道区32进行低剂量的硼(B)离子植入，接着，去除所述低温多晶硅层31上的光阻层5；接下来，请参阅图3，对所述低温多晶硅层31进行蚀刻和离子掺杂，形成有源层3；最后，在所述有源层3上自下而上依次制备栅极绝缘层6、栅极7、层间绝缘层8、以及源/漏极9。上述N型薄膜晶体管的制作过程中通过在沟道区32植入硼离子来调节沟道区32内的多晶硅的空穴载流子浓度，使N型薄膜晶体管的阈值电压向正方向移动，然而该方法要用昂贵的离子植入设备在一定真空下进行，生产效率较低，生产成本较高。
发明内容
本发明的目的在于提供一种N型薄膜晶体管的制作方法，该方法能够调节N型薄膜晶体管的阈值电压，保证制得的N型薄膜晶体管在低电压下能及时关闭，且制作简单，生产效率高，生产成本低。
为实现上述目的，本发明提供了一种N型薄膜晶体管的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上自下而上依次制备缓冲层、低温多晶硅层与氧化硅层所述低温多晶硅层的表层在空气中被氧化形成氧化硅层；
步骤2、在所述低温多晶硅层上涂布光阻层，并采用光罩对其进行曝光、显影后，在所述低温多晶硅层上定义出沟道区；
步骤3、采用化学溶液对所述沟道区的低温多晶硅层进行蚀刻，去除所述沟道区上方的氧化硅层，并对沟道区内的低温多晶硅进行蚀刻，提高所述沟道区内的低温多晶硅的表面粗糙度；
步骤4、对所述低温多晶硅层进行图案化处理和N型离子掺杂，形成有源层；
步骤5、在所述有源层、及缓冲层上自下而上依次制备栅极绝缘层、栅极、及层间绝缘层，采用一道光刻制程对所述栅极绝缘层、层间绝缘层、及氧化硅层进行图形化处理，得到对应于所述有源层两端的两过孔；
步骤6、在所述层间绝缘层上形成源/漏极，所述源/漏极通过两过孔与所述有源层的两端相接触。
可选的，所述步骤3中采用四甲基氢氧化铵水溶液对所述沟道区的低温多晶硅层进行蚀刻。
可选的，所述步骤3中先采用双氧水对所述沟道区的低温多晶硅层进行氧化处理，之后再采用氟化铵水溶液对所述沟道区的的低温多晶硅层进行蚀刻。
所述缓冲层、栅极绝缘层、及层间绝缘层的材料均为氧化硅、氮化硅中的一种或多种的堆栈组合。
所述步骤4中掺杂的N型离子为磷离子。
所述有源层包括位于中间的沟道区和位于所述沟道区两端的N型离子掺杂区。
所述步骤1中低温多晶硅层的具体制作过程为：先在所述缓冲层上沉积一层非晶硅，再对非晶硅进行晶化处理，制得低温多晶硅层。
所述栅极与源/漏极的材料均为钼、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种N型薄膜晶体管的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上自下而上依次制备缓冲层与低温多晶硅层，所述低温多晶硅层的表层在空气中被氧化形成氧化硅层；
步骤2、在所述低温多晶硅层上涂布光阻层，并采用光罩对其进行曝光、显影后，在所述低温多晶硅层上定义出沟道区；
步骤3、采用化学溶液对所述沟道区的低温多晶硅层进行蚀刻，去除所述沟道区上方的氧化硅层，并对沟道区内的低温多晶硅进行蚀刻，提高所述沟道区内的低温多晶硅的表面粗糙度；
步骤4、对所述低温多晶硅层进行图案化处理和N型离子掺杂，形成有源层；
步骤5、在所述有源层、及缓冲层上自下而上依次制备栅极绝缘层、栅极、及层间绝缘层，采用一道光刻制程对所述栅极绝缘层、层间绝缘层、及氧化硅层进行图形化处理，得到对应于所述有源层两端的两过孔；
步骤6、在所述层间绝缘层上形成源/漏极，所述源/漏极通过两过孔与所述有源层的两端相接触；
其中，所述缓冲层、栅极绝缘层、及层间绝缘层的材料均为氧化硅、氮化硅中的一种或多种的堆栈组合；
其中，所述有源层包括位于中间的沟道区和位于所述沟道区两端的N型离子掺杂区。
本发明的有益效果：本发明提供一种N型薄膜晶体管的制作方法，在制作过程中采用化学溶液对N型薄膜晶体管的沟道区进行蚀刻，提高所述N型薄膜晶体管的沟道区内的低温多晶硅的表面粗糙度，从而提高所述N型薄膜晶体管的沟道区内的低温多晶硅的表面缺陷浓度，使制得的N型薄 膜晶体管的阈值电压向正方向移动，保证制得的N型薄膜晶体管在低电压下能及时关闭，相比于现有技术，该方法使用更便宜的设备并且能做到多片基板同时生产，能够降低生产成本，提升生产效率。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的N型薄膜晶体管的制作过程中对光阻层进行曝光的示意图；
图2为现有的N型薄膜晶体管的制作过程中对沟道区进行离子掺杂的示意图；
图3为现有的N型薄膜晶体管的结构示意图；
图4为本发明的N型薄膜晶体管的制作方法的示意流程图；
图5为本发明的N型薄膜晶体管的制作方法的步骤1的示意图；
图6为本发明的N型薄膜晶体管的制作方法的步骤2的示意图；
图7为本发明的N型薄膜晶体管的制作方法的步骤3的第一实施例的示意图；
图8为本发明的N型薄膜晶体管的制作方法的步骤3的第二实施例的示意图；
图9为本发明的N型薄膜晶体管的制作方法的步骤4的示意图；
图10为本发明的N型薄膜晶体管的制作方法的步骤5的示意图；
图11为本发明的N型薄膜晶体管的制作方法的步骤6的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图4，本发明提供一种N型薄膜晶体管的制作方法，包括如下步骤：
步骤1、请参阅图5，提供一衬底基板10，在所述衬底基板10上依次制备缓冲层20与低温多晶硅层310，所述低温多晶硅层310的表层在空气中被氧化形成氧化硅层40。
具体地，所述缓冲层20的材料为氧化硅、氮化硅中的一种或多种的堆 栈组合。所述低温多晶硅层310的具体制作过程为：先在所述缓冲层20上沉积一层非晶硅，再对非晶硅进行晶化处理，制得低温多晶硅层310。
步骤2、请参阅图6，在所述低温多晶硅层310上涂布光阻层50，并采用光罩对其进行曝光、显影后，在所述低温多晶硅层310上定义出沟道区320。
步骤3、请参阅图7和图8，采用化学溶液对所述沟道区320的低温多晶硅层310进行蚀刻，去除所述沟道区320上方的氧化硅层40，并对沟道区320内的低温多晶硅进行蚀刻，提高所述沟道区320内的低温多晶硅的表面粗糙度。
可选地，请参阅图7，所述步骤3中采用四甲基氢氧化铵(Tetramethylammonium Hydroxide，TMAH)水溶液对所述沟道区320的低温多晶硅层310进行蚀刻。优选的，所述四甲基氢氧化铵水溶液中四甲基氢氧化铵的质量百分比为5％～30％。
可选地，请参阅图8，所述步骤3中先采用双氧水对所述沟道区320的低温多晶硅层310进行进一步氧化处理，使得表层的氧化硅层40的厚度更加均匀，之后再采用氟化铵(NH4F)水溶液对所述沟道区320的低温多晶硅层310进行蚀刻。其中，双氧水和NH4F溶液可多次循环使用。优选的，所述双氧水中过氧化氢(H2O2)的体积百分比为20％～80％；所述氟化铵水溶液中氟化铵的质量百分比为3％～20％。
特别地，采用化学溶液对N型薄膜晶体管的沟道区进行蚀刻，能够提高所述N型薄膜晶体管的沟道区内的低温多晶硅的表面粗糙度，从而提高所述N型薄膜晶体管的沟道区内的低温多晶硅的表面缺陷浓度，使制得的N型薄膜晶体管的阈值电压向正方向移动，相比于现有的通过硼离子植入来调节NTFT阈值电压的方法，化学溶液蚀刻所使用的设备更加便宜，还能够多片基板同时生产，进而降低生产成本，提升生产效率。
步骤4、请参阅图9，对所述低温多晶硅层310进行图案化处理和N型离子掺杂，形成有源层30。
具体地，所述步骤4掺杂的N型离子为磷离子。所述有源层30包括位于中间的沟道区320和位于所述沟道区320两端的N型离子掺杂区330。沟道区320为未进行离子掺杂的低温多晶硅。
步骤5、请参阅图10，在所述有源层30、及缓冲层20上自下而上依次制备栅极绝缘层60、栅极70、及层间绝缘层80，采用一道光刻制程对所述栅极绝缘层60、层间绝缘层80、及氧化硅层40进行图形化处理，得到对应于所述有源层30两端的两过孔81。
具体地，所述栅极绝缘层60、及层间绝缘层80的材料均为氧化硅、氮化硅中的一种或多种的堆栈组合。
步骤6、请参阅图11，在所述层间绝缘层80上形成源/漏极90，所述源/漏极90通过两过孔81与所述有源层30的两端相接触。
具体地，所述栅极70与源/漏极90的材料均为钼、铝、铜中的一种或多种的堆栈组合。
综上所述，本发明提供一种N型薄膜晶体管的制作方法，在制作过程中采用化学溶液对N型薄膜晶体管的沟道区进行蚀刻，提高所述N型薄膜晶体管的沟道区内的低温多晶硅的表面粗糙度，从而提高所述N型薄膜晶体管的沟道区内的低温多晶硅的表面缺陷浓度，使制得的N型薄膜晶体管的阈值电压向正方向移动，保证制得的N型薄膜晶体管在低电压下能及时关闭，相比于现有技术，该方法使用更便宜的设备并且能做到多片基板同时生产，能够降低生产成本，提升生产效率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种N型薄膜晶体管的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上自下而上依次制备缓冲层与低温多晶硅层，所述低温多晶硅层的表层在空气中被氧化形成氧化硅层；
    步骤2、在所述低温多晶硅层上涂布光阻层，并采用光罩对其进行曝光、显影后，在所述低温多晶硅层上定义出沟道区；
    步骤3、采用化学溶液对所述沟道区的低温多晶硅层进行蚀刻，去除所述沟道区上方的氧化硅层，并对沟道区内的低温多晶硅进行蚀刻，提高所述沟道区内的低温多晶硅的表面粗糙度；
    步骤4、对所述低温多晶硅层进行图案化处理和N型离子掺杂，形成有源层；
    步骤5、在所述有源层、及缓冲层上自下而上依次制备栅极绝缘层、栅极、及层间绝缘层，采用一道光刻制程对所述栅极绝缘层、层间绝缘层、及氧化硅层进行图形化处理，得到对应于所述有源层两端的两过孔；
    步骤6、在所述层间绝缘层上形成源/漏极，所述源/漏极通过两过孔与所述有源层的两端相接触。
  2. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述步骤3中采用四甲基氢氧化铵水溶液对所述沟道区的低温多晶硅层进行蚀刻。
  3. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述步骤3中先采用双氧水对所述沟道区的低温多晶硅层进行氧化处理，之后再采用氟化铵水溶液对所述沟道区的低温多晶硅层进行蚀刻。
  4. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述缓冲层、栅极绝缘层、及层间绝缘层的材料均为氧化硅、氮化硅中的一种或多种的堆栈组合。
  5. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述步骤4中掺杂的N型离子为磷离子。
  6. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述有源层包括位于中间的沟道区和位于所述沟道区两端的N型离子掺杂区。
  7. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述步骤1中低温多晶硅层的具体制作过程为：先在所述缓冲层上沉积一层非晶硅，再对非晶硅进行晶化处理，制得低温多晶硅层。
  8. 如权利要求1所述的N型薄膜晶体管的制作方法，其中，所述栅极 与源/漏极的材料均为钼、铝、铜中的一种或多种的堆栈组合。
  9. 一种N型薄膜晶体管的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上自下而上依次制备缓冲层与低温多晶硅层，所述低温多晶硅层的表层在空气中被氧化形成氧化硅层；
    步骤2、在所述低温多晶硅层上涂布光阻层，并采用光罩对其进行曝光、显影后，在所述低温多晶硅层上定义出沟道区；
    步骤3、采用化学溶液对所述沟道区的低温多晶硅层进行蚀刻，去除所述沟道区上方的氧化硅层，并对沟道区内的低温多晶硅进行蚀刻，提高所述沟道区内的低温多晶硅的表面粗糙度；
    步骤4、对所述低温多晶硅层进行图案化处理和N型离子掺杂，形成有源层；
    步骤5、在所述有源层、及缓冲层上自下而上依次制备栅极绝缘层、栅极、及层间绝缘层，采用一道光刻制程对所述栅极绝缘层、层间绝缘层、及氧化硅层进行图形化处理，得到对应于所述有源层两端的两过孔；
    步骤6、在所述层间绝缘层上形成源/漏极，所述源/漏极通过两过孔与所述有源层的两端相接触；
    其中，所述缓冲层、栅极绝缘层、及层间绝缘层的材料均为氧化硅、氮化硅中的一种或多种的堆栈组合；
    其中，所述有源层包括位于中间的沟道区和位于所述沟道区两端的N型离子掺杂区。
  10. 如权利要求9所述的N型薄膜晶体管的制作方法，其中，所述步骤3中采用四甲基氢氧化铵水溶液对所述沟道区的低温多晶硅层进行蚀刻。
  11. 如权利要求9所述的N型薄膜晶体管的制作方法，其中，所述步骤3中先采用双氧水对所述沟道区的低温多晶硅层进行氧化处理，之后再采用氟化铵水溶液对所述沟道区的低温多晶硅层进行蚀刻。
  12. 如权利要求9所述的N型薄膜晶体管的制作方法，其中，所述步骤4中掺杂的N型离子为磷离子。
  13. 如权利要求9所述的N型薄膜晶体管的制作方法，其中，所述步骤1中低温多晶硅层的具体制作过程为：先在所述缓冲层上沉积一层非晶硅，再对非晶硅进行晶化处理，制得低温多晶硅层。
  14. 如权利要求9所述的N型薄膜晶体管的制作方法，其中，所述栅极与源/漏极的材料均为钼、铝、铜中的一种或多种的堆栈组合。
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