WO2017122110A1 - Display device, display module, and electronic instrument - Google Patents

Abstract

Provided is a display device in which transistors are reduced in size and the frame is narrowed. The present invention provides a display device having a first insulating film on a first electroconductive film, a first oxide semiconductor film on the first insulating film, a second insulating film on the first oxide semiconductor film, a second oxide semiconductor film on the second insulating film, and a third insulating film on the first oxide semiconductor film and the second oxide semiconductor film. The display device has a demultiplexer having transistors in which a first electroconductive layer and the second oxide semiconductor film are electrically connected via openings provided in the first insulating film and the second insulating film.

Description

Display device, display module, and electronic device

One embodiment of the present invention relates to a display device, a display module, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

2. Description of the Related Art A technique for forming a transistor (also referred to as a field effect transistor (FET) or a thin film transistor (TFT)) using a semiconductor layer formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to an electronic device such as a display device.

In recent years, electronic devices equipped with a display device having high-definition pixels, such as smartphones, have become widespread. In such a display device of an electronic device, the number of wirings for supplying data signals increases, and the number of output terminals of the source driver increases.

In order to suppress an increase in the number of output terminals of the source driver, a configuration in which a demultiplexer is provided between the source driver and the pixel has been proposed (for example, see Patent Document 1).

International Publication No. 2011/096125

Transistors used in demultiplexers are required to have a high current supply capability. Therefore, in the transistor in the demultiplexer of Patent Document 1, it is necessary that the semiconductor layer has a U-shape (comb shape) and has a large channel width. In this case, there is a problem that the transistor size becomes large and it is difficult to narrow the frame of the display device.

In view of the above problems, an object of one embodiment of the present invention is to provide a display device or the like having a novel structure.

Another object of one embodiment of the present invention is to provide a display device or the like having a novel structure with a narrowed frame. Another object of one embodiment of the present invention is to provide a display device or the like with a novel structure in which pixels can be arranged with high definition. Another object of one embodiment of the present invention is to provide a display device or the like having a novel structure in which an increase in manufacturing cost is suppressed.

Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and / or other problems.

One embodiment of the present invention is a display device including a demultiplexer, the demultiplexer including a transistor, the transistor including a first insulating film over the first conductive film, and the first insulating film over the first insulating film. A first oxide semiconductor film, a second insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the second insulating film, a first oxide semiconductor film, and A third insulating film over the second oxide semiconductor film, and the first conductive layer and the second oxide semiconductor film are formed on the first insulating film and the second insulating film, respectively. A display device that is electrically connected to each other through provided openings.

One embodiment of the present invention is a display device including a demultiplexer, the demultiplexer including a transistor, the transistor including a first insulating film over the first conductive film, and the first insulating film over the first insulating film. A first oxide semiconductor film; a second insulating film over the first oxide semiconductor film; a second oxide semiconductor film over the second insulating film; and a second oxide semiconductor film A second conductive film, a first oxide semiconductor film, and a third insulating film over the second conductive film, the first conductive layer, the second oxide semiconductor film, Is a display device that is electrically connected to each other through openings provided in the first insulating film and the second insulating film.

In one embodiment of the present invention, the first oxide semiconductor film includes a channel region in contact with the second insulating film, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film. The second oxide semiconductor film preferably includes a display device having a carrier density higher than that of the first oxide semiconductor film.

In one embodiment of the present invention, the third insulating film is preferably a display device including one or both of nitrogen and hydrogen.

In one embodiment of the present invention, one or both of the first oxide semiconductor film and the second oxide semiconductor film includes oxygen, In, Zn, and M (M is Al, Ga, Y, Or a display device having Sn).

In one embodiment of the present invention, one or both of the first oxide semiconductor film and the second oxide semiconductor film includes a crystal part, and the crystal part is a display device having c-axis alignment. preferable.

Note that other aspects of the present invention are described in the following embodiments and drawings.

One embodiment of the present invention can provide a display device or the like having a novel structure. Alternatively, according to one embodiment of the present invention, a display device or the like having a novel structure with a narrow frame can be provided. Alternatively, according to one embodiment of the present invention, a display device or the like with a novel structure in which pixels can be arranged with high definition can be provided. Alternatively, according to one embodiment of the present invention, a display device or the like having a novel structure in which an increase in manufacturing cost is suppressed can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the above effects and / or other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 6 illustrates a block diagram of a display device and a block diagram of a demultiplexer. The figure explaining the block diagram, circuit diagram, and timing chart of a demultiplexer. The figure explaining the block diagram of a demultiplexer. The figure explaining the circuit diagram of a demultiplexer. The figure explaining the block diagram of a demultiplexer. The figure explaining the block diagram, circuit diagram, and timing chart of a demultiplexer. The figure explaining the block diagram of a demultiplexer. The figure explaining the circuit diagram of a demultiplexer. 10A and 10B illustrate a top surface and a cross section of a transistor. 6A and 6B illustrate energy bands in a transistor in which an oxide semiconductor film is used for a channel region. 10A and 10B illustrate a top surface and a cross section of a transistor. 10A and 10B illustrate a top surface and a cross section of a transistor. 10A and 10B illustrate a top surface and a cross section of a transistor. 6A and 6B illustrate a cross section of a transistor. 6A and 6B illustrate a cross section of a transistor. 6A and 6B illustrate a cross section of a transistor. The figure explaining a band structure. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. 10 is a cross-sectional view illustrating a method for manufacturing a transistor. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. FIG. 14 is a top view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 10A and 10B are a block diagram and a circuit diagram illustrating a display device. The figure explaining a display module. 10A and 10B each illustrate an electronic device. 10 is a graph comparing drain currents of a transistor of one embodiment of the present invention and an LTPS transistor.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the layer thickness, or the region is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings.

In addition, the ordinal numbers “first”, “second”, and “third” used in the present specification are attached to avoid confusion between components, and are not limited numerically. Appendices.

Further, in this specification, terms indicating arrangement such as “above” and “below” are used for convenience in order to describe the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done. Note that in this specification and the like, a channel region refers to a region through which a current mainly flows.

Also, the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In addition, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In addition, in this specification and the like, the terms “film” and “layer” can be interchanged. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The transistor off current may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, when the threshold voltage Vth is 0.5 V, the drain current when Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ⁻¹³ A. Assume that the n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

In this specification and the like, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current / length (for example, A / μm).

∙ Transistor off-state current may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, it may represent a temperature at which reliability required for the transistor or the like is guaranteed, or an off-state current at a temperature at which the transistor or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.). is there. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability required for the transistor is guaranteed, or a temperature at which the transistor is used (For example, any one temperature of 5 ° C. to 35 ° C.) may indicate that there is a value of Vgs at which the off-state current of the transistor is I or less.

The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability required for the transistor is guaranteed, or off-state current in Vds in which the transistor is used may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V In some cases, there is a value of Vgs at which the off current of the transistor is less than or equal to Vds at which the reliability required for the transistor is guaranteed or Vds used in the transistor.

In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

In addition, in this specification and the like, it may be described as league current in the same meaning as off-current. In this specification and the like, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

(Embodiment 1)
In this embodiment, a display device including a demultiplexer, a demultiplexer including a transistor, and a transistor will be described with reference to FIGS.

<1-1. Circuit Configuration Example 1>
A circuit configuration of the demultiplexer will be described.

FIG. 1A is a block diagram of a display device. The display device 10 includes a source driver 20, a data distribution circuit 30, a pixel unit 40, a gate driver 50A, and a gate driver 50B.

The source driver 20 is preferably an integrated circuit (Integrated Circuit; IC), that is, a source driver IC. By using an IC, a high-speed operation such as an operation of outputting a data signal to the source line can be easily performed.

The data distribution circuit 30 distributes and outputs data signals output from n (n is a natural number) output terminals of the source driver 30 to (m × n) source lines by controlling m sampling signals. To do.

The pixel unit 40 has a plurality of pixels. Each pixel is connected to a source line and a scanning line.

Although two gate drivers 50A and 50B are arranged, one gate driver may be used. By arranging them on the left and right, for example, the odd-numbered and even-numbered scanning lines can be driven separately.

The data distribution circuit 30 can be represented by a block diagram shown as an example in FIG. The data distribution circuit 30 includes n demultiplexers 31_1 to 31_n. The plurality of demultiplexers 31_1 to 31_n are provided according to the number of output terminals of the source driver 30. In the case of FIG. 1B, the number of output terminals of the source driver 30 is n, and the data signals DATA_1 to DATA_n can be output from the respective terminals.

The demultiplexers 31_1 to 31_n distribute and output the data signals DATA_1 to DATA_n output to the n output terminals of the source driver 20 to the source lines SL_1 to SL_2n at different timings. In FIG. 1B, data signals DATA_1 to DATA_n are output to different source lines in different periods by two sampling signals SMP_1 and SMP_2. By changing the data signals DATA_1 to DATA_n depending on the period, different data signals can be output to the source lines SL_1 to SL_2n.

For example, in the first period, the data signals DATA_1 to DATA_n are used as data signals supplied to the odd-numbered source lines, and the demultiplexers 31_1 to 31_n output the data signals to the odd-numbered source lines. In the second period, the data signals DATA_1 to DATA_n are used as data signals to be supplied to even-numbered source lines, and the demultiplexers 31_1 to 31_n output the data signals to even-numbered source lines. By switching the output destination of the demultiplexers 31_1 to 31_n by changing the data voltage applied to the data signals DATA_1 to DATA_n in the first period and the second period, the data signals are output from n output terminals of the source driver 30. Data signals can be distributed and output to (2n) source lines. Therefore, the number of terminals that connect the source driver 20 and the pixel portion 40 can be reduced. In a display device having high-definition pixels, the number of source lines increases as the number of pixels increases. Therefore, reducing the number of terminals between the source driver 20 and the pixel portion 40 is particularly effective.

The transistor included in the demultiplexer can output a data voltage to more source lines even if the number of output terminals of the source driver is small. Therefore, it is suitable for a display device in which pixels are arranged with high definition. Since the number of connection failures can be reduced by reducing the number of output terminals of the source driver, an increase in manufacturing cost can be suppressed.

2A to 2C, a circuit configuration of one demultiplexer illustrated in FIG. 1B will be described. One demultiplexer shown in FIG. 1B, that is, two sampling signals SMP_1 and SMP_2, distributes from one source driver 20 terminal (terminal that outputs the data signal DATA) to two source lines SL_A and SL_B. The demultiplexer 31 to be used can be represented by a symbol shown in FIG. The symbol shown in FIG. 2A can be represented by a circuit diagram shown in FIG.

2B includes two transistors 32 and 33. The demultiplexer 31 illustrated in FIG. The transistor 32 is controlled to be conductive or non-conductive by the sampling signal SMP_1. The transistor 33 is controlled to be conductive or non-conductive by the sampling signal SMP_2. By making the sampling signal SMP_1 and the sampling signal SMP_2 conductive at different timings, the data signal can be distributed from one output terminal of the source driver 20 to which the data signal DATA is supplied to the source line SL_A or SL_B. .

In the demultiplexer 31 illustrated in FIG. 2B, the transistors 32 and 33 each include an oxide semiconductor film in a semiconductor layer. The transistors 32 and 33 each include a first gate electrode and a second gate electrode, and electrically convert an oxide semiconductor film that functions as a semiconductor layer by an electric field of the first gate electrode and the second gate electrode. Surrounding structure. Like the transistors 32 and 33, a device structure of a transistor that surrounds an oxide semiconductor film in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is surrounded by a surround channel (s-channel). Called structure. The s-channel structure will be described in detail later in <1-5 Transistor configuration example>.

FIG. 2C shows a timing chart for explaining the operation of the demultiplexer 31 shown in FIG. In FIG. 2C, a period _THO is one horizontal selection period. Period _{T HO} sampling signal SMP_1 the sampling signal SMP_2 and different timings (period _{T WR_A, T WR_B)} and high level. Then, the transistors 32 and 33 are sequentially turned on. Therefore, the data signal DATA_A is supplied to the source line SL_A from one output terminal of the source driver 20 to which the data signal DATA is supplied, and the data signal DATA_B is supplied to the source line SL_B from one output terminal of the source driver 20 to which the data signal DATA is supplied. Can be distributed at different times. Note that as illustrated in FIG. 2D, a structure in which a different voltage (eg, a voltage for initialization) different from the data signal may be applied in a period in which the data signal is applied.

Since the transistor included in the demultiplexer includes an oxide semiconductor film in a semiconductor layer, off-state current can be reduced. Therefore, it is advantageous in reducing the layout area without taking a configuration for reducing the off-current such as increasing the channel length of the transistor. Therefore, a display device with a narrow frame can be obtained.

In addition, since the transistor included in the demultiplexer has an s-channel structure, the thickness of the gate insulating film provided above the semiconductor layer can be reduced as compared with the gate insulating film of the bottom-gate transistor. In addition, since the s-channel structure is employed, an oxide semiconductor film in which a channel region is formed is electrically surrounded by an electric field of the first gate electrode and the second gate electrode. Therefore, the amount of current flowing through the transistor can be increased. Therefore, it is suitable as a transistor included in the demultiplexer.

<1-2. Circuit configuration example 2>
A configuration example of the data distribution circuit illustrated in FIG. 1B will be described with reference to FIGS.

FIG. 3A is a block diagram of the data distribution circuit 30A. A data distribution circuit 30A illustrated in FIG. 3A illustrates demultiplexers 34_1 to 34_4 as an example.

The demultiplexer 34_1 distributes the data signal DATA_1 given to one output terminal of the source driver 20 to the source line SL_R1 or SL_B1 with the two sampling signals SMP_1 and SMP_2, and outputs them. The demultiplexer 34_2 distributes the data signal DATA_2 given to one output terminal of the source driver 20 by the two sampling signals SMP_1 and SMP_2, and outputs them to the source line SL_G1 or SL_R2. The demultiplexer 34_3 distributes the data signal DATA_3 supplied to the two output terminals of the source driver 20 by using the two sampling signals SMP_1 and SMP_2, and outputs them to the source line SL_G2 or SL_R3. The demultiplexer 34_4 distributes the data signal DATA_4 given to one output terminal of the source driver 20 by using the two sampling signals SMP_1 and SMP_2, and outputs them to the source line SL_B2 or SL_G3.

In addition, the pixel connected to each source line is described as a pixel in which pixels corresponding to three colors of RGB (red, green, and blue) are arranged in stripes. For example, the source line SL_R1 is a source line connected to the pixel in the first column of red. For example, the source line SL_G1 is a source line connected to the pixels in the first column of green. For example, the source line SL_B1 is a source line connected to the pixels in the first column of blue.

FIG. 3B illustrates a circuit configuration of one demultiplexer illustrated in FIG. By one demultiplexer shown in FIG. 3A, that is, two sampling signals SMP_1 and SMP_2, the terminal of one source driver 20 (terminal that outputs the data signal DATA) is changed to two source lines SL_C and SL_D. The demultiplexer 34 to be distributed can be represented by a symbol shown in FIG. The symbol shown in FIG. 3B can be represented by the circuit diagram shown in FIG.

The source line SL_C in FIG. 3B corresponds to, for example, an odd column (or even column) source line. A source line SL_D in FIG. 3B corresponds to, for example, a source line in an odd column (or even column) different from the source line SL_C. That is, FIG. 3A can be represented by the circuit diagram illustrated in FIG.

4, the transistors 35_1 and 36_1 connected to the source lines SL_R1 and SL_B1 constitute a circuit corresponding to one demultiplexer. Therefore, the data signals DATA_1 given to one output terminal of the source driver 20 can be distributed and supplied to the source lines SL_R1 and SL_B1 by making the timings of the sampling signals SMP_1 and SMP_2 different.

The transistors 35_2 and 36_2 connected to the source lines SL_G1 and SL_R2 are circuits corresponding to one demultiplexer. Therefore, by making the timings of the sampling signals SMP_1 and SMP_2 different, the data signal DATA_2 given to one output terminal of the source driver 20 can be distributed and given to the source lines SL_G1 and SL_R2.

The transistors 35_3 and 36_3 connected to the source lines SL_G2 and SL_R3 form a circuit corresponding to one demultiplexer. Therefore, the data signals DATA_3 supplied to one output terminal of the source driver 20 can be distributed and supplied to the source lines SL_G2 and SL_R3 by making the timings of the sampling signals SMP_1 and SMP_2 different.

The transistors 35_4 and 36_4 connected to the source lines SL_B2 and SL_G3 form a circuit corresponding to one demultiplexer. Therefore, by making the timings of the sampling signals SMP_1 and SMP_2 different, the data signal DATA_4 given to one output terminal of the source driver 20 can be distributed and given to the source lines SL_B2 and SL_G3.

In the configuration of FIG. 4, in one horizontal selection period, the polarity of the data signal applied to one output terminal of the source driver is the same, the data signals DATA_1 and DATA_3 corresponding to the odd columns, and the data signal DATA_2 corresponding to the even columns. Further, the source line inversion drive can be easily realized by making the polarity different from that of DATA_4. Therefore, it is particularly preferable when the pixel in the pixel portion has a liquid crystal element.

4, the transistors 35_1 to 35_4 and 36_1 to 36_4 included in the demultiplexer 34 included in the data distribution circuit 30A each include an oxide semiconductor film in a semiconductor layer. The transistors 35_1 to 35_4 and 36_1 to 36_4 each include a first gate electrode and a second gate electrode, and function as a semiconductor layer by an electric field of the first gate electrode and the second gate electrode. An electrically surrounding s-channel structure is adopted.

Since the transistor included in the demultiplexer includes an oxide semiconductor film in a semiconductor layer, off-state current can be reduced. Therefore, it is advantageous in reducing the layout area without taking a configuration for reducing the off-current such as increasing the channel length of the transistor. Therefore, a display device with a narrow frame can be obtained.

In addition, since the transistor included in the demultiplexer has an s-channel structure, the thickness of the gate insulating film provided above the semiconductor layer can be reduced as compared with the gate insulating film of the bottom-gate transistor. In addition, since the s-channel structure is employed, an oxide semiconductor film in which a channel region is formed is electrically surrounded by an electric field of the first gate electrode and the second gate electrode. Therefore, the amount of current flowing through the transistor can be increased. Therefore, it is suitable as a transistor included in the demultiplexer.

<1-3. Circuit Configuration Example 3>
A structure different from the data distribution circuit illustrated in FIG. 1B will be described with reference to FIGS.

FIG. 5 is a block diagram of the data distribution circuit 30B. The data distribution circuit 30B illustrated in FIG. 5 illustrates demultiplexers 37_1 to 37_n as an example.

The demultiplexers 37_1 to 37_n distribute and output the data signal given to one output terminal of the source driver 20 to the three source lines at different timings. In FIG. 5, the data signals DATA_1 to DATA_n given to the output terminal of the source driver 20 in different periods are output to the source lines SL_1 to SL_3n by three sampling signals SMP_1, SMP_2, and SMP_3.

For example, the data signals DATA_1 to DATA_n supplied to the output terminal of the source driver 20 in the first period are output to the source lines (for example, SL_1, SL_4, SL_3n-2, etc.) corresponding to the (3n-2) th column. Data signals DATA_1 to DATA_n supplied to the output terminal of the source driver 20 in the second period are output to source lines (for example, SL_2, SL_5, SL_3n-1, etc.) corresponding to the (3n-1) th column. Data signals DATA_1 to DATA_n supplied to the output terminal of the source driver 20 in the third period are output to source lines (for example, SL_3, SL_6, SL_3n, etc.) corresponding to the (3n) th column. The data signals DATA_1 to DATA_n given to the output terminal of the source driver 20 are distributed and output to (3n) source lines by making them different in the first period, the second period, and the third period. be able to. Therefore, the number of terminals that connect the source driver 20 and the pixel portion 40 can be reduced. In a display device having high-definition pixels, the number of source lines increases as the number of pixels increases. Therefore, reducing the number of terminals between the source driver 20 and the pixel portion 40 is particularly effective.

One demultiplexer shown in FIG. 5, that is, three sampling signals SMP_1, SMP_2, and SMP_3, three output lines (terminals that output the data signal DATA) from one source driver 20 to three source lines SL_E, SL_F, The demultiplexer 37 distributed to SL_G can be represented by a symbol shown in FIG. The symbol shown in FIG. 6A can be represented by a circuit diagram shown in FIG.

The source line SL_E in FIG. 6B corresponds to the source line corresponding to the (3n-2) th column, for example. Further, the source line SL_F in FIG. 6B corresponds to the source line corresponding to the (3n−1) th column, for example. Further, the source line SL_G in FIG. 6B corresponds to the source line corresponding to the (3n) column, for example.

6B includes three transistors 41, 42, and 43. The demultiplexer 37 illustrated in FIG. The transistor 41 is controlled to be conductive or non-conductive by the sampling signal SMP_1. The transistor 42 is controlled to be conductive or non-conductive by the sampling signal SMP_2. The transistor 43 is controlled to be conductive or non-conductive by the sampling signal SMP_3. By making the sampling signal SMP_1, the sampling signal SMP_2, and the sampling signal SMP_3 conductive at different timings, the data signal is distributed from the output terminal of the source driver 20 to the source line SL_E, the source line SL_F, or the source line SL_G. Can do.

6B, the transistors 41 to 43 included in the demultiplexer 37 included in the data distribution circuit 30B each include an oxide semiconductor layer in the semiconductor layer. The transistors 41 to 43 each include a first gate electrode and a second gate electrode, and electrically convert an oxide semiconductor film that functions as a semiconductor layer by an electric field of the first gate electrode and the second gate electrode. The surrounding s-channel structure is used.

FIG. 6C shows a timing chart for explaining the operation of the demultiplexer 37 shown in FIG. In FIG. 6C, a period _THO is one horizontal selection period. Period _{T HO} sampling signal SMP_1 the sampling signal SMP_2 the sampling signal SMP_3 and different timings (period _{T WR_E, T WR_F, T WR_G} ) and high level. Then, the transistors 41 to 43 are sequentially turned on. Therefore, the data signal DATA_E is supplied from one output terminal of the source driver 20 to which the data signal DATA is supplied to the source line SL_E, and the data signal DATA_F is supplied from the one output terminal of the source driver 20 to which the data signal DATA is supplied to the source line SL_F. The data signal DATA_G can be distributed at different timings from one output terminal of the source driver 20 to which DATA is supplied to the source line SL_G.

Since the transistor included in the demultiplexer includes an oxide semiconductor film in a semiconductor layer, off-state current can be reduced. Therefore, it is advantageous in reducing the layout area without taking a configuration for reducing the off-current such as increasing the channel length of the transistor. Therefore, a display device with a narrow frame can be obtained.

In addition, since the transistor included in the demultiplexer has an s-channel structure, the thickness of the gate insulating film provided above the semiconductor layer can be reduced as compared with the gate insulating film of the bottom-gate transistor. In addition, since the s-channel structure is employed, an oxide semiconductor film in which a channel region is formed is electrically surrounded by an electric field of the first gate electrode and the second gate electrode. Therefore, the amount of current flowing through the transistor can be increased. Therefore, it is suitable as a transistor included in the demultiplexer.

<1-4. Circuit Configuration Example 4>
A configuration example of the data distribution circuit shown in FIG. 5 will be described with reference to FIGS.

FIG. 7A is a block diagram of the data distribution circuit 30C. The data distribution circuit 30C illustrated in FIG. 7A illustrates demultiplexers 44_1 to 44_4 as an example.

The demultiplexer 44_1 distributes and outputs the data signal DATA_1 given to one output terminal of the source driver 20 to the source lines SL_R1, SL_B1, or SL_G2 by three sampling signals SMP_1, SMP_2, and SMP_3. The demultiplexer 44_2 distributes the data signal DATA_2 supplied to one output terminal of the source driver 20 by using the three sampling signals SMP_1, SMP_2, and SMP_3, and outputs them to the source lines SL_G1, SL_R2, or SL_B2. The demultiplexer 44_3 distributes the data signal DATA_3 given to one output terminal of the source driver 20 by the three sampling signals SMP_1, SMP_2, and SMP_3, and outputs them to the source lines SL_R3, SL_B3, or SL_G4. The demultiplexer 44_4 distributes the data signal DATA_4 given to one output terminal of the source driver 20 by the three sampling signals SMP_1, SMP_2, and SMP_3, and outputs them to the source lines SL_G3, SL_R4, or SL_B4.

In addition, the pixel connected to each source line is described as a pixel in which pixels corresponding to three colors of RGB (red, green, and blue) are arranged in stripes. For example, the source line SL_R1 is a source line connected to the pixel in the first column of red. For example, the source line SL_G1 is a source line connected to the pixels in the first column of green. For example, the source line SL_B1 is a source line connected to the pixels in the first column of blue.

FIG. 7B illustrates a circuit configuration of one demultiplexer illustrated in FIG. By one demultiplexer shown in FIG. 7A, that is, two sampling signals SMP_1 and SMP_2, three source lines SL_H, SL_I, and one source driver 20 terminals (terminals that output the data signal DATA) The demultiplexer 34 distributed to SL_J can be represented by a symbol shown in FIG. The symbol shown in FIG. 7B can be represented by the circuit diagram shown in FIG.

The source line SL_H in FIG. 7B corresponds to, for example, an odd column (or even column) source line. In addition, the source line SL_I in FIG. 7B corresponds to, for example, an odd column (or even column) source line different from the source lines SL_H and SL_J. In addition, the source line SL_J in FIG. 7B corresponds to, for example, an odd column (or even column) source line different from the source lines SL_H and SL_I. That is, FIG. 7A can be represented by the circuit diagram illustrated in FIG.

In the configuration of FIG. 8, the transistors 45_1, 46_1, and 47_1 connected to the source lines SL_R1, SL_B1, and SL_G2 are circuits corresponding to one demultiplexer. Therefore, the data signal DATA_1 applied to one output terminal of the source driver 20 can be distributed and supplied to the source line SL_R1, the source lines SL_B1, and SL_G2 by making the timings of the sampling signals SMP_1, SMP_2, and SMP_3 different.

The transistors 45_2, 46_2, and 47_2 connected to the source lines SL_G1, SL_R2, and SL_B2 form a circuit corresponding to one demultiplexer. Therefore, by varying the timing of the sampling signals SMP_1, SMP_2, and SMP_3, the data signal DATA_2 applied to one output terminal of the source driver 20 can be distributed and provided to the source lines SL_G1, SL_R2, and SL_B2.

The transistors 45_3, 46_3 and the transistor 47_3 connected to the source lines SL_R3, SL_B3, and SL_G4 form a circuit corresponding to one demultiplexer. Therefore, the data signals DATA_3 applied to one output terminal of the source driver 20 can be distributed and supplied to the source lines SL_R3, SL_B3, and SL_G4 by making the timings of the sampling signals SMP_1, SMP_2, and SMP_3 different.

The transistors 45_4, 46_4, and 47_4 connected to the source lines SL_G3, SL_R4, and SL_B4 are circuits corresponding to one demultiplexer. Therefore, by varying the timing of the sampling signals SMP_1, SMP_2, and SMP_3, the data signal DATA_4 applied to one output terminal of the source driver 20 can be distributed and supplied to the source lines SL_G3, SL_R4, and SL_B4.

The configuration of FIG. 8 is that the data signals applied to one output terminal of the source driver have the same polarity in the horizontal selection period, the data signals DATA_1 and DATA_3 corresponding to the odd columns, and the data signal DATA_2 corresponding to the even columns. The source line inversion drive can be easily realized by making the polarity different from that of DATA_4. Therefore, it is particularly preferable when the pixel in the pixel portion has a liquid crystal element.

8, the transistors 45_1 to 45_4, 46_1 to 46_4, and 47_1 to 47_4 included in the demultiplexer 34 included in the data distribution circuit 30A each include an oxide semiconductor film in a semiconductor layer. The transistors 45_1 to 45_4, 46_1 to 46_4, and 47_1 to 47_4 each include a first gate electrode and a second gate electrode, and function as a semiconductor layer by an electric field of the first gate electrode and the second gate electrode. An s-channel structure that electrically surrounds the oxide semiconductor film is employed.

Since the transistor included in the demultiplexer includes an oxide semiconductor film in a semiconductor layer, off-state current can be reduced. Therefore, it is advantageous in reducing the layout area without taking a configuration for reducing the off-current such as increasing the channel length of the transistor. Therefore, a display device with a narrow frame can be obtained.

In addition, since the transistor included in the demultiplexer has an s-channel structure, the thickness of the gate insulating film provided above the semiconductor layer can be reduced as compared with the gate insulating film of the bottom-gate transistor. In addition, since the s-channel structure is employed, an oxide semiconductor film in which a channel region is formed is electrically surrounded by an electric field of the first gate electrode and the second gate electrode. Therefore, the amount of current flowing through the transistor can be increased. Therefore, it is suitable as a transistor included in the demultiplexer.

<1-5. Transistor Configuration Example 1>
9A and 9B illustrate structure examples of transistors applicable to the transistors 32 to 33, the transistors 35_1 to 35_4, 36_1 to 36_4, the transistors 41 to 43, and the transistors 45_1 to 45_4, 46_1 to 46_4, and 47_1 to 47_4. A description will be given using (C).
FIGS. 9A, 9B, and 9C illustrate an example of a transistor. Note that the transistors illustrated in FIGS. 9A, 9B, and 9C have an s-channel structure.

9A is a top view of the transistor 100, FIG. 9B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 9A, and FIG. 9C is FIG. 9A. It is sectional drawing between dashed-dotted lines Y1-Y2. Note that in FIG. 9A, components such as the insulating film 110 are omitted for clarity. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 9A. In addition, the alternate long and short dash line X1-X2 direction may be referred to as a channel length (L) direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as a channel width (W) direction.

9A, 9B, and 9C includes a conductive film 106 formed over a substrate 102, an insulating film 104 over the conductive film 106, and an oxide semiconductor film 108 over the insulating film 104. The insulating film 110 over the oxide semiconductor film 108, the oxide semiconductor film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, the insulating film 116 over the oxide semiconductor film 112, and the opening 143. The oxide semiconductor film 108 includes a channel region 108 i in contact with the insulating film 110, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116. Have.

The opening 143 is provided in the insulating films 104 and 110. In addition, the conductive film 106 is electrically connected to the oxide semiconductor film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the oxide semiconductor film 112.

Further, the transistor 100 includes an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.

Note that the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the oxide semiconductor film 112 functions as a second gate electrode (also referred to as a top gate electrode). . The insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.

As described above, the transistor 100 illustrated in FIGS. 9A to 9C has a structure in which a conductive film or an oxide semiconductor film which functions as a gate electrode is provided above and below the oxide semiconductor film 108.

Further, as illustrated in FIG. 9C, the oxide semiconductor film 108 faces the conductive film 106 functioning as the first gate electrode and the oxide semiconductor film 112 functioning as the second gate electrode. And is sandwiched between conductive films or oxide semiconductor films functioning as two gate electrodes.

The length of the oxide semiconductor film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire channel width direction of the oxide semiconductor film 108 is oxidized through the insulating film 110. The physical semiconductor film 112 is covered. In addition, since the oxide semiconductor film 112 and the conductive film 106 are connected to each other in the opening 143 provided in the insulating film 104 and the insulating film 110, one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is an insulating film. It faces the oxide semiconductor film 112 with 110 interposed therebetween.

In other words, in the channel width direction of the transistor 100, the conductive film 106 and the oxide semiconductor film 112 are connected to each other through the opening 143 provided in the insulating film 104 and the insulating film 110, and the insulating film 104 and the insulating film 110 are interposed therebetween. Thus, the oxide semiconductor film 108 is surrounded.

With such a structure, the oxide semiconductor film 108 included in the transistor 100 is electrically converted by the electric field of the conductive film 106 functioning as the first gate electrode and the oxide semiconductor film 112 functioning as the second gate electrode. Can be surrounded. With such a structure, the transistor 100 can effectively apply an electric field for inducing a channel by the conductive film 106 or the oxide semiconductor film 112 to the oxide semiconductor film 108. Therefore, the current driving capability of the transistor 100 is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100 can be miniaturized. In addition, since the transistor 100 has a structure surrounded by the conductive film 106 and the oxide semiconductor film 112, the mechanical strength of the transistor 100 can be increased.

Note that an opening different from the opening 143 may be formed on the side where the opening 143 of the oxide semiconductor film 108 is not formed in the channel width direction of the transistor 100.

Note that in this specification and the like, the insulating film 104 may be referred to as a first insulating film, the insulating film 116 may be referred to as a second insulating film, and the insulating film 118 may be referred to as a third insulating film. The insulating film 110 functions as a gate insulating film, and the oxide semiconductor film 112 functions as a gate electrode. The conductive film 120a functions as a source electrode, and the conductive film 120b functions as a drain electrode.

Further, the insulating film 116 has one or both of nitrogen and hydrogen. With the structure in which the insulating film 116 includes one or both of nitrogen and hydrogen, one or both of nitrogen and hydrogen can be supplied to the oxide semiconductor film 108 and the oxide semiconductor film 112.

In addition, the oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110. When the oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110, excess oxygen can be contained in the insulating film 110. When the insulating film 110 includes the excess oxygen region, the excess oxygen can be supplied into the oxide semiconductor film 108, more specifically, the channel region 108i. Thus, a highly reliable display device can be provided.

Note that in order to supply excess oxygen into the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108. Note that in this case, oxygen contained in the insulating film 104 can be supplied to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and the drain region 108d, the resistance in the source region 108s and the drain region 108d may increase.

On the other hand, when the insulating film 110 formed over the oxide semiconductor film 108 has excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density in the source region 108s and the drain region 108d may be selectively increased.

In addition, after supplying oxygen to the insulating film 110, the oxide semiconductor film 112 is supplied with one or both of nitrogen and hydrogen from the insulating film 116, so that the carrier density is increased. In other words, the oxide semiconductor film 112 also has a function as an oxide conductor (OC: Oxide Conductor). Therefore, the oxide semiconductor film 112 has a higher carrier density than the oxide semiconductor film 108.

The source region 108s, the drain region 108d, and the oxide semiconductor film 112 included in the oxide semiconductor film 108 may each include an element that forms oxygen vacancies. Examples of the element that forms oxygen vacancies typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut, and oxygen vacancies are formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.

In the transistor 100, it is preferable that the side end portion of the insulating film 110 and the side end portion of the oxide semiconductor film 112 have a region where they are aligned. In other words, the transistor 100 has a structure in which the upper end portion of the insulating film 110 and the lower end portion of the oxide semiconductor film 112 are substantially aligned. For example, the above structure can be obtained by processing the insulating film 110 using the oxide semiconductor film 112 as a mask.

Next, details of the components of the transistor shown in FIGS. 9A, 9B, and 9C will be described.

[substrate]
Various substrates can be used as the substrate 102, and the substrate 102 is not limited to a specific substrate. As an example of a substrate, a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, Examples include a substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the laminated film, and the base film include the following. For example, there are plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Another example is a synthetic resin such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. As an example, there are polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

Alternatively, a flexible substrate may be used as the substrate 102, and the transistor may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. The separation layer can be used to separate the substrate 102 from the substrate 102 and transfer it to another substrate after part or all of the transistor is completed thereover. At that time, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. Note that, for example, a structure in which an inorganic film of a tungsten film and a silicon oxide film is stacked, or a structure in which an organic resin film such as polyimide is formed over a substrate can be used for the above-described release layer.

Examples of a substrate on which a transistor is transferred include a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber) in addition to the above-described substrate capable of forming a transistor. (Silk, cotton, hemp), synthetic fibers (including nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

[First insulating film]
The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating film 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film from which oxygen is released by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 It is possible to reduce oxygen vacancies contained in 108i.

As the insulating film 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 104 can be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104. In this manner, oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

[Oxide semiconductor film]
One or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 is formed using a metal oxide such as In-M-Zn oxide (M is Al, Ga, Y, or Sn). Further, as the oxide semiconductor film 108 and the oxide semiconductor film 112, an In—Ga oxide or an In—Zn oxide may be used. In particular, the oxide semiconductor film 108 and the oxide semiconductor film 112 are preferably formed using a metal oxide including the same constituent elements because manufacturing costs can be reduced.

Note that in the case where the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxide, the atomic ratio of In to M is higher than 25 atomic% when In is set to 100 atomic%. , M is less than 75 atomic%, or In is higher than 34 atomic% and M is less than 66 atomic%.

The energy gap of the oxide semiconductor film 108 and the oxide semiconductor film 112 is preferably 2 eV or more, 2.5 eV or more, or 3 eV or more.

The thickness of the oxide semiconductor film 108 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm. The thickness of the oxide semiconductor film 112 is 5 nm to 500 nm, preferably 10 nm to 300 nm, more preferably 20 nm to 100 nm.

In the case where the oxide semiconductor film 108 and the oxide semiconductor film 112 are In-M-Zn oxide, the atomic ratio of the metal element of the sputtering target used for forming the In-M-Zn oxide is In ≧ M It is preferable to satisfy M and Zn ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7, etc. are preferable. Note that the atomic ratio of the oxide semiconductor film 108 and the oxide semiconductor film 112 to be formed may vary by about plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target. For example, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target, the atomic ratio of the oxide semiconductor film to be formed is In: Ga: Zn = 4: 2: In some cases, it is close to 3.

In addition, in the oxide semiconductor film 108 and the oxide semiconductor film 112, when silicon or carbon which is one of Group 14 elements is included, oxygen vacancies increase, which may be n-type. Therefore, in the oxide semiconductor film 108, particularly in the channel region 108i, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁷ atoms. / Cm ³ or less. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

In the channel region 108i, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry is 1 × 10 ¹⁸ atoms / cm ³ or less, or 2 × 10 ¹⁶ atoms / cm ³ or less. Can do. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the channel region 108i. As a result, the transistor has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage is positive.

In addition, when nitrogen is contained in the channel region 108i, electrons as carriers are generated, the carrier density is increased, and the n-type may be obtained. As a result, a transistor including an oxide semiconductor film containing nitrogen is likely to be normally on. Therefore, nitrogen is preferably reduced as much as possible in the channel region 108i. For example, the nitrogen concentration obtained by secondary ion mass spectrometry may be 5 × 10 ¹⁸ atoms / cm ³ or less.

Further, in the channel region 108i, the carrier density of the oxide semiconductor film can be reduced by reducing the impurity element.

As a factor that affects the carrier density of the oxide semiconductor film, oxygen vacancies (Vo) in the oxide semiconductor film, impurities in the oxide semiconductor film, and the like can be given.

When the number of oxygen vacancies in the oxide semiconductor film increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the number of impurities in the oxide semiconductor film is increased, the density of defect states is increased due to the impurities. Therefore, the carrier density of the oxide semiconductor film can be controlled by controlling the density of defect states in the oxide semiconductor film.

Here, a transistor using an oxide semiconductor film for a channel region is considered.

In the case where the object is to suppress a negative shift in the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor film. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. The carrier density of the high-purity intrinsic oxide semiconductor film is less than 8 × 10 ¹⁵ cm ⁻³ , preferably less than 1 × 10 ¹¹ cm ⁻³ , more preferably less than 1 × 10 ¹⁰ cm ⁻³ , and 1 × What is necessary is just to set it as 10 ^<-9 > cm ^<-3 > or more.

On the other hand, for the purpose of improving the on-state current of a transistor or improving the field-effect mobility of a transistor, it is preferable to increase the carrier density of an oxide semiconductor film. In the case of increasing the carrier density of the oxide semiconductor film, the impurity concentration of the oxide semiconductor film may be slightly increased or the defect state density of the oxide semiconductor film may be slightly increased. Alternatively, the band gap of the oxide semiconductor film is preferably made smaller. For example, an oxide semiconductor film with a slightly high impurity concentration or a slightly high defect state density within a range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained can be regarded as substantially intrinsic. In addition, an oxide semiconductor film in which the electron affinity is large and the band gap is accordingly reduced, and as a result, the density of thermally excited electrons (carriers) is increased, can be substantially regarded as intrinsic. Note that in the case where an oxide semiconductor film with higher electron affinity is used, the threshold voltage of the transistor is lower.

The oxide semiconductor film with the increased carrier density is slightly n-type. Therefore, an oxide semiconductor film with an increased carrier density may be referred to as “Slightly-n”.

The carrier density of the substantially intrinsic oxide semiconductor film is preferably 1 × 10 ⁵ cm ⁻³ or more and less than 1 × 10 ¹⁸ cm ⁻³ , preferably 1 × 10 ⁷ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. More preferably, it is 1 × 10 ⁹ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less, more preferably 1 × 10 ¹⁰ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less, and further preferably 1 × 10 ¹¹ cm ^−3. More preferably, it is 1 × 10 ¹⁵ cm ⁻³ or less.

In addition, the use of the above-described substantially intrinsic oxide semiconductor film may improve the reliability of the transistor. Here, the reason why the reliability of a transistor in which an oxide semiconductor film is used for a channel region is improved will be described with reference to FIGS. FIG. 10 illustrates an energy band in a transistor in which an oxide semiconductor film is used for a channel region.

10, GE represents a gate electrode, GI represents a gate insulating film, OS represents an oxide semiconductor film, and SD represents a source electrode or a drain electrode. That is, FIG. 10 illustrates an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source or drain electrode in contact with the oxide semiconductor film.

In FIG. 10, a silicon oxide film is used as the gate insulating film, and an In—Ga—Zn oxide is used as the oxide semiconductor film. Further, the transition level (εf) of defects that can be formed in the silicon oxide film is formed at a position separated by about 3.1 eV from the conduction band of the gate insulating film, and the oxidation when the gate voltage (Vg) is 30V. The Fermi level (Ef) of the silicon oxide film at the interface between the physical semiconductor film and the silicon oxide film is formed at a position separated from the conduction band of the gate insulating film by about 3.6 eV. Note that the Fermi level of the silicon oxide film varies depending on the gate voltage. For example, when the gate voltage is increased, the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is lowered. Further, white circles in FIG. 10 represent electrons (carriers), and X in FIG. 10 represents defect levels in the silicon oxide film.

As shown in FIG. 10, for example, when carriers are thermally excited in a state where a gate voltage is applied, the carriers are trapped at the defect level (X in the figure), and from the plus (“+”) to the neutral (“0”). ”), The charge state of the defect level changes. That is, when the value obtained by adding the above-described thermal excitation energy to the Fermi level (Ef) of the silicon oxide film becomes higher than the defect transition level (εf), the charge state of the defect level in the silicon oxide film is positive. From this state, the transistor becomes neutral, and the threshold voltage of the transistor fluctuates in the positive direction.

In addition, when oxide semiconductor films having different electron affinities are used, the depth at which the Fermi level at the interface between the gate insulating film and the oxide semiconductor film is formed may be different. When an oxide semiconductor film with high electron affinity is used, the conduction band of the gate insulating film moves upward in the vicinity of the interface between the gate insulating film and the oxide semiconductor film. In this case, since a defect level (X in FIG. 10) that can be formed in the gate insulating film also moves upward, the energy difference between the Fermi level at the interface between the gate insulating film and the oxide semiconductor film increases. By increasing the energy difference, the charge trapped in the gate insulating film is reduced. For example, the change in the charge state of the defect level that can be formed in the above-described silicon oxide film is reduced, and the gate bias heat ( The variation of the threshold voltage of the transistor under stress can be reduced under stress (Gate Bias Temperature: GBT).

On the other hand, the source region 108s, the drain region 108d, and the oxide semiconductor film 112 are in contact with the insulating film 116. The source region 108 s, the drain region 108 d, and the oxide semiconductor film 112 are in contact with the insulating film 116, so that either the source region 108 s, the drain region 108 d, or the oxide semiconductor film 112 is hydrogen or nitrogen or Since both are added, the carrier density is increased.

Further, one or both of the oxide semiconductor film 108 and the oxide semiconductor film 112 may have a non-single-crystal structure. The non-single crystal structure includes, for example, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

Note that the oxide semiconductor film 108 includes a single-layer film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Or the structure where this film | membrane was laminated | stacked may be sufficient. The oxide semiconductor film 112 includes a single-layer film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region, Or the structure where this film | membrane was laminated | stacked may be sufficient.

Note that in the oxide semiconductor film 108, the channel region 108i may have different crystallinity from the source region 108s and the drain region 108d. Specifically, in the oxide semiconductor film 108, the source region 108s and the drain region 108d may have lower crystallinity than the channel region 108i. This is because when the impurity element is added to the source region 108s and the drain region 108d, the source region 108s and the drain region 108d are damaged, and crystallinity is lowered.

[Insulating film functioning as a gate insulating film]
The insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 110 is preferably formed using an oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 110 can be provided as a single layer or a stacked layer.

Further, by providing an insulating film having a blocking effect of oxygen, hydrogen, water, or the like as the insulating film 110, diffusion of oxygen from the oxide semiconductor film 108 to the outside and hydrogen from the outside to the oxide semiconductor film 108 are performed. Invasion of water, etc. can be prevented. Examples of the insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

Further, as the insulating film 110, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), hafnium oxide, By using a high-k material such as yttrium oxide, gate leakage of the transistor can be reduced.

Further, by using an oxide insulating film from which oxygen is released by heating as the insulating film 110, oxygen contained in the insulating film 110 can be moved to the oxide semiconductor film 108 by heat treatment.

The thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.

[Second insulating film]
The insulating film 116 includes one or both of nitrogen and hydrogen. An example of the insulating film 116 is a nitride insulating film. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The concentration of hydrogen contained in the insulating film 116 is preferably 1 × 10 ²² atoms / cm ³ or more. The insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. The insulating film 116 is in contact with the oxide semiconductor film 112. Accordingly, the hydrogen concentration in the source region 108s, the drain region 108d, and the oxide semiconductor film 112 in contact with the insulating film 116 is increased, and the carrier density of the source region 108s, the drain region 108d, and the oxide semiconductor film 112 is increased. it can. Note that each of the source region 108s, the drain region 108d, and the oxide semiconductor film 112 may have a region where the hydrogen concentration in the film is the same by being in contact with the insulating film 116.

[Third insulating film]
As the insulating film 118, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 118 can be provided as a single layer or a stacked layer.

Further, the insulating film 118 is preferably a film that functions as a barrier film of hydrogen, water, etc. from the outside.

The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[Conductive film]
The conductive films 106, 120a, and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. In addition, as the conductive films 120a and 120b, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, or an alloy containing the above metal element as a component, It can be formed using an alloy or the like in which the above metal elements are combined. Alternatively, a metal element selected from one or more of manganese and zirconium may be used. In addition, the conductive films 106, 120a, and 120b may have a single-layer structure or a stacked structure including two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, a two layer structure in which a titanium film is laminated on an aluminum film, a two layer structure in which a titanium film is laminated on a titanium nitride film, and nitriding Two-layer structure in which tungsten film is laminated on titanium film, two-layer structure in which tungsten film is laminated on tantalum nitride film or tungsten nitride film, two-layer structure in which copper film is laminated on copper film containing manganese, on titanium film A two-layer structure in which a copper film is laminated, a titanium film, an aluminum film is laminated on the titanium film, and a three-layer structure in which a titanium film is formed thereon, and a copper film is laminated on a copper film containing manganese Further, there is a three-layer structure on which a copper film containing manganese is formed. Alternatively, an alloy film or a nitride film in which aluminum is combined with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The conductive films 106, 120a, and 120b are made of indium tin oxide (Indium Tin Oxide: ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and titanium oxide. A light-transmitting conductive material such as indium tin oxide containing silicon, indium zinc oxide, or indium tin oxide containing silicon (In-Sn-Si oxide: also referred to as ITSO) can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal element can be employed.

The thickness of the conductive films 106, 120a, and 120b can be 30 nm to 500 nm, or 100 nm to 400 nm.

<1-6. Transistor configuration example 2>
Next, a structure different from the transistors illustrated in FIGS. 9A, 9B, and 9C is described with reference to FIGS.

11A is a top view of the transistor 150, FIG. 11B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 11A, and FIG. 11C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.

A transistor 150 illustrated in FIGS. 11A to 11C includes a conductive film 106 formed over a substrate 102, an insulating film 104 over the conductive film 106, and an oxide semiconductor film 108 over the insulating film 104. , The insulating film 110 over the oxide semiconductor film 108, the oxide semiconductor film 112 over the insulating film 110, the conductive film 114 over the oxide semiconductor film 112, the insulating film 104, the oxide semiconductor film 108, and the conductive film Insulating film 116 on opening 114 and opening 143. The oxide semiconductor film 108 includes a channel region 108 i in contact with the insulating film 110, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116. Have.

The opening 143 is provided in the insulating films 104 and 110. In addition, the conductive film 106 is electrically connected to the oxide semiconductor film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the oxide semiconductor film 112.

The transistor 150 includes the insulating film 118 over the insulating film 116, the conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.

Note that the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the oxide semiconductor film 112 and the conductive film 114 are also referred to as second gate electrodes (also referred to as top gate electrodes). ). The conductive film 114 has a function of making the oxide semiconductor film 112 an n-type. When the conductive film 114 has a function of making the oxide semiconductor film 112 an n-type, the oxide semiconductor film 112 functions as part of the gate electrode. The insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.

As described above, the transistor 150 illustrated in FIGS. 11A to 11C has a structure in which a conductive film or an oxide semiconductor film functioning as a gate electrode is provided above and below the oxide semiconductor film 108.

With such a structure, the oxide semiconductor film 108 included in the transistor 150 includes the conductive film 106 functioning as the first gate electrode and the oxide semiconductor film 112 and conductive film 114 functioning as the second gate electrode. It can be electrically surrounded by the electric field. With such a structure, the transistor 150 can effectively apply an electric field for inducing a channel by the conductive film 106 or the oxide semiconductor film 112 and the conductive film 114 to the oxide semiconductor film 108. Therefore, the current driving capability of the transistor 150 is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 150 can be miniaturized. In addition, since the transistor 100 has a structure surrounded by the conductive film 106, the oxide semiconductor film 112, and the conductive film 114, the mechanical strength of the transistor 150 can be increased.

Further, the insulating film 116 has one or both of nitrogen and hydrogen. With the structure in which the insulating film 116 includes one or both of nitrogen and hydrogen, either or both of nitrogen and hydrogen can be supplied to the source region 108s and the drain region 108d.

In addition, the oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110. When the oxide semiconductor film 112 has a function of supplying oxygen to the insulating film 110, excess oxygen can be contained in the insulating film 110. When the insulating film 110 includes the excess oxygen region, the excess oxygen can be supplied into the channel region 108i. Thus, a highly reliable display device can be provided.

Note that the oxide semiconductor film 112 has high carrier density when it is in contact with the conductive film 114 after oxygen is supplied to the insulating film 110. In other words, the oxide semiconductor film 112 also has a function as an oxide conductor (OC). Therefore, the oxide semiconductor film 112 can function as part of the gate electrode without increasing the number of manufacturing steps.

The conductive film 114 is formed using the same formation method and the same material as the conductive films 106, 120a, and 120b described above. In particular, the conductive film 114 is preferably formed using titanium, copper, or tungsten by a sputtering method. By using titanium, copper, or tungsten for the conductive film 114, conductivity of the oxide semiconductor film 112 in contact with the conductive film 114 can be improved. Alternatively, the conductive film 114 may have a stacked structure. As the stacked structure, for example, a structure having a copper film on a copper film containing manganese or a structure having an aluminum film on a tungsten film may be used.

<1-7. Transistor Configuration Example 4>
Next, a structure different from that of the semiconductor device illustrated in FIGS. 9A to 9C is described with reference to FIGS.

12A is a top view of the transistor 100B, FIG. 12B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 12A, and FIG. 12C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.

12A, 12B, and 12C are different in the shape of the oxide semiconductor film 112 from the transistor 100 described above. Specifically, the lower end portion of the oxide semiconductor film 112 included in the transistor 100B is formed inside the upper end portion of the insulating film 110. In other words, the side end portion of the insulating film 110 is located outside the side end portion of the oxide semiconductor film 112.

For example, the oxide semiconductor film 112 and the insulating film 110 are processed with the same mask, the oxide semiconductor film 112 is processed with a wet etching method, and the insulating film 110 is processed with a dry etching method. can do.

Further, when the oxide semiconductor film 112 has the above structure, the region 108f may be formed in the oxide semiconductor film 108 in some cases. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

The region 108f functions as either a high resistance region or a low resistance region. The high-resistance region is a region that has the same resistance as the channel region 108 i and does not overlap with the oxide semiconductor film 112 that functions as a gate electrode. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. In the case where the region 108f functions as an offset region, the region 108f may be 1 μm or less in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 100B.

Further, the low resistance region is a region having a resistance lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. In the case where the region 108f functions as an LDD region, electric field relaxation in the drain region is possible, so that variation in threshold voltage of the transistor due to the electric field in the drain region can be reduced.

Note that in the case where the region 108f is a low-resistance region, for example, one or both of hydrogen and nitrogen is supplied from the insulating film 116 to the region 108f, or the insulating film 110 and the oxide semiconductor film 112 are used as masks. By adding an impurity element from above the oxide semiconductor film 112, the impurity is added to the oxide semiconductor film 108 through the insulating film 110.

Further, the transistor 150B described above can have a structure similar to that of the transistor 100B by changing the shape of the oxide semiconductor film 112 functioning as the second gate electrode. An example of this case is shown in FIGS. 13 (A), (B), and (C). 13A is a top view of the transistor 150B, FIG. 13B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 13A, and FIG. It is sectional drawing between dashed-dotted lines Y1-Y2 of A).

<1-8. Modification Example 1 of Transistor>
Next, modified examples of the transistors illustrated in FIGS. 1A, 1B, and 1C are described with reference to FIGS.

14A and 14B are cross-sectional views of the transistor 100C. A top view of the transistor 100C is similar to the transistor 100B illustrated in FIG. 12A, and thus will be described with reference to FIG. 14A is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 12A, and FIG. 14B is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG.

The transistor 100C is different from the transistor 100B described above in that an insulating film 122 functioning as a planarization insulating film is provided. Other configurations are similar to those of the transistor 100B described above, and have the same effects.

The insulating film 122 has a function of flattening unevenness caused by a transistor or the like. The insulating film 122 only needs to be insulative and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. As this organic material, photosensitive resin materials, such as an acrylic resin or a polyimide resin, are mentioned, for example.

14A and 14B, the shape of the opening included in the insulating film 122 is smaller than that of the openings 141a and 141b. However, the shape is not limited to this, and for example, the openings 141a and 141b are used. The shape may be the same as or larger than the openings 141a and 141b.

14A and 14B illustrate the structure in which the conductive films 120a and 120b are provided over the insulating film 122, the present invention is not limited thereto. For example, the conductive films 120a and 120b are provided over the insulating film 118. Alternatively, the insulating film 122 may be provided over the conductive films 120a and 120b.

<1-9. Modification Example 3 of Transistor>
Next, modified examples of the transistors illustrated in FIGS. 9A, 9B, and 9C are described with reference to FIGS.

15A and 15B are cross-sectional views of the transistor 100F. A top view of the transistor 100F is similar to the transistor 100 illustrated in FIG. 9A, and thus will be described with reference to FIG. 9A. 15A is a cross-sectional view taken along alternate long and short dash line X1-X2 in FIG. 9A, and FIG. 15B is a cross-sectional view taken along alternate long and short dash line Y1-Y2 in FIG.

The transistor 100F is different from the transistor 100 described above in the structure of the oxide semiconductor film 108. Other configurations are similar to those of the transistor 100 described above, and have the same effects.

The oxide semiconductor film 108 included in the transistor 100F includes an oxide semiconductor film 108_1 over the insulating film 116, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. Have.

The channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.

16A and 16B are cross-sectional views of the transistor 100G. A top view of the transistor 100G is similar to the transistor 100 illustrated in FIG. 9A, and thus will be described with reference to FIG. 16A is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 9A, and FIG. 16B is a cross-sectional view taken along the dashed-dotted line Y1-Y2 in FIG.

The transistor 100G is different from the transistor 100 described above in the structure of the oxide semiconductor film 108. Other configurations are similar to those of the transistor 100 described above, and have the same effects.

The oxide semiconductor film 108 included in the transistor 100G includes an oxide semiconductor film 108_2 over the insulating film 116 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.

Further, the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3.

The transistor 100G has a multilayer structure of the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3 in the channel region 108i.

Here, the band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110, and the band structure of the insulating film 104, the oxide semiconductor films 108_2, 108_3, and the insulating film 110 are described with reference to FIGS. Will be described.

FIG. 17A illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110. FIG. 17B illustrates an example of a band structure in the thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. Note that the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.

FIG. 17A illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110 and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. An oxide semiconductor film is used, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 2 as an oxide semiconductor film 108_3 is used. It is a band diagram.

In FIG. 17B, a silicon oxide film is used as the insulating films 104 and 110, and a metal oxide atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the oxide semiconductor film 108_2. An oxide semiconductor film formed using an object target is used, and the oxide semiconductor film 108_3 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 1: 3: 2. FIG. 10 is a band diagram of a structure using an oxide semiconductor film.

As shown in FIG. 17A, in the oxide semiconductor films 108_1, 108_2, and 108_3, the energy level at the lower end of the conduction band changes gently. In addition, as illustrated in FIG. 17B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.

In order to form a continuous bond with the oxide semiconductor films 108_1, 108_2, and 108_3, each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.

17A and 17B, the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure. Recognize.

Note that when the oxide semiconductor films 108_1 and 108_3 are provided, the trap level can be further away from the oxide semiconductor film 108_2.

In addition, the trap level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the trap level. . Accumulation of electrons at the trap level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, a structure in which the trap level is closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 is preferable. By doing so, electrons are unlikely to accumulate in the trap level, the on-state current of the transistor can be increased, and field effect mobility can be increased.

The oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.

With such a structure, the oxide semiconductor film 108_2 becomes a main current path. In other words, the oxide semiconductor film 108_2 functions as a channel region, and the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed. With such a structure, interface scattering hardly occurs at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.

The oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions. Alternatively, in the oxide semiconductor films 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is lower than that of the oxide semiconductor film 108_2, and the energy level at the bottom of the conduction band is an oxide. A material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used. In addition, in order to suppress the difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to use a material closer to the vacuum level than the energy level at the lower end of the band. For example, the difference between the energy level at the bottom of the conduction band of the oxide semiconductor film 108_2 and the energy level at the bottom of the conduction bands of the oxide semiconductor films 108_1 and 108_3 is 0.2 eV or more, preferably 0.5 eV or more. It is preferable.

Further, it is preferable that the oxide semiconductor films 108_1 and 108_3 do not include a spinel crystal structure. In the case where the oxide semiconductor films 108_1 and 108c_3 include a spinel crystal structure, the constituent elements of the conductive films 120a and 120b enter the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. May diffuse. Note that it is preferable that the oxide semiconductor films 108_1 and 108_3 be a CAAC-OS because blocking properties of constituent elements of the conductive films 120a and 120b, for example, a copper element are increased.

In this embodiment, the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2. Although the configuration using the film is exemplified, the configuration is not limited thereto. For example, as the oxide semiconductor films 108b and 108c, In: Ga: Zn = 1: 1: 1 [atomic ratio], In: Ga: Zn = 1: 1: 1.2 [atomic ratio], In: Ga : Zn = 1: 3: 4 [atomic ratio], or an oxide semiconductor film formed using a metal oxide target of In: Ga: Zn = 1: 3: 6 [atomic ratio] Good.

Note that in the case where a metal oxide target with In: Ga: Zn = 1: 1: 1 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2). In the case where a metal oxide target with In: Ga: Zn = 1: 3: 4 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) in some cases. In the case where a metal oxide target with In: Ga: Zn = 1: 3: 6 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) in some cases.

<1-10. Method for Manufacturing Transistor>
Next, an example of a method for manufacturing the transistor 100 illustrated in FIGS. 14A to 14C will be described with reference to FIGS. 18 to 21 are cross-sectional views in the channel length (L) direction and the channel width (W) direction, which illustrate a method for manufacturing the transistor 100.

First, a conductive film 106 is formed on the substrate 102. Next, the insulating film 104 is formed over the substrate 102 and the conductive film 106, and an oxide semiconductor film is formed over the insulating film 104. After that, the oxide semiconductor film is processed into an island shape, so that the oxide semiconductor film 107 is formed (see FIG. 18A).

The conductive film 106 can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. In the embodiment, a tungsten film with a thickness of 100 nm is formed as the conductive film 106 by a sputtering method.

The insulating film 104 can be formed using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film are formed as the insulating film 104 using a PECVD apparatus.

Alternatively, oxygen may be added to the insulating film 104 after the insulating film 104 is formed. Examples of oxygen added to the insulating film 104 include oxygen radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions. Examples of the addition method include an ion doping method, an ion implantation method, and a plasma treatment method. Alternatively, after a film for suppressing desorption of oxygen is formed over the insulating film, oxygen may be added to the insulating film 104 through the film.

As a film that suppresses the desorption of oxygen described above, a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, and the above-described metal element are components. Conductive materials such as alloys described above, alloys combining the above metal elements, metal nitrides including the above metal elements, metal oxides including the above metal elements, and metal nitride oxides including the above metal elements Can be used.

In addition, when oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 104 can be increased by exciting oxygen with a microwave to generate high-density oxygen plasma.

The oxide semiconductor film 107 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that the oxide semiconductor film 107 can be processed by forming a mask over the oxide semiconductor film by a lithography process and then etching part of the oxide semiconductor film using the mask. Alternatively, the element-separated oxide semiconductor film 107 may be directly formed by a printing method.

When an oxide semiconductor film is formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, a rare gas, and a mixed gas of oxygen are used as appropriate. Note that in the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

Note that when the oxide semiconductor film is formed, for example, when a sputtering method is used, the substrate temperature is set to 150 ° C. to 750 ° C., 150 ° C. to 450 ° C., or 200 ° C. to 350 ° C. Forming a film is preferable because crystallinity can be improved.

Note that in this embodiment, a sputtering apparatus is used as the oxide semiconductor film 107, and an In—Ga—Zn metal oxide (In: Ga: Zn = 1: 1: 1.2 [atomic ratio] is used as a sputtering target. ]) Is used to form an oxide semiconductor film having a thickness of 40 nm.

Alternatively, after the oxide semiconductor film 107 is formed, heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film 107. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

The heat treatment can be performed in an inert gas atmosphere containing nitrogen or a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, or the like. The treatment time may be 3 minutes or more and 24 hours or less.

For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed, heat treatment is performed, so that the hydrogen concentration obtained by secondary ion mass spectrometry in the oxide semiconductor film is 5 × 10 ¹⁹ atoms / cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, Alternatively, it can be set to 1 × 10 ¹⁶ atoms / cm ³ or less.

Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film 107 (see FIG. 18B).

As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD method. In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

Further, as the insulating film 110_0, the flow rate of the oxidizing gas is greater than 20 times and less than 100 times, or greater than or equal to 40 times and less than or equal to 80 times, and the pressure in the treatment chamber is less than 100 Pa or less than 50 Pa. By using the PECVD method, a silicon oxynitride film with a small amount of defects can be formed.

In addition, as the insulating film 110_0, the substrate placed in the processing chamber evacuated in the PECVD apparatus is held at 280 ° C. or higher and 400 ° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa. Hereinafter, a dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 110_0 under conditions where the pressure is higher than or equal to 100 Pa and lower than or equal to 250 Pa and high-frequency power is supplied to an electrode provided in the treatment chamber.

Alternatively, the insulating film 110_0 may be formed by a plasma CVD method using a microwave. Microwave refers to the frequency range from 300 MHz to 300 GHz. In the microwave, the electron temperature is low and the electron energy is small. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110_0 with little plasma damage to the deposition surface and deposits and few defects can be formed.

The insulating film 110_0 can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. Use of silicon-containing compounds such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) it can. By using a CVD method using an organosilane gas, the insulating film 110_0 with high coverage can be formed.

In this embodiment, as the insulating film 110_0, a silicon oxynitride film with a thickness of 100 nm is formed using a PECVD apparatus.

Next, after a mask is formed by lithography at a desired position over the insulating film 110_0, the insulating film 110_0 and part of the insulating film 104 are etched, so that an opening 143 reaching the conductive film 106 is formed (FIG. 18 (C)).

As a method for forming the opening 143, a wet etching method and / or a dry etching method can be used as appropriate. In this embodiment, the opening 143 is formed using a dry etching method.

Next, an oxide semiconductor film 112_0 is formed over the insulating film 110_0 so as to cover the opening 143. Note that when the oxide semiconductor film 112_0 is formed, oxygen is added from the oxide semiconductor film 112_0 to the insulating film 110_0 (see FIG. 18D).

As a method for forming the oxide semiconductor film 112_0, a sputtering method is preferably used in an atmosphere containing oxygen gas at the time of formation. By forming the oxide semiconductor film 112_0 in an atmosphere containing oxygen gas at the time of formation, oxygen can be preferably added to the insulating film 110_0.

Note that in FIG. 18D, oxygen added to the insulating film 110_0 is schematically represented by an arrow. In addition, by forming the oxide semiconductor film 112_0 so as to cover the opening 143, the conductive film 106 and the oxide semiconductor film 112_0 are electrically connected to each other.

In this embodiment, a sputtering apparatus is used as the oxide semiconductor film 112_0, and an In—Ga—Zn metal oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) is used as a sputtering target. Is used to form an oxide semiconductor film with a thickness of 100 nm.

Next, a mask 140 is formed by a lithography process at a desired position over the oxide semiconductor film 112_0 (see FIG. 19A).

Next, the oxide semiconductor film 112_0 is processed by etching from above the mask 140, so that the island-shaped oxide semiconductor film 112 is formed (see FIG. 19B).

In this embodiment, the oxide semiconductor film 112_0 is processed by a wet etching method.

Subsequently, the insulating film 110_0 is processed by etching from above the mask 140 to form the island-shaped insulating film 110 (see FIG. 19C).

In this embodiment, the insulating film 110_0 is processed using a dry etching method.

Note that when the oxide semiconductor film 112 and the insulating film 110 are processed, the thickness of the oxide semiconductor film 107 in a region where the oxide semiconductor film 112 is not overlapped may be thin. Alternatively, when the oxide semiconductor film 112 and the insulating film 110 are processed, the thickness of the insulating film 104 in a region where the oxide semiconductor film 107 does not overlap may be reduced.

Next, after removing the mask 140, an impurity element 145 is added over the insulating film 104, the oxide semiconductor film 107, and the oxide semiconductor film 112 (see FIG. 19D).

As a method for adding the impurity element 145, there are an ion doping method, an ion implantation method, a plasma treatment method, and the like. In the case of the plasma treatment method, the impurity element can be added by performing plasma treatment by generating plasma in a gas atmosphere containing the impurity element to be added. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

Note that as source gases for the impurity element 145, B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, H ₂ and rare One or more of the gases can be used. Alternatively, one or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas can be used. One or more of B ₂ H ₆ , PH ₃ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , F ₂ , HF, and H ₂ diluted with a rare gas is used to convert the impurity element 145 into the oxide semiconductor film 107 and By adding the oxide semiconductor film 112, one or more of a rare gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor film 107 and the oxide semiconductor film 112. it can.

Alternatively, after adding a rare gas, one of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ The above may be added to the oxide semiconductor film 107 and the oxide semiconductor film 112.

Or, after adding one or more of B ₂ H ₆ , PH ₃ , CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ , Si ₂ H ₆ , F ₂ , HF, and H ₂ , rare A gas may be added to the oxide semiconductor film 107 and the oxide semiconductor film 112.

The addition of the impurity element 145 may be controlled by appropriately setting implantation conditions such as an acceleration voltage and a dose. For example, when argon is added by an ion implantation method, the acceleration voltage may be 10 kV to 100 kV and the dose may be 1 × 10 ¹³ ions / cm ^{2 to} 1 × 10 ¹⁶ ions / cm ² , for example, 1 × It may be 10 ¹⁴ ions / cm ² . In addition, when phosphorus ions are added by an ion implantation method, an acceleration voltage of 30 kV and a dose amount of 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less may be used, for example, 1 × 10 ¹⁵ ions. / Cm ² is sufficient.

Further, in this embodiment mode, the structure in which the impurity element 145 is added after the mask 140 is removed is illustrated; however, the present invention is not limited to this. For example, the impurity element 145 is left in a state where the mask 140 remains. Addition may be performed.

In this embodiment, argon is added to the oxide semiconductor film 107 and the oxide semiconductor film 112 as the impurity element 145 using a doping apparatus. Note that although the structure in which argon is added as the impurity element 145 is described in this embodiment, the present invention is not limited thereto, and for example, the step of adding the impurity element 145 may not be performed.

Note that when the impurity element 145 is added, a large amount of impurities are added to a region where the surface of the oxide semiconductor film 107 is exposed (a region to be the source region 108s and the drain region 108d later). On the other hand, an impurity element 145 is added through the insulating film 110 to a region where the oxide semiconductor film 112 of the oxide semiconductor film 107 does not overlap and the insulating film 110 overlaps (a region to be a region 108f later). Therefore, the amount of the impurity element 145 added is smaller than that of the source region 108s and the drain region 108d.

In this embodiment, argon is added to the oxide semiconductor film 107 and the oxide semiconductor film 112 as the impurity element 145 using a doping apparatus.

Note that although a structure in which argon is added as the impurity element 145 is illustrated in this embodiment mode, the present invention is not limited thereto, and for example, the step of adding the impurity element 145 may not be performed. When the step of adding the impurity element 145 is not performed, the region 108f has an impurity concentration equivalent to that of the channel region 108i.

Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 107, the insulating film 110, and the oxide semiconductor film 112. Note that when the insulating film 116 is formed, the oxide semiconductor film 107 in contact with the insulating film 116 becomes the source region 108s and the drain region 108d. In addition, the oxide semiconductor film 107 that is not in contact with the insulating film 116, in other words, the oxide semiconductor film 107 that is in contact with the insulating film 110 serves as a channel region 108i. Thus, the oxide semiconductor film 108 including the channel region 108i, the source region 108s, and the drain region 108d is formed (see FIG. 20A).

The insulating film 116 can be formed by selecting a material that can be used for the insulating film 116. In this embodiment, a 100-nm-thick silicon nitride film is formed as the insulating film 116 using a PECVD apparatus.

By using a silicon nitride film as the insulating film 116, hydrogen in the silicon nitride film enters the oxide semiconductor film 112, the source region 108 s, and the drain region 108 d in contact with the insulating film 116, so that the oxide semiconductor film 112 and the source region The carrier density of 108s and the drain region 108d can be increased.

Note that a region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.

Next, an insulating film 118 is formed over the insulating film 116 (see FIG. 20B).

The insulating film 118 can be formed by selecting a material that can be used for the insulating film 118. In this embodiment, a 300-nm-thick silicon oxynitride film is formed as the insulating film 118 using a PECVD apparatus.

Next, after a mask is formed by lithography at a desired position of the insulating film 118, a part of the insulating film 118 and the insulating film 116 is etched, so that the opening 141a reaching the source region 108s and the drain region 108d are formed. And reaching the opening 141b (see FIG. 20C).

Next, an insulating film 122 is formed over the insulating film 118 (see FIG. 20D).

Note that the insulating film 122 functions as a planarization insulating film. In addition, the insulating film 122 has openings at positions overlapping with the openings 141a and 141b.

In this embodiment mode, as the insulating film 122, a photosensitive acrylic resin is applied using a spin coater, and then a desired region of the acrylic resin is exposed to expose the insulating film 122 having an opening. Form.

Next, a conductive film 120 is formed over the insulating film 122 so as to cover the openings 141a and 141b (see FIG. 21A).

Next, after a mask is formed at a desired position on the conductive film 120 by a lithography process, part of the conductive film 120 is etched to form conductive films 120a and 120b (see FIG. 21B). .

In this embodiment, a dry etching method is used for processing the conductive film 120. Further, when the conductive film 120 is processed, part of the upper portion of the insulating film 122 may be removed.

Through the above steps, the transistor 100C illustrated in FIG. 14 can be manufactured.

Note that a film (an insulating film, an oxide semiconductor film, a conductive film, or the like) included in the transistor 100 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulse laser deposition (PLD) method, or an ALD (atom). It can be formed using a layer deposition method. Alternatively, it can be formed by a coating method or a printing method. As a film forming method, a sputtering method and a plasma enhanced chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used. An example of the thermal CVD method is an MOCVD (metal organic chemical vapor deposition) method.

In the thermal CVD method, the inside of a chamber is set to atmospheric pressure or reduced pressure, and a raw material gas and an oxidant are simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. Thus, the thermal CVD method is a film forming method that does not generate plasma, and thus has an advantage that no defect is generated due to plasma damage.

In addition, in the ALD method, film formation is performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, introducing and reacting a source gas for reaction into the chamber, and repeating this. An inert gas (such as argon or nitrogen) may be introduced as a carrier gas together with the source gas. For example, two or more kinds of source gases may be sequentially supplied to the chamber. At that time, an inert gas is introduced after the reaction of the first source gas so that a plurality of types of source gases are not mixed, and a second source gas is introduced. Alternatively, the second source gas may be introduced after the first source gas is exhausted by evacuation instead of introducing the inert gas. The first source gas is adsorbed and reacted on the surface of the substrate to form the first layer, and the second source gas introduced later is adsorbed and reacted to make the second layer the first layer. A thin film is formed by being laminated on top. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repeated gas introductions, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

A thermal CVD method such as an MOCVD method can form a film such as the above-described conductive film, insulating film, oxide semiconductor film, or metal oxide film. For example, an In—Ga—Zn—O film is formed. In this case, trimethylindium (In (CH ₃ ) ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), and dimethyl zinc are used (Zn (CH ₃ ) ₂ ). Without being limited to these combinations, triethylgallium (Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (Zn (C ₂ H ₅ ) ₂ ) is used instead of dimethylzinc. You can also

For example, when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ] ₄ ) ) Or tetrakis (ethylmethylamide) hafnium) or the like, and two gases of ozone (O ₃ ) are used as an oxidizing agent.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a raw material gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA, Al (CH ₃ ) ₃ )) containing a solvent and an aluminum precursor is used. Two types of gas, H ₂ O, are used as the oxidizing agent. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, when a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by sequentially introducing WF ₆ gas and B ₂ H ₆ gas, and then WF ₆ gas and H ₂ gas. To form a tungsten film. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, an In—O layer is formed using In (CH ₃ ) ₃ gas and O ₃ gas. Then, a GaO layer is formed using Ga (CH ₃ ) ₃ gas and O ₃ gas, and then a ZnO layer is formed using Zn (CH ₃ ) ₂ gas and O ₃ gas. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred.

As described above, the structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 2)
In this embodiment, the structure and the like of an oxide semiconductor will be described with reference to FIGS.

<2-1. Structure of oxide semiconductor>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

In other words, a stable oxide semiconductor cannot be called a complete amorphous semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.

<2-2. CAAC-OS>
First, the CAAC-OS will be described.

CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 22E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 22E is considered to be derived from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, it is considered that the second ring in FIG. 22E is caused by the (110) plane or the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of CAAC-OS is observed with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

FIG. 23A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 23A shows a pellet that is a region where metal atoms are arranged in layers. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). The CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS and is parallel to the surface or top surface of the CAAC-OS.

FIGS. 23B and 23C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. FIGS. 23D and 23E are images obtained by performing image processing on FIGS. 23B and 23C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is acquired by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 23D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 23 (E), a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting the surrounding lattice points around the lattice points near the dotted line. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the bond distance between atoms is not dense in the ab plane direction, or the bond distance between atoms changes when a metal element is substituted. This is thought to be possible.

As described above, the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction and have a strain. Therefore, the CAAC-OS can also be referred to as an oxide semiconductor having CAA crystal (c-axis-aligned ab-plane-anchored crystal).

CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, in reverse, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

When an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light or heat. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and a carrier of 1 × 10 ⁻⁹ / cm ³ or more. A dense oxide semiconductor can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<2-3. nc-OS>
Next, the nc-OS will be described.

A case where nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm in parallel to the formation surface, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 24B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 24B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

FIG. 24D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

Thus, nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

Nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<2-4. a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 25 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 25A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 25B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIG. 25A and FIG. 25B, it can be seen that in the a-like OS, a striped bright region extending in the vertical direction is observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.

Prepare a-like OS, nc-OS, and CAAC-OS as samples. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 26 is an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 26, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative irradiation amount of electrons related to acquisition of a TEM image or the like. According to FIG. 26, in the crystal part (also referred to as initial nucleus) which was about 1.2 nm in the initial observation by TEM, the cumulative dose of electrons (e ⁻ ) is 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 26 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, the crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

Further, since it has a void, the a-like OS has a structure with a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

In addition, when single crystals having the same composition do not exist, the density corresponding to the single crystal having a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments or examples.

(Embodiment 3)
In this embodiment, an example of a display device in which the transistor described in the above embodiment is applied to a transistor included in a pixel will be described below with reference to FIGS.

FIG. 27 is a top view showing an example of the display device. A display device 700 illustrated in FIG. 27 includes a pixel portion 702 provided over a first substrate 701, a demultiplexer 703, a source driver 704, a gate driver 706, and a pixel portion 702 provided over the first substrate 701. The sealant 712 is disposed so as to surround the demultiplexer 703 and the gate driver 706, and the second substrate 705 is provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the demultiplexer 703, and the gate driver 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 27, a display element is provided between the first substrate 701 and the second substrate 705.

The display device 700 includes a pixel portion 702, a demultiplexer 703, a source driver 704, a gate driver 706, and a gate driver 706 in a region different from the region surrounded by the sealant 712 over the first substrate 701. FPC terminal portions 708 (FPC: Flexible printed circuit) that are electrically connected to each other are provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the demultiplexer 703, the source driver 704, and the gate driver 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the demultiplexer 703, the source driver 704, the gate driver 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the demultiplexer 703, the source driver 704, the gate driver 706, and the FPC terminal portion 708 through the signal line 710.

Further, a plurality of gate drivers 706 may be provided in the display device 700. In addition, although an example in which the gate driver 706 is formed over the same first substrate 701 as the pixel portion 702 and the source driver is a source driver IC is shown as the display device 700, the present invention is not limited to this structure. For example, the source driver 704 may be formed on the first substrate 701. Note that the source driver IC can be provided by a COG (Chip On Glass) method, a wire bonding method, or the like.

Further, the transistor exemplified in the above embodiment can be applied to a plurality of transistors in the gate driver 706 in addition to the transistor included in the demultiplexer 703 and the transistor included in the pixel.

In addition, the display device 700 can have various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grading light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements, interferometric modulation (IMOD) elements, etc.), piezoelectric ceramic displays, and the like.

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

In addition, a colored layer (also referred to as a color filter) may be used in order to display white light (W) in a backlight (an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like) and display a full color display device. Good. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when a full color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.

In addition, as a colorization method, in addition to a method (color filter method) in which part of the light emission from the white light emission described above is converted into red, green, and blue through a color filter, red, green, and blue light emission is performed. A method of using each (three-color method) or a method of converting a part of light emission from blue light emission into red or green (color conversion method, quantum dot method) may be applied.

In this embodiment mode, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 28 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 27 and has a configuration using a liquid crystal element as a display element. FIG. 29 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 27, and has a configuration in which an EL element is used as a display element.

First, common parts shown in FIGS. 28 and 29 will be described first, and then different parts will be described below.

<3-1. Explanation of common parts of display device>
A display device 700 illustrated in FIGS. 28 and 29 includes a lead wiring portion 711, a pixel portion 702, a demultiplexer 703, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the demultiplexer 703 includes a transistor 752.

The transistor 750 and the transistor 752 have the same structure as the transistor 100 described above. Note that as the structures of the transistor 750 and the transistor 752, other transistors described in the above embodiment may be used.

The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

The capacitor 790 includes a first oxide semiconductor film included in the transistor 750, a lower electrode formed through a step of processing the same oxide semiconductor film, and a conductive material functioning as a source electrode and a drain electrode included in the transistor 750. A film and an upper electrode formed through a process of processing the same conductive film. In addition, a step of forming the same insulating film as the second insulating film and the insulating film functioning as the third insulating film included in the transistor 750 between the lower electrode and the upper electrode is performed. An insulating film formed through the above is provided. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric is sandwiched between a pair of electrodes.

28 and 29, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.

As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Further, the planarization insulating film 770 may be omitted.

Further, the signal line 710 is formed through the same process as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752. Note that the signal line 710 is a conductive film formed through a different process from the source and drain electrodes of the transistors 750 and 752, for example, an oxide semiconductor formed through the same process as an oxide semiconductor film functioning as a gate electrode. A membrane may be used. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.

The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

In addition, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.

Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.

<3-2. Configuration Example of Display Device Using Liquid Crystal Element>
A display device 700 illustrated in FIG. 28 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. A display device 700 illustrated in FIG. 28 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.

The conductive film 772 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. The conductive film 772 functions as a reflective electrode. A display device 700 illustrated in FIG. 28 is a so-called reflective color liquid crystal display device that displays light through a colored film 736 by reflecting light with a conductive film 772 using external light.

As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used. In this embodiment, a conductive film that reflects visible light is used as the conductive film 772.

In the display device 700 shown in FIG. 28, unevenness is provided in part of the planarization insulating film 770 of the pixel portion 702. The unevenness can be formed, for example, by forming the planarization insulating film 770 with a resin film and providing the unevenness on the surface of the resin film. In addition, the conductive film 772 functioning as a reflective electrode is formed along the unevenness. Accordingly, when external light is incident on the conductive film 772, light can be diffusely reflected on the surface of the conductive film 772, and visibility can be improved.

Note that the display device 700 illustrated in FIG. 28 is described as an example of a reflective color liquid crystal display device; however, the present invention is not limited to this. For example, the conductive film 772 is transmitted by using a light-transmitting conductive film in visible light. Type color liquid crystal display device. In the case of a transmissive color liquid crystal display device, the unevenness provided in the planarization insulating film 770 may not be provided.

Note that although not shown in FIG. 28, an alignment film may be provided on each of the conductive films 772 and 774 on the side in contact with the liquid crystal layer 776. Although not shown in FIG. 28, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

In addition, when the horizontal electric field method is adopted, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . A liquid crystal material exhibiting a blue phase has a small viewing angle dependency.

In addition, when a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroOcell) mode. A Compensated Birefringence mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.

Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.

<3-3. Display device using light emitting element>
A display device 700 illustrated in FIG. 29 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 29 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.

Further, the conductive film 784 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive film 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used.

29, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. In the display device 700 illustrated in FIG. The insulating film 730 covers part of the conductive film 784. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 784 side or a dual emission structure in which light is emitted to both the conductive film 784 and the conductive film 788 can be used.

Further, a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the routing wiring portion 711, and the source driver 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 29, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.

Note that a display element using a light-emitting element and a display element using a liquid crystal element may be provided to overlap each other. A cross-sectional view in this case is shown in FIG. FIG. 30 illustrates the transistors M1 and M2, the liquid crystal element LC, and the light emitting element EL.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

<4. Circuit configuration of display device>
A display device illustrated in FIG. 31A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a pixel portion 502) that is disposed outside the pixel portion 502 and includes a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting elements (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.

It is desirable that part or all of the drive circuit portion 504 is formed on the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

The pixel unit 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driving circuit unit 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a data signal). , Source driver 504b, demultiplexer 504c) and the like.

The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

The source driver 504b has a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

The demultiplexer 504c is configured using, for example, the transistor described in the above embodiment. The demultiplexer 504c can time-divide the data signal by sequentially turning on the plurality of transistors, and can output the data signal to wirings to which the data signal is applied (hereinafter referred to as data lines DL_1 to DL_Y).

Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), the data signal is input from the demultiplexer 504c.

The protection circuit 506 shown in FIG. 31A is connected to, for example, the scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the demultiplexer 504 c and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

The protection circuit 506 is a circuit that brings the wiring and another wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 31A, by providing a protection circuit 506 in each of the pixel portion 502 and the driver circuit portion 504, resistance of the display device to an overcurrent generated by ESD (Electro Static Discharge) is increased. be able to.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 31A can have a structure illustrated in FIG. 31B, for example.

A pixel circuit 501 illustrated in FIG. 31B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (axially aligned micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Frequential) mode. AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

For example, in the display device including the pixel circuit 501 in FIG. 31B, for example, the pixel circuit 501 in each row is sequentially selected by the gate driver 504a illustrated in FIG. Write data.

The pixel circuit 501 in which data is written is in a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

In addition, the plurality of pixel circuits 501 illustrated in FIG. 31A can have a structure illustrated in FIG. 31C, for example.

In addition, the pixel circuit 501 illustrated in FIG. 31C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

The transistor 552 has a function of controlling data writing of the data signal by being turned on or off.

One of the pair of electrodes of the capacitor 562 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

The capacitor element 562 functions as a storage capacitor for storing written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a). Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.

Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

In the display device including the pixel circuit 501 in FIG. 31C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

The pixel circuit 501 in which data is written is in a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, a display module and an electronic device each including the display device of one embodiment of the present invention will be described with reference to FIGS.

<5-1. Display module>
A display module 8000 shown in FIG. 32 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. 8011.

The display device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

As the touch panel 8004, a resistive film type or capacitive type touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.

The backlight 8007 has a light source 8008. Note that although FIG. 32 illustrates the configuration in which the light source 8008 is provided over the backlight 8007, the present invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010 in addition to the protection function of the display panel 8006. The frame 8009 may have a function as a heat sink.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, and a prism sheet.

<5-2. Electronic equipment>
FIG. 33A to FIG. 33G illustrate electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, Includes functions to measure rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared ), A microphone 9008, and the like.

The electronic devices illustrated in FIGS. 33A to 33G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 33A to 33G are not limited to these, and can include a variety of functions. Although not illustrated in FIGS. 33A to 33H, the electronic device may have a plurality of display portions. In addition, the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.

Details of the electronic devices illustrated in FIGS. 33A to 33G will be described below.

FIG. 33A is a perspective view showing the television device 9100. FIG. The television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with a size of 50 inches or more, or 100 inches or more.

FIG. 33B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display that notifies an incoming call such as an e-mail, SNS (social networking service) or a telephone, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date, a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.

FIG. 33C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.

FIG. 33D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

33 (E), 33 (F), and 33 (G) are perspective views showing a foldable portable information terminal 9201. FIG. FIG. 33E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 33F is a state in which the portable information terminal 9201 is expanded or is in the middle of changing from the folded state to the other. FIG. 33G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

The drain currents of the transistor of one embodiment of the present invention and the LTPS (Low Temperature Poly Silicon) transistor were compared. The transistor of one embodiment of the present invention is the transistor illustrated in the above <1-5 Example of transistor structure> (hereinafter referred to as TGSA-OS). The LTPS transistor is a general n-channel transistor (hereinafter referred to as N-ch LTPS) and a p-channel transistor (hereinafter referred to as P-ch LTPS).

FIG. 34 is a graph comparing the drain currents of TGSA-OS, N-ch LTPS, and P-ch LTPS in order of the transistor size from the left. FIG. 34 shows the channel width (W) and channel length (L) of each transistor. As can be seen from FIG. 34, the TGSA-OS was confirmed to have characteristics comparable to the drain current between N-ch LTPS and P-ch LTPS of the same size.

DESCRIPTION OF SYMBOLS 10 Display apparatus 20 Source driver 30 Data distribution circuit 30A Data distribution circuit 30B Data distribution circuit 40 Pixel part 50A Gate driver 50B Gate driver 31 Demultiplexer 31_1 Demultiplexer 31_2 Demultiplexer 31_n-1 Demultiplexer 31_n Demultiplexer 32 Transistor 33 Transistor 34 De Demultiplexer 34_1 Demultiplexer 34_2 Demultiplexer 34_3 Demultiplexer 34_4 Demultiplexer 35_1 Transistor 36_1 Transistor 35_2 Transistor 36_2 Transistor 35_3 Transistor 36_3 Transistor 35_4 Transistor 36_4 Transistor 37 Demultiplexer 37_1 Demultiplexer 37_2 Demal Plexer 37_n-1 demultiplexer 37_n demultiplexer 41 transistor 42 transistor 43 transistor 100 transistor 100B transistor 100C transistor 100F transistor 100G transistor 102 substrate 104 insulating film 104_1 insulating film 104_2 insulating film 104_3 insulating film 104_4 insulating film 106 conductive film 107 oxide semiconductor film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108b Oxide semiconductor film 108c Oxide semiconductor film 108d Drain region 108f Region 108i Channel region 108s Source region 110 Insulating film 110_0 Insulating film 112 Oxide Semiconductor film 112_0 Oxide semiconductor film 112a Conductive film 112 b conductive film 114 conductive film 116 insulating film 118 insulating film 120 conductive film 120a conductive film 120b conductive film 122 insulating film 140 mask 141a opening 141b opening 143 opening 145 impurity element 147 hollow region 150 transistor 150B transistor 158 insulating film 300A transistor 302 substrate 304 conductive film 306 insulating film 306_1 insulating film 306_2 insulating film 306_3 insulating film 307 insulating film 308 oxide semiconductor film 308_1 oxide semiconductor film 308_2 oxide semiconductor film 308_3 oxide semiconductor film 312a conductive film 312b conductive film 312c conductive film 312C Conductive film 314 Insulating film 316 Insulating film 317 Insulating film 318 Insulating film 320 Conductive film 341 Opening 342 Opening 501 Pixel circuit 502 Pixel part 504 Circuit portion 504a Gate driver 504b Source driver 504c Demultiplexer 506 Protection circuit 507 Terminal portion 550 Transistor 552 Transistor 554 Transistor 560 Capacitance element 562 Capacitance element 570 Liquid crystal element 572 Light emitting element 700 Display device 701 Substrate 702 Pixel portion 703 Demultiplexer 704 Source driver 705 Substrate 706 Gate driver 708 FPC terminal portion 710 Signal line 711 Wiring portion 712 Seal material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive film 782 Light-emitting element 784 Conductive film 786 EL layer 788 Conductive film 790 Capacitor element 1280a P-type transistor 1280b N-type transistor 1280c N-type transistor 1281 Capacitor element 1282 Transistor 1311 Wiring 1312 Wiring 1313 Wiring 1314 Wiring 1315 Wiring 1316 Wiring 1317 Wiring 1351 Transistor 1352 Transistor 1353 Transistor 1354 Transistor 1360 Photoelectric conversion element 1401 Signal 1402 Signal 1403 Signal 140 Signal 1405 signal 8000 display module 8001 top cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television apparatus 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal

Claims (8)

A display device having a demultiplexer,
The demultiplexer includes a transistor,
The transistor is
A first insulating film on the first conductive film;
A first oxide semiconductor film on the first insulating film;
A second insulating film on the first oxide semiconductor film;
A second oxide semiconductor film on the second insulating film;
The first oxide semiconductor film, and a third insulating film on the second oxide semiconductor film,
The first conductive layer and the second oxide semiconductor film are electrically connected to each other through an opening provided in the first insulating film and the second insulating film. Display device. A display device having a demultiplexer,
The demultiplexer includes a transistor,
The transistor is
A first insulating film on the first conductive film;
A first oxide semiconductor film on the first insulating film;
A second insulating film on the first oxide semiconductor film;
A second oxide semiconductor film on the second insulating film;
A second conductive film on the second oxide semiconductor film;
The first oxide semiconductor film, and a third insulating film over the second conductive film,
The first conductive layer and the second oxide semiconductor film are electrically connected to each other through an opening provided in the first insulating film and the second insulating film. Display device. In claim 1 or 2,
The first oxide semiconductor film includes:
A channel region in contact with the second insulating film;
A source region in contact with the third insulating film;
A drain region in contact with the third insulating film,
The second oxide semiconductor film is
A display device having a carrier density higher than that of the first oxide semiconductor film. In claim 1 or 2,
The third insulating film is
Having one or both of nitrogen and hydrogen,
A display device characterized by that. In claim 1 or 2,
One or both of the first oxide semiconductor film and the second oxide semiconductor film are
Oxygen, In, Zn, and M (M is Al, Ga, Y, or Sn),
A display device characterized by that. In claim 1 or 2,
One or both of the first oxide semiconductor film and the second oxide semiconductor film are
Having a crystal part, the crystal part has c-axis orientation,
A display device characterized by that. A display device according to claim 1 or 2,
A touch sensor;
A display module comprising: A display device according to claim 1 or 2,
An electronic device comprising an operation key or a battery.

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