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WO2017113191A1 - Dispositif d'affichage porté sur la tête - Google Patents

Dispositif d'affichage porté sur la tête Download PDF

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Publication number
WO2017113191A1
WO2017113191A1 PCT/CN2015/099871 CN2015099871W WO2017113191A1 WO 2017113191 A1 WO2017113191 A1 WO 2017113191A1 CN 2015099871 W CN2015099871 W CN 2015099871W WO 2017113191 A1 WO2017113191 A1 WO 2017113191A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
circuit
display device
output
power input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/099871
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English (en)
Chinese (zh)
Inventor
施宏艳
郭继龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Royole Technologies Co Ltd
Original Assignee
Shenzhen Royole Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Royole Technologies Co Ltd filed Critical Shenzhen Royole Technologies Co Ltd
Priority to PCT/CN2015/099871 priority Critical patent/WO2017113191A1/fr
Priority to CN201580075340.3A priority patent/CN107209379B/zh
Publication of WO2017113191A1 publication Critical patent/WO2017113191A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/01—Head-up displays
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones

Definitions

  • the present invention relates to display devices, and more particularly to a head mounted display device.
  • the embodiment of the invention discloses a head-mounted display device, which can charge the head-mounted display device anytime and anywhere by using a portable solar panel, satisfies the requirement of battery life and does not increase the volume of the head-mounted display device and weight.
  • a head-mounted display device includes a display device, an earphone device, a solar panel disposed on a surface of the display device and/or the earphone device, and a voltage stabilization control disposed inside the display device or the earphone device Circuit.
  • the solar panel is configured to convert solar energy into electrical energy
  • the voltage stabilizing control circuit is configured to voltage the power voltage output by the solar panel to a predetermined voltage, and supply the display device and the earphone device with the predetermined voltage.
  • the head-mounted display device of the present invention supplies power through the solar panel, improves the endurance capability, and only needs a small-capacity built-in battery, which is advantageous for the lightness of the head-mounted display device.
  • the head-mounted display device of the present invention can charge the head-mounted display device anytime and anywhere by using a portable solar panel, which satisfies the requirements of battery life without increasing the size and weight of the head-mounted display device.
  • FIG. 1 is a perspective view of a head mounted display device in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a solar panel of a head mounted display device according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a light path of a solar panel of a head mounted display device according to an embodiment of the invention
  • FIG. 4 is a structural block diagram of a voltage stabilizing control circuit of a head mounted display device according to an embodiment of the present invention
  • FIG. 5 is a specific circuit diagram of a voltage stabilizing control circuit of a head mounted display device according to an embodiment of the present invention.
  • FIG. 1 is a perspective view of a head mounted display device 100 according to an embodiment of the invention.
  • the head mounted display device 100 includes a display device 10, an earphone device 20, a solar panel 30 disposed on a surface of the display device 10 and/or the earphone device 20, and a voltage stabilizing control circuit 40 (shown in FIG. 4).
  • the solar panel 30 is configured to convert solar energy into electrical energy.
  • the voltage stabilizing control circuit 40 is configured to regulate the electrical energy output by the solar panel 30 to a predetermined voltage, and supply power to the display device 10 and the earphone device 20 at the predetermined voltage.
  • the predetermined voltage is a normal operating voltage of the display device 10 and the earphone device 20, for example, 5 volts.
  • the solar panel 30 by using the solar panel 30, charging or pairing can be performed anytime and anywhere
  • the head mounted display device 100 is powered, and the battery of the head mounted display device 100 can be made smaller, improving the endurance and facilitating the head mounted display device 100 to reduce the size and weight.
  • the earphone device 20 includes an endless belt 21 and an earpiece 22 disposed at both ends of the endless belt 21.
  • the number of the solar panels 30 is at least two, which are respectively disposed on an outer surface of the display device 10 and an outer surface of the endless belt 21 of the earphone device 20, and the solar panels are respectively disposed. 30 parallel or series to form a solar battery pack.
  • the voltage stabilizing control circuit 40 is coupled to all of the solar panels 30 for converting the total output electrical energy of all of the solar panels 30 to a predetermined voltage to power the display device 10 and the earphone device 20.
  • the solar cell panel 30 includes aspherical microlens layer 31 and a photoelectric conversion layer 32 which are stacked.
  • the aspherical microlens layer 31 is used to conduct solar light convergence to the photoelectric conversion layer 32.
  • the photoelectric conversion layer 32 is used for photoelectric conversion to convert sunlight into electrical energy.
  • the aspherical microlens layer 31 has a wavy aspherical surface on the outer surface thereof, which can increase the light-receiving area.
  • each microlens has a small focusing spot and a high energy density, and the light is effectively concentrated.
  • the photoelectric conversion efficiency of the photoelectric conversion layer 32 is improved.
  • the aspherical microlens layer 31 can be made of a highly transparent material (polymer material or glass) material, and both sides of the aspherical microlens layer 31 are plated with a visible-near infrared antireflection film for increasing visible light and near infrared. Light penetration rate.
  • the photoelectric conversion layer 32 may include a plurality of semiconductor photodiodes arranged in an array, and when the sunlight is conducted to the semiconductor photodiode through the aspherical microlens layer 31, the semiconductor photodiode converts the light energy into electrical energy.
  • the voltage regulator control circuit 40 includes a power input interface 41, a voltage detecting unit 42, a boosting circuit 43, a step-down circuit 44, a circuit selecting unit 45, and a power output interface 46.
  • the power input interface 41 is for connecting to the solar panel 30 and receiving the electrical energy converted by the solar panel 30.
  • the voltage detecting unit 42 is configured to detect the voltage of the power input by the power input interface 41.
  • the boosting circuit 43 and the step-down circuit 44 are electrically connected in parallel between the power input interface 41 and the power output interface 46.
  • the circuit selecting unit 45 is configured to compare the voltage detected by the voltage detecting unit 42 with a predetermined voltage, and establish a connection between the boosting circuit 43 and the power input interface 41 when determining that the detected voltage is less than the predetermined voltage.
  • the connection between the buck circuit 44 and the power input interface 41 is disconnected.
  • the boosting circuit 43 boosts the power voltage input by the power input interface 41 to the predetermined voltage, and supplies it to the display device 10 of the head mounted display device 100 and each of the earphone devices 20 through the power output interface 46.
  • Functional components are configured to compare the voltage detected by the voltage detecting unit 42 with a predetermined voltage, and establish a connection between the boosting circuit 43 and the power input interface 41 when determining that the detected voltage is less than the predetermined voltage.
  • the connection between the buck circuit 44 and the power input interface 41 is disconnected.
  • the boosting circuit 43 boosts the power voltage input by the power input interface 41 to the predetermined voltage, and supplies it to the display device 10 of the head mounted display device 100 and each of the
  • the circuit selecting unit 45 establishes a connection between the step-down circuit 44 and the power input interface 41 to disconnect the connection between the boosting circuit 43 and the power input interface 41 when determining that the detected voltage is greater than the predetermined voltage.
  • the step-down circuit 44 steps down the power voltage connected to the power input interface 41 to the predetermined voltage, and supplies it to the display device 10 of the head mounted display device 100 and each of the earphone devices 20 through the power output interface 46.
  • the boosting circuit 43 or the step-down circuit 44 can be automatically operated in accordance with the level of the voltage output from the solar panel 30, and the output voltage is maintained at a predetermined voltage, thereby maintaining a stable voltage supply.
  • the voltage stabilization control circuit 40 further includes a first path switch 47 and a second path switch 48.
  • the first path switch 47 is electrically connected between the power input interface 41 and the boost circuit 43.
  • the second path switch 48 is electrically connected between the power input interface 41 and the step-down circuit 44.
  • the circuit selection unit 45 is connected to the first path switch 47 and the second path switch 48. When it is determined that the detected voltage is less than the predetermined voltage, the first path switch 47 is controlled to be turned on and the second path switch 48 is turned off. A connection between the booster circuit 43 and the power input interface 41 is established to disconnect the buck circuit 44 from the power input interface 41.
  • the circuit selecting unit 45 controls the first path switch 47 to be turned off and the second path switch 48 to be turned on when determining that the detected voltage is greater than the predetermined voltage, thereby establishing a connection between the step-down circuit 44 and the power input interface 41. The connection between the booster circuit 43 and the power input interface 41 is disconnected.
  • FIG. 5 is a specific circuit diagram of the voltage stabilization control circuit 40 according to an embodiment of the present invention.
  • the voltage detecting unit 42 includes resistors R1, R2 connected in series between the positive terminal V+ and the ground terminal V- of the power input interface 41.
  • the circuit selection unit 45 includes a detection terminal AD_IN, a first enable terminal EN1, and a second enable terminal. EN2.
  • the detecting terminal AD_IN is connected to the connection node of the resistor R1 and the resistor R2 for obtaining the voltage of the connection node of the resistor R1 and the resistor R2.
  • the circuit selection unit 45 compares the voltage received by the detection terminal AD_IN with a first reference voltage Vr1, and determines the output of the power input interface 41 when the voltage received by the comparison detection terminal AD_IN is greater than the first reference voltage Vr1.
  • the voltage is greater than the predetermined voltage, and the second enable terminal EN2 is controlled to output a high level enable signal, and the first enable terminal EN1 outputs a low level signal.
  • the circuit selecting unit 45 determines that the voltage output by the power input interface 41 is less than the predetermined voltage when the voltage received by the detecting terminal AD_IN is less than the first reference voltage Vr1, and controls the second enabling terminal EN2 to output a low level signal. , EN1 outputs a high level enable signal.
  • the first reference voltage Vr1 predetermined voltage*R2/(R1+R2), so that when the voltage output by the power input interface 41 is greater than the predetermined voltage, the voltage received by the detecting terminal AD_IN will also be greater than the first The reference voltage Vr1, when the voltage output by the power input interface 41 is less than the predetermined voltage, the voltage received by the detecting terminal AD_IN will also be less than the first reference voltage Vr1.
  • the first path switch 47 includes a PMOS transistor Q1 and an NPN transistor Q2.
  • the source of the PMOS transistor Q1 is connected to the positive terminal V+ of the power input interface 41, the drain is connected to the boosting circuit 43, and the gate is connected to the NPN transistor Q2.
  • the emitter of the NPN transistor Q2 is grounded, and the base is connected to the first enable terminal EN1 of the circuit selection unit 45.
  • the NPN transistor Q2 receives the high level enable signal from the first enable terminal EN1
  • the NPN transistor Q2 is turned on, and the gate of the PMOS transistor Q1 is grounded through the turned-on NPN transistor Q2 and is also turned on.
  • the first path switch 47 turns on the electrical connection between the positive terminal V+ of the power input interface 41 and the boosting circuit 43.
  • the second path switch 48 includes a PMOS transistor Q3 and an NPN transistor Q4.
  • the source of the PMOS transistor Q3 is connected to the positive terminal V+ of the power input interface 41, the drain is connected to the step-down circuit 44, and the gate is connected to the NPN transistor Q4.
  • the emitter of the NPN transistor Q4 is grounded, and the base is connected to the second enable terminal EN2 of the circuit selection unit 45.
  • the NPN transistor Q4 receives the high level enable signal from the second enable terminal EN2
  • the NPN transistor Q4 is turned on, the PMOS
  • the gate of the transistor Q3 is also turned on by the conduction of the turned-on NPN transistor Q4.
  • the second path switch 48 turns on the electrical connection between the positive terminal V+ of the power input interface 41 and the step-down circuit 44.
  • the booster circuit 43 includes a boost controller 431, an NMOS transistor Q5, an inductor L1, a capacitor C1, a diode D1, and an output terminal Vcc1.
  • the inductor L1 and the capacitor C1 form an LC filter tank circuit.
  • the boost controller 431 includes a voltage terminal vin1 and a PWM (plus width modulation) output terminal sw1.
  • the voltage terminal vin1 is used to connect to the positive terminal V+ of the power input interface 41 to receive the operating voltage.
  • the PWM output terminal sw1 is connected to the gate of the NMOS transistor Q5 for outputting a PWM signal to the NMOS transistor Q5.
  • the first end P11 of the inductor L1 is electrically connected to the source of the PMOS transistor Q1 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, and the second end P12 of the inductor L1 is connected to the anode of the diode D1 and the source of the NMOS transistor Q5.
  • the cathode of the diode D1 is connected to the output terminal Vcc1.
  • the drain of the NMOS transistor Q5 is grounded through a resistor R3.
  • the boost controller 431 controls the PMOS transistor Q1 to be turned on to establish an electrical connection between the power input interface 41 and the booster circuit 43, the PWM output Sw1 outputs A PWM signal having a certain duty cycle causes the NMOS transistor Q5 to be turned on and off periodically.
  • the PWM signal is at a high level
  • the NMOS transistor Q5 is turned on, and at this time, the inductor L1 forms a current loop through the turned-on NMOS transistor Q5, and current flows from the power input interface 41 through the PMOS transistor Q1.
  • the D1 cutoff does not conduct, and the voltage across the capacitor C2 is equal to the output voltage Vcc1.
  • the NMOS transistor Q5 When the PWM signal is at a low level, the NMOS transistor Q5 is turned off, and the inductor L1 generates a right positive left negative negative electromotive force, and the back electromotive force is superimposed with the voltage output from the power input interface 41 and larger than the voltage output by the power input interface 41.
  • the output voltage of the second terminal P12 of the inductor L1 is substantially equal to the sum of the voltage output from the power input interface 41 and the counter electromotive force generated by the inductor L1.
  • the output voltage of the second terminal P12 of the inductor L1 will be approximately equal to the 0V voltage for a period of time, and for a further period of time greater than the voltage output by the power input interface 41.
  • the equivalent voltage of the voltage outputted by the output terminal Vcc1 will be greater than the voltage outputted by the power input interface 41, and the boosting effect is exerted.
  • the functional element 50 of the head mounted display device 100 is thereby powered by the power output interface 46.
  • the functional component 50 is a respective power consuming component in the display device 10 and the earphone device 20.
  • the boosting circuit 43 further includes a capacitor C2 connected between the cathode of the diode D1, the output terminal Vcc1 and the ground for filtering and further regulating the voltage outputted by the output terminal Vcc1.
  • the booster circuit 43 further includes a resistor R4 and a resistor R5 connected in series between the output terminal Vcc1 and the ground.
  • the boost controller 431 is further configured to control a duty ratio of the PWM signal output by the PWM output terminal sw1 according to the feedback voltage Vref1 received by the feedback terminal F1, so that the output voltage of the output terminal Vcc1 is maintained at the predetermined voltage, for example, Maintain at 5V.
  • the boost controller 431 compares the feedback voltage Vref1 with the second reference voltage Vr2. If the feedback voltage Vref1 is greater than the second reference voltage Vr2, it is determined that the output voltage of the output terminal Vcc1 is greater than the predetermined voltage.
  • the boost controller 431 controls the duty ratio of the PWM signal that reduces the output such that the time greater than the voltage output by the power input interface 41 in one cycle becomes shorter, thereby reducing the output voltage of the output terminal Vcc1.
  • the boost controller 431 controls the duty ratio of the PWM signal that increases the output, so that one cycle The time larger than the voltage output from the power input interface 41 becomes longer, thereby increasing the output voltage of the output terminal Vcc1.
  • the output voltage of the output terminal Vcc1 is maintained at the predetermined voltage.
  • the second reference voltage Vr2 predetermined voltage*R4/(R3+R4).
  • the boost controller 431 further includes a detecting end Dt1 connected to the connection node of the NMOS transistor Q5 and the resistor R3 for detecting the current flowing through the NMOS transistor Q5, and detecting according to the detected The current is overcurrent protected to avoid damage to the NMOS transistor Q5. Specifically, when the current detected by the detecting terminal Dt1 is greater than an overcurrent protection value, the boost controller 431 controls to reduce the duty ratio of the PWM signal output by the PWM output terminal sw1 or directly turn off the output of the PWM waveform. Therefore, the current flowing through the NMOS transistor Q5 becomes small.
  • the buck circuit 44 includes a buck controller 441, an NMOS transistor Q6, and an inductor. L2, capacitor C3, diode D2 and output terminal Vcc2. This capacitor C3 is used for energy storage filtering.
  • the buck controller 441 includes a voltage terminal vin2 and a PWM output terminal sw2. The voltage terminal vin2 is used to connect to the positive terminal V+ of the power input interface 41 to receive an operating voltage.
  • the PWM output terminal sw2 is connected to the gate of the NMOS transistor Q6 for outputting a PWM signal to the NMOS transistor Q6.
  • the source of the NMOS transistor Q6 is connected to the drain of the PMOS transistor Q3 and one end of the capacitor C3, and the drain of the NMOS transistor Q6 is connected to the first terminal P21 of the inductor L2 and the cathode of the diode D2.
  • the other end of the capacitor C3 is grounded to the anode of the diode D2.
  • the second end P22 of the inductor L2 is electrically connected to the output terminal Vcc2.
  • the circuit selection unit 45 controls the PMOS transistor Q3 to be turned on to establish an electrical connection between the power input interface 41 and the step-down circuit 44, and the PWM output terminal sw2 has an output.
  • a certain duty cycle PWM signal causes the NMOS transistor Q6 to be turned on and off periodically.
  • the NMOS transistor Q6 is turned on.
  • the current output from the power input interface 41 passes through the PMOS transistor Q3, the NMOS transistor Q6 flows to the inductor L2, and passes through the inductor.
  • L2 is output to the output terminal Vcc2.
  • the sum of the voltage of the second terminal P22 of the inductor L2 and the voltage output by the power input interface 41 is equal to V+ of the power input interface 41.
  • the NMOS transistor Q6 When the PWM signal is at a low level, the NMOS transistor Q6 is turned off, the electrical connection between the power input interface 41 and the inductor L2 is broken, and the inductor L2 generates a right positive left negative negative electromotive force, which is substantially equal to the output voltage Vcc2. At this time, the output voltage of the second terminal P22 of the inductor L2 is smaller than the voltage output by the power input interface 41. Thus, during one PWM signal period, the output voltage of the second terminal P22 of the inductor L2 will be equal to the output voltage Vcc2 for a period of time, and less than the voltage output by the power input interface 41 for another period of time.
  • the equivalent voltage of the voltage outputted by the output terminal Vcc2 will be smaller than the voltage output by the power input interface 41, and the voltage drop effect is achieved.
  • the voltage output by the output terminal Vcc2 supplies power to the functional elements 50 of the head mounted display device 100 through the power output interface 46.
  • the buck circuit 44 further includes a capacitor C4 connected between the second end P22 of the inductor L2, the output terminal Vcc2 and the ground for filtering and further regulating the voltage outputted by the output terminal Vcc2. .
  • the step-down circuit 44 further includes a resistor R6 and a resistor R7 connected in series between the output terminal Vcc2 and the ground.
  • the buck controller 441 further includes a feedback terminal F2, the feedback terminal F2 and the resistor R6 and the resistor
  • the buck controller 441 is further configured to control the duty ratio of the PWM signal output by the PWM output terminal sw2 according to the feedback voltage Vref2 received by the feedback terminal F2, so that the output voltage of the output terminal Vcc2 is maintained at the predetermined voltage, for example, Maintain at 5V.
  • the buck controller 441 compares the feedback voltage Vref2 with the third reference voltage Vr3. If the feedback voltage Vref2 is greater than the third reference voltage Vr3, it is determined that the output voltage of the output terminal Vcc2 is greater than the predetermined voltage.
  • the buck controller 441 controls the duty ratio of the PWM signal that reduces the output such that the time less than the voltage output by the power input interface 41 in one cycle becomes longer, thereby reducing the output voltage of the output terminal Vcc2.
  • the buck controller 441 controls the duty ratio of the PWM signal to increase the output so that one cycle
  • the sum of the internal inductor voltage and the output voltage Vcc2 is equal to the time of the voltage outputted by the power input interface 41, thereby increasing the output voltage of the output terminal Vcc2.
  • the output voltage of the output terminal Vcc2 is maintained at the predetermined voltage.
  • the third reference voltage Vr3 predetermined voltage*R7/(R6+R7).
  • the power output terminal 46 of the voltage regulator control circuit 40 can be a USB interface, and the output terminal Vcc1 of the boosting circuit 43 and the output terminal Vcc2 of the voltage reducing circuit 44 are both connected to the power supply pin VCC of the power output terminal 46. connection.
  • the head mounted display device 100 further includes a battery 60.
  • the power output 46 is also connected to the battery 60.
  • the boost circuit 43 or the step-down circuit 44 boosts or steps down the power voltage of the solar panel 30.
  • the battery 60 is charged.
  • the circuit selection unit 45 further includes a voltage terminal Vin connected to the battery 60 to receive an operating voltage from the battery 60.
  • the battery 60 can be a battery with a small capacity, so that it can be made thin and light. Since the solar panel 30 can be charged at any time, it does not affect the endurance of the head mounted display device 100.
  • the MOS tube of the present invention can be replaced by a BJT transistor, an IGBT, etc.
  • the triode can be replaced by a MOS tube and an IGBT, and the types of the MOS tube and the triode are also interchangeable.
  • the PMOS tube Q1 and Q3 can also be NMOS transistors.
  • the NPN transistors Q2 and Q4 can be PNP transistors, and the NMOS transistors Q5 and Q6 can also be PMOS transistors.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Dc-Dc Converters (AREA)

Abstract

La présente invention concerne un dispositif d'affichage porté sur la tête comprenant un appareil d'affichage (10), un appareil de casque audio (20), un panneau solaire (30) disposé sur la surface de l'appareil d'affichage (10) et/ou de l'appareil de casque audio (20) et un circuit de commande de stabilisation de tension (40) disposé à l'intérieur de l'appareil d'affichage (10) ou de l'appareil de casque audio (20). Le panneau solaire (30) est utilisé pour convertir l'énergie solaire en énergie électrique ; le circuit de commande de stabilisation de tension (40) est utilisé pour stabiliser la tension délivrée par le panneau solaire (30) à une tension prédéfinie et pour utiliser ladite tension prédéfinie afin d'alimenter en énergie l'appareil d'affichage (10) et l'appareil de casque audio (20). Le dispositif d'affichage porté sur la tête est alimenté en énergie par le panneau solaire (30), ce qui permet d'améliorer la durée de vie de la batterie et ne nécessite qu'une batterie intégrée de faible capacité, rendant ainsi le dispositif d'affichage porté sur la tête plus léger et facile à utiliser.
PCT/CN2015/099871 2015-12-30 2015-12-30 Dispositif d'affichage porté sur la tête Ceased WO2017113191A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2015/099871 WO2017113191A1 (fr) 2015-12-30 2015-12-30 Dispositif d'affichage porté sur la tête
CN201580075340.3A CN107209379B (zh) 2015-12-30 2015-12-30 头戴式显示设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2015/099871 WO2017113191A1 (fr) 2015-12-30 2015-12-30 Dispositif d'affichage porté sur la tête

Publications (1)

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WO2017113191A1 true WO2017113191A1 (fr) 2017-07-06

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CN108879973A (zh) * 2018-07-11 2018-11-23 广东电网有限责任公司 高压输电线路感应取电装置及系统
CN111065015A (zh) * 2019-12-31 2020-04-24 歌尔科技有限公司 头戴式耳机及照明方法
WO2021013042A1 (fr) * 2019-07-22 2021-01-28 华为技术有限公司 Circuit de réglage et de commande, écouteur bluetooth, chargeur et système de charge
CN113285515A (zh) * 2021-06-18 2021-08-20 东莞新能安科技有限公司 开关驱动电路、电池控制电路、电源管理系统及电池包
CN113364299A (zh) * 2021-06-25 2021-09-07 珠海格力电器股份有限公司 自适应检火电压产生电路及检火设备
KR20240033983A (ko) * 2022-09-06 2024-03-13 주식회사 피앤씨솔루션 태양광 패널을 활용한 전력생산이 가능한 증강현실 글래스 장치

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CN215185933U (zh) * 2021-02-10 2021-12-14 无锡中感微电子股份有限公司 充电管理电路、充电电路、无线耳机以及无线耳机系统

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CN203435121U (zh) * 2013-07-26 2014-02-12 张霁源 带有太阳能充电模块的头戴式耳机
CN104184396A (zh) * 2014-08-13 2014-12-03 上海电机学院 光伏供电系统及其控制方法
CN104331188A (zh) * 2014-11-06 2015-02-04 深圳市华星光电技术有限公司 一种触控模组及移动终端
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CN108879973A (zh) * 2018-07-11 2018-11-23 广东电网有限责任公司 高压输电线路感应取电装置及系统
WO2021013042A1 (fr) * 2019-07-22 2021-01-28 华为技术有限公司 Circuit de réglage et de commande, écouteur bluetooth, chargeur et système de charge
CN111065015A (zh) * 2019-12-31 2020-04-24 歌尔科技有限公司 头戴式耳机及照明方法
CN111065015B (zh) * 2019-12-31 2024-07-02 歌尔科技有限公司 头戴式耳机及照明方法
CN113285515A (zh) * 2021-06-18 2021-08-20 东莞新能安科技有限公司 开关驱动电路、电池控制电路、电源管理系统及电池包
CN113364299A (zh) * 2021-06-25 2021-09-07 珠海格力电器股份有限公司 自适应检火电压产生电路及检火设备
KR20240033983A (ko) * 2022-09-06 2024-03-13 주식회사 피앤씨솔루션 태양광 패널을 활용한 전력생산이 가능한 증강현실 글래스 장치
KR102800654B1 (ko) * 2022-09-06 2025-04-30 주식회사 피앤씨솔루션 태양광 패널을 활용한 전력생산이 가능한 증강현실 글래스 장치

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