[go: up one dir, main page]

WO2017111894A1 - Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant - Google Patents

Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant Download PDF

Info

Publication number
WO2017111894A1
WO2017111894A1 PCT/US2015/067042 US2015067042W WO2017111894A1 WO 2017111894 A1 WO2017111894 A1 WO 2017111894A1 US 2015067042 W US2015067042 W US 2015067042W WO 2017111894 A1 WO2017111894 A1 WO 2017111894A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
transistor
threshold switch
carbide
tantalum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2015/067042
Other languages
English (en)
Inventor
Elijah V. KARPOV
Ravi Pillarisetty
Uday Shah
Roza Kotlyar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to PCT/US2015/067042 priority Critical patent/WO2017111894A1/fr
Priority to TW105137907A priority patent/TW201731102A/zh
Publication of WO2017111894A1 publication Critical patent/WO2017111894A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822—Sulfides, e.g. CuS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Definitions

  • Scaling of logic devices is typically accomplished by increased leakage due to shorter channel length of the transistor.
  • a transistor When a transistor is turned off (e.g., when there is no voltage between the gate and drain terminals of the transistor), ideally no current should be flowing through the transistor. However, that is not the case. There is some current flowing even when the transistor is off. This current is called the leakage current and includes subthreshold current, gate-oxide leakage current, reverse-biased junction leakage current, etc. This current contributes to the overall power dissipation of the processor having these transistors.
  • FIG. 1A illustrates an n-type hybrid phase FET (HP-FET) with a multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • Fig. IB illustrates a p-type HP-FET with a multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • FIG. 2 illustrates an n-type HP-FET showing cross-section of the multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • Fig. 3 illustrates a plot showing Current-Voltage (IV) characteristics of the multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • Fig. 4 illustrates a plot comparing IV characteristics of the regular n-type FET with IV characteristics of an n-type HP-FET having a multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • Fig. 5 illustrates a plot showing the low resistance bound of the multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • Fig. 6 illustrates a plot showing the high resistance bound of the multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • Fig. 7 illustrates a cross-section of an HP-FET with a multi-layer threshold switch formed on the interconnect stack, in accordance with some embodiments of the disclosure.
  • FIG. 8 illustrates a cross-section of an HP-FET with a multi-layer threshold switch formed on the source region of the HP-FET, in accordance with some embodiments of the disclosure.
  • FIGs. 9A-H illustrate cross-sections of various fabrication processes for fabricating an HP-FET with a multi-layer threshold switch on the source region of the HP- FET, in accordance with some embodiments of the disclosure.
  • FIGs. 10A-O illustrate cross-sections of various fabrication processes for fabricating an HP-FET (bulk tri-gate) with a multi-layer threshold switch on the interconnect stack, where the interconnect stack is coupled to the source region of the HP-FET, in accordance with some embodiments of the disclosure.
  • Figs. 10P-Q illustrate three dimensional views of various cross-sections of
  • Figs. llA-O illustrate cross-sections of various fabrication processes for fabricating an HP-FET (Silicon-on-Insulator (SOI) tri-gate) with a multi-layer threshold switch on the interconnect stack, where the interconnect stack is coupled to the source region of the HP-FET, in accordance with some embodiments of the disclosure.
  • HP-FET Silicon-on-Insulator (SOI) tri-gate
  • Figs. 12A-C illustrate orthogonal cross-section of Fig. 10K and a 3D view of the transistor of Fig. 10C3, in accordance with some embodiments of the disclosure.
  • Figs. 13A-C illustrate orthogonal cross-section of Fig. 11K and a 3D view of the transistor of Fig. 11C3, in accordance with some embodiments of the disclosure.
  • Fig. 14 illustrates a smart device or a computer system or a SoC (System-on-
  • Various embodiments describe integration schemes and material choices for a multi-layer threshold switch of a Hybrid Phase Field Effect Transistor (HP-FET).
  • the materials are selected according to the fabrication processes. For example, in some embodiments, where the multi-layer threshold switch is formed directly on a source region of the HP-FET, a high temperature oxide material is used for the multi-layer threshold switch. In some embodiments, where the multi-layer threshold switch is formed on an interconnect stack coupled to the source region of the HP-FET, a chalcogenide based multi- layer threshold switch is used.
  • the resistance of the multi-layer threshold switch is designed such that the ON current of the HP-FET is set by the high resistance bound of the multi-layer threshold switch while the OFF current of the HP-FET is set by the maximum current that the transistor can drive.
  • ON current refers to the current through the HP-FET when the HP-FET is turned on
  • OFF current refers to the current through the HP-FET when the HP-FET is turned off.
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
  • coupled means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
  • the meaning of "a,” “an,” and “the” include plural references.
  • the meaning of "in” includes “in” and "on.”
  • scaling generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area.
  • scaling generally also refers to downsizing layout and devices within the same technology node.
  • scaling may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.
  • substantially generally refer to being within +/- 10% of a target value.
  • phrases “A and/or B” and “A or B” mean (A), (B), or (A and B).
  • phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
  • the terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
  • the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include diffusion regions such as drain and source regions, gate, and bulk terminals.
  • MOS transistors and/or the MOS transistor derivatives also include Tri- Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes, spintronic, planar (e.g., planar MOS) devices.
  • MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here.
  • a TFET device has asymmetric Source and Drain terminals.
  • transistors for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc.
  • BJT PNP/NPN Bi-polar junction transistors
  • CMOS complementary metal-oxide-semiconductor
  • MP p-type transistor
  • MN n-type transistor
  • Fig. 1A illustrates an n-type HP-FET having a multi-layer threshold switch, in accordance with some embodiments of the disclosure.
  • the n-type HP- FET comprises an n-type transistor MN1 and a multi-layer threshold switch 101 coupled in series with the transistor MN1.
  • transistor MN1 is one of: Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, TFET, Square Wire, or Rectangular Ribbon Transistors, FeFETs, or other devices implementing transistor functionality like carbon nanotubes, spintronic, planar (e.g., planar MOS) devices.
  • the transistor MN1 is one of: a tri-gate transistor with body thickness less than 5nm; Gated All Around nanowire with wire widths less than 5nm; or a device with multiple transistor fins having a gate electrode and a pair of source and drain regions that share source and drain contacts.
  • the transistor MN1 has short channel control with a subthreshold slope (SS) of 60 mV/decade to achieve maximum gain of io vth/ss in the ON to OFF current ratio over that ratio obtained in a transistor, where "Vth" is a threshold voltage of threshold switch 101
  • multi-layer threshold switch 101 is a two terminal device.
  • the first terminal of multi-layer threshold switch 101 is coupled to a source terminal Vin of transistor MN1 while the second terminal of multi-layer threshold switch 101 is coupled to ground or to a load device.
  • n-type HP-FET 100 forms a four terminal device with a gate terminal coupled to Vg, drain terminal coupled to Vd, source terminal coupled to the second terminal of multi-layer threshold switch 101, and a bulk or substrate terminal of transistor MN1.
  • Cov is the overlap capacitance due to the source region of transistor MN1 and due to multi-layer threshold switch 101.
  • the drain terminal Vd of transistor MN1 is coupled to another circuit or supply node Vdd.
  • labels for signals and nodes are interchangeably used.
  • Vg may refer to voltage Vg or node Vg depending on the context of the sentence.
  • multi-layer threshold switch 101 has a variable resistance with a high resistance bound above which the transistor MN1 does not turn on.
  • the high resistance bound of multi-layer threshold switch 101 is given by the resistance of transistor MN1 in the OFF state (i.e., ROFF) divided by the factor of (Vd/Vth- 1) where "Vd” is applied source drain bias across these two devices (i.e., transistor MN1 and multi-layer threshold switch 101) in series, and where "Vth” is a threshold voltage of multilayer threshold switch 101.
  • multi-layer threshold switch 101 has a low resistance bound below which the transistor MN1 does not turn off.
  • the low resistance bound is given by the resistance "Ron" of transistor MN1 in the ON state divided by the factor of (Vd/Vh-1), where "Vh” is a holding voltage of multi-layer threshold switch 101 below which multi-layer threshold switch 101 becomes resistive.
  • the ON current of HP-FET 100 is set by the high resistance bound of multilayer threshold 101 while the OFF current of HP-FET 100 is set by the maximum current that the transistor MN1 can drive.
  • IB illustrates p-type HP-FET 120 with multi-layer threshold switch 101, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. IB having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • HP-FET 120 forms a four terminal device with a gate terminal coupled to Vg, drain terminal coupled to Vd, source terminal coupled to the second terminal of multi -layer threshold switch 101, and a bulk or substrate terminal (not shown) of transistor MP1.
  • the source terminal of HP-FET 120 is coupled to a supply node (e.g., Vdd).
  • the ON current of HP-FET 120 is set by the high resistance bound of multi -layer threshold 101 while the OFF current of HP- FET 120 is set by the maximum current that the transistor MP1 can drive as described with reference to Fig. IB (except that the transistor is a p-type transistor).
  • FIG. 2 illustrates n-type HP-FET 200 showing the cross-section of multi-layer threshold switch 101, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • cross-section of multi-threshold device 101 includes a first electrode 201, a first barrier layer 202, a switching layer 203, a second barrier layer 204, and a second electrode 205.
  • first electrode 201 is coupled to the source terminal of transistor MNl.
  • first barrier layer 202 is coupled to first electrode 201 and switching layer 203.
  • second barrier layer 204 is coupled to switching layer 204 and second electrode 205.
  • the second electrode 205 provides the source terminal of HP-FET 200.
  • switching layer 204 comprises multicomponent ternary or quarternary alloys.
  • the multicomponent ternary or quarternary alloys include: Se, S, Te, and/or O.
  • first and second barrier layers 202 and 204, respectively, are formed of one of: metal nitrides such as TiN, TaN, and WN;
  • refractory metal carbides such as TiC, TaC, WC
  • refractory metal carbonitrides such as TaCN
  • conductive metal oxides such as Ru02, Cr02, WO2, Ir02, Pt02, or RI1O2.
  • the first and second electrodes layers 201 and 205 are formed of one of: metals, e.g., copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead; metal alloys which are alloys of metal above; metal nitrides, e.g., titanium nitride, tantalum nitride; metal carbides, e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof.
  • switching layer 204 comprises of chalcogenide material.
  • the chalcogenide material is one of: alloys of Si sulfide, selenide or telluride with Ge sulfide, selenide or telluride where fraction of Si, Ge can vary from 0% to 100%
  • As or Bi are part of Si/Ge based chalcogenides alloy discussed above.
  • transition metals such as Cu, Ga, In, Ag, and V can be used with Ge-Se/Se/Te or Si-Se/Te/S based chalcogenides.
  • switching layer 204 comprises multilayer device including one of: metal-insulator-transition (MIT) material or Mott transition material.
  • the MIT or Mott materials are formed of one of: Mott Oxides such as: NbC , metal doped NbC , VC , metal-doped V2O3, Fe304, FeS, Ta20s, T13O5, T12O3, LaCoCb, or SmNiCb, In some embodiments other MIT materi als, which undergo a volatile metal insulator transition can be used.
  • Fig. 3 illustrates plot 300 showing Current-Voltage (IV) characteristics of multi-layer threshold switch 101, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • the x-axis is voltage (in Volts (V)) and the y-axis is Current (in Amperes
  • multi-layer threshold switch 101 is engineered to have two states— metallic state (or conductive state) and insulating state. In some embodiments, the two states are switched according a bias voltage applied across the two terminals of multilayer threshold switch 101.
  • Vt e.g., 0.5V
  • multi-layer threshold switch 101 switches from an insulating state to a conducting state. At that state, the current is Ih, which is substantially non-zero.
  • voltage V e.g., Vin with reference to Fig. 1A
  • multi-layer threshold switch 101 becomes more conductive. This states is labeled as the ON state.
  • multi-layer threshold switch 101 when the initial or current condition of multi-layer threshold switch 101 is a conducting state, as voltage across multi-layer threshold switch 101 reduces and reaches a second threshold voltage Vh (e.g., 0.3V), multi-layer threshold switch 101 switches from a conducting state to an insulating state. At that state, the current is It, which is substantially zero.
  • Vh e.g., 0.3V
  • the slope of the IV curve above the second threshold voltage Vh is the resistance of multi-layer threshold switch 101 in the conductive state (i.e., Rmetaiic), while the slope of the IV curve below the second threshold voltage Vh is the resistance of multi-layer threshold switch 101 in the insulating state (i.e., Rinsuiating).
  • the first and second threshold voltages Vt and Vh are selected such that the ON current of HP-FET 200/100 is set by the high resistance bound of multi-layer threshold switch 101 while the OFF current of HP-FET 200/100 is set by the maximum current that the transistor MN1 can drive.
  • Fig. 4 illustrates plot 400 comparing the IV characteristics of the regular n- type FET and with an n-type HP-FET having a multi-layer threshold switch, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 4 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • the x-axis is Voltage (in V) and the y-axis is Current (in A).
  • Plot 400 shows two waveforms 401 and 402. Waveform 401 is the IV curve
  • Waveform 402 is the IV curve of HP-FET 200 having multi-layer threshold switch 101. Waveform 402 follows the IV curve of waveform 401 for drain-source voltage (Vds) across transistor MN1 greater than Vtdev (e.g., Vt of Fig. 3). Waveform 402 shows steep drop in current for the drain-source voltages (Vds) across transistor MN1 less than Vtdev (e.g., when Vin is closer to Vh of Fig. 3). The steep drop in current in HP-FET device allows for reduced leakage current when the transistor MN1 of HP-FET 200 is in the OFF state.
  • Fig. 5 illustrates plot 500 showing the low resistance bound of multi-layer threshold switch 101, in accordance with some embodiments of the disclosure.
  • Fig. 6 illustrates plot 600 showing the high resistance bound of multi -layer threshold switch 101, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 5-6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • the x-axis is the Vin voltage (in V) and the y-axis is the drain current (in A).
  • Fig. 5 illustrates the device operation and design principal of HP-FET 200 for the OFF state.
  • waveform 501 is the IV curve of multi-layer threshold switch 101.
  • waveform 502 is the IV curve of transistor MN1 for a gate voltage that results in the intersection of waveforms 501 and 502 at intersection point 503.
  • this intersection point 503 determines the low resistance bound of multi-layer threshold switch 101 (i.e., the design solution for the low resistance state).
  • Vd i.e., the drain voltage of transistor MNl
  • multi -layer threshold switch 101 may not allow transistor MNl to switch off, and if Vd is too high then multi-layer threshold switch 101 will always switch from conducting state to insulating state. In some embodiments, if Vd is too low, multi -layer threshold switch 101 may not allow transistor MNl to switch off, and if Vd is too high then multi-layer threshold switch 101 will always switch from conducting state to insulating state. In some embodiments, if Vd is too low, multi -layer threshold switch 101 may not allow transistor MNl to switch off, and if Vd is too high then multi-layer threshold switch 101 will always switch from conducting state to insulating state. In some embodiments, if Vd is too low, multi -layer threshold switch 101 may not allow transistor MNl to switch off, and if Vd is too high then multi-layer threshold switch 101 will always switch from conducting state to insulating state. In some embodiments, if Vd is too low, multi -layer threshold switch 101 may not allow transistor MNl to switch off, and if V
  • the subthreshold slope (SS) is determined by transistor MNl for constant RHRS (i.e., high resistance state of multilayer threshold switch 101). As such, with bias-dependent RHRS, SS is less than
  • the ratio of resistances ROFF should be greater than Vd/Vt-1 (i.e., Rt/RHRS > Vd/Vt-1, where Rt is the resistance of transistor MNl in the off state) to maintain IOFF (e.g., RHRS should not be too resistive).
  • Fig. 6 illustrates the device operation and design principal of HP-FET 200 for the ON state.
  • waveform 601 is the IV curve of transistor MNl for a gate voltage that results in the intersection of waveforms 501 and 601 at point 603.
  • this intersection point 603 determines the high resistance bound of multi-layer threshold switch 101 (i.e., the design solution for the high resistance state).
  • multilayer threshold switch 101 transitions to low resistance state (i.e., conductive state). This point of transition is illustrated by device threshold Vtdev in Fig. 4.
  • HP FET 200 in the low resistive state (LRS) is equal to It, then multi-layer threshold switch 101 switches to LRS. This is illustrated by device threshold Vtdev in Fig. 4.
  • the ratio of resistances RON i.e., Rt/Ruis
  • the ratio of resistances RON should be less than Vd/Vh-1 (i.e., Rt/RLRS ⁇ Vd/Vh-1).
  • increasing RLRS allows to lower Vtdev, but there may be an increasing penalty on ION, since RON + RLRS give the increased total resistance in the on state.
  • HP-FET 200 also referred to as one transistor
  • I S one series coupled multi-layer threshold switch 101 (I S), or simply 1T1S) is given by: ON *0N RoN(v D , v g ) RQFF(VD V TH , Vg V TH )
  • V D 1T,V D RoN V D -V H , V g -V H ) R 0 F F (v D , v g )
  • ION is the current through 1T1 S in the conductive state
  • IOFF is the leakage current through 1T1 S in the insulating state
  • W is the drain voltage (same as Vd) applied at the drain terminal Vd of transistor MN1
  • V is the gate voltage applied to transistor MN1.
  • the maximum current ratio of "ION” to “IOFF” through 1T1 S is determined by the characteristics of the transistor MN1 “ROFF” and “RON", and by the characteristics of the switch (I S) the threshold voltage Vth and the holding voltage Vh.
  • ROFF is the resistance of transistor MN1 in the off state
  • RON is the resistance of transistor MN1 in the on state
  • VH is the threshold voltage at which multi-layer threshold switch 101 switches from conducting state to insulating state (as shown with reference to Fig. 3)
  • VTH is the threshold voltage at which multi-layer threshold switch 101 switches from an insulating state to a conducting state (as shown by the transition of state at Vt with reference to Fig. 3).
  • the maximum increase of ION/IOFF is by 10 5 from ION/IOFF of transistor ratio at the same Vcc for MOSFET MN1 with an ideal subthreshold slope (SS) of 60 mV/decade.
  • the maximum resistance (RHRS.max) of multi-layer threshold switch 101 in the insulating state is engineered to be:
  • Vcc or Vdd 0.5V, Vt target of 0.3V, the
  • the minimum resistance (RLRS.min) of multi-layer threshold switch 101 in the insulating state is engineered to be:
  • R LRS min provides the low resistance bound for multi-layer threshold switch 101.
  • FIG. 7 illustrates cross-section 700 of an HP-FET with a multi-layer threshold switch formed on the interconnect stack, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • multi-layer threshold switch 101 is formed on an interconnect stack.
  • interconnect stack refers to a stack of at least one via and one metal layer.
  • Cross-section 700 illustrates a simplified version of the transistor having source region 701, drain region 702, gate region 703, substrate, vias (e.g., Vial through Via4), metal layers (e.g., Ml through M4), and multi-layer threshold switch 704/101.
  • multi-layer threshold switch 704/101 couples to a metal layer (e.g., M3) which is indirectly coupled to source region 701.
  • transistor MNl which is here shown having source region 701, drain region 702, and gate region 703
  • chalcogenide material for switching layer 203 of multi-layer threshold switch 704/101.
  • MIT or Mott based materials can also be used for forming switching layer 203 of multi-layer threshold switch 704/101.
  • Fig. 7 illustrates the multi-layer threshold switch 704/101 being placed between M3 (metal layer 3) and Via4, it can be placed anywhere on the interconnect stack indirectly coupled to source region 701, in accordance with some embodiments.
  • Fig. 8 illustrates 800 cross-section of an HP-FET with a multi-layer threshold switch formed on the source region of the HP-FET, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiment of Fig. 8, differences between Fig. 7 and Fig. 8 are described. [0055] Here, instead of multi-layer threshold switch 704/101 being placed on the interconnect stack indirectly coupled to source region 701, multi-layer threshold switch 804/101 is directly coupled to source region 701. In this configuration, in some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiment of Fig. 8, differences between Fig. 7 and Fig. 8 are described. [
  • MIT or Mott switching material is used for switching layer 203 to withstand high temperature flow for fabricating transistor MNl .
  • FIGs. 9A-H illustrate cross-sections of various fabrication processes for fabricating an HP-FET with a multi-layer threshold switch on the source region of the HP- FET, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 9A-H having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • FIG. 9A-H Although the blocks in the flowchart with reference to Figs. 9A-H are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Figs. 9A-H are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.
  • Fig. 9A shows the formation of a transistor using any known suitable process.
  • the transistor has a substrate region 901 (e.g., SiC ), active region, 902 (e.g., a lightly doped p- region), drain region 903 (e.g., n+ diffusion region), source region 904 (e.g., n+ diffusion region), dielectric region, and gate region 905 (e.g., metal gate or high K dielectric gate).
  • Fig. 9B shows a cross-section of the device after depositing multi-layer threshold switch 906 (e.g., switch layers 201-205 of Fig. 2). In some embodiments, a layer of multi-layer threshold switch 906 is deposited on top of the transistor (i.e., above drain region 903, gate region 905, and source region 904).
  • Fig. 9B shows a cross-section of the device after depositing multi-layer threshold switch 906 (e.g., switch layers 201-205 of Fig. 2).
  • a layer of multi-layer threshold switch 906 is deposited on top of the transistor (i.e.,
  • FIG. 9C illustrates a cross-section of the device after isolation fill 907 and planarization of the isolation fill.
  • S1O2 907 is deposited over layer of multi-layer threshold switch 906, and then S1O2 is planarized on the top the S1O2 layer to make a smooth flat surface of S1O2.
  • Fig. 9D illustrates a cross-section of the device after a resist material 908 is deposited on S1O2 907 (or layer of isolation fill) such that the resist material 908 is above the source region 904 but separated by a portion of the layer of multi-layer threshold switch 906 and S1O2 907. So as not to obscure the embodiments, etching of resist material 908 to show the pattern of the resist material as illustrated is not described.
  • Fig. 9E illustrates a cross-section of the device after etching of the isolation fill S1O2 907 such that a portion of multi-layer threshold switch 906 is exposed and a small portion of multi-layer threshold switch 906 remains coupled to S1O2 under resist 908.
  • Fig. 9F illustrates a cross-section of the device after etching the exposed portion of multi-layer threshold switch 906. Any known process can be used for etching the exposed portion of multi-layer threshold switch 906. As such, the portion of multi-layer threshold switch 906 underneath isolation fill S1O2 907 and directly coupled to source region 904 is left.
  • Fig. 9G illustrates a cross-section of the device after resist 908 is removed. Any known process can be used for removing resist 908.
  • Fig. 9H illustrates a cross-section of the device after the remaining portion of isolation fill S1O2 907 is etched, which leaves behind the portion of multi-layer threshold switch 906 coupled to source region 904. Following this process, vias or contacts can be formed on multi-layer threshold switch 906 to couple it to another node (e.g., ground if the transistor is an n-type FET or to power supply if the transistor is a p-type FET).
  • another node e.g., ground if the transistor is an n-type FET or to power supply if the transistor is a p-type FET.
  • FIGs. 10A-O illustrate cross-sections of various fabrication processes for fabricating an HP-FET with a multi-layer threshold switch on the interconnect stack, wherein the interconnect stack is coupled to the source region of the HP-FET, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 10A-O having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Fig. 10A shows the formation of a transistor using any known suitable process.
  • the transistor has a substrate region 1001 (e.g., S1O2), active region, 1002 (e.g., a lightly doped p- region), drain region 1003 (e.g., n+ diffusion region), source region 1004 (e.g., n+ diffusion region), and gate region 1005a (e.g., metal gate or high K dielectric gate).
  • Fig. 10B shows a cross-section of the device after depositing spacers 1006 on either sides of gate region 1005a.
  • Fig. 10C1 illustrates a cross-section of the device after isolation fill 1007 and planarization of the isolation fill.
  • SiCh 1007 is deposited over gate region 1006, drain region 1003, and source region 1004, and then SiCh 1007 is planarized on the top of SiCh layer 1007 to make a smooth flat surface of SiCh.
  • Fig. 10C2 illustrates a cross-section of the device after the isolation fill 1007 is planarized and a trench is made between spacers 1006 removing gate region 1005a and the dielectric.
  • Fig. 10C3 illustrates a cross-section of the device after dielectric is deposited along the sidewalls of spacers 1006 and the base region adjacent to active region 1002.
  • Fig. 10C4 illustrates a detailed view of metal 1005 which includes a Work Function metal and Fill metal. So as not to obscure the embodiments, the remaining figures do not show the work function metal and Fill metal separately (i.e., they are lumped together as metal 1005).
  • Fig. 10C5 illustrates a cross-section of the device after isolation fill 1007 is grown for preparation of forming trenches, in accordance with some embodiments.
  • Fig. 10D illustrates a cross-section of the device after openings 1008 and 1009 are trenched or drilled to form future contact/via regions to gate region 1005 and source region 1004.
  • openings 1008 and 1009 are collect contact regions.
  • Fig. 10E illustrates a cross-section of the device after holes 1008 and 1009 are filled with metal or via material (e.g., W).
  • contacts/vias 1010 and 1011 are formed (which are later labeled as 1010a and 1011a, respectively).
  • Fig. 10F illustrates a cross-section of the device after a series of fabrication processes to form via and metal towers (e.g., interconnect stack) over both contacts/vias 1010a and 1011a.
  • each interconnect stack or tower has three contacts/vias and three metal layers formed on top of their respective contacts/vias.
  • fewer or more contacts/vias and metal layers may be used.
  • the first interconnect stack or tower is formed of contact/via 1010a, metal layer 1 (Ml) 1012a, contact/via 1010b, metal layer 2 (M2) 1012b, contact/via 1010c, and metal layer 3 (M3) 1012c as shown.
  • the second interconnect stack or tower is formed of contact/via 1011a, metal layer 1 (Ml) 1013a, contact/via 1011b, metal layer 2 (M2) 1013b, contact/via 1011c, and metal layer 3 (M3) 1013c as shown.
  • the metal layers 1012c and 1013c are polished or planarized, and then a layer of multi-layer threshold switch 1014/704 (e.g., switch layers 201-205 of Fig. 2) is deposited.
  • the first interconnect stack or tower is formed of a contact/via stack without intervening metal interconnects.
  • the second interconnect stack or tower is formed of a contact/via stack without intervening metal interconnects.
  • Fig. 10G illustrates a cross-section of the device after a layer of hard mask
  • Fig. 10H illustrates a cross- section of the device after resist material 1016 is deposited on the layer of hard mask 1015 such that the resist material 1016 is above the source region 1004 but separated by the second interconnect stack. So as not to obscure the embodiments, etching of resist material 1016 to show the pattern of the resist material as illustrated is not described.
  • Fig. 101 illustrates a cross-section of the device after a portion of hard mask 1015 outside of resist material 1016 is etched. Any suitable etching process may be used to remove portion of hard mask 1015.
  • Fig. 10 J illustrates a cross-section of the device after resist material 1016 is removed.
  • Fig. 10K illustrates a cross-section of the device after a portion of multi-layer threshold switch 1014/704 outside of resist material 1016 is etched. Any suitable etching process may be used to remove portion of multi-layer threshold switch 1014/704.
  • Fig. 10L illustrates a cross-section of the device after more isolation fill (e.g., Si0 2 ) 1007 is deposited. As such, isolation fill (e.g., Si0 2 ) 1007 covers the portion of hard mask 1015.
  • Fig. 10M illustrates a cross-section of the device after two holes 1016 and 1017 are drilled as shown. Here, opening 1016 is drilled to M3 1013c while opening 1017 is drilled to hard mask 1015.
  • FIG. 10N illustrates a cross-section of the device after hard mask 1015 is etched out.
  • Fig. 10O illustrates a cross-section of the device after metal 1018 for via is deposited in opening 1016, and metal 1019 for contact/via is deposited over portion of multi -layer threshold switch 1014/704.
  • multi-layer threshold switch 1014/704 is formed on the interconnect stack indirectly coupled to source region 1004.
  • Figs. 10P-Q illustrate three dimensional (3D) views of various cross-sections of Fig. 10C3 (bulk tri-gate transistor). It is pointed out that those elements of Figs. 10P-Q having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • the 3D views illustrate 2 fins (finl and fin2).
  • Figs. 10P-Q show two orientations of the same cross-section of the bulk tri-gate transistor.
  • Transistor cross-section illustrated in Fig. 10P is the cross-section of the bulk tri-gate transistor facing finl 1002 side while Fig. 10P illustrates a slightly tilted 3D view of Fig. 10C3.
  • Figs. llA-O illustrate cross-sections of various fabrication processes for fabricating an HP-FET (Silicon-on-Insulator (SOI) tri-gate) with a multi-layer threshold switch on the interconnect stack, where the interconnect stack is coupled to the source region of the HP-FET, in accordance with some embodiments of the disclosure.
  • HP-FET Silicon-on-Insulator
  • SOI Silicon-on-Insulator
  • Figs. IIA-O having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Figs. IIA-O are same as Figs. 10A-O except that an Oxide layer 1101 is sandwiched between substrate 1001 and active region 1002, in accordance with some embodiments.
  • Figs. 11P-Q illustrate 3D views of various cross-sections of Fig. 11C3 (SOI tri-gate transistor). It is pointed out that those elements of Figs. 11P-Q having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • the 3D views illustrates 2 fins (finl and fin2).
  • Transistor cross-section illustrated in Fig. 12P is the cross-section of the bulk tri-gate transistor facing finl 1002 side while Fig. IIP illustrates a slightly tilted 3D view of Fig. 11C3.
  • Figs. 12A-C illustrate orthogonal cross-section of Fig. 10K and a 3D view of the transistor of Fig. 10C3, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Figs. 12A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Cross-section 1200 of Fig. 12A is same as Fig. 10K.
  • Cross-section 1220 of Fig. 12B is the orthogonal view of the vertical cut XX through the region 1004, in accordance with some embodiments.
  • Cross-section 1230 of Fig. 12C is the 3D view of bulk transistor of Fig. 10C3.
  • Figs. 13A-C illustrate orthogonal cross-section of Fig. 11K and a 3D view of the transistor of Fig. 11C3, in accordance with some embodiments of the disclosure. It is pointed out that those elements of Fig. 13A-C having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Cross-section 1300 of Fig. 13A is same as Fig. 11K.
  • Cross-section 1320 of Fig. 13B is the orthogonal view of the vertical cut XX through the region 1004 of Fig. 13A, in accordance with some embodiments.
  • Cross-section 1330 of Fig. 13C is the 3D view of SOI transistor of Fig. 11C3.
  • Fig. 14 illustrates a smart device or a computer system or a SoC (System-on-
  • Fig. 14 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used.
  • computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.
  • computing device 1600 includes first processor 1610 with an HP-FET, according to some embodiments discussed. Other blocks of the computing device 1600 may also include an HP-FET, according to some embodiments.
  • the various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 1610 can include one or more physical devices, such as microprocessors, application processors,
  • microcontrollers programmable logic devices, or other processing means.
  • the processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I/O.
  • computing device 1600 includes audio subsystem
  • Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.
  • computing device 1600 comprises display subsystem
  • Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600.
  • Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display.
  • display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • computing device 1600 comprises I/O controller 1640.
  • I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1640 can interact with audio subsystem
  • display subsystem 1630 For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.
  • I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1600 includes power management
  • Memory subsystem 1660 includes memory devices for storing information in computing device 1600.
  • Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices.
  • Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.
  • the machine-readable medium may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions.
  • embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • BIOS a computer program
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • computing device 1600 comprises connectivity 1670.
  • Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices.
  • the computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1670 can include multiple different types of connectivity.
  • the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674.
  • Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • Connectivity 1670 includes parallel sensing arrays as described with reference to Figs. 10-13.
  • computing device 1600 comprises peripheral connections 1680.
  • Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections.
  • the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from” 1684) connected to it.
  • the computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600.
  • a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.
  • the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Firewire or other types.
  • an apparatus which comprises: a transistor having a gate electrode, a source region, and a drain region; and a threshold switch coupled to one of the source or drain regions, wherein the threshold switch is a multilayer device having chalcogenide material.
  • the chalcogenide material is formed of a material selected from a group consisting of: alloys of Si sulfide, Si selenide or Si telluride with Ge sulfide, Ge selenide or Ge telluride; a Si chalcogenide alloy comprising As or Bi; and a Ge chalcogenide alloy comprising As or Bi.
  • the material is selected from the group consisting of: Cu, Ga, In, Ag, and V used with: Ge-Se, GeSe, GeTe; or Si-Se, SiTe, and SiS.
  • the chalcogenide material is formed using one or more transition metals including Cu, Ga, In, Ag, and V used with: Ge-Se, GeSe, GeTe; or Si-Se, SiTe, and SiS.
  • the multilayer device comprises: a first electrode; a first barrier region adjacent to the first electrode; a switching layer adjacent to the first barrier region; a second barrier region adjacent to the switching layer; and a second electrode adjacent to the second barrier region.
  • the switching layer comprises multicomponent ternary or quarternary alloys.
  • the multicomponent ternary or quarternary alloys are formed of a material selected from a group consisting of: Se, S, Te, and O.
  • the first barrier region is formed of a material selected from a group consisting of: metal nitrides including TiN, TaN, and WN; refractory metal carbides including TiC, TaC, and WC; refractory metal carbon nitrides including TaCN; and conductive metal oxides including RuC , CrC , WO2, IrC , PtC , and RhC ; and the second barrier region is formed of a material selected from a group consisting of: metal nitrides including TiN, TaN, and WN; refractory metal carbides including TiC, TaC, and WC;
  • refractory metal carbon nitrides including TaCN; and conductive metal oxides including Ru0 2 , CrCh, WO2, IrCh, PtC , and PJ1O2.
  • the first electrode is formed of a material selected from a group consisting of: metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal alloys including alloys of metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal nitrides including titanium nitride and tantalum nitride; and metal carbides including hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide; and the second electrode is formed of a material selected from a group consisting of: metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal alloys including alloys of metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal alloy
  • the threshold switch has a variable resistance with a high resistance bound above which the transistor does not turn on, and a low resistance bound below which the transistor does not turn off.
  • the transistor and the threshold switch are coupled in series.
  • the threshold switch is a two terminal device with one terminal coupled to one of the source or drain regions of the transistor and another terminal coupled to a ground or supply node.
  • the threshold switch is an Ovshinsky Threshold Switch (OTS).
  • the transistor is one of: a FinFET; a tri-gate transistor with body thickness less than 5nm; a planar transistor; Gated All Around nanowire with wire widths less than 5nm; or a device with multiple transistor fins having a gate electrode and a pair of source and drain regions that share source and drain contacts.
  • a system which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to
  • an apparatus which comprises: a transistor having a gate electrode, a source region, and a drain region; and a threshold switch adjacent to a metal layer which is adjacent to one of the source or drain regions through one or more layers of via and metal, wherein the threshold switch is a multilayer device including one of: metal-insulator-transition (MIT) material or Mott transition material.
  • MIT metal-insulator-transition
  • the threshold switch is a two terminal device with one terminal coupled to the metal layer and another terminal coupled to a ground or supply node.
  • the transistor and the threshold switch are coupled in series.
  • the multilayer device comprises of: a first electrode; a first barrier region adjacent to the first electrode; a switching layer adjacent to the first barrier region; a second barrier region adjacent to the switching layer; and a second electrode adjacent to the second barrier region.
  • the switching layer is formed of a material selected from a group consisting of: metal-insulator-transition (MIT) oxide and Mott transition oxide;
  • MIT oxide is formed of a material selected from a group consisting of: NbCh, metal doped NbCh, V0 2 , metal-doped V2O3, Fe 3 0 4 , FeS, Ta 2 0 5 , T13O5, T12O3, LaCoC , and SmNiC ;
  • the Mott transition oxide is formed of a material selected from a group consisting of: NbCh, metal doped NbCh, VO2, metal-doped V2G3, Fe304, FeS, Ta2C , T13O5, T12O3, LaCo03, and SmNi0 3 .
  • the first barrier region is formed of a material selected from a group consisting of: metal nitrides including TiN, TaN, and WN; refractory metal carbides including TiC, TaC, and WC; refractory metal carbon nitrides including TaCN; and conductive metal oxides including RuCh, CrCh, WO2, IrCh, PtCh, and RhCh; and the second barrier region is formed of a material selected from a group consisting of: metal nitrides including TiN, TaN, and WN; refractory metal carbides including TiC, TaC, and WC;
  • refractory metal carbon nitrides including TaCN; and conductive metal oxides including RuCh, Cr0 2 , WO2, Ir0 2 , Pt0 2 , and RhCh.
  • the first electrode is formed of a material selected from a group consisting of: metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal alloys including alloys of metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal nitrides including titanium nitride and tantalum nitride; and metal carbides including hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide; and the second electrode is formed of a material selected from a group consisting of: metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal alloys including alloys of metals including copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, and lead; metal alloy
  • the transistor is one of: a FinFET; a tri-gate transistor with body thickness less than 5nm; a planar transistor; Gated All Around nanowire with wire widths less than 5nm; or a device with multiple transistor fins having a gate electrode and a pair of source and drain regions that share source and drain contacts.
  • a system which comprises: a memory; a processor coupled to the memory, the processor including an apparatus according to the apparatus described above; and a wireless interface for allowing the processor to
  • a method which comprises: coupling a threshold switch to one of source or drain regions of a transistor, wherein the threshold switch is a multilayer device having chalcogenide material.
  • the chalcogenide material is formed of a material selected from a group consisting of: alloys of Si sulfide, Si selenide or Si telluride with Ge sulfide, Ge selenide or Ge telluride; a Si chalcogenide alloy comprising As or Bi; and a Ge chalcogenide alloy comprising As or Bi.
  • the material is selected from the group consisting of: Cu, Ga, In, Ag, and V used with: Ge-Se, GeSe, GeTe; or Si-Se, SiTe, and SiS.
  • the chalcogenide material is formed using one or more transition metals including Cu, Ga, In, Ag, and V used with: Ge-Se, GeSe, GeTe; or Si-Se, SiTe, and SiS.
  • the multilayer device comprises: a first electrode; a first barrier region adjacent to the first electrode; a switching layer adjacent to the first barrier region; a second barrier region adjacent to the switching layer; and a second electrode adjacent to the second barrier region.
  • an apparatus which comprises: means for coupling a threshold switch to one of source or drain regions of a transistor, wherein the threshold switch is a multilayer device having chalcogenide material.
  • the chalcogenide material is formed of a material selected from a group consisting of: alloys of Si sulfide, Si selenide or Si telluride with Ge sulfide, Ge selenide or Ge telluride; a Si chalcogenide alloy comprising As or Bi; and a Ge chalcogenide alloy comprising As or Bi.
  • the material is selected from the group consisting of: Cu, Ga, In, Ag, and V used with: Ge-Se, GeSe, GeTe; or Si-Se, SiTe, and SiS.
  • the chalcogenide material is formed using one or more transition metals including Cu, Ga, In, Ag, and V used with: Ge-Se, GeSe, GeTe; or Si-Se, SiTe, and SiS.
  • the multilayer device comprises: a first electrode; a first barrier region adjacent to the first electrode; a switching layer adjacent to the first barrier region; a second barrier region adjacent to the switching layer; and a second electrode adjacent to the second barrier region.

Landscapes

  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un appareil qui comprend : un transistor comportant une électrode de grille, une zone de source et une zone de drain ; et un interrupteur à seuil adjacent à l'une des zones de source et de drain, l'interrupteur à seuil étant un dispositif multicouche contenant un matériau chalcogénure. L'invention concerne également un appareil qui comprend : un transistor comportant une électrode de grille, une zone de source et une zone de drain ; et un interrupteur à seuil adjacent à une couche métallique qui est adjacente à l'une des zones de source et de drain par l'intermédiaire d'une ou plusieurs couches de contact/interconnexion et du métal, l'interrupteur à seuil étant un dispositif multicouche dont l'une des couches est un alliage à base de chalcogénure.
PCT/US2015/067042 2015-12-21 2015-12-21 Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant Ceased WO2017111894A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2015/067042 WO2017111894A1 (fr) 2015-12-21 2015-12-21 Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant
TW105137907A TW201731102A (zh) 2015-12-21 2016-11-18 混合相場效應電晶體之製造和裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/067042 WO2017111894A1 (fr) 2015-12-21 2015-12-21 Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant

Publications (1)

Publication Number Publication Date
WO2017111894A1 true WO2017111894A1 (fr) 2017-06-29

Family

ID=59091111

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/067042 Ceased WO2017111894A1 (fr) 2015-12-21 2015-12-21 Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant

Country Status (2)

Country Link
TW (1) TW201731102A (fr)
WO (1) WO2017111894A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101950097B1 (ko) * 2017-08-17 2019-02-19 포항공과대학교 산학협력단 문턱전압이 조절 가능한 트랜지스터
US10825861B2 (en) 2016-03-31 2020-11-03 Intel Corporation Multilayer selector device with low leakage current
US10840431B2 (en) 2016-03-31 2020-11-17 Intel Corporation Multilayer selector device with low holding voltage
EP4030625A1 (fr) 2021-01-15 2022-07-20 ETH Zurich Circuit logique avec interrupteur de seuil à tension contrôlée

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050029505A1 (en) * 2003-08-04 2005-02-10 Lowrey Tyler A. Phase change access device for memories
US20100176367A1 (en) * 2009-01-12 2010-07-15 Micron Technology, Inc. Memory cell having dielectric memory element
US20130214234A1 (en) * 2012-02-22 2013-08-22 Adesto Technologies Corporation Resistive Switching Devices and Methods of Formation Thereof
US20140110765A1 (en) * 2012-10-22 2014-04-24 International Business Machines Corporation Field effect transistor having phase transition material incorporated into one or more components for reduced leakage current
US20150091067A1 (en) * 2013-09-27 2015-04-02 Ravi Pillarisetty Hybrid phase field effect transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050029505A1 (en) * 2003-08-04 2005-02-10 Lowrey Tyler A. Phase change access device for memories
US20100176367A1 (en) * 2009-01-12 2010-07-15 Micron Technology, Inc. Memory cell having dielectric memory element
US20130214234A1 (en) * 2012-02-22 2013-08-22 Adesto Technologies Corporation Resistive Switching Devices and Methods of Formation Thereof
US20140110765A1 (en) * 2012-10-22 2014-04-24 International Business Machines Corporation Field effect transistor having phase transition material incorporated into one or more components for reduced leakage current
US20150091067A1 (en) * 2013-09-27 2015-04-02 Ravi Pillarisetty Hybrid phase field effect transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10825861B2 (en) 2016-03-31 2020-11-03 Intel Corporation Multilayer selector device with low leakage current
US10840431B2 (en) 2016-03-31 2020-11-17 Intel Corporation Multilayer selector device with low holding voltage
KR101950097B1 (ko) * 2017-08-17 2019-02-19 포항공과대학교 산학협력단 문턱전압이 조절 가능한 트랜지스터
EP4030625A1 (fr) 2021-01-15 2022-07-20 ETH Zurich Circuit logique avec interrupteur de seuil à tension contrôlée
WO2022152917A1 (fr) 2021-01-15 2022-07-21 Eth Zurich Circuit logique doté d'un commutateur à seuil commandé en tension

Also Published As

Publication number Publication date
TW201731102A (zh) 2017-09-01

Similar Documents

Publication Publication Date Title
US10366753B2 (en) Correlated electron switch programmable fabric
KR102162676B1 (ko) 상보형 터널링 fet 디바이스와 그 형성 방법
KR102549162B1 (ko) 프로그래밍 가능한 전압 기준
US9917104B1 (en) Hybrid MOS-PCM CMOS SOI switch
KR102120805B1 (ko) 하이브리드 상 전계 효과 트랜지스터
TWI717439B (zh) 對相關電子開關的存取裝置及其形成方法
US10868246B2 (en) Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayer
TWI575717B (zh) 用於積體電路之柱狀電阻結構
US10170520B1 (en) Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system
US20200220024A1 (en) Charge trap layer in back-gated thin-film transistors
US11152429B2 (en) Threshold switching contact in a field-effect transistor as a selector
WO2017111894A1 (fr) Fabrication d'un transistor à effet de champ à phase hybride et appareil le comprenant
WO2017222525A1 (fr) Dispositifs de rram avec ballast intrinsèque sur deux faces
US20190296081A1 (en) Selector-based electronic devices, inverters, memory devices, and computing devices
US10825861B2 (en) Multilayer selector device with low leakage current
US11581417B2 (en) Improper ferroelectric active and passive devices
EP3706168A1 (fr) Mémoire ferroélectrique ultra-dense à motifs auto-alignés
WO2019139598A1 (fr) Neurones ferroélectriques et synapses à transistors ferroélectriques à double grille
WO2018004587A1 (fr) Dispositifs de rram à couches de barrière thermique bidimensionnelles
US20190198100A1 (en) Conductive bridge resistive random access memory cell
WO2018125065A1 (fr) Dispositif nanomécanique à base de matériau 2-d
WO2017111876A1 (fr) Appareil d'interconnexion configurable et procédé
EP4333604A1 (fr) Dispositif de mémoire et appareil de mémoire le comprenant
US9741931B1 (en) Semiconductor integrated circuit device including switching elements and method of manufacturing the same
WO2018004671A1 (fr) Dispositifs rram à ballast inférieur

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15911588

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15911588

Country of ref document: EP

Kind code of ref document: A1