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WO2017149743A1 - Dispositif à semi-conducteurs à large espace - Google Patents

Dispositif à semi-conducteurs à large espace Download PDF

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Publication number
WO2017149743A1
WO2017149743A1 PCT/JP2016/056732 JP2016056732W WO2017149743A1 WO 2017149743 A1 WO2017149743 A1 WO 2017149743A1 JP 2016056732 W JP2016056732 W JP 2016056732W WO 2017149743 A1 WO2017149743 A1 WO 2017149743A1
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Prior art keywords
conductivity type
type region
outer peripheral
semiconductor device
insulating layer
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Japanese (ja)
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雄介 前山
俊一 中村
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Priority to PCT/JP2016/056732 priority Critical patent/WO2017149743A1/fr
Priority to JP2016571442A priority patent/JP6200107B1/ja
Publication of WO2017149743A1 publication Critical patent/WO2017149743A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 

Definitions

  • the present invention relates to a wide gap type semiconductor device.
  • the present invention has been made from such a viewpoint, and provides a wide gap type semiconductor device capable of sufficiently suppressing discharge.
  • a wide gap type semiconductor device includes: A first conductivity type semiconductor layer; An inner peripheral second conductivity type region provided on the first conductivity type semiconductor layer; A first electrode in which a part is located on the inner peripheral second conductivity type region and a remaining part is located on the first conductivity type semiconductor layer; An insulating layer provided on the first conductive semiconductor layer and adjacent to the first electrode and extending to an end of the wide gap semiconductor device; An outer peripheral side second conductive type region provided on the outer peripheral side of the inner peripheral side second conductive type region on the first conductive type semiconductor layer; With A distance between an end portion of the inner peripheral second conductivity type region and an end portion of the outer peripheral second conductivity type region is larger than a depletion layer width extending from the inner peripheral second conductivity type region to the outer peripheral side. It has become.
  • the outer peripheral second conductivity type region may be arranged away from an end of the wide gap type semiconductor device by a distance that does not cause damage that occurs when the wide gap type semiconductor device is cut and manufactured.
  • the inner periphery side second conductivity type region includes a high concentration inner periphery side second conductivity type region and a low concentration inner periphery side second region having a second conductivity type impurity concentration lower than that of the high concentration inner periphery side second conductivity type region.
  • Two conductivity type regions, The second conductivity type impurity concentration of the outer periphery side second conductivity type region may be higher than the second conductivity type impurity concentration of the low concentration inner periphery side second conductivity type region.
  • the second conductivity type impurity concentration in the high concentration inner periphery side second conductivity type region may be equal to the second conductivity type impurity concentration in the outer periphery side second conductivity type region.
  • the insulating layer includes a first insulating layer provided on the first conductivity type semiconductor layer, and a second insulating layer provided on the first insulating layer, The second insulating layer may extend from any position above the inner peripheral second conductivity type region to at least the inner peripheral end of the outer peripheral second conductivity type region.
  • the second insulating layer may be a nitride film.
  • the second insulating layer may extend from any position above the inner peripheral second conductivity type region to at least a central portion in the width direction of the outer peripheral second conductivity type region.
  • the insulating layer further includes a third insulating layer provided on the second insulating layer, The third insulating layer may extend to the outer peripheral side of the second insulating layer and may not extend to the end of the wide gap type semiconductor device.
  • the distance between the end of the inner peripheral second conductivity type region and the end of the outer peripheral second conductivity type region is a depletion layer extending from the end of the inner peripheral second conductivity type region to the outer peripheral side. It may be larger than the sum of the width and the width of the depletion layer extending from the outer peripheral second conductivity type region to the inner peripheral side.
  • a wide gap type semiconductor device includes: You may further provide the 2nd electrode provided in an outer peripheral side rather than the said outer peripheral side 2nd conductivity type area
  • the outer peripheral side second conductive type region is provided on the outer peripheral side of the inner peripheral side second conductive type region, and the end of the inner peripheral side second conductive type region and the end of the outer peripheral side second conductive type region are provided.
  • the distance to the part is larger than the depletion layer width.
  • FIG. 1 is a longitudinal sectional view showing an outline of a layer configuration in a silicon carbide semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a longitudinal sectional view showing an outline of a layer configuration in the silicon carbide semiconductor device according to the first modification of the first embodiment of the present invention.
  • FIG. 3 is an upper plan view of the silicon carbide semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is an upper plan view of the silicon carbide semiconductor device according to the second modification of the first embodiment of the present invention.
  • FIG. 5 is a longitudinal sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the invention.
  • FIG. 6 is a longitudinal sectional view showing an outline of a layer configuration in the silicon carbide semiconductor device according to the second embodiment of the present invention.
  • FIG. 7A is a diagram for explaining the inversion layer
  • FIG. 7B is a diagram for explaining the effect of the second electrode according to the second embodiment of the present invention.
  • a silicon carbide semiconductor device is described as an example of a wide gap type semiconductor device.
  • the present invention is not limited to this, and the present invention is also applied to other wide gap type semiconductor devices such as gallium nitride and gallium oxide. The invention can be used.
  • the silicon carbide semiconductor device of the present embodiment is provided on a first conductivity type semiconductor substrate 31 and the first conductivity type semiconductor substrate 31, and is more first than the first conductivity type semiconductor substrate 31.
  • the first conductivity type semiconductor layer 32 having a low conductivity type impurity concentration and inner peripheral second conductivity type regions 41 and 42 provided on the first conductivity type semiconductor layer 32 are provided.
  • the inner peripheral second conductivity type regions 41 and 42 of the present embodiment are higher than the high concentration inner peripheral second conductivity type region 41 and the high concentration inner peripheral second conductivity type region 41. May also have a low concentration inner peripheral second conductivity type region 42 having a low second conductivity type impurity concentration.
  • n-type is used as the “first conductivity type”
  • p-type is used as the “second conductivity type”.
  • the present invention is not limited to this mode, and the p-type may be used as the “first conductivity type” and the n-type may be used as the “second conductivity type”.
  • the first conductive semiconductor substrate 31 has an upper surface as one main surface and a lower surface as the other main surface.
  • the high concentration inner peripheral second conductivity type region 41 is located closer to the first electrode 10 (inner peripheral side) than the low concentration inner peripheral second conductivity type region 42.
  • a low-concentration inner peripheral side second conductivity type region 42 may be provided so as to surround the inner peripheral side second conductivity type region 41.
  • the depth of the low concentration inner peripheral side second conductivity type region 42 may be deeper than the depth of the high concentration inner peripheral side second conductivity type region 41.
  • the width of the low concentration inner peripheral side second conductivity type region 42 may be wider than the width of the high concentration inner peripheral side second conductivity type region 41.
  • the silicon carbide semiconductor device includes the first electrode 10, part of which is located on the inner periphery side second conductivity type regions 41, 42 and the remaining part is located on the first conductivity type semiconductor layer 32.
  • the first electrode 10 may form a Schottky junction with the first conductivity type semiconductor layer 32.
  • the inner peripheral second conductivity type regions 41 and 42 are located below the peripheral edge of the first electrode 10, and the inner peripheral second conductivity type regions 41 and 42 alleviate the electric field. It has a function.
  • the silicon carbide semiconductor device is provided on the first conductivity type semiconductor layer 32 and adjacent to the first electrode 10, and the insulating layers 51, 52, extending to the end portion (right end in FIG. 1) of the silicon carbide semiconductor device. 53 and the outer peripheral side second conductivity type region 20 provided on the outer peripheral side of the inner peripheral side second conductivity type regions 41 and 42.
  • the second conductivity type impurity concentration (p-type impurity concentration) in the outer peripheral second conductivity type region 20 is higher than the second conductivity type impurity concentration (p-type impurity concentration) in the low-concentration inner peripheral side second conductivity type region 42. It may be.
  • the second conductivity type impurity concentration of the outer peripheral second conductivity type region 20 may be 1 ⁇ 10 18 to 1 ⁇ 10 23 , more specifically 1 ⁇ 10 19 to 1 ⁇ 10 23 . It may be.
  • the “end portion of the silicon carbide semiconductor device” means a region near the end face of the silicon carbide semiconductor device.
  • the distance X between the end portions of the inner periphery side second conductivity type regions 41 and 42 and the end portion of the outer periphery side second conductivity type region 20 is equal to the inner periphery side second conductivity type region 41. , 42 is larger than the depletion layer width extending from the outer peripheral side.
  • the distance X may be 1.5 to 2 times larger than the value obtained by the above (formula 1).
  • Equation 1 ⁇ s is the dielectric constant of the semiconductor, V bi is the built-in potential, and N d is the donor concentration.
  • the distance X of the present embodiment is equal to the end of the low concentration inner peripheral second conductivity type region 42 (the right end of the low concentration inner peripheral second conductivity type region 42 in FIG. 1), It means the distance between the end portion of the outer peripheral second conductivity type region 20 (the left end of the contact surface in FIG. 1).
  • the distance X between the end portions of the inner peripheral side second conductivity type regions 41 and 42 and the end portion of the outer peripheral side second conductivity type region 20 is from the end portion of the inner peripheral side second conductivity type regions 41 and 42 to the outer periphery. It may be larger than the sum of the width of the depletion layer extending to the side and the width of the depletion layer extending from the outer peripheral second conductivity type region 20 to the inner peripheral side.
  • the theoretical depletion layer width extending from the outer peripheral side second conductivity type region 20 to the inner peripheral side is obtained by adding the second conductivity type impurity concentration of the outer peripheral side second conductivity type region 20 as the donor concentration in the above (Equation 1). It can be calculated by
  • the outer peripheral side second conductivity type region 20 is arranged away from the end of the silicon carbide semiconductor device by a distance that does not cause damage when the silicon carbide semiconductor device is cut and manufactured (specifically, when dicing). May be. Since the damaged distance is 30 ⁇ m to 60 ⁇ m as an example, when this embodiment is adopted, the outer peripheral side second conductivity type region 20 extends from the end of the silicon carbide semiconductor device in the left-right direction in FIG. A distance of 30 ⁇ m to 60 ⁇ m or more is provided apart.
  • the second conductivity type impurity concentration (p-type impurity concentration) in the high-concentration inner peripheral second conductivity type region 41 is equal to the second conductivity type impurity concentration (p-type impurity concentration) in the outer peripheral second conductivity type region 20. May be.
  • the insulating layers 51, 52, and 53 of the present embodiment are formed on the first conductive semiconductor layer 32, the inner peripheral second conductive type regions 41 and 42, and the outer peripheral second conductive type region 20.
  • the first insulating layer 51 provided on the first insulating layer 51 and the second insulating layer 52 provided on the first insulating layer 51 may be included.
  • the outer peripheral second conductivity type region 20 may be provided below the second insulating layer 52.
  • the third insulating layer 53 may be provided on the second insulating layer 52.
  • the third insulating layer 53 may extend to the outer peripheral side (end portion side) than the second insulating layer 52 and may not extend to the end portion of the silicon carbide semiconductor device.
  • the first insulating layer 51 can include a material containing PSG (Phosphorus Silicon Glass) and SiO 2
  • the second insulating layer 52 can include a nitride film (for example, a material including SiN).
  • a polyimide for example, a material containing high heat-resistant polyimide can be used as the third insulating layer 53.
  • the thickness of the first insulating layer 51 is, for example, about 1 to 2 ⁇ m.
  • the second insulating layer 52 may extend from any position above the inner peripheral second conductivity type regions 41 and 42 to at least the inner peripheral end of the outer peripheral second conductivity type region 20.
  • the second insulating layer 52 is at least a central portion in the width direction of the outer peripheral second conductivity type region 20 from any position above the inner peripheral second conductivity type regions 41, 42. It may extend to. More specifically, the second insulating layer 52 extends from any position above the low-concentration inner peripheral side second conductivity type region 42 to at least the center of the outer peripheral side second conductivity type region 20 in the width direction. May be.
  • the second insulating layer 52 extends from any position above the inner peripheral second conductivity type regions 41, 42 to at least the outer peripheral side end in the width direction of the outer peripheral second conductivity type region 20. Also good.
  • the first insulating layer 51 located on the surface in the vicinity of the end face should reach the end of the semiconductor device in order to suppress discharge. In this case, the first insulating layer 51 reaches the end of the adjacent wide gap type semiconductor device (element) before the dicing division. It is sufficient that first insulating layer 51 extends to the extent that no discharge occurs between first electrode 10 and the end portion of the silicon carbide semiconductor device. For this reason, the area
  • the third insulating layer 53 does not need to extend to the end face (the right end face in FIG. 1) of the first insulating layer 51 (it may not be provided on the end of the wide gap type semiconductor device).
  • the material can be appropriately selected depending on the material applied to the third insulating layer 53 and the dicing division method.
  • the first conductivity type impurity concentration (for example, nitrogen concentration) of the first conductivity type semiconductor substrate 31 is 5 ⁇ 10 17 cm ⁇ 3 to 5 ⁇ 10 19 , and the first conductivity type semiconductor layer 32 has the first conductivity type.
  • the type impurity concentration may be 1 ⁇ 10 15 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the first conductive semiconductor substrate 31 may have a thickness of 30 ⁇ m to 400 ⁇ m, for example, and the first conductive semiconductor layer 32 may have a thickness of 3 ⁇ m to 20 ⁇ m, for example.
  • the first electrode 10 may have a laminated structure using a plurality of types of metals. For example, titanium having a thickness of 0.5 ⁇ m and a thickness of 3 ⁇ m provided on the titanium, for example. You may have aluminum. Further, nickel may be provided on aluminum.
  • the first electrode 10 and the first conductivity type semiconductor layer 32 of the present embodiment form a Schottky junction.
  • the present invention is not limited to this, and as a modification, the first electrode 10 ′ and the first conductive type semiconductor layer 32 or the inner peripheral second conductive type regions 41 and 42 may form an ohmic junction.
  • the high concentration inner peripheral second conductivity type region 41 is located below the first electrode 10 ′, and the high concentration inner peripheral second conductivity type region 41 and the first electrode 10 ′ Forms an ohmic junction. Further, as shown in FIG.
  • an island-shaped p-type region 59 may be formed so as to form an island region in the first conductive type semiconductor layer 32, and the p-type region and the first electrode 10 are An ohmic junction may be formed, and the first conductivity type semiconductor layer 32 and the first electrode 10 may form a Schottky junction.
  • one outer peripheral second conductivity type region 20 may be provided so as to surround part or all of the first electrode 10 continuously or intermittently (see FIG. 3). That is, in the present embodiment, a plurality of outer peripheral second conductivity type regions 20 are not provided, and only one outer peripheral second conductivity type region 20 may be provided. Of course, a plurality of outer peripheral second conductivity type regions 20 may be provided, and when a plurality of outer peripheral second conductivity type regions 20 are provided, a part of one outer peripheral second conductivity type region 20 or It may be provided such that another outer peripheral second conductivity type region 20 surrounds the whole continuously or intermittently. Further, the plurality of outer peripheral second conductivity type regions 20 may be provided at equal intervals from the center, may be provided so that the intervals are gradually narrowed, or may be provided so that the intervals are gradually increased. May be.
  • the outer peripheral side second conductivity type region 20 When a part of the first electrode 10 is surrounded by the outer peripheral side second conductivity type region 20, a portion that is not surrounded by the outer peripheral side second conductivity type region 20 occurs on the outer periphery of the first electrode 10.
  • the outer peripheral side second conductivity type region 20 surrounds the entire first electrode 10
  • the entire first electrode 10 is continuously surrounded by the outer peripheral side second conductivity type region 20.
  • the outer peripheral side second conductivity type region 20 continuously surrounds all of the first electrodes 10 as shown in FIG. 3 in a plan view (when viewed from above in FIG. 1). ), And the outer peripheral side second conductivity type region 20 continuously surrounds all of the first electrode 10.
  • FIG. 1 the outer peripheral side second conductivity type region 20 continuously surrounds all of the first electrode 10.
  • the outer peripheral side second conductivity type region 20 has a substantially hollow rectangular shape and surrounds the substantially rectangular first electrode 10.
  • the mold region 20 may be, for example, a substantially circular shape with a hollow and may surround the first electrode 10.
  • the silicon carbide semiconductor device of the present embodiment may have a back electrode 80 that is a back electrode on the back side of the first conductivity type semiconductor substrate 31 (the lower side in FIG. 1).
  • the back electrode 80 forms, for example, an ohmic junction with the first conductivity type semiconductor substrate 31.
  • the back electrode 80 may have a single-layer structure of nickel or a multilayer structure including nickel and titanium.
  • a high-concentration first conductive semiconductor substrate 31 is prepared (see FIG. 5A).
  • a low-concentration first conductive semiconductor layer 32 is formed by epitaxial growth on the high-concentration first conductive semiconductor substrate 31 (see FIG. 5A).
  • the inner peripheral side second conductive type regions 41 and 42 including the low concentration inner peripheral side second conductive type region 42 and the high concentration inner peripheral side second conductive type region 41 and the outer peripheral side second conductive type region 20 are formed. (See FIG. 5B).
  • a known method can be used. As an example, the following method can be used.
  • a mask having openings at portions corresponding to the inner peripheral second conductivity type regions 41 and 42 and the outer peripheral second conductivity type region 20 is formed.
  • p-type impurity ions for example, aluminum ions
  • p-type impurity ions for example, aluminum ions
  • the mask is removed.
  • a mask having openings in portions corresponding to the high-concentration inner peripheral second conductivity type region 41 and the outer peripheral second conductivity type region 20 is formed.
  • p-type impurity ions for example, aluminum ions
  • the p-type impurity is activated by heating to a temperature of 1600 ° C. or higher.
  • the first insulating layer 51 is provided on the first conductive type semiconductor layer 32 and the inner peripheral second conductive type regions 41 and 42. Thereafter, an opening for the first electrode 10 is formed at a position where a part of the first insulating layer 51 is located on the second conductivity type regions 41 and 42 and the remaining part is located on the first conductivity type semiconductor layer 32. (See FIG. 5B).
  • buffer hydrofluoric acid can be used, for example.
  • the first electrode 10 is provided in the first electrode 10 opening 51a (see FIG. 5C).
  • a well-known method can be used also when providing the 1st electrode 10 in this way.
  • an electrode containing titanium, nickel, and / or aluminum is provided by, for example, vapor deposition, chemical vapor deposition (CVD), coating / coating, electroplating, or the like.
  • the first electrode 10 is formed so as to have the stepped portion 11 at the peripheral portion thereof.
  • the second insulating layer 52 is provided on the first insulating layer 51 (see FIG. 5D). Thereafter, the third insulating layer 53 is provided so as to cover a part (peripheral portion) of the step-shaped portion 11 of the first electrode 10 and the entire second insulating layer 52.
  • a back electrode 80 is formed on the lower surface (back surface) of the first conductivity type semiconductor substrate 31 (see FIG. 5D). Also in this case, the back electrode 80 can be formed by using a well-known method. For example, a metal containing nickel and / or titanium is formed by, for example, vapor deposition, chemical vapor deposition (CVD), coating / coating. It is provided by an electroplating method or the like.
  • CVD chemical vapor deposition
  • the first electrode 10 is heat-treated at an appropriate timing in the above-described process and at a predetermined temperature (for example, 500 ° C.) so as to form a Schottky junction with the first conductivity type semiconductor layer 32.
  • heat treatment is performed at an appropriate timing in the above-described process and at a predetermined temperature (for example, 1000 ° C. or higher) so that the lower surface (back surface) of the first conductivity type semiconductor substrate 31 and the back electrode 80 form an ohmic junction. Done.
  • the outer peripheral side second conductivity type region 20 is provided on the outer peripheral side of the inner peripheral side second conductivity type regions 41, 42, and the end portions of the inner peripheral side second conductivity type regions 41, 42 and The distance to the end of the outer peripheral second conductivity type region 20 is larger than the depletion layer width. For this reason, the effect different from a general guard ring can be acquired.
  • the depletion layer can be expanded from the outer peripheral side second conductivity type region 20 to the outer peripheral side. As a result, the first electrode 10 And the vicinity of the end of the wide gap type semiconductor device can be prevented from generating discharge.
  • the inner periphery side second conductivity type region 41 is connected in order to relax the electric field by connecting the depletion layer and gradually decreasing the anode potential.
  • the end X of the outer peripheral side second conductivity type region 20 are designed such that the distance X is equal to or smaller than the depletion layer width.
  • the outer peripheral second conductivity type region 20 of the present embodiment is not intended to connect the depletion layers.
  • the distance X is It may be 1.5 times to 2 times or more the value obtained in (1).
  • the distance X is it is possible to prevent the depletion layer from being unexpectedly connected.
  • the distance X in the case of a silicon carbide Schottky barrier diode with a rated voltage of 1200 V, assuming that N d is 0.8 ⁇ 10 16 cm ⁇ 3 and applying a rated voltage of 1200 V, the distance X must be at least 12.9 ⁇ m. is there. In such a case, it is conceivable to design the distance X to about 18 ⁇ m to 25 ⁇ m (for example, 20 ⁇ m) from the viewpoint of preventing the depletion layer from being unexpectedly connected.
  • insulating layers 51, 52, and 53 extend to the end of the silicon carbide semiconductor device, the first electrode 10 and the end of the silicon carbide semiconductor device Can be prevented from occurring between the two.
  • the second conductivity type impurity concentration of the outer peripheral side second conductivity type region 20 is higher than the second conductivity type impurity concentration of the low concentration inner periphery side second conductivity type region 42 (reverse bias).
  • a wide depletion layer can be generated from the outer peripheral second conductivity type region 20. For this reason, it can prevent more reliably that discharge generate
  • the second conductivity type impurity concentration of the outer peripheral second conductivity type region 20 is low, the outer peripheral second conductivity type region 20 itself is depleted by the depletion layer spreading in the outer peripheral second conductivity type region 20. It can happen.
  • the second conductivity type impurity concentration of the outer peripheral side second conductivity type region 20 is preferably 1 ⁇ 10 18 to 1 ⁇ 10 23 , and more preferably 1 ⁇ 10 19 to 1 ⁇ 10 23 .
  • the width L (see FIG. 1) of the outer peripheral second conductivity type region 20 only needs to satisfy the following formula.
  • the reason why the depletion layer is doubled is that the depletion layer extends from both directions of the outer peripheral second conductivity type region. Since it is not preferable that the width L of the outer peripheral second conductivity type region 20 is increased, in order to reduce the width L of the outer peripheral second conductivity type region 20, the second in the outer peripheral side second conductivity type region 20 is used. it is necessary to increase the concentration N d of the conductive impurity.
  • the interface state density at the interface between the insulating layers 51, 52, 53 and silicon carbide is larger than that at the interface between the insulating layers 51, 52, 53 and silicon (Si). Electrons are trapped by this interface state existing at the interface between the insulating layers 51, 52, 53 and the first conductivity type semiconductor layer 32 made of silicon carbide. Of the captured electrons, Since electrons at the interface state have a large time constant and cannot escape, they behave substantially as negative fixed charges (see FIG. 7A).
  • the fixed charge is ⁇ 1 ⁇ 10 11 to ⁇ 1 ⁇ 10 13, which is larger than that of silicon.
  • the band of the first conductivity type semiconductor layer 32 located immediately below the insulating layers 51, 52, and 53 is raised by the trapped electrons to be changed to the second conductivity type (the region having the second conductivity type is referred to as “ Inversion layer ").
  • Such a phenomenon in the silicon carbide semiconductor device can also occur in a wide gap type semiconductor such as gallium nitride (GaN) or gallium oxide (Ga 2 O 3 ) other than silicon carbide.
  • the second insulating layer 52 is at least on the inner peripheral side of the outer peripheral second conductive type region 20 from any position above the inner peripheral second conductive type regions 41 and 42.
  • the inversion layer could be formed up to the outer peripheral second conductivity type region 20.
  • the potential of the outer peripheral second conductivity type region 20 becomes almost the same value as the inner peripheral second conductivity type regions 41 and 42 by this inversion layer, and the depletion layer is sufficiently removed from the outer peripheral second conductivity type region 20. Can be spread. For this reason, it can prevent more reliably that discharge generate
  • the effect of forming the inversion layer was remarkably shown when the second insulating layer 52 was a nitride film, and was particularly prominent when it was SiN. Therefore, it is very beneficial that the second insulating layer 52 is a nitride film (particularly SiN). Furthermore, since it has also been confirmed that this effect is sufficiently obtained when the second insulating layer 52 extends at least to the center in the width direction of the outer peripheral side second conductivity type region 20, It is beneficial to extend from any position above the inner peripheral second conductivity type regions 41 and 42 to at least the center of the outer peripheral side second conductivity type region 20 in the width direction. In addition, when the 2nd insulating layer 52 extended at least to the edge part of the outer peripheral side of the width direction of the outer peripheral side 2nd conductivity type area
  • the inversion layer is formed to the end of the wide gap type semiconductor device by providing the outer peripheral side second conductivity type region 20 and / or the second insulating layer 52 (which is a nitride film) does not extend to the end. Can be prevented. As a result, leakage current can be prevented from being generated by the inversion layer.
  • the outer periphery side second conductivity type region 20 When the outer periphery side second conductivity type region 20 is disposed away from the end of the wide gap type semiconductor device by a distance that does not cause damage when the wide gap type semiconductor device is cut and manufactured. Can prevent the depletion layer extending from the outer peripheral second conductivity type region 20 from touching such damage. This is because an electric field is generated in the depletion layer, and if the depletion layer touches such damage, a leakage current is generated. From this point of view, the outer peripheral second conductivity type region 20 has a distance (30 ⁇ m to 60 ⁇ m or more) that does not cause damage when the wide gap type semiconductor device is cut from the end of the wide gap type semiconductor device. It is more advantageous to arrange them apart from the “sum” of the width of the depletion layer extending from the outer peripheral second conductivity type region 20 to the outer peripheral side.
  • the distance X between the end portions of the inner peripheral second conductivity type regions 41 and 42 and the end portion of the outer peripheral second conductivity type region 20 is the end portion of the inner peripheral second conductivity type regions 41 and 42.
  • the inner periphery side second conductivity type region It is possible to prevent the depletion layer extending from the end portions of 41 and 42 to the outer peripheral side from overlapping with the depletion layer extending from the outer peripheral second conductivity type region 20 to the inner peripheral side, thereby preventing the influence of both.
  • the design content regarding the inner peripheral side second conductivity type regions 41 and 42 for withstand voltage can be used when designing other semiconductor devices, and the outer peripheral side second for preventing discharge.
  • the design content regarding the conductivity type region 20 can be used when designing another semiconductor device.
  • the already acquired data can be made versatile.
  • the first component including the inner peripheral second conductivity type regions 41 and 42 and the second component including the outer peripheral second conductivity type region 20 are manufactured separately, and a semiconductor device is manufactured by appropriately combining them. You can also
  • the design for realizing the withstand voltage is complicated, and therefore, when the guard ring is affected by the outer peripheral side second conductivity type region 20, the design is performed. Reworking is very time consuming. For this reason, the distance (distance in the left-right direction in FIG. 1) between the end of the outer peripheral second conductivity type region 20 and the pressure-resistant structure such as the guard ring is the inner distance from the end of the outer peripheral second conductivity type region 20. It is beneficial that the depletion layer extending on the peripheral side does not overlap with the depletion layer extending on the outer peripheral side from the pressure-resistant structure.
  • the second conductivity type impurity concentration in the high concentration inner peripheral side second conductivity type region 41 is equal to the second conductivity type impurity concentration in the outer periphery side second conductivity type region 20
  • the high concentration Since the inner periphery side second conductivity type region 41 and the outer periphery side second conductivity type region 20 can be manufactured by the same method, the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • the depletion layer can be expanded evenly when viewed from above. It is beneficial in that it can be done. Even when only one outer peripheral second conductivity type region 20 is provided, it is sufficient as an effect of suppressing discharge from the first electrode 10 to the end of the wide gap semiconductor device (element). Note that you can expect to get
  • the outer peripheral side second conductivity type region 20 may be provided intermittently so as to surround the first electrode 10, or provided so as to surround only a part of the first electrode 10. May be.
  • a second Schottky junction is formed with the first conductivity type semiconductor layer 32 on the outer peripheral side (end portion side) than the outer peripheral second conductivity type region 20.
  • An electrode 90 is provided.
  • the second electrode 90 is provided between the outer peripheral second conductivity type region 20 and the end of the wide gap type semiconductor device, and the second electrode 90 and the first conductivity type semiconductor layer 32 are connected to each other.
  • a Schottky junction is formed. For this reason, it is possible to prevent the “inversion layer” that has passed through the outer peripheral side second conductivity type region 20 from being formed on the outer peripheral side of the second electrode 90 without trapping electrons and raising the band at the position (FIG. 7). (See (b)). As a result, it is possible to more reliably prevent leakage current from being generated by the inversion layer.
  • the discharge between the first electrode 10 and the second electrode 90 can be suppressed.

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  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteurs à large espace qui a : une première couche à semi-conducteurs électroconductrice (32) ; des secondes régions électroconductrices périphériques internes (41, 42) disposées sur la première couche à semi-conducteurs électroconductrice (32) ; une première électrode (10) ; des couches d'isolation (51, 52, 53) qui sont disposées sur la première couche à semi-conducteurs électroconductrice (32), adjacente à la première électrode (10), et s'étendant vers la partie d'extrémité du dispositif à semi-conducteurs à large espace ; et une seconde région électroconductrice périphérique externe (20) disposée sur la périphérie externe des secondes régions électroconductrices périphériques internes (41, 42). La distance entre la partie d'extrémité des secondes régions électroconductrices périphériques internes (41, 42) et la partie d'extrémité de la seconde région électroconductrice périphérique externe (20) est supérieure à la largeur de la couche d'appauvrissement qui s'étend vers la périphérie externe à partir des secondes régions électroconductrices périphériques internes (41, 42).
PCT/JP2016/056732 2016-03-04 2016-03-04 Dispositif à semi-conducteurs à large espace Ceased WO2017149743A1 (fr)

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US11804555B2 (en) 2019-01-29 2023-10-31 Mitsubishi Electric Corporation Semiconductor device and power conversion device
JP2024533761A (ja) * 2021-09-28 2024-09-12 ヒタチ・エナジー・リミテッド 炭化ケイ素半導体デバイスおよび製造方法

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JP2010056100A (ja) * 2008-08-26 2010-03-11 Sumitomo Electric Ind Ltd ショットキーバリアダイオード
JP2013055211A (ja) * 2011-09-05 2013-03-21 Toshiba Corp 半導体装置およびその製造方法
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US11804555B2 (en) 2019-01-29 2023-10-31 Mitsubishi Electric Corporation Semiconductor device and power conversion device
JP2024533761A (ja) * 2021-09-28 2024-09-12 ヒタチ・エナジー・リミテッド 炭化ケイ素半導体デバイスおよび製造方法
JP7748549B2 (ja) 2021-09-28 2025-10-02 ヒタチ・エナジー・リミテッド 炭化ケイ素半導体デバイスおよび製造方法

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