WO2017033596A1 - Image correction device, liquid crystal display device, and image correction method - Google Patents

Abstract

This image correction device minimizes linear display failures along the extending direction of a gate bus line in a liquid crystal display device. The image correction device includes: a correction requirement determination unit (22) for determining whether or not an input gradation value of pixels corresponding to a selected gate bus line need to be corrected in accordance with the number of bits having values changed between the binary input gradation value of each pixel corresponding to the selected gate bus line and the binary input gradation value of each pixel corresponding to the gate bus line immediately before the selected gate bus line in a display order; and a correction processing unit (23) for correcting the input gradation value so as to create variations in the input gradation value of each pixel corresponding to the selected gate bus line.

Description

Image correction device, liquid crystal display device, and image correction method

One embodiment of the present invention relates to a video correction device and a video correction method for correcting a gradation value of an input video signal to a liquid crystal display device, and a liquid crystal display device including the video correction device.

Conventionally, a technique for preventing malfunction due to the parasitic capacitance of a shift register provided in a driver of a liquid crystal display device or the influence of a clock has been developed.

For example, Patent Document 1 discloses that in a bottom gate type TFT (Thin Film Transistor) having a comb-like source / drain structure constituting a shift register, at least in a region overlapping a source electrode and a region overlapping a drain electrode. On the other hand, a technique is disclosed in which a gate electrode having at least one of a notch and an opening is arranged to reduce parasitic capacitance and prevent malfunction.

International Publication No. WO2011 / 065055 (released on June 3, 2011)

However, conventional techniques for preventing malfunction are not always perfect, and malfunction may not be sufficiently prevented depending on driving conditions.

In particular, on a liquid crystal display panel with a high driving frequency, high resolution, and multi-gradation display, an image (so-called VRAMP video) that changes by one gradation for each line in the extending direction of the source bus line (data signal line) is displayed. In some cases, the line-shaped display abnormality along the extending direction of the gate bus line (scanning signal line) that occurs in the case of being performed cannot be prevented appropriately.

More specifically, a source driver for driving a liquid crystal panel generates an analog voltage corresponding to an input gradation value of each pixel indicated by digital by DA conversion (digital analog conversion) and supplies it to a source bus line. Output.

However, in recent liquid crystal display devices, the drive time per gate bus line is significantly shortened by increasing the drive frequency (for example, 120 Hz or 240 Hz) and increasing the resolution (for example, 2K1K, 4K2K, 8K4K, etc.). Yes. In recent liquid crystal display devices, since the number of gradations is increasing, it takes time to generate an analog voltage corresponding to an input gradation value.

For this reason, the generation of the analog voltage according to the input gradation value may not be in time for the application timing of the analog voltage to the pixel, and a desired luminance may not be displayed, resulting in display abnormality.

In particular, in a liquid crystal display panel with a high drive frequency, high resolution, and multi-gradation display, when displaying an image that changes by one gradation for each line in the extending direction of the source bus line, the noise generation position is the gate bus. By aligning in the line extending direction, a line-like display abnormality corresponding to one gate bus line is likely to occur.

For example, as shown in FIG. 6A, when an image that changes by one gradation for each gate bus line is to be displayed from the upper end to the lower end (the extending direction of the source bus line) of the display screen, As shown in (b), a line-like display abnormality (luminance deviation) extending in the horizontal direction (extending direction of the gate bus line) may occur periodically.

7A and 7B are explanatory diagrams showing an analog voltage generation process in a source driver that generates an analog voltage corresponding to an input gradation value of 3 bits (8 gradations). When the input gradation value changes from gradation level 2 (binary number “010”) to gradation level 3 (binary number “011”), (b) indicates that the input gradation value is gradation level 3 ( In this example, the gradation level changes from “011” in binary number to gradation level 4 (“100” in binary number).

The shift register provided in the source driver changes the input gradation value (binary number) from the pixel corresponding to the gate bus line in the previous display order to the pixel corresponding to the next gate bus line from the upper bit. Confirm in order and change the analog voltage to be generated according to the change in the value of each bit.

Therefore, as shown in FIG. 7A, when there is only one bit in which the value of the input gradation value (binary number) changes from the pixel corresponding to the previous gate bus line in the display order. Thus, an analog voltage corresponding to the input gradation value can be generated by a one-step voltage change. However, as shown in FIG. 7B, when there are three bits in which the value of the input gradation value (binary number) changes, three steps of voltage changes are required.

That is, the more bits that change the value of the input gradation value (binary number) from the pixel corresponding to the gate bus line in the previous display order, the longer it takes to generate the target analog voltage. For this reason, in a liquid crystal display panel with a high drive frequency, high resolution, and multiple gradations, the generation of the analog voltage corresponding to the input gradation value is not in time for the application timing of the analog voltage to the pixel, and the display cannot display the desired luminance. Abnormalities may occur.

Note that in such display abnormality, the input gradation value of each pixel in the extending direction of the gate bus line is the same, and the input gradation value gradually increases for each gate bus line along the extending direction of the source bus line. It is particularly easy to visually recognize an image that changes monotonously.

One embodiment of the present invention has been made in view of the above-described problems, and the purpose thereof is that a line-shaped display abnormality along the extending direction of the gate bus line is visually recognized in a liquid crystal display device. It is to suppress.

A video correction apparatus according to an aspect of the present invention is a video correction apparatus that corrects an input video signal to a liquid crystal display device, and inputs binary numbers in at least some of the pixels corresponding to a gate bus line of interest. A grayscale value, and a binary input grayscale value of a pixel connected to the same source bus line as the at least some pixels, the display order of which corresponds to the gate bus line immediately before the gate bus line of interest A correction necessity determination unit that determines whether or not the input gradation value of the pixel corresponding to the gate bus line of interest needs to be corrected according to the number of bits whose value changes between the correction value and the correction necessity determination unit. When it is determined that the input gradation value of the pixel corresponding to the target gate bus line is corrected so as to cause variation in the gradation value of each pixel corresponding to the target gate bus line. It is characterized in that it comprises a processing unit.

According to the above configuration, even when the generation of the analog voltage corresponding to the input gradation value in the source driver is not in time for the application timing of the analog voltage to the pixel, the display abnormality caused by the generation is visually recognized by the viewer. This can be suppressed.

It is explanatory drawing which shows schematic structure of the liquid crystal display device concerning one Embodiment of this invention. FIG. 2 is an explanatory diagram illustrating a configuration of a gradation correction unit provided in the liquid crystal display device of FIG. 1. 2 is a flowchart showing a flow of processing in the liquid crystal display device shown in FIG. 1. FIG. 2 is an explanatory diagram illustrating an example of an input video signal for a plurality of gate bus lines in the liquid crystal display device of FIG. 1. FIG. 5 is an explanatory diagram showing an example of input tone value correction processing in the liquid crystal display device shown in FIG. 1, where (a) is an input tone value corresponding to FIG. 4, and (b) is an input tone value correction. Correction data (dither matrix) to be applied, (c) shows an example of the corrected gradation value obtained by correcting the input gradation value of (a) with the correction data of (b). (A) is explanatory drawing which shows the image corresponding to an example of the input video signal with respect to a liquid crystal display device, (b) of the display abnormality which arises when displaying the input video signal of (a) in the conventional liquid crystal display device. It is explanatory drawing which shows an example. (A) And (b) is explanatory drawing which shows the production | generation process of the analog voltage in the source driver which produces | generates the analog voltage corresponding to the input gradation value of 3 bits (8 gradations), (a) is an input floor. When the tone value changes from tone level 2 (binary 010) to tone level 3 (binary 011), (b) shows the input tone value from tone level 3 (binary 011) to the level. An example in which the key level changes to 4 (100 in binary) is shown. It is explanatory drawing which shows the structural example of the liquid crystal display panel of a double source structure. It is explanatory drawing which shows the example of the input gradation value with respect to each line when displaying the VRAMP image which changes 1 gradation for every 2 horizontal lines in the liquid crystal display panel of a double source structure.

Embodiment 1
An embodiment of the present invention will be described.

(1-1. Overall Configuration of Liquid Crystal Display Device 1)
An embodiment of the present invention will be described. FIG. 1 is an explanatory diagram showing a schematic configuration of a liquid crystal display device 1 according to the present embodiment. As shown in this figure, the liquid crystal display device 1 includes a gradation correction unit (video correction device) 11, a liquid crystal controller 12, a gate driver 13, a source driver 14, and a liquid crystal display panel 15.

The gradation correction unit 11 corrects the gradation value (input gradation value) of an input video signal input from a video supply device (not shown) (for example, a video storage device, a tuner, an information processing device) as necessary. The corrected video signal is output to the liquid crystal controller 12.

In the present embodiment, a 10-bit input video signal (a digital signal indicating an input gradation value in a 10-bit binary number) is input to the gradation correction unit 11. Therefore, in the present embodiment, an applied voltage corresponding to the gradation level in 1024 stages corresponding to the input video signal is applied to each pixel of the liquid crystal display panel 15.

The liquid crystal controller 12 generates various control signals for controlling the operation of the liquid crystal display panel 15 based on the corrected video signal input from the gradation correction unit 11 and outputs the control signals to the gate driver 13 and the source driver 14.

The liquid crystal display panel 15 is formed at each intersection of a plurality of gate bus lines connected to the gate driver 13, a plurality of source bus lines connected to the source driver 14, and the gate bus line and the source bus line. Pixels (both not shown).

The gate driver 13 sequentially applies a voltage to each gate bus line (scanning signal line) of the liquid crystal display panel 15 at a timing according to a control signal input from the liquid crystal controller 12.

The source driver 14 generates an analog voltage corresponding to the gradation value of the video signal in accordance with the control signal and the video signal input from the liquid crystal controller 12, and each source bus line (data signal line) of the liquid crystal display panel 15. Apply to. Note that a shift register (not shown) provided in the source driver 14 has a gradation value for pixels corresponding to each source bus line from the pixel before one gate bus line to the pixel of the next gate bus line in the video signal. The change of (binary number) is confirmed in order from the upper bit, and the generated analog voltage is changed according to the change of each bit.

In the present embodiment, the liquid crystal display panel 15 is a 4K2K class (liquid crystal display panel having a resolution of about 4000 pixels × 2000 pixels) and is driven at a frame frequency of 120 Hz. Further, in the present embodiment, a so-called double source structure (having two source bus lines per pixel column and connecting an odd-numbered pixel to one of these two source bus lines via a transistor, A liquid crystal display panel 15 having a structure in which a pixel is connected to the other through a transistor, two adjacent gate bus lines are simultaneously selected, and two gate bus lines are simultaneously driven) is used.

However, the resolution, frame frequency, and source structure of the liquid crystal display panel 15 are not limited to this. For example, (i) resolution 4K2K class, frame frequency 120 Hz, single source structure liquid crystal display panel, (ii) resolution 4K2K class, frame frequency 240 Hz, double source structure liquid crystal display panel, (iii) resolution 8K4K class, frame frequency 60 Hz Also, a liquid crystal display panel with a single source structure, (iv) a level 8K4K class, a frame frequency of 120 Hz, and a liquid crystal display panel with a double source structure are likely to cause line-like display anomalies and display by the same method as in this embodiment. It can suppress that abnormality is visually recognized. A liquid crystal display panel having a double source structure will be described later.

(1-2. Configuration of Tone Correction Unit 11)
FIG. 2 is an explanatory diagram showing the configuration of the gradation correction unit 11. As shown in FIG. 2, the gradation correction unit 11 includes a line memory 21, a correction necessity determination unit 22, a correction processing unit 23, and a correction data storage unit 24.

The line memory 21 stores input video signals for a predetermined line (for a predetermined number of gate bus lines) out of input video signals input from a video supply device (not shown). In the present specification, the simple description of “line” means a gate bus line.

The number of lines for storing the input video signal in the line memory 21 may be appropriately set according to the number of lines included in the correction target range in the gradation value correction processing in the correction processing unit 23 described later. When the liquid crystal display device 1 has processing functions such as unevenness correction processing, ghost correction processing, edge processing, and block noise processing, the line memory 21 is shared with the line memory used for these processing. May be.

The correction necessity determination unit 22 sets one of the gate bus lines in which the corresponding input video signal is stored in the line memory 21 as the target gate bus line, and the input gradation value and the display order of the target gate bus line correspond to the relevant gate video lines. Whether or not it is necessary to correct the input gradation value of the gate bus line of interest based on the input gradation value corresponding to the gate bus line (previous gate bus line of the previous attention) that is one before the gate gate line of interest. judge. A method for determining whether or not the input gradation value needs to be corrected will be described later.

The correction processing unit 23 is a gradation value (input gradation value) of an input video signal corresponding to a predetermined range of gate bus lines including the gate bus line of interest that is determined to be corrected by the correction necessity determination unit 22. Is corrected based on the correction data stored in advance in the correction data storage unit 24. Then, the correction processing unit 23 outputs the corrected video signal generated by the correction to the liquid crystal controller 12. For the input video signal corresponding to the gate bus line for which the gradation value is not corrected, the correction processing unit 23 uses the input video signal input from the correction necessity determination unit 22 as the corrected video signal as it is as the liquid crystal controller. 12 is output.

(1-3. Flow of processing in the gradation correction unit 11)
FIG. 3 is a flowchart showing the flow of processing in the gradation correction unit 11.

As shown in FIG. 3, the correction necessity determination unit 22 selects one of the gate bus lines in which the corresponding input video signal is stored in the line memory 21 as the target gate bus line (S1). The correction necessity determination unit 22 sequentially selects each gate bus line as a target gate bus line in the order in which the source driver 14 performs the generation process of the analog voltage (display order). At this time, the gate bus line already included in the correction target range in the process of S7 described later may not be selected as the gate bus line of interest.

Next, based on the input video signal corresponding to the target gate bus line read from the line memory 21, the correction necessity determination unit 22 determines whether the gradation value of each pixel corresponding to the gate bus line is the same. Is determined (S2).

In S2, when it is determined that the gradation values of the pixels corresponding to the target gate bus line are not the same, the correction necessity determination unit 22 determines whether the target gate bus line has the above-described line-shaped display abnormality ( It is determined that the tone value is not a line that needs to be corrected, and the process proceeds to S8.

On the other hand, when it is determined in S2 that the gradation value of each pixel corresponding to the target gate bus line is the same, the correction necessity determination unit 22 stores the display order stored in the line memory 21 in the target gate bus. For the gate bus line immediately preceding the line (the gate bus line in which the analog voltage is generated immediately before the target gate bus line in the source driver 14), the gradation value of each pixel corresponding to the gate bus line is It is determined whether or not they are the same (S3).

In S3, when it is determined that the gradation value of each pixel corresponding to the previous gate bus line in the display order is not the same, the correction necessity determination unit 22 displays the noticed gate bus line in the line-shaped display described above. It is determined that the line does not cause an abnormality (a line that requires correction of gradation values), and the process proceeds to S8.

In the present embodiment, a description will be given of a configuration for confirming whether or not the gradation value is the same for all the pixels arranged in the extending direction of the gate bus line in S2 and S3. However, the gradation value of each pixel in S2 and S3 is The range (number of pixels) for checking whether or not they are equal is not limited to this.

For example, it is not realistic from the viewpoint of processing resources and it is not preferable to check whether images of 4000 pixels are all equal in a 4K2K panel. This is because even if not all of the lines have the same gradation, if a video image such as VRAMP has a certain size or more, the line-shaped display abnormality that is a problem in one embodiment of the present invention is visually recognized. It is.

Also, the preferred size (number of pixels) for checking whether the gradation values are equal in S2 and S3 varies depending on the resolution of the display device, the angle of view, the number of gradations, and the like. In addition, if the range is too narrow, the problem is hardly visible in the first place, and if the range is too wide, the problem may be overlooked.

For this reason, it is preferable that the range for checking whether or not the gradation values are equal in S2 and S3 is determined in advance by conducting a display experiment using a liquid crystal display panel and taking into account the use and specifications of the display device.

According to experiments conducted by the present inventors, the above range is set from 4 pixels to 16 pixels for 2K1K and from 8 pixels to 32 pixels for 8K4K, assuming an angle of view size of about 50 inches to 100 inches. Was preferred. That is, in the processes of S2 and S3, in the case of an angle of view of about 50 inches to 100 inches, the range is more than a predetermined number of pixels set within the range of 4 pixels to 16 pixels in 2K1K, and the range of 8 pixels to 32 pixels in 8K4K It is preferable to check whether or not the gradation values of pixels arranged continuously in a predetermined number of pixels or more are equal.

The reason why the preferred size of the range for checking whether the gradation values are equal in S2 and S3 is not proportional to the resolution is considered to be because the video quality expected for display devices with different resolutions is different. It is done.

Also, the processing of S2 and S3 can be omitted depending on the use conditions of the liquid crystal display panel. This is because the pattern in which the display abnormality is most easily visually recognized can be avoided by the process of S4 described later.

Further, according to a request in circuit mounting, the gradation comparison in S4 and the processing in S2 and S3 may be performed in parallel. For example, the number of pixels in which a change in a predetermined gradation level continues may be counted while taking the difference between the target line and the comparison line. One example of simplification will also be described in the second and later embodiments.

On the other hand, if it is determined in S3 that the gradation value of each pixel corresponding to the previous gate bus line in the display order is the same, the correction necessity determination unit 22 displays the display stored in the line memory 21. Based on the input video signal of the previous gate bus line and the input video signal of the target gate bus line, the display order corresponds to the target gate bus line from each pixel corresponding to the previous gate bus line. It is determined whether or not the amount of change in gradation level for each pixel is within a predetermined range (for example, within one step or within two steps) (S4).

Note that the above-described line-shaped display abnormality is hardly visually recognized when the change amount of the gradation level between the gate bus lines in which the display order is continuous is large (for example, when there are four or more levels). Therefore, the predetermined range may be set as appropriate so as to include the amount of change in the gradation level at which display abnormality is visually recognized by conducting an experiment in advance.

In S4, when it is determined that the amount of change in the gradation level of each pixel is not within the predetermined range, the correction necessity determination unit 22 determines that the attention gate bus line is a line in which the above-described line-shaped display abnormality occurs (gradation value). Therefore, the process proceeds to S8.

On the other hand, when it is determined in S4 that the change amount of the gradation level of each pixel is within the predetermined range, the correction necessity determination unit 22 determines that the display order stored in the line memory 21 is the previous gate bus. Based on the input video signal of the line and the input video signal of the target gate bus line, the display order corresponds to the gradation value (binary number) of each pixel corresponding to the previous gate bus line and the target gate bus line. It is determined whether or not the number of bits whose value changes with the gradation value (binary number) of each pixel is a predetermined number (for example, 5) or more (S5).

Note that the above-described line-shaped display abnormality is more visible as the number of bits in which the gradation value (binary number) changes is larger. For this reason, the predetermined number may be appropriately set so as to include the number in which the display abnormality is visually recognized by conducting an experiment in advance.

In S5, when it is determined that the number of bits whose value changes is less than the predetermined number, the correction necessity determination unit 22 determines that the target gate bus line is a line in which the above-described line-shaped display abnormality occurs (tone value correction). Therefore, the process proceeds to S8.

On the other hand, if it is determined in S5 that the number of bits whose value changes is equal to or greater than the predetermined number, the correction necessity determination unit 22 determines that the target gate bus line is a line in which the above-described line-shaped display abnormality occurs (the gradation value). It is determined that the line is a line that needs to be corrected), and notifies the correction processing unit 23 that the target gate bus line is a line that requires correction of the gradation value (S6).

When the correction processing unit 23 is notified from the correction necessity determination unit 22 that the correction of the gradation value of the target gate bus line is necessary, the correction processing unit 23 selects a predetermined range of gate bus lines including the target gate bus line as a correction target range. The input video signal corresponding to each gate bus line included in the correction target range is read from the line memory 21, and the input gradation value corresponding to each gate bus line is corrected data stored in the correction data storage unit 24. (S7). The gradation value correction process will be described later.

Then, the corrected video signal generated by performing the above correction is output to the liquid crystal controller 12 (S8). The correction processing unit 23 outputs the input video signal read from the line memory 21 as it is to the liquid crystal controller 12 as a corrected video signal for the video signal corresponding to the gate bus line that does not need correction.

Thereafter, the correction necessity determination unit 22 determines whether or not the processing of S1 to S7 is completed for all the gate bus lines in the input video signal for one frame (S9), and unprocessed gate bus lines remain. If yes, the process returns to S1.

On the other hand, when it is determined in S9 that the processing has been completed for all the gate bus lines in the input video signal for one frame, the correction necessity determination unit 22 determines whether or not to process the next frame (S10). ) If so, the process returns to S1, and if not, the process ends.

(1-4. Processing Example in Tone Correction Unit 11)
FIG. 4 is an explanatory diagram illustrating an example of an input video signal with respect to a plurality of gate bus lines in which the display order is continuous (gate bus lines in which analog voltages are sequentially generated in the source driver 14). In the example shown in this figure, input video signals corresponding to gradation levels 894 to 898 are input to the pixels corresponding to the gate bus lines of line numbers 98 to 102.

When the gradation level 894 changes to the gradation level 895 as in the case of the line number 98 → 99 shown in FIG. 4, the number of bits whose value changes in the gradation value (binary number) is one. When the gradation level 896 changes to the gradation level 897 as in the case of the line number 100 → 101, the number of bits whose value changes in the gradation value (binary number) is one, and the line number 101 → 102. There are two cases where the gradation level 897 changes to the gradation level 898 as shown in FIG. However, when the gradation level 895 changes to the gradation level 896 as in line number 99 → 100, the number of bits whose value changes in the gradation value (binary number) is seven.

Thus, even if the gradation level changes in one step, the number of bits in which the gradation value (binary number) changes varies depending on the gradation level.

If the analog voltage is generated by the source driver 14 without correcting the input video signal at a position where the number of bits whose values change is large, as described above, the generation of the analog voltage is not in time and the line-like display abnormality is generated. May occur.

Therefore, in the present embodiment, when all the conditions of steps S2 to S5 shown in FIG. 3 are satisfied (when S2 to S5 are all YES), it is necessary to correct the gradation value of the input video signal. Judgment is made and the gradation value of the input video signal is corrected so that the display abnormality is not easily recognized.

FIG. 5 is an explanatory diagram showing an example of input tone value correction processing, where (a) is an input tone value corresponding to FIG. 4, and (b) is correction data applied to input tone value correction ( (Dither matrix) and (c) show an example of the corrected gradation value obtained by correcting the input gradation value of (a) with the correction data of (b). 5A and 5C show pixels corresponding to the source bus lines of the source bus line numbers (column numbers) 98 to 102 in the gate bus lines of the gate bus line numbers (row numbers) 98 to 102. FIG. Are shown.

When the correction necessity determination unit 22 determines that the target gate bus line is a line that requires correction of the gradation value, the correction processing unit 23 is a gate bus line in which the display order is continuous, and the target gate bus A predetermined number of gate bus lines including the line are selected as a correction target range. In the present embodiment, five gate bus lines centered on the target gate bus line are selected as the correction target range. However, the number of gate bus lines included in the correction target range is not limited to this, and it is sufficient that at least the target gate bus line is included.

Then, the correction processing unit 23 corrects the correction data stored in the correction data storage unit 24 for the input video signal in the correction target range (in this embodiment, a 5 × 5 dither matrix shown in FIG. 5B). ) Is applied to correct the input tone value by the dither method. That is, the correction processing unit 23 corrects each of the gate bus lines to be corrected using the dither method so that the gradation values of the pixels corresponding to the same gate bus line vary.

Thereby, for example, in the case of the input gradation value shown in FIG. 5A, the corrected gradation value shown in FIG. 5C is corrected.

In the corrected gradation value, random noise is added to the gradation value of the input video signal, and the combination of gradation values increases the number of bits in which the gradation value (binary number) changes (FIG. 5). In this example, the combination in which the gradation level changes from 895 to 896) is dispersed without being arranged in a line along the extending direction of the gate bus lines.

As a result, even if a pixel in which the analog voltage is not generated in time in the source driver 14 and the analog voltage corresponding to the original gradation value cannot be applied is generated, it is possible to suppress the display abnormality caused by the user from being visually recognized. .

In this embodiment, the 5 × 5 dither matrix shown in FIG. 5B is repeatedly used along the extending direction of the gate bus line. That is, the dither matrix shown in FIG. 5B is sequentially applied to the source bus line numbers 98 to 102, 103 to 107, 108 to 112,.

However, the present invention is not limited to this, and a plurality of types of 5 × 5 dither matrices are stored in the correction data storage unit 24, and the plurality of types of dither matrices are stored in a predetermined order or randomly along the extending direction of the gate bus lines. You may make it use in order. Further, the application position (or application order) of a plurality of types of dither matrices may be changed for each frame. By using these methods, the gradation change pattern corresponding to the dither matrix can be prevented from being visually recognized by the user, and the display quality can be further improved.

The dither matrix shape is not limited to a square shape (the shape in which the number of pixels in the row direction is the same as the number of pixels in the column direction). For example, a rectangular shape (the number of pixels in the row direction) is longer in the extending direction of the gate bus line. The shape may be larger than the number of pixels in the column direction).

In this embodiment, a case has been described in which a 5 × 5 dither matrix is used and the number of gate bus lines included in the correction target range is set to five. However, the present invention is not limited to this. The above-described line-shaped display abnormality is caused by a combination of gradation values in which the number of bits whose gradation value (binary number) changes increases in a line along the extending direction of the gate bus line. Therefore, it is only necessary to correct the combinations so that they do not line up in the extending direction of the gate bus lines, and it is sufficient to correct the gradation values for at least one gate bus line.

However, if the number of gate bus lines included in the correction target range is too small, the dither matrix pattern may be visually recognized or flicker may be visually recognized at a specific position. On the other hand, if the number of gate bus lines included in the correction target range is excessively increased, the circuit scale of the line memory 21 (or the circuit scale of each part of the gradation correction unit 11) increases. For this reason, the number of gate bus lines included in the correction target range is preferably set within a range from 4 lines to 16 lines, and more preferably set from 8 lines to 12 lines.

In addition, the number of pixels in the column direction (extension direction of the source bus line) and the number of pixels in the row direction (extension direction of the gate bus line) in the dither matrix do not necessarily have to match. For example, a dither matrix having a larger number of pixels in the column direction than the number of pixels in the row direction may be used, and correction may be performed using an arbitrary portion in the column direction in the dither matrix.

Further, in the example shown in FIG. 5B, the configuration in which the range of noise to be added (gradation change amount due to dither) is four gradations of +2 to −2 has been described. The range of noise to be added is not limited to this. However, in order to appropriately correct the line-like display abnormality so that it is difficult to visually recognize, it is preferable to set the range to about 2 to 4 gradations.

In addition, a plurality of types of dither matrices (correction data) having different noise ranges (tone change amounts due to dither) are stored in the correction data storage unit 24 in accordance with the ease of visual recognition of line-shaped display abnormalities. These dither matrices may be used properly. That is, combinations of a plurality of gradation values in which line-shaped display abnormalities are easily visible (combinations that require correction of gradation values) are classified according to the ease of visual recognition of display abnormalities. In the case of a combination that is easy to be visually recognized, a dither pattern with a wide range of noise to be added (gradation change amount due to dither) is used, and in the case of a combination that is relatively low in visibility of a display abnormality, the range of noise to be added ( A dither pattern having a narrow tone change amount due to dither may be used.

Further, a plurality of types of dither matrices (correction data) having different ranges of noise to be added (tone change amounts due to dither) are stored in the correction data storage unit 24, and display abnormalities in the individual liquid crystal display panels 15 become obvious. Depending on the degree of display, a liquid crystal display panel 15 in which a display abnormality is likely to be visually recognized uses a dither pattern with a wide range of noise (tone change amount due to dither), and the liquid crystal display panel is relatively less likely to be visually recognized. A dither pattern having a narrow range of noise to be added (tone change amount due to dither) may be used for 15.

In addition, after the correction processing unit 23 corrects the gradation value of the input video signal, the number of bits in which the gradation value (binary number) value is changed by the correction necessity determination unit 22 based on the corrected video signal. It is determined (tracked) whether or not there are adjacent dots (pixels) having a predetermined number (for example, 7) or more (whether 2 dots or more do not continue). Some of the gradation values of (pixels) may be changed.

Also, to prevent the observer from recognizing the dither pattern strongly, prepare a dither pattern with a large amount of noise and a dither pattern with a small amount of noise. Use a pattern with a small amount of noise when correction is not necessary. The pattern may be switched to a pattern with a large amount of noise. This makes it difficult for the observer to recognize dither correction.

(1-5. Example of double source structure)
In this embodiment, a single source in which each pixel arranged along the gate scanning direction (a direction perpendicular to the extending direction of the gate bus line. The extending direction of the source bus line) is connected to one source bus line. An example of the structure has been described. However, the application target of the liquid crystal display device according to one embodiment of the present invention is not limited thereto. In the liquid crystal display device according to one embodiment of the present invention, for example, two source bus lines are arranged for each pixel column arranged in the gate scanning direction, and even-numbered pixels are connected to one source bus line. The present invention can also be applied to a liquid crystal display panel having a so-called double source structure in which the first source bus line is connected to the other source bus line.

FIG. 8 is an explanatory diagram showing a configuration example of a liquid crystal display panel having a double source structure. As shown in this figure, two source bus lines Sa (Sa1, Sa2,...), Sb (Sb1, Sb2,...) Are arranged for each pixel column arranged in the gate scanning direction. The th-th pixel is connected to one of the two source bus lines, and the even-numbered pixel is connected to the other source bus line. In the double source structure, a plurality of source drivers are provided, and one of the two source bus lines Sa and Sb corresponding to the same pixel column is one source bus line Sa and the other source bus line Sb. Connected to different source drivers. In addition, the gate bus line is arranged for every two pixels arranged in the gate scanning direction, and two adjacent pixels in the gate scanning direction are connected to a common gate bus line. Thereby, when one gate bus line becomes active, two adjacent horizontal lines (two lines of pixel lines arranged in the extending direction of the gate bus line) are simultaneously written.

Therefore, in the case of the double source structure, when a VRAMP image that changes by one gradation every two horizontal lines is displayed, a line-shaped display abnormality is likely to be visually recognized.

FIG. 9 is an explanatory diagram showing an example of input gradation values for each line when displaying a VRAMP image that changes by one gradation every two horizontal lines in a liquid crystal display panel having a double source structure.

In the case of the example shown in FIG. 9, the horizontal lines 96 and 97, 98 and 99, 100 and 101, 102 and 103 are written at the same gate scanning timing, and the horizontal lines 96, 98, 100, 102 and 104 are written. Are connected to one source driver via the same source bus line Sa, and the pixels of the horizontal lines 97, 99, 101, 103, 105 are connected to the other source driver via another identical source bus line Sb. It is connected.

In this case, the one source driver changes the voltage applied to the source bus line Sa in accordance with the input gradation signals of the horizontal lines 96, 98, 100, 102, 104, and the other source driver uses the horizontal lines 97, 99. , 101, 103, and 105, the voltage applied to the other source bus line Sb is changed in accordance with the input gradation signals. Therefore, in the horizontal lines 100 (98 → 100) and 101 (99 → 101) in which the gradation level changes from 895 to 896, line-like display abnormalities are likely to occur as in the case of the single source structure.

Therefore, by correcting the gradation value of the pixel corresponding to one source bus line Sa and the gradation value of the pixel corresponding to the other source bus line Sb, respectively, as in the case of the single source structure, It can suppress that a line-like display abnormality is visually recognized.

Note that a line-like display abnormality which is a problem in one embodiment of the present invention is caused by source line inversion driving (a driving method in which the polarity of a voltage applied to a source bus line is inverted every scanning period and driving is performed with the same polarity during the period. ) Is particularly easily visible on a liquid crystal display panel. Therefore, the liquid crystal display device according to one embodiment of the present invention can be particularly preferably applied to a liquid crystal display panel that performs source line inversion driving.

[Embodiment 2]
Another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted.

In the first embodiment, the correction necessity determination unit 22 determines the gradation value (binary number) of each pixel corresponding to the gate bus line whose display order is one before the target gate bus line in step S5 of FIG. When it is determined that the number of bits whose value changes with the gradation value (binary number) of each pixel corresponding to the target gate bus line is equal to or greater than a predetermined number (for example, 5 or more), the correction processing unit 23 The case where the input gradation value is corrected has been described.

On the other hand, in the present embodiment, the correction necessity determination unit 22 determines the level of each pixel corresponding to the gate bus line whose display order is one before the target gate bus line in the process of step S5 in FIG. The number of bits whose value changes between the gradation value (binary number) and the gradation value (binary number) of each pixel corresponding to the gate bus line of interest is a predetermined number or more (for example, 5 or more), and the input floor When the gradation values of the lower 5 bits in the tone value (binary number) are all the same value (for example, 1), it is determined that correction is necessary. When the correction necessity determination unit 22 determines that correction is necessary, the correction processing unit 23 performs correction to change the value of the least significant bit of the input gradation value. For example, an input gradation value (binary number “11011111111”) at a gradation level 895 is corrected to a gradation level 894 (binary number “11011111110”).

Thereby, compared with the configuration of the first embodiment, the correction necessity determination process and the correction process can be simplified. In theory, there is a worst-case gradation transition for all gradations. However, the transition is visually recognized except when a predetermined number of lower-order bits transition between all 1s and all 0s. There are very few cases. Therefore, the line-shaped display abnormality can be easily and appropriately prevented from being visually recognized by the correction method of the present embodiment.

[Embodiment 3]
Still another embodiment of the present invention will be described. For convenience of explanation, members having the same functions as those in the above-described embodiment are denoted by the same reference numerals and description thereof is omitted.

In the present embodiment, the correction necessity determination unit 22 determines the gradation value (binary number) of each pixel corresponding to the gate bus line whose display order is one before the target gate bus line in the process of step S5 of FIG. ) And the gradation value (binary number) of each pixel corresponding to the target gate bus line, the number of bits whose value changes is a predetermined number or more (for example, 7 or more), and the value of the least significant bit is If it is determined that there is a change, it is determined that correction of the gradation value is necessary. When the correction necessity determination unit 22 determines that correction of the gradation value is necessary, the correction processing unit 23 corrects the gradation value so as to cancel the change in the least significant bit. That is, the least significant bit in the gradation value (binary number) of each pixel corresponding to the target gate bus line is the gradation value in each pixel corresponding to the gate bus line whose display order is one before the target gate bus line. Correction to match with the least significant bit of (binary number) is performed.

This makes it possible to simplify the determination process of whether correction is necessary and the correction process.

[Embodiment 4]
The gradation correction unit (video correction device) 11 of the liquid crystal display device 1 may be realized by a logic circuit (hardware) formed in an integrated circuit (IC chip) or the like, or using a CPU (Central Processing Unit). It may be realized by software.

In the latter case, the gradation correction unit 11 includes a CPU that executes instructions of a program that is software for realizing each function, and a ROM (Read Only Memory) in which the program and various data are recorded so as to be readable by a computer (or CPU). ) Or a storage device (these are referred to as “recording media”), a RAM (Random Access Memory) that expands the program, and the like. The computer (or CPU) reads the program from the recording medium and executes the program, thereby achieving the object of one embodiment of the present invention. As the recording medium, a “non-temporary tangible medium” such as a tape, a disk, a card, a semiconductor memory, a programmable logic circuit, or the like can be used. The program may be supplied to the computer via an arbitrary transmission medium (such as a communication network or a broadcast wave) that can transmit the program. Note that one embodiment of the present invention can also be realized in the form of a data signal embedded in a carrier wave, in which the program is embodied by electronic transmission.

[Summary]
The video correction device (gradation correction unit 11) according to the first aspect of the present invention is a video correction device (gradation correction unit 11) that corrects an input video signal to the liquid crystal display device 1, and corresponds to the gate bus line of interest. The source bus that is the same as that of the at least some of the pixels, the binary input gradation value of at least some of the pixels to be processed and the display order corresponding to the gate bus line immediately before the gate bus line of interest Correction for determining whether or not it is necessary to correct the input gradation value of the pixel corresponding to the gate bus line of interest according to the number of bits whose value changes with the binary input gradation value of the pixel connected to the line When the necessity determination unit 22 and the correction necessity determination unit 22 determine that correction is necessary, the input gradation value of the pixel corresponding to the target gate bus line is set to each pixel corresponding to the target gate bus line. of It is characterized by comprising a correction processing unit 23 for correcting to produce a variation in tone value.

When the shift register provided in the source driver 14 of the liquid crystal display device 1 generates an analog voltage corresponding to the input gradation value (binary number) of each pixel of the gate bus line of interest, the display order corresponding to each pixel is displayed. Check the change of the value of each bit (value of each binary number) from the input gradation value (binary number) of each pixel of the gate bus line that is one before the target gate bus line in order from the upper bit. The analog voltage value is adjusted for each bit whose value has changed. For this reason, when the number of bits whose value changes is large, the generation of the analog voltage may not be in time for the application timing of the analog voltage to each pixel of the target gate bus line, and display abnormality may occur.

On the other hand, according to the above configuration, the correction necessity determination unit 22 determines that the binary input gradation value and the display order in at least some of the pixels corresponding to the target gate bus line are the target gate bus. Depends on the number of bits corresponding to the gate bus line preceding the line and the binary input gradation value of the pixel connected to the same source bus line as the at least some pixels. Determining whether or not the input gradation value of the pixel corresponding to the target gate bus line needs to be corrected, and when the correction processing unit 23 determines that correction is necessary by the correction necessity determination unit 22, the target gate bus The input gradation value of the pixel corresponding to the target gate bus line is corrected so that the input gradation value of each pixel corresponding to the line is varied. Thereby, even when the generation of the analog voltage according to the input gradation value in the source driver 14 is not in time for the application timing of the analog voltage to the pixel, it is possible to suppress the display abnormality caused by the viewer from being visually recognized. can do.

In the video correction device (gradation correction unit 11) according to aspect 2 of the present invention, in the above aspect 1, the correction necessity determination unit 22 is equal to or greater than a predetermined number of consecutive pixels among the pixels corresponding to the gate gate line of interest. The input gradation values of all the pixels of the pixel are the same gradation value, and the display order is a pixel equal to or more than the predetermined number of consecutive pixels among the pixels corresponding to the gate bus line immediately before the gate bus line of interest The input gradation values of the pixels connected to the same source bus line are all the same gradation value, and the input gradation values of the pixels of the predetermined number of consecutive pixels or more corresponding to the target gate bus line A difference between an input gradation value of a pixel connected to the same source bus line as a pixel having a predetermined number or more corresponding to the previous gate bus line in the display order is within a predetermined range; and Attention gate Basra The binary input gradation value and the display order of each pixel that is equal to or greater than the predetermined number of pixels corresponding to the number of pixels are equal to or greater than the predetermined number of pixels corresponding to the gate bus line immediately before the gate bus line of interest. When the number of bits whose value changes between the binary input gradation value of each pixel connected to the same source bus line as the pixel is equal to or greater than a predetermined number, the pixel corresponding to the gate bus line of interest In this configuration, it is determined that the input tone value needs to be corrected.

According to said structure, even if it is a case where the generation of the analog voltage according to the input gradation value in the source driver 14 is not in time, it can suppress that the display abnormality resulting from it is visually recognized by a viewer. .

In the video correction apparatus (gradation correction unit 11) according to the aspect 3 of the present invention, in the above aspect 1 or 2, when the correction processing unit 23 determines that the correction is necessary by the correction necessity determination unit 22, An input gradation value of pixels corresponding to a plurality of gate bus lines including the target gate bus line and having a continuous display order is caused to vary in gradation values of pixels corresponding to the same gate bus line. It is the structure correct | amended to.

According to the above configuration, the correction pattern can be prevented from being visually recognized by the viewer, and the display abnormality can be corrected more appropriately.

In the video correction device (gradation correction unit 11) according to aspect 4 of the present invention, in any one of the above aspects 1 to 3, the correction processing unit 23 is determined to be correction required by the correction necessity determination unit 22. In this case, the input gradation value of the pixel corresponding to the gate gate line of interest can be corrected by the dither method.

According to the above configuration, the display abnormality can be appropriately corrected by a simple method.

In the video correction apparatus (gradation correction unit 11) according to aspect 5 of the present invention, in the above aspect 1, the correction necessity determination unit 22 is equal to or more than a predetermined number of consecutive pixels among the pixels corresponding to the gate gate line of interest. The input gradation value of the binary number and the display order of the pixels connected to the same source bus line as the pixels having the predetermined number of consecutive pixels or more corresponding to the gate bus line immediately before the gate bus line of interest are displayed. The binary input gradation of the number of bits whose value changes between the binary input gradation value and a predetermined number or more corresponding to the gate bus line of interest, When the predetermined number of lower-order bits in the value are the same value, it is determined that correction is necessary, and when the correction processing unit 23 determines that correction is necessary by the correction necessity determination unit 22, the gate gate of interest Vs line It is configured to perform correction of changing the value of the least significant bit in the binary input tone values of successive predetermined number of pixels or more pixels.

According to the above configuration, the display abnormality can be appropriately corrected by a simple method.

In the video correction apparatus (gradation correction unit 11) according to the sixth aspect of the present invention, in the first aspect, the correction necessity determination unit 22 is equal to or more than a predetermined number of consecutive pixels among the pixels corresponding to the target gate bus line. The input gradation value of the binary number and the display order of the pixels connected to the same source bus line as the pixels having the predetermined number of consecutive pixels or more corresponding to the gate bus line immediately before the gate bus line of interest are displayed. The binary input gradation of the number of bits whose value changes between the binary input gradation value and a predetermined number or more corresponding to the gate bus line of interest, The value of the least significant bit in the value is the binary value of the pixel connected to the same source bus line as the pixels having the display order corresponding to the gate bus line immediately preceding the target gate bus line and having the predetermined number of consecutive pixels or more. If the value of the least significant bit in the input tone value has changed, it is determined that correction is necessary, and the correction processing unit 23 determines that correction is necessary by the correction necessity determination unit 22. In this configuration, correction is performed to change the value of the least significant bit in the binary input gradation value of the pixel corresponding to the target gate bus line.

According to the above configuration, the display abnormality can be appropriately corrected by a simple method.

In the video correction device (gradation correction unit 11) according to the seventh aspect of the present invention, in any one of the first to sixth aspects, the liquid crystal display device 1 is configured to perform gate scanning in a direction that intersects the extending direction of the gate bus line. Two source bus lines are arranged for each pixel column composed of pixels arranged in the direction, and odd-numbered pixels among the pixels arranged in the gate scanning direction are connected to one of the two source bus lines. A pixel is connected to the other of the two source bus lines, and pixels arranged in the gate scanning direction are connected to a common gate bus line for every two adjacent pixels.

According to the above configuration, even in the case of a liquid crystal display device having a double source structure, it is possible to appropriately prevent the viewer from visually recognizing a line-shaped display abnormality.

The liquid crystal display device 1 according to the eighth aspect of the present invention includes the video correction device (gradation correction unit 11) according to any one of the first to seventh aspects.

According to the above configuration, even when the generation of the analog voltage corresponding to the input gradation value in the source driver is not in time, it is possible to suppress the display abnormality caused by the viewer from being visually recognized.

The video correction method according to the aspect 9 of the present invention is a video correction method for correcting an input video signal to the liquid crystal display device 1 and is a binary number in at least some of the pixels corresponding to the gate gate line of interest. An input gradation value and a binary input gradation value of a pixel connected to the same source bus line as the at least some pixels, the display order of which corresponds to the gate bus line immediately preceding the target gate bus line The correction necessity determination step for determining whether or not the input gradation value of the pixel corresponding to the target gate bus line needs to be corrected according to the number of bits whose value changes between the correction value and the correction necessity determination step. When it is determined that it is necessary, the input gradation value of the pixel corresponding to the target gate bus line is corrected so as to cause variation in the input gradation value of each pixel corresponding to the target gate bus line. It is characterized by comprising a correction processing step.

According to the above method, even if the generation of the analog voltage corresponding to the input gradation value in the source driver 14 is not in time for the application timing of the analog voltage to the pixel, the display abnormality caused by the generation is visually recognized by the viewer. Can be suppressed.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

(Cross-reference of related applications)
This application claims the benefit of priority to the Japanese patent application filed on August 25, 2015: Japanese Patent Application No. 2015-166189, and by referring to it, all of its contents Included in this document.

1 Liquid Crystal Display 11 Gradation Correction Unit (Video Correction Device)
12 liquid crystal controller 13 gate driver 14 source driver 15 liquid crystal display panel 21 line memory 22 correction necessity determination unit 23 correction processing unit 24 correction data storage unit

Claims (9)

A video correction device for correcting an input video signal to a liquid crystal display device,
The binary input gradation value in at least some of the pixels corresponding to the target gate bus line and the at least part of which the display order corresponds to the gate bus line immediately before the target gate bus line Correction of the input gradation value of the pixel corresponding to the gate bus line of interest according to the number of bits whose value changes between the binary input gradation value of the pixel connected to the same source bus line as the pixel A correction necessity determination unit for determining necessity, and
When the correction necessity determination unit determines that correction is necessary, the input gradation value of the pixel corresponding to the target gate bus line varies in the gradation value of each pixel corresponding to the target gate bus line. An image correction apparatus comprising: a correction processing unit that corrects the image to be corrected. The correction necessity determination unit
Of the pixels corresponding to the gate bus line of interest, the input gradation values of pixels that are a predetermined number of consecutive pixels or more are all the same gradation value, and
Of the pixels corresponding to the gate bus line immediately before the gate bus line of interest, the input gradation values of all the pixels connected to the same source bus line as the pixels having the predetermined number of pixels or more are all displayed. The same tone value, and
The same source bus as that of the pixels of the predetermined number of pixels or more corresponding to the gate bus line of the previous one and the input gradation value of the pixels of the predetermined number of pixels or more corresponding to the gate bus line of interest. The difference between the input gradation value of the pixels connected to the line is within a predetermined range, and
The continuous predetermined pixels whose binary input gradation value and display order of each pixel equal to or larger than the predetermined predetermined number of pixels corresponding to the target gate bus line correspond to the gate bus line immediately preceding the target gate bus line Corresponds to the gate bus line of interest when the number of bits whose value changes between the binary input gradation value of each pixel connected to the same source bus line and the number of pixels is a predetermined number or more The video correction apparatus according to claim 1, wherein it is determined that the input gradation value of the pixel to be corrected is necessary. The correction processing unit, when it is determined that correction is necessary by the correction necessity determination unit, input gradation values of pixels corresponding to a plurality of gate bus lines including the target gate bus line and having a continuous display order 3. The video correction apparatus according to claim 1, wherein the correction is performed so as to cause variation in gradation values of pixels corresponding to the same gate bus line. 4. The correction processing unit corrects an input gradation value of a pixel corresponding to the target gate bus line by a dither method when it is determined that correction is necessary by the correction necessity determination unit. 4. The image correction device according to any one of items 1 to 3. The correction necessity determining unit includes a gate whose binary input gradation value and display order of pixels of a predetermined number of consecutive pixels or more among the pixels corresponding to the target gate bus line are one before the target gate bus line. The number of bits whose value changes between a predetermined number of pixels corresponding to the bus line and the binary input gradation value of a pixel connected to the same source bus line is equal to or more than a predetermined number, And when the predetermined number of lower bits in the binary input gradation value of the pixels of the continuous predetermined number of pixels or more corresponding to the target gate bus line have the same value, it is determined that correction is necessary,
The correction processing unit, when it is determined that correction is necessary by the correction necessity determination unit, is the lowest in the binary input gradation value of the pixels that are equal to or more than the predetermined number of pixels corresponding to the gate bus line of interest. The video correction apparatus according to claim 1, wherein correction is performed to change a bit value. The correction necessity determining unit includes a gate whose binary input gradation value and display order of pixels of a predetermined number of consecutive pixels or more among the pixels corresponding to the target gate bus line are one before the target gate bus line. The number of bits whose value changes between a predetermined number of pixels corresponding to the bus line and the binary input gradation value of a pixel connected to the same source bus line is equal to or more than a predetermined number, In addition, the value of the least significant bit in the binary input gradation value of the pixels of the predetermined number of pixels or more corresponding to the target gate bus line is the gate bus line whose display order is one before the target gate bus line. If the value of the least significant bit in the binary input gradation value of the pixel connected to the same source bus line as the pixel of the predetermined number of pixels corresponding to the above is changed, it is determined that correction is necessary,
The correction processing unit performs correction to change the value of the least significant bit in the binary input gradation value of the pixel corresponding to the gate bus line of interest when the correction necessity determination unit determines that the correction is necessary. The video correction device according to claim 1, wherein the video correction device is performed. The liquid crystal display device
Two source bus lines are arranged for each pixel column composed of pixels arranged in the gate scanning direction, which is a direction intersecting the extending direction of the gate bus lines, and odd-numbered pixels among the pixels arranged in the gate scanning direction are the 2 pixels. Connected to one of the two source bus lines, the even-numbered pixel is connected to the other of the two source bus lines, and the pixels arranged in the gate scanning direction are connected to a common gate bus line for every two adjacent pixels The video correction apparatus according to claim 1, wherein the video correction apparatus is a video correction apparatus. A liquid crystal display device comprising the image correction device according to any one of claims 1 to 7. A video correction method for correcting an input video signal to a liquid crystal display device,
The binary input gradation value in at least some of the pixels corresponding to the target gate bus line and the at least part of which the display order corresponds to the gate bus line immediately before the target gate bus line Correction of the input gradation value of the pixel corresponding to the gate bus line of interest according to the number of bits whose value changes between the binary input gradation value of the pixel connected to the same source bus line as the pixel A correction necessity determination step for determining necessity, and
When it is determined that correction is required in the correction necessity determination step, the input gradation value of the pixel corresponding to the target gate bus line varies in the input gradation value of each pixel corresponding to the target gate bus line. And a correction processing step of correcting the image so as to cause it to occur.

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