WO2017052637A1

WO2017052637A1 - Multi-layer hardmask etch processes

Info

Publication number: WO2017052637A1
Application number: PCT/US2015/052436
Authority: WO
Inventors: Satyarth Suri; Tejaswi K. INDUKURI; Kaan OGUZ; Brian S. Doyle; Kevin P. O'brien; Mark L. Doczy; Robert B. TURKOT, Jr.
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2015-09-25
Filing date: 2015-09-25
Publication date: 2017-03-30
Anticipated expiration: 2018-03-25
Also published as: TW201724187A

Abstract

Many silicon wafers include a mixture of structures including a first number of first structures, such as memory elements, having a first height and high component density and a second number of second structures, such as logic elements, having a second height that is greater than the first height and low component density. An etch process may be used to achieve the high component density using a multi-layer hardmask in which a first hardmask is formed on a surface of the semiconductor wafer. After forming the first hardmask, an etch process may be used to provide or otherwise facilitate the fabrication of a first number of first structures having a relatively high component density. A second hardmask may be selectively fabricated on at least a portion of the first hardmask. The combined thickness of first hardmask and the second hardmask may approximately equal the height of the second structures.

Description

MULTI-LAYER HARDMASK ETCH PROCESSES

TECHNICAL FIELD

The present disclosure relates to semiconductor fabrication, and more particularly, to multi-layer hardmasks to improve component density.

BACKGROUND

Integrated circuit (IC) fabrication may involve a series of fabrication operations that result in layers of material being deposited on a substrate, the layering of materials resulting in the formation of features that may operate alone or cooperatively to provide functionality. In many instances, these features are based on groups of transistors configured to operate in a certain manner. The amount of functionality that can be implemented in an IC may depend on the size of the transistors and other devices formed on the substrate. As the footprint of each component (e.g., transistor) is reduced in size, the amount of functionality that may be implemented on a single substrate increases while still be able to operate within power, heat, etc. requirements. It is in this manner, functionality (e.g., data processing, memory, I/O, etc.) that was previously only able to be implemented in separate physical IC packages may now be implemented in a single system-on-chip (SOC) IC package.

As set forth above, the ability to integrate more and more functionality in a single IC may depend heavily on the ability to shrink the footprint of each feature. IC fabrication may, for example, employ a series of material deposition, mask and etch operations to fabricate an IC. A layer of semiconductor material may be deposited followed by photoresist. Narrow wavelength light may then be passed through a mask to draw patterns onto the photoresist. During etching, portions of the material may be removed (e.g., either the material portions that were exposed to light, or were not exposed to light, depending on whether a positive or negative photoresist was used), the material that remains may form parts of the features that may make up the IC. When the light wavelength is narrower the features may be fabricated to be smaller, and thus, more functionality may be included on a single substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:

FIG. 1 A is a cross-section of an illustrative semiconductor wafer that includes first structures and taller second structures, each of the first structures and the second structures spaced at a similar pitch, in accordance with at least one embodiment of the present disclosure;

FIG. IB is a cross-section of an illustrative semiconductor wafer that includes first structures and taller second structures, each of the first structures spaced at a first pitch using a first hardmask and the second structures spaced at a second pitch, in accordance with at least one embodiment of the present disclosure;

FIG. 1C is a cross-section of an illustrative semiconductor wafer that includes first structures and second structures, each of the first structures spaced at a first pitch and including a selectively fabricated second hardmask on the first hardmask and the second structures spaced at a second pitch, in accordance with at least one embodiment of the present disclosure;

FIG. 2 is a high-level flow diagram of an illustrative method of depositing a first hardmask on a semiconductor wafer to provide a first pitch between the first structures and selectively fabricating a second hardmask on at least a portion of the first hardmask, in accordance with at least one embodiment of the present disclosure.

FIG. 3 is a high-level flow diagram of an illustrative method of depositing a first hardmask having a first thickness on a semiconductor wafer and selectively fabricating a second hardmask having a second thickness on at least a portion of the first hardmask to provide a defined thickness, in accordance with at least one embodiment of the present disclosure.

FIG. 4 is a high-level flow diagram of an illustrative method of depositing a first hardmask having a first thickness on a semiconductor wafer and selectively fabricating a second hardmask having a second thickness on at least a portion of the first hardmask to provide a defined thickness and resistance, in accordance with at least one embodiment of the present disclosure. FIG. 5 is a block diagram of an illustrative processor-based device in which at least a portion of the memory stacks may incorporate the two-layer hardmask described in FIGs. 1 -4 above, in accordance with at least one embodiment of the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.

DETAILED DESCRIPTION

In memory fabrication such as magnetoresistive random access memory (MRAM), angled etch processes may deliver improved device performance but typically only work in large pitch/large space device or structure layouts due to etch shadowing caused by the hard mask used to pattern the wafer. In the etching process, a multi-layer hardmask may include a first hardmask that is sufficiently thin to permit a high component density while having physical and electrical properties that facilitate the etching process. A second hardmask may be applied to at least a portion of the first hardmask to increase the thickness of the hardmask to match the thickness of other components disposed on the wafer, thereby enabling the use of a single interconnect layer to conductively couple structures of differing heights across the wafer.

The use of multi-layer hardmasks addresses the issues with shadowing and beneficially supports the use of a standard etch (e.g. , a 90° etch) or angled etch processes with high-density memory products. In a multi-layer hardmask process, a height of a first hardmask is tuned to achieve the desired pitch between memory stacks and a height of a second hardmask is selectively fabricated on at least a portion of the first hardmask to match the total dual damascene layer height required by the integrated logic/interconnect circuits. The materials for the first and/or second hardmasks may be selected to provide a desired resistance between the memory stack and the interconnect layer. A two-layer hardmask approach enables etch processes, including angled etch processes, to achieve a memory device pitch in the range of 40 nanometers (versus 120 to 200 nanometers minimum pitch for single hardmask angled etch processes).

An integrated circuit device is provided. In embodiments, the integrated circuit device may include a substrate having a surface, a first number of first structures fabricated on the surface of the substrate, and a second number of second structures fabricated on the surface of the substrate, each of the second structures projecting a second height above the surface of the substrate. The integrated circuit device may include a first hardmask having a first thickness formed on at least a portion of the surface of the substrate where the first thickness of the first hardmask provides an aspect ratio (AR) that spaces each of the first structures at a first pitch. The integrated circuit may also include a second hardmask having a second thickness that is selectively fabricated on at least a portion of the first hardmask. The combined thickness of the first hardmask and the second hardmask may approximately equal the second height of the second structures.

A hardmask system to selectively etch on a semiconductor wafer a first number of first structures at a first pitch is provided. The hardmask system may include a first hardmask having a first thickness formed on at least a portion of a surface of the semiconductor wafer, the first thickness selected to provide the first pitch between each of the first structures, and a second hardmask having a second thickness that is selectively fabricated on at least a portion of the first hardmask, where a combined thickness of the first thickness and the second thickness approximately equals a height of at least one of a second number of second structures deposited on the semiconductor wafer.

A multi-layer hardmask method for selectively etching a first number of first structures disposed on a semiconductor wafer at a first pitch and a second number of structures disposed on the semiconductor wafer is provided. The method may include forming a first hardmask having a first thickness proximate a surface of the semiconductor wafer, etching the semiconductor wafer to provide the first pitch between each of the first structures, and selectively fabricating a second hardmask having a second thickness on the first hardmask to provide a multi-layer hardmask having a thickness approximately equal to the height of at least a portion of the number of second structures.

A multi-layer hardmask system for selectively etching a first number of first structures disposed on a semiconductor wafer at a first pitch and a second number of structures disposed on the semiconductor wafer at a second pitch is provided. The system may include a means for depositing a first hardmask having a first thickness on at least a portion of a surface of the semiconductor wafer, a means for etching the semiconductor wafer to provide the first pitch between each of the first structures, and a means for selectively fabricating a second hardmask having a second thickness on at least a portion of the first hardmask to provide a multi-layer hardmask having a thickness approximately equal to the height of at least a portion of the number of second structures.

FIG. 1 A is a cross-section of an illustrative semiconductor wafer 100 that includes a substrate 106 that includes at least a number of first structures 102A-102n (collectively "first structures 102), a thick hardmask 104A-104n (collectively, "thick hardmask 104"), and a number of physically taller second structures 112A-112n (collectively "second structures 112"), in accordance with at least one embodiment of the present disclosure. As depicted in FIG. 1A, a thick hardmask 104A-104n (collectively "thick hardmask 104") is deposited on a surface of a substrate 106. The height, of the thick hardmask 104 (HTM) approximately equals the height of the second structure 112. The roughly equal height of the thick hardmask 104 and the second structure 112 permits the conductive coupling of at least some of the first structures 102 with at least some of the second structures 112 using interconnect layer 120.

The distance 134 (Di) between the elements forming the thick hardmask 104 is the same as the distance 134 (Di) between the second structures 112 since the height of the thick hardmask 104 (HTM) approximately equals the height of the second structure 112. Since the height of the thick hardmask 104 (HTM) and the height of the second structures 112 (Hi) are similar, the shadow region 132 produced by the thick hardmask 104 and the second structure 112 are similar in dimension. Consequently, the device pitch 136 (Pi) between first structures 102 is approximately the same as the pitch 136 (Pi) between second structures 112. Where the first structures 102 represent memory devices and the second structures 112 represent logic devices, the device pitch 136 between the memory devices 102 effectively precludes the formation of high-density memory on the semiconductor memory 106.

FIG. IB is a cross-section of an illustrative semiconductor wafer 140 that includes a number of first structures 102A-102n and a relatively thin first hardmask 150A-150n

(collectively "first hardmask 150"), in accordance with at least one embodiment of the present disclosure. The height, of the first hardmask 150 (HMI) is less than the overall height, Hi, of the second structures 112. In embodiments, using an angled etch process 130, the reduced height HMI of the first hardmask 150 creates a significantly smaller shadow region 158 between first structures 102 than the thick hardmask 104 depicted in FIG. 1A. The significantly smaller shadow region 158 reduces the distance 154 (D₂) between neighboring first structures 102, thereby permitting the formation of first structures 102 on a tighter pitch 156 (P₂) than the thick hardmask 104 depicted in FIG. 1A (i.e., a higher component density). The tighter pitch 156 (P2) or higher component density achievable with the thinner first hardmask 150 permits the formation of a high-density memory on a semiconductor wafer 106 that contains both memory devices (i.e., the first structures 102) and logic devices (i.e. , the second structures 112). Each of the first structures 102 may include any number or combination of any current or future semiconductor components, systems, and/or devices. In embodiments, each of the first structures 102 may include one or more current or future developed memory devices, such as one or more magnetic tunnel junction (MTJ) memory cells.

Each of the second structures 112 may include any number or combination of conductors such as one or more vias or metal layers either alone or in combination with one or more current or future semiconductor components, systems, and/or devices. In embodiments, each of the second structures 112 may include one or more current or future developed logic devices. Each of the second structures 1 12 may project from, extend a distance from, or have a height (Hi) measured from a surface of a semiconductor wafer 106. Each of the second number of second structures 112 may project from the surface of the semiconductor wafer 106 the same or a different distance. In embodiments, each of the second structures 1 12 may have a height (Hi), measured from the surface of the

semiconductor wafer 106, of from about 50 nanometers (nm) to about 300 nm; from about 50 nm to about 200 nm; or from about 50 nm to about 100 nm.

The first hardmask 150 may include any material deposited on, proximate, or adjacent to either or both the first number of first structures 102 and/or a surface of the semiconductor wafer 106 that is capable of masking at least a portion of the surface of the semiconductor wafer 106 during an etching process. In at least some implementations, the first hardmask 150 may provide a mask during one or more etch processes. In at least some

implementations, the first hardmask 150 may provide a mask during one or more angled etch processes. The smaller the thickness of the first hardmask 150, the tighter the pitch 156 (P₂) between the first structures 102, consequently, the first hardmask 150 may be tailored to have a thickness that provides the desired pitch 156 (P₂) between first structures 102 while retaining sufficient thickness to accommodate etch shadowing and ensure adequate pattern transfer to the semiconductor wafer 106. In some implementations, the first hardmask 150 may have a height (HMI) or thickness of: about 1 nanometer (nm) or more; about 2 nm or more; about 5 nm or more; or about 10 nm or more. In some implementations, the first hardmask 150 may have a height (HMI) or thickness of: about 20 micrometers (μιη) or less; about 30 μιη or less; about 40 μιη or less; or about 50 μιη or less. The first hardmask 150 may be deposited on the surface of the semiconductor wafer 106 in locations that are proximate or wholly or partially adjacent to some or all of the first structures 102 using any current or future developed deposition processes or techniques. For example, the first hardmask 150 may be photolithographed on all or a portion of the surface of the

semiconductor wafer 106.

In some implementations, all or a portion of the first hardmask 150 may include one or more electrically conductive materials. In some implementations, all or a portion of the first hardmask 150 may be a slightly electrically conductive material. In some

implementations, the height or thickness of the first hardmask 150 may be based or otherwise determined in whole or in part on maintaining an electrical resistance through the first hardmask 150 to the underlying first structure 102 that is at or below a defined value. In some implementations, the height or thickness of the first hardmask 150 may be based or otherwise determined in whole or in part based on the etching process used to pattern the number of first structures 102 and/or the number of second structures 112.

The height or thickness (HMI) of the first hardmask 150 determines the extent of the shadow 158 created during an angled etch process 130. In embodiments, an aspect ratio may be defined as a ratio of the height of the first hardmask 150 (HMI) to the minimum distance 154 (D₂) between first structures 102 based upon the shadow region 158 created during the angle etch process 130. Of note, for a defined etch angle, the minimum distance 154 (D₂) between first structures 102 is proportional to the height of the respective first hardmask 150.

The height or thickness (HMI) of the first hardmask 150 is generally less than the height (Hi) of the second structures 112. Consequently, as depicted in FIG. IB, conductively coupling some or all of the first structures 102 to some or all of the second structures 1 12 could not be accomplished using a single interconnect layer 120 such as depicted in FIG. 1A.

FIG. 1 C is a cross-section of an illustrative semiconductor wafer 160 that includes a number of first structures 102A-102n, a first hardmask 150A- 150n and a second hardmask 170A- 170n (collectively, "second hardmask 170") that has been selectively deposited, formed, or otherwise placed on at least a portion of the first hardmask 150, in accordance with at least one embodiment of the present disclosure. In some implementations, the second hardmask 170 may be selectively fabricated, deposited, formed, or otherwise placed on the first hardmask 150 and may not be deposited elsewhere on the surface of the semiconductor wafer 106 or on other components or devices disposed in, on, or about the semiconductor wafer 106, including the second structures 112. In other embodiments, at least a portion of the second hardmask 170 may be deposited on at least a portion of the semiconductor wafer 106. The second hardmask 170 may have any thickness (HM₂) and may have a thickness that is less than, equal to, or greater than the thickness (HMI) of the first hardmask 150. In embodiments, the second hardmask 170 may include any material that may be selectively fabricated or otherwise deposited on the first hardmask 150 and that is capable of providing a mask during a subsequent etching process. In other embodiments, the second hardmask 170 may include any material that may be deposited using any current or future developed self-assembled material technologies such as directed self-assembly, self- assembled monolayers, and similar. In at least some implementations, the first hardmask 150 and the second hardmask 170 may, either alone or in combination, provide a mask during one or more angled etch processes 130. All or a portion of the second hardmask 170 may include one or more electrically conductive materials to electrically conductively couple the underlying first structure 102 with the interconnect layer 120. In some implementations, the composition and/or physical configuration of the second hardmask 170 may be based or otherwise determined in whole or in part on maintaining the electrical resistance provided by the first hardmask 150, the second hardmask 170, or the multi-layer hardmask formed by the first hardmask 150 and the second hardmask 170 at or below a defined electrical resistance.

Although not depicted in FIGs. IB and 1C, in yet other embodiments, a dielectric material may be deposited prior to the second hardmask 170 and the second hardmask 170 patterned into the dielectric material, for example by photolithographic techniques. In such implementations, the patterned dielectric material may be filled with one or more materials such as a barrier/liner (that includes, but is not limited to tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), or cobalt (Co)), a bulk material (that includes, but is not limited to, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), or ruthenium (Ru)), and one or more alloying materials (that include, but are not limited to aluminum (Al), copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), manganese (Mn), or magnesium (Mg)).

Unlike the first hardmask 150, the second hardmask 170 is not intended as a thin mask, instead the second hardmask 170 extends the overall height of the first structure 102 and first hardmask 150 such that the finished surface of completed two-layer hardmask is approximately equal to the height (Hi) of the second structure 112 and/or the dual damascene layer containing the second structure 112. Similar to FIG. 1A, above, setting the finished height of the first hardmask 150 and second hardmask 170 at about the same as the height (Hi) of the second structure 112 beneficially permits the use of a single interconnect layer 120 to conductively couple some or all of the first structures 102 to some or all of the second structures 112. In some implementations, the second hardmask 170 may have a height (HM₂) or thickness of: about 50 micrometers (μιη) or less; about 100 μιη or less; about 150 μιη or less; or about 200 μιη or less. In some implementations, the second hardmask 170 may have a height (HM₂) or thickness of: about 1 nanometer (nm) or more; about 2 nm or more; about 5 nm or more; or about 10 nm or more. The second hardmask 170 may be selectively fabricated on, adjacent, or proximate some or all of the first hardmask 150 using any current or future developed selective deposition processes or techniques.

FIG. 2 is a high-level logic flow diagram of an illustrative method 200 of depositing a two-layer hardmask on a substrate 106, such as a semiconductor wafer that includes a number of first structures 102, in accordance with at least one embodiment of the present disclosure. A semiconductor wafer 106 may incorporate a first number of first structures 102 and a second number of second structures 1 12 that project a height (Hi) from the surface of the wafer. The first structures 102 may include one or more devices, systems, or components that benefit from a high component density (e.g. , MRAM memory), therefore minimizing the distance (D₂) between the first structures may represent a design goal. The second structures 112 may include a fewer number of devices, systems, or components for which high component density may or may not be a design goal, and in fact may be detrimental to component and/or system cost or other optimization considerations. In such instances, the distance (Di) between the second structures 1 12 may be greater than the distance (D₂) between the first structures 102. Where the conductive coupling of at least some of the first structures 102 to at least some of the second structures 112 is desirable, the use of a single interconnect layer may be preferred. In such instances, an electrically conductive hardmask may be used to conductively couple at least some of the first structures 102 to the second structures 112 using a single interconnect layer 120 by building the combined height of the first hardmask 150 (HMI) and second hardmask 170 (HM₂) to approximately equal the height of the second structures 112 (Hi).

In embodiments, such multi-layer hardmasks may beneficially assist in achieving high component densities using etch processes 130, such as one or more angle etch processes. For example, a two-layer hardmask system in which a first hardmask 150 is deposited on the semiconductor wafer 106 in such a manner that the shadow region 158 created by the first hardmask 150 permits a high component density after the etch process 130. The two-layer hardmask system includes a second hardmask 170 that is selectively fabricated on, about, adjacent, or proximate at least a portion of the first hardmask 150. The height (HM₂) of the second hardmask 170 serves to increase the overall height of the first hardmask 150 (HMI) to an overall or combined height comparable to the height of the second structure 112 (Hi). The method 200 of forming such a two-layer hardmask system commences at 202.

At 204, the first hardmask 150 is deposited on a surface of the semiconductor wafer 106. The first hardmask 150 may have a thickness that is sufficient for pattern transfer to the semiconductor wafer 106. In some implementations, the first hardmask 150 facilitates the use of one or more etching processes 130 to pattern the semiconductor wafer 106 and provides the ability to achieve high component densities by virtue of the relatively small shadow region 158 created by the thin first hardmask 150. The first hardmask 150 may be formed, deposited, placed, or otherwise fabricated using any current or future developed pattern transfer technology, such as photolithography.

In some implementations, the thickness (H_MI) of the first hardmask 150 may be determined based at least in part by the desired spacing or distance between first structures 102. In some implementations, the thickness (H_MI) of the first hardmask 150 may be determined based at least in part on a defined resistance to current flow through the first hardmask 150 to the first structure 102. In some implementations, the composition of the first hardmask 150 may be determined based at least in part on a defined resistance to current flow through the first hardmask 150 to the first structure 102.

At 206, the semiconductor wafer 106 containing the first hardmask 150 is subjected to an etch process 130. Such etch processes may include any current or future developed dry etch process including, but not limited to, reactive ion etching, sputter etching, and vapor phase etching. In an angle etch process, the impact angle of the etch process, in combination with the thickness (H_MI) of the first hardmask 150 may define the depth (D₂) of the shadow region 158 cast by the first hardmask 150. The depth (D₂) of the shadow region 158 defines the minimum spacing between first structures 102 on the surface of the semiconductor wafer 106. The ratio of the height (H₂) to the depth (D₂) of the shadow region 158 may define an aspect ratio.

In an example application, the height (HMI) of the first hardmask 150 may be 2 nm to 50 μιη and the depth or minimum spacing between neighboring first structures 102 (D₂) may be 40 nm.

At 208, the second hardmask 170 is selectively fabricated on at least a portion of the first hardmask 150. In some implementations, a portion of the second hardmask 170 may be fabricated on a surface of the semiconductor wafer 106. In some implementations, a portion of the second hardmask 170 may be fabricated in or on a dielectric layer deposited or otherwise formed on the surface of the semiconductor wafer 106. In some embodiments, the selective fabrication of the second hardmask 170 causes an electrically conductive second hardmask 170 to form on an portion of the first hardmask 150 while not forming, depositing, or otherwise accumulating on other areas of the surface of the semiconductor wafer 106. Such selective fabrication of the second hardmask 170 may reduce or even eliminate the need for subsequent post-processing of the second hardmask 170.

In some implementations, the thickness (HM₂) of the second hardmask 170 may be determined based at least in part on the height (Hi) of the second structures 112 and the height of the first hardmask 150 (HMI) such that the surface of the second hardmask 170 opposite the first hardmask 150 is about equal to the surface of the second structure 112 opposite the surface of the semiconductor wafer 106. In some implementations, the composition of the second hardmask 170 may be determined based at least in part on a defined resistance to current flow through the second hardmask 170 to the first structure 102. The second hardmask 170 may include one or more electrically conductive materials including, but not limited to, copper, copper containing alloys, cobalt, and cobalt containing alloys. The method 200 concludes at 210.

FIG. 3 is a high-level logic flow diagram of an illustrative process 300 for using a two-layer hardmask system to match the height (HMI) of a thin first hardmask 150 deposited on a surface of the semiconductor wafer 106 to the height (Hi) of a second structure 112 fabricated on the semiconductor wafer 106, in accordance with at least one embodiment of the present disclosure. The method 300 commences at 302.

At 304, a first number of first structures 102 may be deposited, formed, or otherwise fabricated in, on, or about a surface of the semiconductor wafer 106. The first structures 102 may be deposited, formed, or otherwise fabricated on the surface of the semiconductor wafer 106 using any combination of any current or future developed deposition or implantation technology. In embodiments, the first number of first structures 102 may be deposited, formed, or otherwise fabricated on the surface of the semiconductor wafer in a high density component pattern. In some implementations, some or all of the first structures 102 may include memory devices, memory elements, memory cells, or similar. In some

implementations, some or all of the first structures 102 may include memory devices, memory elements, memory cells arranged in a high component density configuration. In such implementations, a high component density configuration may include component spacing of about 100 nanometers (nm) or less; about 50 nm or less; about 40 nm or less; about 30 nm or less; about 20 nm or less; or about 10 nm or less. At 306, a second number of second structures 1 12 may be deposited, formed, or otherwise fabricated in, on, about the surface of the semiconductor wafer 106. The second structures 112 may be deposited, formed, or otherwise fabricated on the surface of the semiconductor wafer 106 using any combination of current or future developed deposition, fabrication, or implantation technology. In embodiments, the second structure component density may be less than the first structure component density. In embodiments, the height (Hi) of at least some of the second structures 1 12 may be greater than the height (HD) of at least some of the first structures 102. In some implementations, at least some of the second number of second structures 112 may include logic devices or logic elements.

At 308, the thickness of the first hardmask 150 and the second hardmask 170 are selected based at least in part on the height (Hi) of at least some of the second number of second structures 1 12. In some implementations, the desired finished height of the combined, first hardmask 150 (HMI), and second hardmask 170 (HMZ) may be approximately equal to the height (Hi) of at least some of the second structures 112. The method 300 concludes at 310.

FIG. 4 is a high-level flow diagram of an illustrative method 400 of selecting physical and/or compositional parameters for at least one of the first hardmask 150 and/or the second hardmask 170 based at least in part on the combined electrical resistance through the first hardmask 150 and the second hardmask 170 being at or less than a defined resistance value, in accordance with at least one embodiment of the present disclosure. In embodiments, at least a portion of the first number of first structures 102 are electrically conductively coupled to an interconnect layer 120 via the first hardmask 150 and the second hardmask 170. In such instances, the electrical resistance of the first hardmask 150 and the second hardmask 170 is preferably maintained below a defined value to minimize losses and heating. The method 400 commences at 402.

At 404, the composition of the first hardmask 150 and/or the second hardmask 170 may be altered, changed, or otherwise adjusted to maintain the electrical resistance through the combined first hardmask 150 and second hardmask 170 at or below a defined value. In some instances, one or more physical parameters of the first hardmask 150 and/or second hardmask 170 may be altered, changed, or otherwise adjusted to maintain the electrical resistance through the combined first hardmask 150 and second hardmask 170 at or below a defined value. The method 400 concludes at 406.

FIG. 5 depicts a processor-based environment 500 in which the two-layer hardmask system depicted in FIGs. 1B-1 C may be incorporated, in accordance with at least one embodiment of the present disclosure. The processor-based device 502 may, on occasion, include one or more processor-based devices 502 communicably coupled to one or more nontransitory processor-readable storage devices 504. The associated nontransitory processor-readable storage medium 504 is communicatively coupled to the one or more processor-based devices 502 via one or more communications links 516, for example one or more parallel cables, serial cables, or wireless channels capable of high speed

communications, for instance via BLUETOOTH^®, universal serial bus (USB), FIREWIRE^®, or similar.

The one or more processor-based devices 502 may be communicably coupled to one or more external devices using one or more wireless or wired network interfaces 560.

Example wireless network interfaces 560 may include, but are not limited to,

BLUETOOTH^®, near field communications (NFC), ZigBee, IEEE 802.11 (Wi-Fi), 3G, 4G, LTE, CDMA, GSM, and similar. Example wired network interfaces 560 may include, but are not limited to, IEEE 802.3 (Ethernet), and similar. Unless described otherwise, the construction and operation of the various blocks shown in FIG. 5 are of conventional design. As a result, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art.

The processor-based system 500 may include one or more circuits capable of executing processor-readable instructions to provide any number of particular and/or specialized processor circuits 512, a system memory 506 and a system communications link 516 that bidirectionally communicably couples various system components including the system memory 506 to the processor circuit(s) 512. The processor circuit(s) 512 may include, but are not limited to, any circuit capable of executing one or more machine-readable and/or processor-readable instruction sets, such as one or more single or multi-core central processing units (CPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), systems on a chip (SOCs), etc. In at least some implementations, at least a portion of the processor circuit(s) 512 may include one or more storage devices employing the two-layer hardmask system described in FIGs. 1B-1C.

The communications link 516 may employ any known bus structures or architectures, including a memory bus with memory controller, a peripheral bus, and/or a local bus. The system memory 506 includes read-only memory ("ROM") 518 and random access memory ("RAM") 520. In at least some implementations, at least a portion of the system memory 506 may include one or more storage devices employing the two-layer hardmask system described in FIGs. 1B-1C. A basic input/output system ("BIOS") 522, which may, on occasion, form part of the ROM 518, contains basic routines that may cause the transfer information between elements within the processor-based device 502, such as during start-up.

The processor-based device 502 may include one or more disk drives 524, one or more optical storage devices 528, one or more magnetic storage devices 530, and/or one or more atomic or quantum storage devices 532. The one or more optical storage devices 528 may include, but are not limited to, any current or future developed optical storage drives (e.g. , compact disc (CD), digital versatile disk (DVD), and similar). The one or more magnetic storage devices 530 may include, but are not limited to, any type of current or future developed rotating or stationary device in which data is stored in a magnetic and/or electromagnetic format such as a solid-state drive (SSD) and various forms of removable storage media (e.g. , secure digital (SD), secure digital high capacity (SD-HC), universal serial bus (USB) memory stick, and similar). The one or more atomic or quantum storage devices may include, but are not limited to, any current or future developed atomic spin, molecular storage devices. The one or more disk drives 524, the one or more optical storage devices 528, the one or more magnetic storage devices 530, and the one or more

atomic/quantum storage devices 532 may include integral or discrete interfaces or controllers (not shown).

Machine-readable instruction sets may be stored or otherwise retained in whole or in part in the system memory 506. Such machine-readable instruction sets may include, but are not limited to an operating system 536, one or more application instruction sets 538, system, program, and/or application data 542, and one or more communications applications such as a Web browser 544. While shown in FIG. 5 as being stored in the system memory 506, the operating system 536, application instruction sets 538, system, program, and/or application data 542 and browser 544 may, on occasion, be stored in whole or in part on one or more other storage devices such as the one or more disk drives 524, the one or more optical storage devices 528, the one or more magnetic storage devices 530, and/or one or more atomic or quantum storage devices 532.

A system user may enter commands and information into the processor-based device 502 using one or more physical input devices 570. Example physical input devices 570 include, but are not limited to, one or more keyboards 572, one or more touchscreen I/O devices 574, one or more audio input devices 576 (e.g. , microphone) and/or one or more pointing devices 578. These and other physical input devices may be communicably coupled the processor-based device 502 through one or more wired or wireless interfaces such as a wired universal serial bus (USB) connection and/or a wireless BLUETOOTH^® connection.

The system user may receive output from the processor-based device 502 via one or more physical output devices 580. Example physical output devices 580 may include, but are not limited to, one or more visual or video output devices 582, one or more tactile or haptic output devices 584, and/or one or more audio output devices 586. The one or more video or visual output devices 582, the one or more tactile output devices 584, and the one or more audio output devices 586 may be communicably coupled to the communications link 516 via one or more interfaces or adapters.

The following examples pertain to embodiments that employ some or all of the described multi-layer hardmask apparatuses, systems, and methods described herein. The enclosed examples should not be considered exhaustive, nor should the enclosed examples be construed to exclude other combinations of the systems, methods, and apparatuses disclosed herein and which are not specifically enumerated herein.

According to example 1 there is provided an integrated circuit device. The integrated circuit device may include a substrate having a surface, a first number of first structures fabricated on the surface of the substrate, and a second number of second structures fabricated on the surface of the substrate, each of the second structures projecting a second height above the surface of the substrate. The integrated circuit device may further include a first hardmask having a first thickness fabricated on at least a portion of the surface of the substrate, where the first thickness of the first hardmask provides an aspect ratio (AR) that spaces each of the first structures at a first pitch. The integrated circuit device may further include a second hardmask having a second thickness selectively fabricated on at least a portion of the first hardmask, where the combined thickness of the first hardmask and the second hardmask approximately equals the second height.

Example 2 may include elements of example 1 where each of the first structures may include at least one semiconductor memory stack.

Example 3 may include elements of example 1 where each of the second structures may include at least one semiconductor logic device.

Example 4 may include elements of example 1 where the first hardmask and the second hardmask may each include an electrically conductive material selected to provide an electrical resistance of less than a defined resistance value when the first hardmask is deposited at the first thickness and the second hardmask is deposited at the second thickness. Example 5 may include elements of example 1 where the second hardmask may include an electrically conductive material.

Example 6 may include elements of example 5 where the second hardmask may include at least one of: a copper (Cu) containing material or a cobalt (Co) containing material.

Example 7 may include elements of any of examples 1 through 6 where the first hardmask may include at least one material having a thickness of from about 2 nanometers (nm) to about 50 micrometers (μιη).

Example 8 may include elements of any of examples 1 through 6 where the second hardmask may include at least one material selectively fabricated on the first hardmask and having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη).

According to example 9, there is provided a hardmask system to selectively etch on a semiconductor wafer a first number of first structures at a first pitch. The system may include a first hardmask having a first thickness formed on a portion of a surface of the

semiconductor wafer, the first thickness selected to provide the first pitch between each of the first structures and a second hardmask having a second thickness selectively fabricated on at least a portion of the first hardmask, where a combined thickness of the first thickness and the second thickness approximately equals a height of at least one of a second number of second structures deposited on the semiconductor wafer.

Example 10 may include elements of example 9 where each of the first structures may include at least one semiconductor memory device formed on a substrate.

Example 11 may include elements of example 10 where each of the second structures may include at least one semiconductor logic device formed on the substrate.

Example 12 may include elements of example 9 where the first hardmask and the second hardmask may each include an electrically conductive material selected to provide an electrical resistance of less than a defined resistance value when the first hardmask is deposited at the first thickness and the second hardmask is deposited at the second thickness.

Example 13 may include elements of example 9 where the second hardmask may include an electrically conductive material.

Example 14 may include elements of example 13 where the second hardmask may include at least one of: a copper (Cu) containing material or a cobalt (Co) containing material.

Example 15 may include elements of example 9 where the first hardmask may include at least one material having a thickness of from about 2 nanometers (nm) to about 50 micrometers (μιη). Example 16 may include elements of example 15 where the second hardmask may include at least one material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη) selectively fabricated on at least a portion of the first hardmask.

According to example 17, there is provided a multi-layer hardmask method for selectively etching a first number of first structures disposed on a semiconductor wafer at a first pitch and a second number of structures disposed on the semiconductor wafer. The method may include forming a first hardmask having a first thickness on at least a portion of a surface of the semiconductor wafer, etching the semiconductor wafer to provide each of the first structures at the first pitch, and selectively fabricating a second hardmask.

Example 18 may include elements of example 17 and may additionally include forming each of the first number of first structures on the semiconductor substrate.

Example 19 may include elements of example 18 where forming each of the first structures on a substrate may include forming each of the first number of first structures on the semiconductor wafer, each of the first structures including at least one memory stack.

Example 20 may include elements of example 18 and may additionally include forming each of the second number of second structures on the semiconductor wafer.

Example 21 may include elements of example 20 where forming each of the second structures on a substrate may include forming each of the second number of second structures on the semiconductor wafer, each of the second structures including at least one logic device.

Example 22 may include elements of example 17 where depositing a first hardmask having a first thickness and selectively fabricating a second hardmask having a second thickness on the first hardmask may include forming the first hardmask and fabricating the second hardmask to provide an electrical resistance of less than a defined resistance value when the first hardmask is deposited at the first thickness and the second hardmask is deposited at the second thickness.

Example 23 may include elements of example 17 where selectively fabricating a second hardmask having a second thickness on the first hardmask may include selectively fabricating a second hardmask that includes an electrically conductive material on the first hardmask.

Example 24 may include elements of example 23 where selectively fabricating a second hardmask that includes an electrically conductive material on the first hardmask may include selectively fabricating a second hardmask having the second thickness on the first hardmask, the second hardmask including at least one of: a copper (Cu) containing material or a cobalt (Co) containing material. Example 25 may include elements of example 17 where forming a first hardmask having a first thickness may include forming at least one material having a thickness of from about 2 nanometers (nm) to about 50 micrometers (μιη), the at least one material forming at least a portion of the first hardmask.

Example 26 may include elements of claim 17 where selectively fabricating a second hardmask having a second thickness may include selectively fabricating at least one material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη), the at least one material forming at least a portion of the second hardmask.

Example 27 may include elements of example 26 where selectively fabricating at least one material having a thickness of from about 50 nanometers (nm) to about 200 nm may include selectively fabricating at least one of: a copper containing material having a thickness of from about 50 nanometers (nm) to about 200 nm or a cobalt containing material having a thickness of from about 50 nanometers (nm) to about 200 nm.

Example 28 may include elements of any of examples 17 through 27 where forming each of the first number of first structures on the semiconductor wafer may include forming each of the first number first structures on the semiconductor wafer wherein a combined thickness of the first thickness, and the second thickness approximately equal a height above the surface of the semiconductor wafer of at least some of the number of second structures.

According to example 29, there is provided a multi-layer hardmask system for selectively etching a first number of first structures disposed on a semiconductor wafer at a first pitch and a second number of structures disposed on the semiconductor wafer at a second pitch. The system may include a means for forming a first hardmask having a first thickness, a means for etching the semiconductor wafer to provide the first pitch between each of the first structures, and a means for selectively fabricating on at least a portion of the first hardmask a second hardmask having a second thickness.

Example 30 may include elements of example 29 and may additionally include a means for forming each of the first number of first structures on the semiconductor wafer.

Example 31 may include elements of example 30 where the means for forming each of the first structures on a substrate may include a means for forming each of the first number of first structures on the semiconductor wafer, each of the first structures including at least one memory stack.

Example 32 may include elements of example 30 and may additionally include a means for forming each of the second number of second structures on the semiconductor wafer. Example 33 may include elements of example 32 where the means for forming each of the second structures on a substrate may include a means for forming each of the second number of second structures on the semiconductor wafer, each of the second structures including at least one logic device.

Example 34 may include elements of example 29 where the means for forming a first hardmask having a first thickness and where the means for selectively fabricating a second hardmask having a second thickness on the first hardmask, the second thickness at least equal to the first thickness may include a means for forming an electrically conductive first hardmask and selectively fabricating an electrically conductive second hardmask to provide an electrical resistance of less than a defined resistance value when the first hardmask is formed at the first thickness and the second hardmask is selectively fabricated on the first hardmask at the second thickness.

Example 35 may include elements of example 29 where the means for selectively fabricating a second hardmask having a second thickness on the first hardmask may include a means for selectively fabricating on the first hardmask a second hardmask that includes an electrically conductive material, the electrically conductive material having the second thickness.

Example 36 may include elements of example 35 where the means for selectively fabricating a second hardmask that includes an electrically conductive material on at least a portion of the first hardmask, the electrically conductive material having the second thickness may include a means for selectively fabricating a second hardmask having the second thickness, the second hardmask including at least one of: a copper (Cu) containing material or a cobalt (Co) containing material on the first hardmask.

Example 37 may include elements of example 29 where the means for forming a first hardmask having a first thickness may include a means for forming at least one material having a thickness of from about 2 nanometers (nm) to about 50 micrometers (μιη), the at least one material forming at least a portion of the first hardmask.

Example 38 may include elements of example 29 where the means for selectively fabricating a second hardmask having a second thickness on the first hardmask may include a means for selectively fabricating on the first hardmask at least one material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη), the at least one material forming at least a portion of the second hardmask.

Example 39 may include elements of example 38 where the means for selectively fabricating a second hardmask that includes at least one material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη) on at least a portion of the first hardmask comprises a means for selectively fabricating a copper containing material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη) or a cobalt containing material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη) on at least a portion of the first hardmask.

Example 40 may include elements of any of examples 29 through 39 where the means for forming each of the first number of first structures on the semiconductor wafer may include a means for forming each of the first number first structures on the semiconductor wafer, wherein a combined thickness of the first thickness, and the second thickness approximately equal a height above the surface of the semiconductor wafer of at least some of the number of second structures.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

Claims

WHAT IS CLAIMED:

1. An integrated circuit device, comprising:

a substrate having a surface;

a first number of first structures fabricated on the surface of the substrate;

a second number of second structures fabricated on the surface of the substrate, each of the second structures projecting a second height above the surface of the substrate;

a first hardmask having a first thickness formed on at least a portion of the surface of the substrate, wherein the first thickness of the first hardmask provides an aspect ratio that spaces each of at least a portion of the number of first structures at a first pitch; and

a second hardmask selectively fabricated on at least a portion of the first hardmask wherein the combined thickness of the first hardmask and the second hardmask

approximately equals the second height.

2. The integrated circuit device of claim 1 wherein each of the first structures comprise at least one memory device.

3. The integrated circuit device of claim 1 wherein each of the second structures comprise at least one logic device.

4. The hardmask system of claim 1 wherein the second hardmask comprises an electrically conductive material selected to provide an electrical resistance of less than a defined resistance value when the second hardmask is deposited at the second thickness.

5. The hardmask system of claim 1 wherein the second hardmask comprises an electrically conductive material.

6. The hardmask system of claim 5 wherein the second hardmask comprises at least one of: a copper (Cu) containing material or a cobalt (Co) containing material.

7. The hardmask system of any of claims 1 through 6 wherein the first hardmask comprises at least one material having a thickness of from about 2 nanometers (nm) to about 50 micrometers (μιη).

8. The hardmask system of any of claims 1 through 6 wherein the second hardmask comprises at least one material selectively fabricated on at least a portion of the first hardmask and having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη).

9. A hardmask system to selectively etch on a semiconductor wafer a first number of first structures at a first pitch, the system comprising:

a first hardmask having a first thickness formed on at least a portion of a surface of the semiconductor wafer, the first thickness selected to provide the first pitch between each of the first structures; and

a second hardmask selectively fabricated on at least a portion of the first hardmask, wherein a combined thickness of the first thickness and the second thickness approximately equals a height of at least one of a second number of second structures deposited on the semiconductor wafer.

10. The hardmask system of claim 9:

wherein each of the first structures comprise at least one memory device formed on the semiconductor wafer; and

wherein each of the second structures comprise at least one logic device formed on the semiconductor wafer.

11. The hardmask system of claim 9 wherein the second hardmask comprises an electrically conductive material selected to provide an electrical resistance of less than a defined resistance value when the second hardmask is deposited at the second thickness.

12. The hardmask system of claim 9 wherein the second hardmask comprises an electrically conductive material.

13. The hardmask system of claim 9 wherein the first hardmask comprises at least one material having a thickness of from about 2 nanometers (nm) to about 50 micrometers (μηι).

14. The hardmask system of claim 13 wherein the second hardmask comprises at least one material having a thickness of from about 2 nanometers (nm) to about 200 micrometers (μιη) selectively fabricated on at least a portion of the first hardmask.

15. A multi-layer hardmask method for selectively etching a first number of first structures disposed on a semiconductor wafer at a first pitch, the method comprising:

formign a first hardmask having a first thickness on at least a portion of a surface of the semiconductor wafer;

etching the semiconductor wafer to provide each of the first structures at the first pitch; and

selectively fabricating a second hardmask on at least a portion of the first hardmask, the second hardmask having a second thickness at least equal to the first thickness.

16. The multi-layer hardmask method of claim 15, further comprising:

forming each of the first number of first structures on the semiconductor wafer, each of the first structures including at least one memory device; and

forming each of the second number of second structures on the semiconductor wafer, each of the second structures including at least one logic device.

17. The multi-layer hardmask method of claim 16:

wherein a combined thickness of the first thickness and the second thickness approximately equal a height of at least some of the number of second structures above the surface of the semiconductor wafer.

18. The multi-layer hardmask method of claim 15 wherein forming a first hardmask having a first thickness comprises:

forming a first hardmask comprising an electrically conductive material having the first thickness.

19. The multi-layer hardmask method of claim 15 wherein selectively fabricating a second hardmask having a second thickness on the first hardmask comprises:

selectively fabricating a second hardmask that includes an electrically conductive material on at least a portion of the first hardmask.

20. A multi-layer hardmask system for selectively etching a first number of first structures at a first pitch on a semiconductor wafer that includes a second number of second structures having a second height, the system comprising:

a means for forming a first hardmask having a first thickness on at least a portion of a surface of the semiconductor wafer;

a means for etching the semiconductor wafer to provide each of the first structures at the first pitch; and

a means for selectively fabricating a second hardmask on at least a portion of the first hardmask, the second hardmask having a second thickness at least equal to the first thickness.

21. The multi-layer hardmask system of claim 20, further comprising:

a means for forming each of the first number of first structures on the semiconductor substrate.

22. The multi-layer hardmask system of claim 21 wherein the means for forming each of the first structures on a substrate comprises:

a means for forming each of the first number of first structures on the semiconductor wafer, each of the first structures including at least one memory device.

23. The multi-layer hardmask system of claim 21, further comprising:

a means for forming each of the second number of second structures on the semiconductor wafer.

24. The multi-layer hardmask system of claim 23 wherein the means for forming each of the second structures on a substrate comprises:

a means for forming each of the second number of second structures on the semiconductor wafer, each of the second structures including at least one logic device.

25. The multi-layer hardmask system of claim 20 wherein the means for forming a first hardmask having a first thickness comprises:

a means for forming at least one material having a thickness of from about 2 nanometers (nm) to about 50 nanometers (nm), the at least one material forming at least a portion of the first hardmask.