WO2016118683A1 - Substrat revêtu destiné à une utilisation dans des capteurs - Google Patents
Substrat revêtu destiné à une utilisation dans des capteurs Download PDFInfo
- Publication number
- WO2016118683A1 WO2016118683A1 PCT/US2016/014209 US2016014209W WO2016118683A1 WO 2016118683 A1 WO2016118683 A1 WO 2016118683A1 US 2016014209 W US2016014209 W US 2016014209W WO 2016118683 A1 WO2016118683 A1 WO 2016118683A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- coated substrate
- sensor
- substrate
- electrostatic discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1329—Protecting the fingerprint sensor against damage caused by the finger
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
Definitions
- the disclosure relates to a coated substrate for use in a sensor, and more particularly to a coated substrate for use in a capacitive fingerprint sensor embedded in a cover assembly of an electronic device.
- sensor elements such as fingerprint sensors
- touchscreens such as cellular phones, tablets, and notebooks.
- Sensor elements can be convenient and useful for consumers.
- fingerprint sensors are advantageous because they add an extra layer of security beyond password protection so that if your device is stolen, the thief cannot gain access to your personal information stored in the device without your fingerprint.
- a coated substrate for use in a sensor, a sensor including the coated substrate, and an electronic device including the sensor having the coated substrate.
- a coated substrate for use in a sensor includes a substrate having a first surface, a second surface opposing the first surface, at least one via hole extending from the first surface to the second surface, and a rigidity of greater than 0.03 Pa*m 3 ; a metal layer disposed on the first surface of the substrate; an electrostatic discharge protection layer disposed on the metal layer having a dielectric breakdown voltage greater than 200 V/ ⁇ ; and an outermost layer disposed on the electrostatic discharge protection layer providing scratch resistance and impact resistance.
- Fig. l is a top plan view of an exemplary electronic device having a cover assembly with an embedded sensor substrate.
- Fig. 2 is an exemplary cross section of the sensor substrate.
- Fig. 3 is a first exemplary coating stack.
- Fig. 4 is a second exemplary coating stack.
- FIG. 5 is a plot of wavelength in nm vs. % reflection for glass samples having a white ink coating with a silicon layer of 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm.
- FIG. 6 is a plot of wavelength in nm vs. % reflection for bare glass samples having a silicon layer of 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm.
- a solution for protecting the surface of the sensor substrate is to apply a coating stack that will provide protection from electrostatic discharge damage and provide scratch and impact resistance.
- the coating stack can also address aesthetic requirements, such as color specifications.
- FIG. 1 illustrates an exemplary embodiment of an electronic device 10 having a cover assembly 12 with a sensor substrate 14 embedded in an opening of a cover substrate 16.
- cover substrate 16 can be glass, ceramic, glass-ceramic, or sapphire.
- FIG. 2 illustrates a cross-section view of sensor substrate 14 having a first surface 18 and an opposing second surface 20. It is noted that the figures are not to scale. First surface 18 of sensor substrate 14 faces can be positioned so that it faces the exterior of electronic device 10 and second surface 20 of sensor element can be positioned so that it faces the interior of electronic device 10. Sensor substrate 14 can have an array of via holes 22 extending from first surface 18 to second surface 20. Vias 22 can be filled with a conductive material to provide a conductive path from first surface 18 of sensor substrate 14 to second surface 20 of sensor substrate 14. In some embodiments, a metal distribution layer 24 is applied to first surface 18 of sensor substrate 14 using conventional techniques and contacts the conductive material in via holes 22.
- a coating stack 26 can be deposited over metal distribution layer 24.
- a circuitry assembly or integrated circuit can be attached to second surface 20 of sensor substrate 14.
- the integrated circuit and sensor substrate assembly can act as a sensor element, including but not limited to, a fingerprint sensor (for example, a capacitive fingerprint sensor), a thermometer, a pulse oximeter, a pressure sensor, or an optics-based sensor.
- Sensor substrate 30 can be a suitable insulative material, including, but not limited to glass, ceramic, glass ceramic, silicon, or a polymeric material. In some embodiments, sensor substrate is sufficiently rigid to support coating stack 26. Rigidity (D) is defined by the equation:
- sensor substrate 30 can have a rigidity greater than 0.03 Pa*m 3 .
- coating stack 26 can include an intermediate layer 28 disposed on metal layer 24 and a top layer 30 disposed on intermediate layer 28.
- the term "dispose” includes coating, depositing and/or forming a material onto a surface using any known method in the art.
- the phrase "disposed on” includes the instance of forming a material onto a surface such that the material is in direct contact with the surface and also includes the instance where the material is formed on a surface, with one or more intervening material(s) between the disposed material and the surface.
- Each of intermediate layer 28 and top layer 30 can be a single layer or can have a plurality of sublayers.
- Intermediate layer 28 can function as an electrostatic discharge (ESD) layer to protect the electronics underneath it (e.g., the integrated circuit/circuitry assembly).
- ESD electrostatic discharge
- intermediate layer 28 provides ESD protection by having a dielectric breakdown voltage greater than 200 V/ ⁇ .
- intermediate layer 28 also provides cushioning to top layer 30 to balance minimizing tensile stresses to top layer 30 and bi-axial flexural stresses to top layer 30 when top layer 30 is subjected to an impact load such as being dropped on a rough surface.
- an elastic modulus of intermediate layer 28 affects the tensile stresss and bi-axial flexural stress to top layer 30.
- intermediate layer 28 can have an elastic modulus in a range from about 50 MPa to about 500 MPa. Such an elastic modulus balances minimizing the tensile stresses and bi-axial flexural stresses to top layer 30 when the top layer has a tensile strength of at least 300 MPa.
- intermediate layer 28 can have a thickness in a range from about 10 ⁇ to about 100 ⁇ .
- top layer 30 provides scratch and impact resistance. In some embodiments, top layer 30 has a thickness less than 2 ⁇ .
- the materials for the layers of coating stack 26 are chosen with a goal of minimizing the overall thickness of coating stack 26 while still achieving adequate electrostatic discharge protection, and impact and scratch resistance.
- the sensitivity of the sensor is measured by the signal-to-noise ratio (SNR) and SNR is dependent on the thickness of the coating stack as the SNR decreases approximately 0.7 dB per micrometer of coating stack 26. In some embodiments, the SNR is greater than 20 dB.
- coating stack 26 has an apparent thickness. As used herein, the term apparent thickness means how thick the coating stack 26 appears to be rather than how thick coating stack 26 actually is in part as a result of the refractive properties of coating stack 26. In some embodiments, the apparent thickness is less than the actual thickness. In some embodiments, coating stack 26 has an apparent thickness less than 20 ⁇ . In some embodiments, the higher the dielectric constant of the electrostatic discharge protection layer the lower the apparent thickness.
- FIG. 3 illustrates an exemplary coating stack 26' .
- Coating stack 26' includes an ESD protection layer 32 as intermediate layer 28' disposed on metal layer 24.
- Top coat 30' includes a color layer 34 disposed on ESD protection layer 32 and a hard coat 36 disposed on color layer 34.
- ESD protection layer 32 can be a colored organic resin based ink, for example a white ink having the breakdown voltage, elastic modulus, and thickness properties discussed above.
- the ink can be applied using conventional techniques such as by screen printing.
- the ink can be a thermally or ultraviolet light curable ink.
- Top coat 30' can have the thickness properties discussed above.
- color layer 34 is a grey-based color.
- color layer 34 can include one or more layers of a metal or metal oxide that provides the grey color and acts as a neutral density filter. Suitable materials include, but not limited to aluminum, silver, gold, and a copper-nickel alloy.
- color layer 34 is not a grey-based color.
- color layer 34 can include one or more layers of material that provide the non- grey-based color that act as an interference filter.
- the interference filter can include one or more layers of silicon.
- the filters can have a thickness of up to about 100 nm.
- the one or more layers of color layer 34 can be deposited using conventional techniques, for example sputtering.
- Hard coat 36 can include a silicon oxide (S1O 2 ) layer, a silicon nitride (S13N 4 ) layer or both. The silicon oxide and/or silicon nitride layer can be deposited using conventional techniques, for example plasma enhanced chemical vapor deposition.
- hard coat 36 can be multilayer with a layer of silicon nitride disposed between two layers of silicon oxide. Each of the sublayers can have a thickness of about 100 nm.
- FIG. 4 illustrates another exemplary coating stack 26" .
- Intermediate layer 28" can include an ESD protection layer 38 disposed on metal layer 24 and a color layer 40 disposed on EDS protection layer 38.
- Top coat 30" can include a hard coat 42. In this embodiment, top layer 30" does not include a color layer because the color layer is incorporated in intermediate layer 28" .
- ESD protection layer 38 can be an organic polymeric material having the breakdown voltage, elastic modulus, and thickness properties discussed above. Suitable polymeric materials can include a polyimide based material, an acrylate based material, or a fluorinated material. International Pub. No. WO2010/099254, which is hereby incorporated by reference in its entirety, discloses suitable materials for ESD protection layer 38.
- the organic polymeric material of ESD protection layer 38 can be filled with inorganic particles including, but not limited to, titanium oxide. Suitable materials for the inorganic particles can include materials having a dielectric constant greater than about 50. In some embodiments, the size of the inorganic particles can be chosen in order to maximize diffusing the reflection of light.
- Color layer 40 can be a black ink.
- the ink can be applied using conventional techniques such as by screen printing.
- the ink can be a thermally or ultraviolet light curable ink.
- the ink can be applied so that color layer 40 has a thickness of about 6 ⁇ .
- Hard coat 42 can be the same as hard coat 36 described above.
- Hard coat 42 can include a silicon oxide (S1O 2 ) layer, a silicon nitride (S1 3 N 4 ) layer or both.
- the silicon oxide and/or silicon nitride layer can be deposited using conventional techniques, for example plasma enhanced chemical vapor deposition.
- hard coat 42 can be multilayer with a layer of silicon nitride disposed between two layers of silicon oxide. Each of the sublayers can have a thickness of about 100 nm. Examples
- the silicon oxide and silicon nitride layers were deposited at a temperature of 200 °C using the following deposition parameters shown in Table 1 below to produce a first layer of silicon oxide having a thickness of 100 nm, a layer of silicon nitride having a thickness of 100 nm, and a layer of silicon oxide having a thickness of 100 nm.
- a first set of Eagle XG ® glass substrates available from Corning Incorporated were provided with a 10 ⁇ thick white ink as described in Example 1 above and then a silicon layer having a thickness of 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm was deposited thereon in the manner described in Example 1.
- a second set of Eagle XG ® glass substrates had a silicon layer having a thickness of 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm deposited thereon in the manner described in Example 1.
- the reflectance of each sample was measured with a F10 Spectrometer over a range from 400 nm to 1000 nm.
- FIG. 5 is a plot of wavelength in nm vs. % reflection for each of the white coated samples (5 nm, 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm silicon layer). As can be seen in FIG. 5, the reflection gradually increases as the wavelength increases for each silicon layer thickness.
- FIG. 6 is a plot of wavelength in nm vs. % reflection for each of the samples without the white ink coating (5 nm, 10 nm, 20 nm, 30 nm, 40 nm, and 50 nm silicon layer). As can be seen in FIG. 6, the reflection stays substantially the same as the wavelength increases for each silicon layer thickness.
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- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Laminated Bodies (AREA)
Abstract
Un substrat destiné à une utilisation dans des capteurs, comme des capteurs d'empreintes digitales capacitifs, peut avoir un empilement de revêtements qui empêche une décharge électrostatique et améliore la résistance aux rayures et aux chocs.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562106894P | 2015-01-23 | 2015-01-23 | |
| US62/106,894 | 2015-01-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2016118683A1 true WO2016118683A1 (fr) | 2016-07-28 |
Family
ID=55310935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2016/014209 Ceased WO2016118683A1 (fr) | 2015-01-23 | 2016-01-21 | Substrat revêtu destiné à une utilisation dans des capteurs |
Country Status (2)
| Country | Link |
|---|---|
| TW (1) | TW201630727A (fr) |
| WO (1) | WO2016118683A1 (fr) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018044661A1 (fr) * | 2016-08-31 | 2018-03-08 | Corning Incorporated | Articles à base de verre renforcé ayant des trous remplis et leur procédé de fabrication |
| US9946915B1 (en) | 2016-10-14 | 2018-04-17 | Next Biometrics Group Asa | Fingerprint sensors with ESD protection |
| KR20190010037A (ko) * | 2017-07-20 | 2019-01-30 | (주)파트론 | 지문 센서 패키지 |
| US10580725B2 (en) | 2017-05-25 | 2020-03-03 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
| US10756003B2 (en) | 2016-06-29 | 2020-08-25 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
| US10794679B2 (en) | 2016-06-29 | 2020-10-06 | Corning Incorporated | Method and system for measuring geometric parameters of through holes |
| US10969526B2 (en) | 2017-09-08 | 2021-04-06 | Apple Inc. | Coatings for transparent substrates in electronic devices |
| US11078112B2 (en) | 2017-05-25 | 2021-08-03 | Corning Incorporated | Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same |
| US11114309B2 (en) | 2016-06-01 | 2021-09-07 | Corning Incorporated | Articles and methods of forming vias in substrates |
| US11152294B2 (en) | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| US11554984B2 (en) | 2018-02-22 | 2023-01-17 | Corning Incorporated | Alkali-free borosilicate glasses with low post-HF etch roughness |
| US11760682B2 (en) | 2019-02-21 | 2023-09-19 | Corning Incorporated | Glass or glass ceramic articles with copper-metallized through holes and processes for making the same |
| US12180108B2 (en) | 2017-12-19 | 2024-12-31 | Corning Incorporated | Methods for etching vias in glass-based articles employing positive charge organic molecules |
| US12200875B2 (en) | 2018-09-20 | 2025-01-14 | Industrial Technology Research Institute | Copper metallization for through-glass vias on thin glass |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030161512A1 (en) * | 2000-06-09 | 2003-08-28 | Svein Mathiassen | Sensor unit, especially for fingerprint sensors |
| WO2010023323A1 (fr) * | 2008-09-01 | 2010-03-04 | Idex Asa | Capteur de surface |
| US20100215968A1 (en) * | 2009-02-26 | 2010-08-26 | Fields Lenwood L | Electrically isolating polymer composition |
| KR101451222B1 (ko) * | 2013-11-05 | 2014-10-16 | (주)드림텍 | 센싱영역을 별도로 형성한 지문인식센서 및 이를 이용한 지문인식 홈키와 그 제조방법 |
-
2016
- 2016-01-21 WO PCT/US2016/014209 patent/WO2016118683A1/fr not_active Ceased
- 2016-01-22 TW TW105102053A patent/TW201630727A/zh unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030161512A1 (en) * | 2000-06-09 | 2003-08-28 | Svein Mathiassen | Sensor unit, especially for fingerprint sensors |
| WO2010023323A1 (fr) * | 2008-09-01 | 2010-03-04 | Idex Asa | Capteur de surface |
| US20100215968A1 (en) * | 2009-02-26 | 2010-08-26 | Fields Lenwood L | Electrically isolating polymer composition |
| KR101451222B1 (ko) * | 2013-11-05 | 2014-10-16 | (주)드림텍 | 센싱영역을 별도로 형성한 지문인식센서 및 이를 이용한 지문인식 홈키와 그 제조방법 |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11114309B2 (en) | 2016-06-01 | 2021-09-07 | Corning Incorporated | Articles and methods of forming vias in substrates |
| US10756003B2 (en) | 2016-06-29 | 2020-08-25 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
| US10794679B2 (en) | 2016-06-29 | 2020-10-06 | Corning Incorporated | Method and system for measuring geometric parameters of through holes |
| US11774233B2 (en) | 2016-06-29 | 2023-10-03 | Corning Incorporated | Method and system for measuring geometric parameters of through holes |
| WO2018044661A1 (fr) * | 2016-08-31 | 2018-03-08 | Corning Incorporated | Articles à base de verre renforcé ayant des trous remplis et leur procédé de fabrication |
| US9946915B1 (en) | 2016-10-14 | 2018-04-17 | Next Biometrics Group Asa | Fingerprint sensors with ESD protection |
| US11078112B2 (en) | 2017-05-25 | 2021-08-03 | Corning Incorporated | Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same |
| US11972993B2 (en) | 2017-05-25 | 2024-04-30 | Corning Incorporated | Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same |
| US10580725B2 (en) | 2017-05-25 | 2020-03-03 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
| US11062986B2 (en) | 2017-05-25 | 2021-07-13 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
| KR20190010037A (ko) * | 2017-07-20 | 2019-01-30 | (주)파트론 | 지문 센서 패키지 |
| KR101993900B1 (ko) * | 2017-07-20 | 2019-09-30 | (주)파트론 | 센서 패키지 |
| US10969526B2 (en) | 2017-09-08 | 2021-04-06 | Apple Inc. | Coatings for transparent substrates in electronic devices |
| US12253697B2 (en) | 2017-09-08 | 2025-03-18 | Apple Inc. | Coatings for transparent substrates in electronic devices |
| US12180108B2 (en) | 2017-12-19 | 2024-12-31 | Corning Incorporated | Methods for etching vias in glass-based articles employing positive charge organic molecules |
| US11554984B2 (en) | 2018-02-22 | 2023-01-17 | Corning Incorporated | Alkali-free borosilicate glasses with low post-HF etch roughness |
| US11201109B2 (en) | 2018-04-09 | 2021-12-14 | Corning Incorporated | Hermetic metallized via with improved reliability |
| US11152294B2 (en) | 2018-04-09 | 2021-10-19 | Corning Incorporated | Hermetic metallized via with improved reliability |
| US12131985B2 (en) | 2018-04-09 | 2024-10-29 | Corning Incorporated | Hermetic metallized via with improved reliability |
| US12200875B2 (en) | 2018-09-20 | 2025-01-14 | Industrial Technology Research Institute | Copper metallization for through-glass vias on thin glass |
| US11760682B2 (en) | 2019-02-21 | 2023-09-19 | Corning Incorporated | Glass or glass ceramic articles with copper-metallized through holes and processes for making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201630727A (zh) | 2016-09-01 |
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