WO2016165091A1 - Apparatus and method for processing signal of absolute value encoder - Google Patents

Abstract

An apparatus for processing a signal of an absolute value encoder, comprising: a reading circuit (110), configured to acquire a position signal and check information output by an absolute value encoder; a pulse counting circuit (120), configured to count pulses according to a waveform signal output by the absolute value encoder; and a position processing circuit (130), configured to judge, according to the check information, whether the position signal is correct, the position processing circuit (130) being further configured to update, when the position signal is correct, position information, clear a count value of the pulse counting circuit (120), calculate, when the position signal is wrong, a correct position signal according to the current position information and count value, update the position information, and then clear the count value. The production cost of the apparatus for processing a signal of an absolute value encoder is low. Also provided is a method for processing a signal of an absolute value encoder.

Description

Absolute encoder signal processing device and method Technical field

The present invention relates to the field of electronic communication technologies, and in particular, to an absolute value encoder signal processing apparatus and method.

Background technique

The absolute encoder has the advantages of absolutely unique position, anti-interference, no power-down memory, no need to find a reference point and no need to count all the time. It has been widely used in angle, length measurement and positioning in various industrial systems. Controlled. The reading and data processing of the traditional absolute encoder position is realized by using a FPGA (Field-Programmable Gate Array) chip according to the protocol between the absolute value encoder and the special bus. Relevant data is provided to subsequent processing devices. The adoption of such a scheme is generally affected by the price of the FPGA chip, and the system cost is high.

Summary of the invention

Based on this, it is necessary to provide a lower cost absolute value encoder signal processing device.

An absolute value encoder signal processing apparatus for processing a position signal output by an absolute value encoder, comprising: a reading circuit for connecting with the absolute value encoder and acquiring the output of the absolute value encoder a position signal and verification information; a pulse counting circuit for connecting to the absolute value encoder and performing pulse counting according to the waveform signal output by the absolute value encoder; and a position processing circuit, and the reading circuit and the The pulse counting circuit is connected to determine whether the position signal is correct according to the verification information; the position processing circuit is further configured to update the position information when the position signal is correct and the count value of the pulse counting circuit Cleared; the position processing circuit is further configured to: according to current position information and the pulse counting circuit when the position signal is wrong The count value updates the position information after calculating the correct position signal and clears the count value of the pulse count circuit.

其中，P_now为正确的位置信号，P_old为当前的位置信号，K为计数值，P_A为绝对值编码器旋转一周后位置信号的变化量，K_A为所述绝对值编码器旋转一周后所述脉冲计数电路的计数值的变化量。In one embodiment, the formula of the position processing circuit calculating the correct position signal based on the current position information and the count value of the pulse counting circuit is:

P _now is the correct position signal, P _old is the current position signal, K is the count value, P _A is the change amount of the position signal after the absolute value encoder rotates one week, and K _A is the absolute value encoder rotation one week. The amount of change in the count value of the pulse counting circuit is described later.

根据所述角度信号生成两路正交的正弦信号瞬时值的计算公式为C＝sinT，D＝cosT；其中，C为第一正弦信号瞬时值，D为第二正弦信号瞬时值；T为角度信号。In one embodiment, the signal processing circuit is further configured to convert the correct position signal into an angle signal, and then generate two orthogonal sinusoidal signal instantaneous values according to the angle signal; convert the correct position signal into an angle signal. The formula is

Calculating the instantaneous value of the two orthogonal sinusoidal signals according to the angle signal is C=sinT, D=cosT; wherein C is the instantaneous value of the first sinusoidal signal, D is the instantaneous value of the second sinusoidal signal; T is the angle signal.

In one embodiment, the method further includes: a conversion control circuit coupled to the position processing circuit for generating an analog quantity control signal according to a correct position signal; an analog quantity generating circuit coupled to the conversion control circuit for The correct position signal is converted into an analog signal according to the analog quantity control signal and output.

In one embodiment, the analog quantity generating circuit is a pulse width modulation circuit; and the analog quantity control signal is used to adjust a duty ratio of a pulse signal output by the pulse width modulation circuit.

In one embodiment, the method further includes: an output circuit connected to the analog quantity generating circuit, configured to output the analog quantity signal to a subsequent processing device; a sampling and verifying circuit, and an output of the analog quantity generating circuit The output end of the output circuit is connected to compare the signal at the output end of the output circuit with the signal at the output end of the analog generating circuit to determine whether the two are the same, and output error information when the two are different. .

In one embodiment, a communication circuit is further included, and is connected to the sampling and verification circuit. And outputting the error information to a subsequent processing device.

In one embodiment, the communication circuit is further connected to the position processing circuit for outputting the position information to the subsequent processing device.

In one of the embodiments, the read circuit, the pulse count circuit, and the position processing circuit are integrated in a digital processing chip.

In one embodiment, the read circuit includes a read interface and an interface drive circuit; the read interface is for connecting to the absolute value encoder and is connected to the interface drive circuit; A circuit is also coupled to the position processing circuit.

In one of the embodiments, the read interface is a serial peripheral interface.

In one of the embodiments, a storage circuit is further coupled to the position processing circuit for storing the position information.

An absolute value encoder signal processing method for processing a position signal output by an absolute value encoder, comprising the steps of: reading a position signal output by the absolute value encoder and verifying information; Determining whether the position signal is correct; if yes, updating the position information and clearing the count value of the pulse counting circuit; if not, calculating the correct value based on the current position information and the count value of the pulse counting circuit The position information is updated after the position signal and the count value of the pulse counting circuit is cleared.

In one embodiment, the step of updating the position information and clearing the count value of the pulse counting circuit further comprises the steps of: generating an analog quantity control signal according to the correct position signal; generating the control signal according to the analog quantity The analog signal is output to the subsequent processing device through the output circuit; the signal at the output end of the output circuit is detected and it is determined whether the signal at the output end of the output circuit is identical to the generated analog signal; if otherwise, the error information is output.

In one embodiment, the step of generating an analog quantity control signal according to the correct position signal comprises: converting the calculated position signal into an angle signal and generating two orthogonal sinusoidal signal instantaneous values according to the angle signal. Generating an analog control signal based on the generated two orthogonal sinusoidal signal instantaneous values.

In one embodiment, the detecting a signal at an output of the output circuit and determining the In the step of synchronizing the signal at the output of the output circuit with the generated analog signal, if the signal output from the output circuit is the same as the generated analog signal, the operation is terminated.

In one of the embodiments, the step of updating the position information and clearing the count value of the pulse counting circuit further comprises the step of storing the updated position information.

In one embodiment, the step of determining whether the location signal is correct according to the verification information is specifically: calculating a verification code according to the read position signal; determining the calculated verification code and the calibration Whether the check code in the information is consistent; if yes, the position signal is correct, and if not, the position signal is wrong.

其中，P_now为正确的位置信号，P_old为当前的位置信号，K为计数值，P_A为绝对值编码器旋转一周后位置信号的变化量，K_A为所述绝对值编码器旋转一周后所述脉冲计数电路的计数值的变化量。In one of the embodiments, the calculation formula for calculating the correct position signal based on the current position information and the count value of the pulse counting circuit is:

P _now is the correct position signal, P _old is the current position signal, K is the count value, P _A is the change amount of the position signal after the absolute value encoder rotates one week, and K _A is the absolute value encoder rotation one week. The amount of change in the count value of the pulse counting circuit is described later.

The above-mentioned absolute value encoder signal processing device and method can realize the processing of the position signal outputted by the absolute value encoder through the reading circuit, the pulse counting circuit and the position processing circuit, and the processing process does not need to use a special FPGA chip, and the production cost is relatively high. low.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and those skilled in the art can obtain drawings of other embodiments according to the drawings without any creative work.

1 is a block diagram showing the structure of an absolute value encoder signal processing apparatus in an embodiment;

2 is a block diagram showing the structure of an absolute value encoder signal processing apparatus in another embodiment;

3 is a flow chart of an absolute value encoder signal processing method in an embodiment;

4 is a flow chart of an absolute value encoder signal processing method in another embodiment.

detailed description

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

An absolute value encoder signal processing apparatus for processing a position signal output by an absolute value encoder for supply to a subsequent processing system. 1 is a schematic structural diagram of an absolute value encoder signal processing apparatus in an embodiment, including a read circuit 110, a pulse count circuit 120, and a position processing circuit 130. The read circuit 110 and the pulse count circuit 120 are respectively connected to the position processing circuit 130.

The read circuit 110 is for connecting to an absolute encoder to receive a position signal of its output and verification information. The verification information output by the absolute encoder is a check code obtained by verifying the output position signal by the internal verification circuit. Specifically, the read circuit 110 includes a read interface 112 and an interface drive circuit 114. The read interface 112 is connected to the interface driving circuit 114, and is connected to the absolute value encoder through the DATA+, DATA-, CLK+, and CLK-ends of the absolute value encoder. In this embodiment, the read interface 112 uses a Serial Peripheral Interface (SPI), and the absolute value encoder is an EnDat absolute encoder. Therefore, the read interface 112 performs the reading of the absolute value encoder position signal and the check information according to the protocol between it and the EnDat absolute value encoder (ie, the EnDat protocol), thereby obtaining the position signal and the check information.

The pulse counting circuit 120 is for connecting to an absolute value encoder and performing pulse counting based on a waveform signal output from the absolute value encoder. In the present embodiment, the absolute value encoder signal processing apparatus further includes an analog quantity processing circuit 140. The analog processing circuit 140 is coupled to the analog sinusoidal signal outputs A+, A-, B+, and B- of the absolute encoder to receive the analog sinusoidal signal carried by the absolute encoder itself. The analog processing circuit 140 processes the received analog sinusoidal signal into a square wave signal and outputs it to the pulse counting circuit 120 for pulse counting. In the present embodiment, the pulse counting circuit 120 is a Quadrature Encoder Pulse (QEP).

The position processing circuit 130 is configured to receive the position signal read by the reading circuit 110 and the verification signal. And judge whether the read position signal is correct according to the received verification information. Specifically, the position processing circuit 130 calculates a check value according to the received position signal, thereby comparing the check value with the check value obtained in the check information. If the two match, the verification is correct, so that the position signal is judged to be the correct position signal, otherwise the position signal is incorrect. The position processing circuit 130 is further configured to update the position information when the position signal is correct, that is, replace the current correct position signal with the position signal in the original position information. At the same time, the position processing circuit 130 also clears the count value of the pulse count circuit 120 for the next position signal reading. In an embodiment, the absolute value encoder signal processing apparatus further includes a storage circuit for storing the updated position information, that is, the position information in the storage unit is the position information at the start of the counting by the pulse counting unit 120 before being updated. (ie the initial position of the absolute encoder).

The position processing circuit 130 is further configured to calculate a correct position signal according to the current position information and the count value of the pulse counting circuit 120 when determining that the position signal is incorrect, thereby updating the position information and obtaining the pulse after obtaining the correct position signal. The count of the counting circuit 120 is cleared. The position processing circuit 130 processes the position signal when the circuit is disturbed to cause a position signal error, thereby preventing the wrong position signal from having a large influence on the subsequent processing device and improving the anti-interference ability of the system. Specifically, the formula for the position processing circuit 130 to calculate the correct position signal is as follows:

Among them, P _now represents the correct position signal, P _old is the current position signal, which can be directly read from the position information, K is the count value, P _A is the absolute value of the position signal change after one rotation of the encoder, K _A is the amount of change in the count value of the pulse counting circuit after one revolution of the absolute value encoder. In an embodiment, it may be determined first whether the count value K of the pulse counting circuit 120 is zero. If it is zero, it indicates that the position of the absolute value encoder has not changed, and the position information is not updated. When the count value K is greater than zero, the correct position signal is obtained by the above formula. In the present embodiment, the amount of change P _A of the position signal of the absolute value encoder is 65536, and the amount of change K _A of the count value of the pulse counting circuit 120 after one rotation is 8192. Therefore, the formula (1) is:

After the above processing, it is possible to avoid the occurrence of a sudden change in the position signal when the verification information is incorrect, thereby improving the reliability of the system.

The above-mentioned absolute value encoder signal processing device can realize the processing of the position signal output by the absolute value encoder through the reading circuit 110, the pulse counting circuit 120 and the position processing circuit 130, and the processing process does not require the use of a special FPGA chip, and the production cost Lower. Moreover, the above device may calculate a correct position signal according to the count value of the pulse counting circuit 120 and the current position information when the data verification fails (ie, the verification information is incorrect), thereby avoiding a sudden change of the position signal when the verification fails. Improve the reliability of the system.

2 is a structural block diagram of an absolute value encoder signal processing apparatus in another embodiment, which includes an interface circuit 212, an interface driving circuit 214, a pulse counting circuit 220, a position processing circuit 230, and an analog processing circuit 240, and includes a conversion. Control circuit 255, analog quantity generating circuit 260, output circuit 265, sample verifying circuit 270, and communication circuit 275. The interface circuit 212, the interface driving circuit 214, the pulse counting circuit 220, the position processing circuit 230, and the analog processing circuit 240 have been described in detail in the foregoing embodiments, and are not described herein.

T为转换后的角度信号。位置处理电路230还用于根据该角度信号T生成两路正交的正弦信号瞬时值(一路为C相，一路为D相)，计算公式如下：In this embodiment, the position processing circuit 230 is further configured to convert the calculated position signal into an angle signal, and the conversion formula is:

T is the converted angle signal. The position processing circuit 230 is further configured to generate two orthogonal sinusoidal signal instantaneous values according to the angle signal T (one phase is C phase and one channel is D phase), and the calculation formula is as follows:

C=sinT, D=cosT;

Where C is the instantaneous value of the first sinusoidal signal and D is the instantaneous value of the second sinusoidal signal.

The period in which the two orthogonal sinusoidal signals generated by the position processing circuit 230 change is matched with the period in which the absolute encoder rotates one revolution. Since the instantaneous value of the sinusoidal signal generated by the position processing circuit 230 is a digital signal, it needs to be converted into an analog quantity and then output.

The conversion control circuit 255 is coupled to the position processing circuit 230 for sinusoidal according to two orthogonal directions The instantaneous value of the signal generates an analog control signal. The analog quantity generating circuit 260 is connected to the conversion control circuit 255 for outputting the position signal into an analog quantity signal according to the analog quantity control signal output from the conversion control circuit 255. In the present embodiment, the analog quantity generating circuit 260 is a PWM pulse width modulation circuit. Therefore, the analog control signal is used to adjust the duty cycle of the pulse signal to control the output analog signal. Specifically, the analog control signal can be calculated according to the following formula:

Wherein, when the duty ratio is 0, the corresponding C and D phases are negative maximum values; when the duty ratio is 50%, the corresponding C and D phases are zero values; when the duty ratio is 100%, the corresponding C and D phases are positive. Maximum value.

Through the above circuit, the absolute value position signal can be converted into two analog signals of the actual position, and then outputted to the subsequent processing device for further signal processing through the output circuit 265, without using a dedicated bus to realize data transmission, The requirements for subsequent processing equipment are reduced, and the compatibility is good. In an embodiment, output circuit 265 is a DA interface.

In this embodiment, the absolute value encoder signal processing device also performs sampling and verification on the output analog signal to ensure the accuracy of the output. The sample verifying circuit 270 is connected to the output of the analog quantity generating circuit 260 and the output of the output circuit 265. The sample verifying circuit 270 is configured to sample the signal at the output of the output circuit 265, and compare the sampled value with the analog signal generated by the analog quantity generating circuit 260 to determine whether the two are the same. It can be understood that when the deviation of the two is within the error tolerance range, the two can be considered to be the same. When the sampling and verification circuit 270 determines that the sampling value is different from the analog quantity signal generated by the analog quantity generating circuit 260, the error information is output, the circuit after the analog quantity generating circuit 260 is prompted to have a problem, and the error information is saved. The communication circuit 275 is coupled to the sample verification circuit 270 for outputting error information to subsequent processing devices. By sampling and verifying the output analog signal, the accuracy of the output can be improved, and the reliability of the system can be further improved. In an embodiment, the communication circuit 275 is also coupled to the position processing circuit 230 for use in the school The condition of the verification information is sent to the subsequent processing device so that the subsequent processing device knows the operation of the absolute value encoder.

In an embodiment, the interface driving circuit 214, the pulse counting circuit 220, the position processing circuit 230, the conversion control circuit 255, the analog quantity generating circuit 260, the sampling and verifying circuit 270, and the communication circuit 275 are all integrated in a digital signal processing (Digital In the Signal Processing (DSP) chip, the FPGA chip is replaced to realize the processing of the position signal output by the absolute encoder, which reduces the production cost and improves the integration of the device.

3 is a flow chart of an absolute value encoder signal processing method in an embodiment, including the following steps:

S310, reading the position signal output by the absolute encoder and the verification information.

The position signal and the verification information are read from the DATA+, DATA-, CLK+, and CLK- terminals of the absolute encoder.

S320. Determine, according to the verification information, whether the location signal is correct.

The check code is calculated according to the read position signal, and it is judged whether the calculated check code is consistent with the check code in the check information, and if they match, the position signal is correct. Conversely, if the check codes are inconsistent, the verification fails and the position signal is incorrect. If the position signal is correct, step S340 is directly performed; otherwise, step S330 and subsequent steps are performed.

S330, calculating a correct position signal according to the current position information and the count value of the pulse counting circuit.

The formula for calculating the correct position signal is as follows:

Among them, P _now represents the correct position signal, P _old is the current position signal, which can be directly read from the position information in the position processing circuit, K is the count value, and P _A is the position signal after the encoder rotates for one week. The amount of change, K _{A ,} is the amount of change in the count value of the pulse counting circuit after one revolution of the absolute value encoder. In the present embodiment, the amount of change P _A of the position signal of the absolute value encoder is 65536, and the amount of change K _A of the count value of the pulse counting circuit 120 after one rotation is 8192. Therefore, the above formula translates to:

After the above processing, it is possible to avoid the occurrence of a sudden change in the position signal when the verification information is incorrect, thereby improving the reliability of the system.

S340, updating the position information and clearing the count value of the pulse counting circuit.

After determining that the position signal is correct or calculating the correct position signal, the position information is updated, that is, the correct position signal is replaced with the original position signal in the position information, and the count value of the pulse counting circuit is cleared to facilitate the next time. Processing of position signals. In this embodiment, the updated location information is also stored after the location information is updated.

The above-mentioned absolute value encoder signal processing method does not require a special FPGA chip, and the production cost is low. Moreover, when the data verification fails (ie, the verification information is wrong), the correct position signal is calculated according to the count value of the pulse counting circuit and the current position information, thereby avoiding a situation where the position signal is abrupt when the verification fails, and the system is improved. reliability.

In an embodiment, the above-mentioned absolute value encoding encoder signal processing method further includes steps S350-390, as shown in FIG.

S350. Convert the calculated position signal into an angle signal and generate two orthogonal sinusoidal signal instantaneous values according to the angle signal.

T即为转换后的角度信号；P_A为绝对值编码器旋转一周后位置信号的变化量。两路正交的正弦信号瞬时值(一路为C相，一路为D相)，计算公式如下：C＝sinT，D＝cosT。其中，C为第一正弦信号瞬时值，D为第二正弦信号瞬时值。The calculation formula for the conversion process is:

T is the converted angle signal; P _A is the amount of change in the position signal after one revolution of the absolute encoder. The instantaneous value of the two orthogonal sinusoidal signals (one for the C phase and one for the D phase) is calculated as follows: C = sinT, D = cosT. Where C is the instantaneous value of the first sinusoidal signal and D is the instantaneous value of the second sinusoidal signal.

S360: Generate an analog quantity control signal according to the generated two orthogonal sinusoidal signal instantaneous values.

In this embodiment, the digital sinusoidal signal value is converted to the analog signal by the PWM pulse width modulation circuit, so the analog control signal is used to control the pulse outputted by the PWM pulse width modulation circuit (analog output circuit). The duty cycle of the signal. Specifically, analog control The signal can be calculated according to the following formula:

Wherein, when the duty ratio is 0, the corresponding C and D phases are negative maximum values; when the duty ratio is 50%, the corresponding C and D phases are zero values; when the duty ratio is 100%, the corresponding C and D phases are positive. Maximum value.

By converting the absolute value position signal into two analog signals of the actual position of the reaction, it can be directly output to the subsequent processing device for further signal processing without using a dedicated bus to realize data transmission, thereby reducing the requirements for subsequent processing equipment. The compatibility of the device is good.

S370: Generate an analog signal according to the analog quantity control signal, and output it to the subsequent processing device through the output circuit.

The PWM pulse width modulation circuit adjusts the duty ratio of the output signal under the control of the analog control signal so that the output analog signal can reflect the actual position of the absolute value encoder.

S380: Detect a signal at an output end of the output circuit and determine whether the signal at the output of the output circuit is the same as the generated analog signal.

By judging whether the signal outputted by the output circuit and the generated analog signal are the same, it is determined whether there is a problem in the subsequent processing circuit such as the output circuit of the analog signal, thereby ensuring the accuracy of the output signal and improving the reliability of the system. If the two are the same, the operation is ended without any operation; if not, it indicates that there may be a problem with the subsequent circuit, and step S390 is performed.

S390, outputting error information.

The error information is output to the subsequent processing device, so that the subsequent processing device knows the operation of the absolute value encoder.

The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.

The above described embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed. It is not to be construed as limiting the scope of the invention patent. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (19)

An absolute value encoder signal processing apparatus for processing a position signal output by an absolute value encoder, comprising: a reading circuit for connecting to the absolute value encoder and acquiring a position signal output by the absolute value encoder and verification information; a pulse counting circuit for connecting to the absolute value encoder and performing pulse counting according to a waveform signal output by the absolute value encoder; a position processing circuit, configured to be connected to the read circuit and the pulse counting circuit, configured to determine whether the position signal is correct according to the check information; and the position processing circuit is further configured to update when the position signal is correct Positioning information and clearing the count value of the pulse counting circuit; the position processing circuit is further configured to calculate a correct position signal according to the current position information and the count value of the pulse counting circuit when the position signal is wrong The position information is then updated and the count value of the pulse counting circuit is cleared. The absolute value encoder signal processing apparatus according to claim 1, wherein the position processing circuit calculates a correct position signal based on the current position information and the count value of the pulse counting circuit:

P _now is the correct position signal, P _old is the current position signal, K is the count value, P _A is the change amount of the position signal after the absolute value encoder rotates one week, and K _A is the absolute value encoder rotation one week. The amount of change in the count value of the pulse counting circuit is described later. The absolute value encoder signal processing apparatus according to claim 2, wherein the signal processing circuit is further configured to convert the correct position signal into an angle signal and generate two orthogonal sinusoidal signals according to the angle signal. Instantaneous value The formula for converting the correct position signal to an angle signal is

Calculating the instantaneous value of the two orthogonal sinusoidal signals according to the angle signal is C=sin T, D=cos T; Where C is the instantaneous value of the first sinusoidal signal, D is the instantaneous value of the second sinusoidal signal; T is the angular signal. The apparatus for processing an absolute value encoder according to claim 1, further comprising: a conversion control circuit coupled to the position processing circuit for generating an analog control signal based on the correct position signal; And an analog quantity generating circuit connected to the conversion control circuit, configured to convert the correct position signal into an analog quantity signal according to the analog quantity control signal, and output the signal. The absolute value encoder signal processing apparatus according to claim 4, wherein said analog quantity generating circuit is a pulse width modulation circuit; said analog quantity control signal is for adjusting a pulse signal output by said pulse width modulation circuit Duty cycle. The apparatus for processing an absolute value encoder according to claim 4, further comprising: An output circuit, coupled to the analog quantity generating circuit, for outputting the analog quantity signal to a subsequent processing device; a sampling and verifying circuit, connected to an output end of the analog quantity generating circuit and an output end of the output circuit, for comparing a signal of the output end of the output circuit with a signal of an output end of the analog quantity generating circuit, and determining two Whether the same is the same, and the error message is output when the two are different. The absolute value encoder signal processing apparatus according to claim 6, further comprising a communication circuit coupled to said sampling verification circuit for outputting said error information to a subsequent processing device. The absolute value encoder signal processing apparatus according to claim 7, wherein said communication circuit is further connected to said position processing circuit for outputting said position information to a subsequent processing device. The absolute value encoder signal processing apparatus according to claim 1, wherein The read circuit, the pulse count circuit, and the position processing circuit are integrated in a digital processing chip. The absolute value encoder signal processing apparatus according to claim 1, wherein said reading circuit comprises a reading interface and an interface driving circuit; said reading interface is for connecting to said absolute value encoder, and Connected to the interface driving circuit; the interface driving circuit is also connected to the position processing circuit. The absolute value encoder signal processing apparatus according to claim 10, wherein said read interface is a serial peripheral interface. The absolute value encoder signal processing apparatus according to claim 1, further comprising a storage circuit coupled to said position processing circuit for storing said position information. An absolute encoder signal processing method for processing a position signal output by an absolute encoder includes the following steps: Reading the position signal output by the absolute value encoder and the verification information; Determining, according to the verification information, whether the location signal is correct; If yes, updating the location information and clearing the count value of the pulse counting circuit; If not, the position information is updated and the count value of the pulse counting circuit is cleared after the correct position signal is calculated based on the current position information and the count value of the pulse counting circuit. The absolute value encoder signal processing method according to claim 13, wherein the step of updating the position information and clearing the count value of the pulse counting circuit further comprises the steps of: Generating an analog control signal based on the correct position signal; Generating an analog quantity signal according to the analog quantity control signal, and outputting to the subsequent processing device through the output circuit; Detecting a signal at an output of the output circuit and determining whether a signal at an output of the output circuit is the same as a generated analog signal; If not, the error message is output. The absolute value encoder signal processing method according to claim 14, wherein The step of generating an analog quantity control signal according to the correct position signal specifically includes: Converting the calculated position signal into an angle signal and generating two orthogonal sinusoidal signal instantaneous values according to the angle signal; An analog control signal is generated based on the generated two orthogonal sinusoidal signal instantaneous values. The absolute value encoder signal processing method according to claim 14, wherein in the step of detecting a signal at the output end of the output circuit and determining whether the signal at the output of the output circuit is identical to the generated analog signal, If the signal output from the output circuit is the same as the generated analog signal, the operation ends. The absolute value encoder signal processing method according to claim 13, wherein the step of updating the position information and clearing the count value of the pulse counting circuit further comprises the steps of: Store updated location information. The absolute value encoder signal processing method according to claim 13, wherein the step of determining whether the position signal is correct according to the verification information is specifically: Calculating a check code according to the read position signal; Determining whether the calculated check code is consistent with the check code in the check information; if yes, the position signal is correct, and if not, the position signal is incorrect. The absolute value encoder signal processing method according to claim 13, wherein the calculation formula for calculating the correct position signal based on the current position information and the count value of the pulse counting circuit is:

P _now is the correct position signal, P _old is the current position signal, K is the count value, P _A is the change amount of the position signal after the absolute value encoder rotates one week, and K _A is the absolute value encoder rotation one week. The amount of change in the count value of the pulse counting circuit is described later.

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