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WO2016145567A1 - Procédé d'entrelacement de données et entrelaceur - Google Patents

Procédé d'entrelacement de données et entrelaceur Download PDF

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Publication number
WO2016145567A1
WO2016145567A1 PCT/CN2015/074194 CN2015074194W WO2016145567A1 WO 2016145567 A1 WO2016145567 A1 WO 2016145567A1 CN 2015074194 W CN2015074194 W CN 2015074194W WO 2016145567 A1 WO2016145567 A1 WO 2016145567A1
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WIPO (PCT)
Prior art keywords
data
address
interleaving
subcarriers
data blocks
Prior art date
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PCT/CN2015/074194
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English (en)
Chinese (zh)
Inventor
贝勒迪多·塞吉奥
蒙托里西·基多
林伟
刘乐
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2015/074194 priority Critical patent/WO2016145567A1/fr
Publication of WO2016145567A1 publication Critical patent/WO2016145567A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present invention relates to the field of wireless communications, and in particular, to a data interleaving processing method and an interleaver.
  • WLAN Wireless Local Area Networks
  • Multiple terminals access the Internet through a wireless router, and perform data interaction with the Internet.
  • the data passes through the carrier in the channel and in the terminal. Transfer between the Internet.
  • the terminal sends data to the Internet through the wireless router, the terminal interleaves the transmission data through the interleaver in the set WiFi (WIreless-Fidelity) chip, and changes the transmission order of the bits in the data to be sent.
  • the data is transmitted to the Internet in an interleaved bit order.
  • the number of subcarriers allocated to the user is a fixed number
  • WiFi The number of data bits that the interleaver of the chip can process is related to the number of allocated subcarriers.
  • the interleaver can also process the interleaving operation. The number of bits of data.
  • an OFDMA Orthogonal Frequency Division Multiple Access
  • a conventional interleaver that can only perform interleaving operations on a fixed number of bits of data
  • it needs to be Different numbers of subcarriers are allocated to design multiple interleavers that can process different bit number data.
  • the number of subcarriers allocated to the user is often large, and a large number of interleavers need to be designed.
  • the data of different bit numbers under the number of subcarriers is separately interleaved, which greatly increases the design complexity of the interleaver.
  • an embodiment of the present invention provides a data interleaving processing method and an interleaver.
  • the technical solution is as follows:
  • an embodiment of the present invention provides a data interleaving processing method, where the method includes:
  • the step of performing interleaving processing on the multiple data blocks that are divided by the data to be interleaved, and obtaining the interleaving address of the multiple data blocks includes:
  • the buffering address and the subcarrier of the data in each data block according to the number of the subcarriers Interleaving parameters, performing the first calculation on the cache address of the data in each data block, and obtaining the first calculation result includes:
  • ⁇ 1 (i) is the first calculation result
  • s is the subcarrier interleaving parameter
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • the greatest common divisor of s and N is 1.
  • the parameters s and N satisfy the following relationship:
  • s is greater than or equal to The smallest integer
  • the buffering address and the modulation of the data in each data block according to the number of the subcarriers a mode order, performing a second calculation on the first calculation result, and obtaining an interleave address of the data in each data block includes:
  • ⁇ 2 (i) is the interleave address
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • m is the modulation mode order.
  • the outputting the multiple data according to an interleave address of the multiple data blocks include:
  • the cache address stored in the interleave address is read in the order of the interleave address, and the read data is output.
  • an interleaver in the embodiment of the present invention, where the interleaver includes:
  • An interleaving parameter determining module configured to determine, according to a bandwidth allocated by the current wireless fidelity WiFi chip, an interleaving parameter in a current bandwidth, where the interleaving parameter includes a number of subcarriers and a modulation mode order;
  • a sequence length calculation module configured to acquire a sequence length of the current interleaving process according to the number of subcarriers and the mode of the modulation mode
  • An interleaving processing module is configured to perform interleaving processing on a plurality of data blocks divided by the data to be interleaved to obtain an interleaving address of the plurality of data blocks, and sequence length and calculation of each data block in the plurality of data blocks The resulting sequences are of the same length;
  • a data output module configured to output data in the plurality of data blocks according to an interleave address of the plurality of data blocks.
  • the interleaving processing module includes:
  • a data acquiring unit configured to acquire data in each of the plurality of data blocks
  • a data cache address obtaining unit configured to cache data in each of the data blocks for each of the data blocks, to obtain a cache address of the data in each of the data blocks;
  • a first calculating unit configured to perform a first calculation on a cache address of data in each data block according to the number of the subcarriers, a buffer address of data in each data block, and a subcarrier interleaving parameter Calculate, get the first calculation result;
  • a second calculating unit configured to perform a second calculation on the first calculation result according to the number of the subcarriers, the buffer address of the data in each of the data blocks, and the modulation mode order, to obtain each of the The interleaved address of the data in the data block.
  • the first computing unit is configured to:
  • ⁇ 1 (i) is the first calculation result
  • s is the subcarrier interleaving parameter
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • the greatest common divisor of s and N is 1.
  • the parameters s and N satisfy the following relationship:
  • s is greater than or equal to The smallest integer
  • the second computing unit is configured to:
  • ⁇ 2 (i) is the interleave address
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • m is the modulation mode order.
  • the data output module is configured to:
  • the cache address stored in the interleave address is read in the order of the interleave address, and the read data is output.
  • the data interleaving processing method and the interleaver determine the number of subcarriers and the mode of the modulation mode as the interleaving parameters of the data to be interleaved according to the bandwidth allocated by the current WiFi chip, and according to the determined number and modulation of subcarriers.
  • the mode order obtains the sequence length of the current interleaving process, and then Dividing the data to be interleaved into a plurality of data blocks according to the obtained sequence length, and then performing interleaving processing on the plurality of data blocks to obtain an interleaving address of the plurality of data blocks, thereby determining the sub-allocated sub-bands in the OFDMA system.
  • the number of carriers is used to obtain the sequence length of the current interleaving process according to the determined number of subcarriers, so that data of different sequence lengths can be interleaved according to the determined number of subcarriers, without depending on the number of allocated subcarriers.
  • Multiple interleavers can be designed to process different bit number data, which reduces the complexity of the interleaver design and is flexible and convenient to use.
  • FIG. 1 is a schematic structural diagram of an implementation environment involved in a data interleaving processing method according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a data interleaving processing method according to Embodiment 1 of the present invention
  • FIG. 3 is a flowchart of a data interleaving processing method according to Embodiment 2 of the present invention.
  • FIG. 4 is a schematic diagram of a first calculation in a data interleaving processing method according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram of performing the first calculation when 16QAM modulation is used in the data interleaving processing method according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic diagram of performing a second calculation when 16QAM modulation is used in the data interleaving processing method according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic structural diagram of an interleaver according to Embodiment 3 of the present invention.
  • FIG. 8 is a schematic structural diagram of an interleaver according to Embodiment 4 of the present invention.
  • FIG. 1 is a schematic structural diagram of an implementation environment involved in a data interleaving processing method according to an embodiment of the present invention.
  • the system includes: a plurality of terminals, a wireless router 10, and the Internet.
  • the plurality of terminals respectively perform data interaction with the Internet through the wireless router 10 through the set WiFi chip, and when any terminal wants to transfer a file stored in the local hard disk to the Internet for sharing, in order to avoid the string of the file
  • the bit in the terminal is in error.
  • the WiFi chip in the terminal interleaves the data of the file through the set interleaver, that is, the interleaver buffers the data, and then maps the buffer address of the file data to an interlace according to the interleaving rule. At the address, the interleaving of the file is completed. After the interleave address is obtained, the interleaver outputs the data of the file according to the interleave address.
  • the terminal may be any server or mobile terminal that can be connected to the Internet through a wireless router, or any other device that can be connected to the Internet through a wireless router, and details are not described herein again.
  • the embodiment provides a data interleaving processing method, where the method process includes:
  • Step 100 According to the bandwidth allocated by the current WiFi chip, the interleaver of the WiFi chip determines the interleaving parameter in the current bandwidth, and the interleaving parameter includes the number of subcarriers and the mode of the modulation mode.
  • the number of subcarriers and the mode of the modulation mode are obtained by the WiFi chip from the WiFi base station.
  • the WiFi chip transmits the obtained number of subcarriers and the modulation mode order to the interleaver.
  • the subcarrier refers to a radio wave having a specific frequency that carries one of a plurality of modulated, parallel transmitted data.
  • the modulation mode order is related to the corresponding modulation mode.
  • the modulation mode is 16QAM (Quadrature Amplitude Modulation)
  • Step 101 The interleaver of the WiFi chip acquires the sequence length of the current interleaving process according to the number of subcarriers and the modulation mode order.
  • the sequence length is obtained by multiplying the number of subcarriers and the order of the modulation mode.
  • the sequence length acquired by the interleaver of the WiFi chip is 96.
  • the sequence length refers to the sequence length of the bit sequence that the interleaver can interleave at one time, and the sequence length is the same as the number of bits included in the bit sequence. For example, if the number of bits contained in the bit sequence is 96, then the sequence length is 96.
  • Step 102 The interleaver of the WiFi chip performs interleaving processing on the plurality of data blocks divided by the data to be interleaved to obtain an interleave address of the plurality of data blocks, and the sequence length of each data block is the same as the calculated sequence length.
  • one data block includes a bit sequence.
  • the WiFi chip Before the interleaver performs interleaving processing on the interleaved data, the WiFi chip divides the data to be interleaved according to the number of subcarriers and the mode of the modulation mode, and divides the data to be interleaved into a plurality of data blocks. During the interleaving process, the WiFi chip inputs a plurality of data blocks into the interleaver one by one, thereby interleaving the plurality of data blocks block by block in the interleaver.
  • the interleave address is an output address sequence sequence corresponding to the bit sequence buffer address sequence after the input data bit sequence is interleaved.
  • Step 103 Output data in a plurality of data blocks according to an interleave address of the plurality of data blocks.
  • the data interleaving processing method provided in this embodiment determines the number of subcarriers and the mode of the modulation mode as the interleaving parameters of the data to be interleaved according to the bandwidth allocated by the current WiFi chip, and according to the determined number of subcarriers.
  • the modulation mode order obtains the sequence length of the current interleaving process, and then divides the data to be interleaved into a plurality of data blocks according to the obtained sequence length, and then performs interleaving processing on the plurality of data blocks to obtain an interleaving address of the plurality of data blocks, thereby
  • the number of subcarriers allocated in the current bandwidth is determined, and then the sequence length of the current interleaving process is obtained according to the determined number of subcarriers, so that data of different sequence lengths can be performed according to the determined number of subcarriers. Interlace processing.
  • this embodiment provides a data interleaving processing method, where the method process includes:
  • Step 200 According to the bandwidth allocated by the current WiFi chip, the interleaver of the WiFi chip determines the interleaving parameter in the current bandwidth, and the interleaving parameter includes the number of subcarriers and the mode of the modulation mode.
  • the currently allocated bandwidth refers to the current working bandwidth of the WiFi chip in the OFDM system or the OFDMA system, and the specific size of the working bandwidth is specified by the upper layer system.
  • T represents a time length of one OFDM symbol.
  • the length of time of one OFDM symbol refers to the duration of one OFDM symbol.
  • the number of subcarriers included in one OFDM symbol is determined by the system. For example, in a WLAN, 64 subcarriers may be included in one OFDM symbol, and the subcarriers have different frequencies.
  • Step 201 The interleaver of the WiFi chip acquires the sequence length of the current interleaving process according to the number of subcarriers and the modulation mode order.
  • the WiFi base station may obtain the sequence length of the current interleaving process of the interleaver according to the product of the number of subcarriers and the modulation mode order. After obtaining the sequence length of the current interleaving process of the interleaver, the obtained sequence length is transmitted to the interleaver. The interleaver obtains the sequence length of the current interleaving process.
  • the data obtained by the interleaver to obtain the sequence length that can be interleaved may be pre-stored in a sequence length table preset by the WiFi chip.
  • the WiFi chip Before the interleaver interleaves the bit sequence, the WiFi chip can also directly select a data from the sequence length table to transmit to the interleaver without determining the sequence length that the current interleaver can interleave without calculation.
  • Step 202 The interleaver of the WiFi chip acquires data in each of the plurality of data blocks.
  • the interleaver obtains data of one of the plurality of data blocks by performing interleaving processing on the plurality of data blocks, interleaving the data in the obtained data block, and completing the interleaving of the data block. After processing, the next data block is processed until multiple data are divided by the data to be interleaved The data blocks are all interleaved.
  • the number of bits to be interleaved is 192, and the length of the sequence that the current interleaver can interleave is 96.
  • the WiFi chip makes the first 96 of the data to be interleaved according to the transmission order of the data to be interleaved.
  • the bit forms a first data block
  • the last 96 bits of the data to be interleaved form a second data block, so that when the interleaver performs the interleaving process, the data of the first data block is first obtained for interleaving processing, and the first data block is interleaved.
  • the data of the second data block is acquired again for interleaving processing.
  • Step 203 For each data block, the interleaver of the WiFi chip buffers the data in each data block to obtain a cache address of the data in each data block.
  • the interleaver of the WiFi chip buffers the data in each data block according to the input order of the data in each data block, and after the data in each data block is buffered, the buffer of the data in each data block is obtained. address.
  • the cache address is an address that the interleaver caches data in each data block.
  • the data and the cache address are in one-to-one correspondence, so as to ensure the order of the data input to the interleaver is adjusted.
  • Step 204 The interleaver of the WiFi chip performs the first calculation on the buffer address of the data in each data block according to the number of subcarriers, the buffer address of the data in each data block, and the subcarrier interleaving parameter, to obtain a first calculation result.
  • the first calculation result may be calculated according to formula one:
  • ⁇ 1 (i) is the first calculation result
  • s is the subcarrier interleaving parameter
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • the greatest common divisor of s and N is 1.
  • the principle of the first calculation is shown in FIG. 4.
  • the first calculation is to first perform the first modulo operation on the buffer address i of the data in each data block for the number N of subcarriers, so that the buffer address in the data is obtained.
  • the data of distance N can be carried by the same subcarrier, and then the result of the first modulo operation is multiplied by s in order to make the data buffered in the adjacent cache address have a sufficiently large separation distance between the outputs.
  • the spacing between the data cached in the adjacent cache addresses is determined by the size of s. The larger the s, the larger the interval between the cached data in the adjacent cache addresses.
  • the buffer address in the data can be made by a simple modulo calculation.
  • the data of distance N can be carried by the same subcarrier, and the data buffered in the adjacent cache address has a sufficiently large separation distance between the outputs, which reduces the complexity of designing the interleaver.
  • the number N of subcarriers carrying data received by the interleaver is 24, and the modulation mode is 16QAM
  • the number of bits of data indicating that the interleaver can perform interleaving processing is 96, and s must satisfy the maximum convention of N and N.
  • the first calculation result ⁇ 1 can be obtained ( i)
  • the first calculated result ⁇ 1 (i) is obtained as shown in Table 2.
  • the data of 4 bits carried by each subcarrier is represented by 4 small circles in each broken line frame in FIG.
  • s may be any natural number that satisfies the greatest common divisor of the condition s and N is 1.
  • N the value of s needs to be 1 and the greatest common divisor of 24 is 1, then the value of s may be 5 7,11, etc., no more details here.
  • s is greater than or equal to The smallest integer; can reduce the complexity of designing the interleaver.
  • Ns can use the same s.
  • the greatest common divisor of 5, 23, and 24 is 1, so when N takes 23 or 24, s can take 5, which can further reduce the design of the interleaver. The complexity.
  • the subcarriers can carry the data according to the cache order of the data buffer in the interleaver: eg: the first sub
  • the carrier is used to carry the data buffered in the 0th, 1st, 2nd, and 3rd cache addresses recorded in Table 1.
  • the second subcarrier is used to carry the 4th record recorded in Table 1. , the data cached in the 5th, 6th, and 7th cache addresses.
  • the interleaver After the first calculation result calculated by the formula 1, the interleaver enables the data in the data buffer address distance N to be carried by the same subcarrier.
  • the number of each column in Table 2 represents The cache address of the data carried by the same subcarrier.
  • the first column is the cache address of the data carried by the first subcarrier
  • the fourth column is the cache address of the data carried by the fourth subcarrier.
  • the data interleaving processing method further includes the following steps to perform a second calculation on the first calculation result.
  • Step 205 The interleaver of the WiFi chip performs a second calculation on the first calculation result according to the number of subcarriers, the buffer address of the data in each data block, and the modulation mode order, to obtain an interleave address of the data in each data block. .
  • the purpose of the second calculation is to determine the location of each data carried by the same subcarrier.
  • the interleave address is calculated:
  • ⁇ 2 (i) is the interleave address
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • m is the modulation mode order.
  • the schematic diagram of the second calculation using the modulation mode of 16QAM is as shown in FIG. 6.
  • the modulation mode is 16QAM modulation
  • the number of bits of the data is 96
  • each subcarrier can be obtained.
  • Carry 4 bits of data The data of 4 bits carried by each subcarrier in Fig. 6 is represented by 4 small circles in each broken line frame in Fig. 6.
  • the second calculation is an interleave address ⁇ 2 (i) for determining data whose buffer address is i.
  • step 205 by simple modulo calculation, it can be determined that it is accepted by the same subcarrier.
  • the location of each data carried reduces the complexity of designing the interleaver.
  • the first calculation result recorded in Table 2 is adjusted according to Formula 2 to obtain an interleave address, and the obtained interleave address is as shown in Table 3.
  • the data cached in the fifth, the 29th, the 53rd, and the 77th cache addresses carried in the second subcarrier recorded in Table 2 is further illustrated as an example, if not in the second table.
  • a calculation result is performed for the second calculation, then after the data is modulated, the 4 bits carried in the second subcarrier are the 5th, 29th, 53rd, and the 5th records according to the second column in Table 2.
  • the order of the data buffered in the 77 cache addresses is carried by the second subcarrier.
  • the interleaver can determine the position of each data carried by the same subcarrier according to the interleaved address calculated in the second time, and the determined position of each data is recorded in Table 3. .
  • Table 3 after the data is modulated, the 4 bits carried in the second subcarrier: according to the 77th, 53rd, 29th, 5th records recorded in the second column of Table 3. The order of the data buffered in the cache address is carried by the second subcarrier.
  • the second calculation is used to adjust the order of the bits carried in each subcarrier, thereby obtaining the final interleaved address as the interleaving result.
  • the length of the interleaver is N ⁇ m, N is the number of subcarriers carrying data, and m is the modulation mode order, when the modulation mode is determined, The length of the sequence that the interleaver can process at one time is determined by the number of subcarriers.
  • the interleaver can obtain the interleave address of the bit sequence not only by calculation, but also pre-store an interleave address table having different sequence lengths in the WiFi chip, and the output address corresponding to the bit sequence buffer address sequence is recorded in the interleave address table. Sequence sequence.
  • the interleaver obtains an interleave address table corresponding to the sequence length according to the sequence length of the current to-be-interleaved data before interleaving, and performs an interleaving operation on the bit sequence through the obtained interleave address table.
  • Step 206 The interleaver of the WiFi chip outputs data according to the obtained interleave address.
  • the interleaver of the WiFi chip reads the cache address stored in the interleave address, and outputs the read data.
  • the output order of the data after the position replacement in the interleave address is from the cache address recorded in the first column of Table 3, and is read until the cache address of the record of the twenty-fourth column in Table 3. order.
  • the data interleaving processing method provided in this embodiment determines the number of subcarriers and the mode of the modulation mode as the interleaving parameters of the data to be interleaved according to the bandwidth allocated by the current WiFi chip, and according to the determined number of subcarriers.
  • the modulation mode order obtains the sequence length of the current interleaving process, and then divides the data to be interleaved into a plurality of data blocks according to the obtained sequence length, and then performs interleaving processing on the plurality of data blocks to obtain an interleaving address of the plurality of data blocks, thereby
  • the number of subcarriers allocated in the current bandwidth is determined, and then the sequence length of the current interleaving process is obtained according to the determined number of subcarriers, so that data of different sequence lengths can be performed according to the determined number of subcarriers.
  • the interleaving process does not need to separately design multiple interleavers that can process different bit number data according to the number of allocated subcarriers, thereby reducing the complexity of the interleaver design and being flexible and convenient to use.
  • the embodiment provides an interleaver, and the interleaver includes:
  • the interleaving parameter determining module 300 the sequence length calculating module 301, the interleaving processing module 302, and the data output module 303.
  • the interleaving parameter determining module 300 is configured to determine, according to the bandwidth allocated by the current WiFi chip, an interleaving parameter in the current bandwidth, where the interleaving parameter includes the number of subcarriers and the mode of the modulation mode; the sequence length calculating module 301 and the interleaving parameter determining module.
  • the 300-phase connection is used to obtain the sequence length of the current interleaving process according to the number of subcarriers and the modulation mode order;
  • the interleave processing module 302 is connected to the sequence length calculation module 301, and is configured to divide multiple data divided by the data to be interleaved.
  • the data block is interleaved to obtain an interleave address of the plurality of data blocks.
  • the sequence length of each data block is the same as the calculated sequence length; the data output module 303 is connected to the interleave processing module 302. And outputting data in the plurality of data blocks according to the interleave address of the plurality of data blocks.
  • the interleaver determines the number of subcarriers and the mode of the modulation mode as the interleaving parameters of the data to be interleaved according to the bandwidth allocated by the current WiFi chip, and according to the determined number of subcarriers and the modulation mode.
  • the order obtains the sequence length of the current interleaving process, and then divides the data to be interleaved into a plurality of data blocks according to the obtained sequence length, and then performs interleaving processing on the plurality of data blocks.
  • the embodiment provides an interleaver, and the interleaver includes:
  • the interleaving parameter determining module 400 is configured to determine an interleaving parameter in the current bandwidth according to the bandwidth allocated by the current WiFi chip, where the interleaving parameter includes the number of subcarriers and the mode of the modulation mode; the sequence length calculating module 401 and the interleaving parameter determining module.
  • the 400-phase connection is used to obtain the sequence length of the current interleaving process according to the number of subcarriers and the modulation mode order.
  • the interleave processing module 402 is connected to the sequence length calculation module 401, and is configured to divide multiple data divided by the data to be interleaved.
  • the data block is interleaved to obtain an interleaving address of the plurality of data blocks.
  • the sequence length of each data block is the same as the calculated sequence length; the data output module 403 is connected to the interleave processing module 402. And outputting data in the plurality of data blocks according to the interleave address of the plurality of data blocks.
  • the interleaving processing module 402 includes:
  • a data obtaining unit 4021 configured to acquire data in each of the plurality of data blocks
  • the data cache address obtaining unit 4022 is connected to the data obtaining unit 4021, and is configured to buffer data in each data block for each data block to obtain a cache address of data in each data block;
  • the first calculating unit 4023 is connected to the data buffer address obtaining unit 4022, and is configured to first perform a buffer address of data in each data block according to the number of subcarriers, the buffer address of data in each data block, and the subcarrier interleaving parameter. Sub-calculation, the first calculation result is obtained;
  • the second calculating unit 4024 is connected to the first calculating unit 4023, and configured to perform a second calculation on the first calculation result according to the number of subcarriers, the buffer address of the data in each data block, and the modulation mode order, to obtain each The interleaved address of the data in the data block.
  • the first calculating unit 4023 is configured to:
  • ⁇ 1 (i) is the first calculation result
  • s is the subcarrier interleaving parameter
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • the greatest common divisor of s and N is 1.
  • s is greater than or equal to The smallest integer
  • the second calculating unit 4024 is configured to:
  • ⁇ 2 (i) is the interleave address
  • i is the buffer address of the data in each data block
  • N is the number of subcarriers
  • m is the modulation mode order.
  • the data output module 403 is configured to:
  • the cache address stored in the interleave address is read in the order of the interleave address, and the read data is output.
  • the interleaver determines the number of subcarriers and the mode of the modulation mode as the interleaving parameters of the data to be interleaved according to the bandwidth allocated by the current WiFi chip, and according to the determined number of subcarriers and the modulation mode.
  • the order obtains the sequence length of the current interleaving process, and then divides the data to be interleaved into a plurality of data blocks according to the obtained sequence length, and then performs interleaving processing on the plurality of data blocks to obtain an interleaving address of the plurality of data blocks, thereby
  • the number of subcarriers allocated in the current bandwidth is determined, and then the sequence length of the current interleaving process is obtained according to the determined number of subcarriers, so that data of different sequence lengths can be interleaved according to the determined number of subcarriers.
  • the interleaver provided by the foregoing embodiment triggers the data interleaving service
  • only the division of the foregoing functional modules is illustrated.
  • the function allocation may be completed by different functional modules as needed.
  • the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.
  • the embodiment of the interleaver and the data interleaving processing method provided by the foregoing embodiments are in the same concept, and the specific implementation process is described in detail in the method embodiment, and details are not described herein again.
  • the completion of the hardware may also be performed by a program to instruct related hardware.
  • the program may be stored in a computer readable storage medium.
  • the storage medium mentioned above may be a read only memory, a magnetic disk or an optical disk.

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La présente invention concerne un procédé d'entrelacement de données et un entrelaceur, qui se rapportent au domaine des communications sans fil. Le procédé d'entrelacement de données consiste : selon la bande passante attribuée actuellement par une puce WiFi, à déterminer la quantité de sous-porteuses et l'ordre de mode de modulation comme paramètres d'entrelacement des données à entrelacer, à obtenir, selon la quantité de sous-porteuses et l'ordre de mode de modulation déterminés, une longueur de séquence d'entrelacement courant ; à diviser, selon la longueur de séquence obtenue par calcul, les données à entrelacer en de multiples blocs de données, et à entrelacer les multiples blocs de données pour obtenir des adresses d'entrelacement des blocs de données. Ainsi, dans le système OFDMA, des données ayant une longueur de séquence différente peuvent être entrelacées selon une quantité de sous-porteuses différente déterminée par détermination de la quantité de sous-porteuses attribuée dans une bande passante courante et calcul de la longueur de séquence d'entrelacement courant selon la quantité de sous-porteuses déterminée.
PCT/CN2015/074194 2015-03-13 2015-03-13 Procédé d'entrelacement de données et entrelaceur Ceased WO2016145567A1 (fr)

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CN101984570A (zh) * 2010-10-25 2011-03-09 北京邮电大学 一种应用于mimo-ofdm系统下克服弱散射的码本选择调制方法
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CN103457894A (zh) * 2012-06-01 2013-12-18 北京数字电视国家工程实验室有限公司 一种正交频分复用系统中的交织方法
WO2014051452A1 (fr) * 2012-09-26 2014-04-03 Intel Corporation Méthode et appareil d'entrelacement pour atténuation d'interférences entre porteuses dans des systèmes de communication sans fil limités par le bruit de phase
CN104065454A (zh) * 2014-06-20 2014-09-24 江苏中兴微通信息科技有限公司 基于空间数据流数的动态符号交织和解交织方法及装置
CN104184550A (zh) * 2014-07-29 2014-12-03 江苏中兴微通信息科技有限公司 一种自适应三维度信息的符号交织和解交织方法及装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007100774A1 (fr) * 2006-02-28 2007-09-07 Atc Technologies, Llc Systèmes, procédés et émetteurs/récepteurs de communication sans fil sur des segments non contigus de spectre
CN101984570A (zh) * 2010-10-25 2011-03-09 北京邮电大学 一种应用于mimo-ofdm系统下克服弱散射的码本选择调制方法
US20130194931A1 (en) * 2012-01-27 2013-08-01 Interdigital Patent Holdings, Inc. Systems and/or methods for providing epdcch in a multiple carrier based and/or quasi-collated network
CN103457894A (zh) * 2012-06-01 2013-12-18 北京数字电视国家工程实验室有限公司 一种正交频分复用系统中的交织方法
WO2014051452A1 (fr) * 2012-09-26 2014-04-03 Intel Corporation Méthode et appareil d'entrelacement pour atténuation d'interférences entre porteuses dans des systèmes de communication sans fil limités par le bruit de phase
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