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WO2016029517A1 - Substrat de réseau de transistors en couches minces et procédé de traitement d'assombrissement de pixels associé - Google Patents

Substrat de réseau de transistors en couches minces et procédé de traitement d'assombrissement de pixels associé Download PDF

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Publication number
WO2016029517A1
WO2016029517A1 PCT/CN2014/086626 CN2014086626W WO2016029517A1 WO 2016029517 A1 WO2016029517 A1 WO 2016029517A1 CN 2014086626 W CN2014086626 W CN 2014086626W WO 2016029517 A1 WO2016029517 A1 WO 2016029517A1
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WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
pixel electrode
pixel
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/086626
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English (en)
Chinese (zh)
Inventor
高鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2016029517A1 publication Critical patent/WO2016029517A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a pixel darkening processing method thereof.
  • a conventional thin film transistor array substrate includes a plurality of pixels including a pixel electrode, a thin film transistor switch, and the like.
  • a thin film transistor switch of a part of a pixel may not be normally switched according to a scan signal. At this time, the pixel becomes a defective pixel, and the defective pixel tends to receive the data line all the time. The data signal is thus always in a bright state.
  • the presence of the defective pixel affects the display quality of the display panel.
  • An object of the present invention is to provide a thin film transistor array substrate and a pixel darkening processing method thereof, which can perform darkening processing on a part of pixels, so that a region corresponding to a dark-dotted pixel is displayed as a normally dark state. .
  • a thin film transistor array substrate comprising: at least one data line; at least one scan line; at least one common line; at least one first pixel, the first pixel comprising a first thin film transistor and a first pixel An electrode, the first thin film transistor being connected to the data line, the scan line and the first pixel electrode, the first pixel electrode being insulated from the common line; and at least one dark-dotted pixel
  • the dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-spotted pixel includes a second thin film transistor and a second pixel electrode
  • the second thin film transistor is connected to the scan line and the second pixel electrode, the second thin film transistor is disconnected from the data line, and the second pixel electrode is in common with the An insulating layer is disposed between the lines, the second pixel electrode is electrically connected to the common line; and the second thin film transistor includes a second gate and a second a second drain, an area of the first overlapping portion of the second source and the second gate is zero
  • the disconnected state is by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor and the data line To form.
  • connection line between the second thin film transistor and the data line is cut using a first laser.
  • a connection line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
  • the electrical connection state is formed by forming a recess at a predetermined position on the surface of the second pixel electrode and providing an electrical connection member in the recess;
  • the second pixel electrode and the common line are electrically connected by the electrical connection.
  • the recess is formed by irradiating the predetermined position with a second laser.
  • the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
  • the recess is formed by dropping a second etching liquid at the predetermined position.
  • a thin film transistor array substrate comprising: at least one data line; at least one scan line; at least one common line; at least one first pixel, the first pixel comprising a first thin film transistor and a first pixel An electrode, the first thin film transistor being connected to the data line, the scan line and the first pixel electrode, the first pixel electrode being insulated from the common line; and at least one dark-dotted pixel
  • the dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-spotted pixel includes a second thin film transistor and a second pixel electrode
  • the second thin film transistor is connected to the scan line and the second pixel electrode, the second thin film transistor is disconnected from the data line, and the second pixel electrode is in common with the An insulating layer is disposed between the lines, and the second pixel electrode is electrically connected to the common line.
  • the disconnected state is by cutting a connection line between the second thin film transistor and the data line to insulate the second thin film transistor and the data line To form.
  • connection line between the second thin film transistor and the data line is cut using a first laser.
  • a connection line between the second thin film transistor and the data line is cut by dropping a first etching liquid.
  • the electrical connection state is formed by forming a recess at a predetermined position on the surface of the second pixel electrode and providing an electrical connection member in the recess;
  • the second pixel electrode and the common line are electrically connected by the electrical connection.
  • the recess is formed by irradiating the predetermined position with a second laser.
  • the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode is located.
  • the recess is formed by dropping a second etching liquid at the predetermined position.
  • a pixel dark spot processing method for the above thin film transistor array substrate comprising: cutting a connection line between the second thin film transistor and the data line, so that the second thin film transistor and the a data line is insulated; a recess is formed at a predetermined position on a surface of the second pixel electrode; and an electrical connection is disposed in the recess to pass the second pixel electrode and the common line
  • the electrical connectors are electrically connected.
  • the step of cutting a connection line between the second thin film transistor and the data line includes: using the first laser to the second thin film transistor and the data The connecting line between the lines is cut.
  • the step of forming a recess at a predetermined position of a surface of the second pixel electrode includes: illuminating the predetermined position with a second laser to be at the predetermined position The cavity is formed.
  • the recess penetrates the second pixel electrode and the insulating layer in a first direction, and the first direction is perpendicular to a plane where the second pixel electrode is located direction.
  • the present invention can make the relative potential of the second pixel electrode in the dark-spotted pixel be 0, and the liquid crystal molecules corresponding to the dark-spotted pixel cannot pass the second The voltage difference conversion of the pixel electrode is deflected, and therefore, the area corresponding to the darkened pixel is displayed as a normally dark state.
  • FIG. 1 is a schematic view of a thin film transistor array substrate of the present invention
  • FIG. 2 is a schematic cross-sectional view of the A-A' of the second pixel of FIG. 1 before forming a recess;
  • FIG. 3 is a schematic cross-sectional view of the A-A' of the second pixel of FIG. 1 after forming a recess;
  • Figure 4 is a cross-sectional view showing the A-A' of the first embodiment in which the electrical connecting member is disposed in the recess of Figure 1;
  • Figure 5 is a cross-sectional view of the A-A' of the second embodiment in which the electrical connector is disposed in the recess of Figure 1;
  • FIG. 6 is an equivalent circuit diagram of a pixel subjected to dark dot processing in FIG. 1;
  • FIG. 7 is a flowchart of a method for processing a pixel dark spot of the thin film transistor array substrate of the present invention.
  • FIG. 1 is a schematic diagram of a thin film transistor array substrate of the present invention.
  • the thin film transistor array substrate of this embodiment includes at least one data line 102, at least one scan line 101, at least one common line 103, at least one first pixel, and at least one dark-dotted pixel.
  • the first pixel includes a first thin film transistor 104 and a first pixel electrode 106, and the first thin film transistor 104 is connected to the data line 102, the scan line 101, and the first pixel electrode 106.
  • the first pixel electrode 106 is insulated from the common line 103. Specifically, a first gate of the first thin film transistor 104 is connected to the scan line 101, and a first source of the first thin film transistor 104 is connected to the data line 102.
  • the first thin film transistor 104 is connected.
  • the drain is connected to the first pixel electrode 106.
  • An insulating layer 201 is disposed between the first pixel electrode 106 and the common line 103.
  • the dark-dotted pixel is formed by darkening a second pixel of the thin film transistor array substrate, and the dark-dotted pixel includes a second thin film transistor 105 and a second pixel electrode 107.
  • the second thin film transistor 105 is connected to the scan line 101 and the second pixel electrode 107. Specifically, the second gate electrode 1051 of the second thin film transistor 105 is connected to the scan line 101. The second drain electrode 1053 of the second thin film transistor 105 is connected to the second pixel electrode 107.
  • the second thin film transistor 105 is disconnected from the data line 102, and the insulating layer 201 is disposed between the second pixel electrode 107 and the common line 103, and the second pixel electrode 107 is The common line 103 is in an electrically connected state.
  • the disconnected state is performed by cutting a connection line between the second thin film transistor 105 and the data line 102 to make the second thin film transistor 105 and the data line 102 insulation is formed.
  • connection line between the second thin film transistor 105 and the data line 102 is cut by using a first laser.
  • the disconnected state may be formed by cutting the connecting wire by etching, for example, by dropping a first corrosive liquid (for example, an acidic liquid).
  • a first corrosive liquid for example, an acidic liquid.
  • FIG. 2 is a schematic cross-sectional view of the second pixel of FIG. 1 before forming the recess 110
  • FIG. 3 is the second pixel of FIG. 1 after the recess 110 is formed.
  • A-A' is a schematic cross-sectional view
  • FIG. 4 is a cross-sectional view taken along line AA' of the first embodiment in which the electrical connector 401 is disposed in the cavity 110 of FIG.
  • the electrical connection state is formed by forming the cavity 110 at a predetermined position 109 on the surface of the second pixel electrode 107, and the electrical connection is disposed in the cavity 110.
  • Piece 401 is formed.
  • the recess 110 is formed by irradiating the predetermined position 109 with a second laser.
  • the excitation of the second laser may cause a portion of the metal material/metal oxide material in the second pixel electrode 107 to be cleaved, thereby forming a An opening portion 1071; or the excitation of the second laser light may cause a portion of the metal material/metal oxide material of the common line 103 to be cleaved to form a second split portion.
  • the first split portion 1071 tends to adhere to the edge of the hole of the recess 110, and the second split portion tends to adhere to the bottom edge of the recess 110, and the first split portion
  • the second opening portion 1071 or the second opening portion may be in contact with the second pixel electrode 107 and the common line 103 at the same time, so that the second pixel electrode 107 and the common line 103 are electrically connected.
  • the event that some of the first split portion 1071 or the second split portion simultaneously contacts the second pixel electrode 107 and the common line 103 is a probability event (ie, an event that rarely occurs)
  • the present invention provides the electrical connector 401 at the recess 110 based on the above-described phenomenon. Therefore, the technical solution of the present invention is advantageous for ensuring the number of pixels in the dark-dot processing.
  • the two-pixel electrode 107 is electrically connected to the common line 103.
  • the recess 110 may be formed by etching the predetermined position 109.
  • the recess 110 may be by dropping a second corrosive liquid at the predetermined position 109 ( For example, an acidic liquid is formed.
  • the second pixel electrode 107 and the common line 103 are electrically connected through the electrical connector 401.
  • the predetermined position 109 is one of overlapping portions of the second pixel electrode 107 and the common line 103.
  • the recess 110 penetrates the second pixel electrode 107 and the insulating layer 201 in a first direction, and the first direction is a direction perpendicular to a plane in which the second pixel electrode 107 is located. Further, the recess 110 extends inside the common line 103 in the first direction.
  • the electrical connector 401 fills the cavity 110.
  • the electrical connector 401 is a metal (eg, iron, copper, etc.), an alloy, a conductive paste, or the like.
  • the electrical connector 401 may be formed by laser gas phase film formation (Laser Chemical Vapor)
  • the manner of Deposition is formed by depositing a conductive material (for example, iron, copper, alloy, conductive paste, etc.) at the cavity 110.
  • FIG. 5 there is shown a cross-sectional view of the second embodiment of the electrical connector 401 in the recess 110 of Figure 1 taken along line A-A'.
  • the electrical connector 401 is attached to the bottom surface and the sidewall of the recess 110, that is, the conductive material is coated on the bottom surface and the sidewall of the recess 110. on.
  • the conductive material may be coated on the bottom surface and the sidewall of the recess 110 by sputtering or spraying.
  • FIG. 6 is an equivalent circuit diagram of a pixel subjected to dark dot processing in FIG.
  • the dark-dotted pixel includes a second thin film transistor 105, a liquid crystal capacitor (by the second pixel electrode 107 and a color filter disposed opposite to the thin film transistor array substrate)
  • the common electrode on the light sheet substrate constitutes 601 and the storage capacitor 602.
  • the connection line between the second source 1052 of the second thin film transistor 105 and the data line 102 is cut off at the disconnection 108, that is, the second source 1052 and the data line
  • the disconnection 108 is disconnected at the disconnection 108; the second pixel electrode 107 and the common line 103 are electrically connected through a connection line.
  • the second source 1052 and the second gate 1051 have a first overlapping portion in the first direction, and the second drain 1053 and the The second gate electrode 1051 also has a second overlapping portion in the first direction; therefore, the second source electrode 1052 and the second gate electrode 1051 constitute a gate-source capacitance Cgs (not shown), The second drain 1053 and the second gate 1051 constitute a gate drain capacitance Cgd (not shown).
  • the second thin film transistor 105 opens a current path between the second source 1052 and the second drain 1053, in order to prevent the charge on the gate source capacitor from passing through the The current channel flows to the second drain electrode 1053 and is transmitted to the second pixel electrode 107.
  • the second source electrode 1052 and the second gate electrode 1051 are disposed.
  • the area of the first overlapping portion is zero, that is, the gate source capacitance disappears (does not exist).
  • the state in which the area of the first overlapping portion is zero is formed by removing the first overlapping portion of the source by laser cutting, etching, or the like.
  • the second drain 1053 and the second gate 1051 are The area of the second overlapping portion is also zero, that is, the gate-drain capacitance disappears (does not exist). Also, the state in which the area of the second overlapping portion is zero is also formed by removing the second overlapping portion of the drain by laser cutting or etching or the like.
  • the relative potential of the second pixel electrode 107 in the dark-dotted pixel is zero.
  • Liquid crystal cell corresponding to the thin film transistor array substrate of the present invention Liquid Crystal After the cell is energized, the pixel voltage corresponding to the dark-spotted pixel is 0, and the liquid crystal molecules corresponding to the dark-spotted pixel cannot be converted by the voltage difference of the second pixel electrode 107. Deflection, therefore, the area of the liquid crystal cell corresponding to the darkened pixel is displayed as a normally dark state.
  • FIG. 7 is a flowchart of a method for processing a pixel dark spot of the thin film transistor array substrate of the present invention.
  • Step 701 cutting a connection line between the second thin film transistor 105 and the data line 102 to insulate the second thin film transistor 105 from the data line 102;
  • Step 702 forming a recess 110 at a predetermined position 109 of the surface of the second pixel electrode 107;
  • Step 703 the electrical connector 401 is disposed in the recess 110 to electrically connect the second pixel electrode 107 and the common line 103 through the electrical connector 401.
  • the step of cutting the connection line between the second thin film transistor 105 and the data line 102 includes:
  • connection line between the second thin film transistor 105 and the data line 102 is cut by a first laser.
  • the connecting line is cut by etching, for example, by dropping a first etching liquid (for example, an acidic liquid).
  • a first etching liquid for example, an acidic liquid
  • the step of forming the recess 110 on the predetermined position 109 of the surface of the second pixel electrode 107 includes:
  • the predetermined position 109 is illuminated with a second laser to form the recess 110 at the predetermined position 109.
  • the predetermined location 109 is etched to form the recess 110 at the predetermined location 109, for example, a second etching liquid is dropped at the predetermined location 109 (eg, The acidic liquid) is used to form the recess 110.
  • a second etching liquid is dropped at the predetermined location 109 (eg, The acidic liquid) is used to form the recess 110.
  • the predetermined position 109 is one of the overlapping portions of the second pixel electrode 107 and the common line 103.
  • the recess 110 penetrates the second pixel electrode 107 and the insulating layer 201 in a first direction, and the first direction is perpendicular to a plane where the second pixel electrode 107 is located. direction.
  • the recess 110 extends inside the common line 103 in the first direction.
  • the step of disposing the electrical connector 401 in the cavity 110 includes:
  • a conductive material for example, iron, copper, alloy, conductive paste, or the like is deposited at the recess 110 by laser vapor phase film formation to form the electrical connector 401.
  • the electrical connector 401 can fill the cavity 110.
  • the step of disposing the electrical connector 401 in the cavity 110 includes:
  • the conductive material is coated on the bottom surface and the sidewall of the recess 110 by sputtering or spraying to form the electrical connector 401.
  • the electrical connector 401 is attached to the bottom surface and the sidewall of the recess 110, that is, the conductive material is coated on the bottom surface and the sidewall of the recess 110.
  • the pixel dark spot processing method of the thin film transistor array substrate of the present invention further includes the following steps:
  • the above technical solution is advantageous for avoiding that the charge on the gate source capacitor flows through the current path to the second drain 1053, and is transmitted to the second pixel electrode 107, and is beneficial to avoid the gate leakage capacitance.
  • the charge is transferred to the second pixel electrode 107.
  • the above technical solution of the present invention is advantageous for ensuring that the second pixel electrode 107 in the dark-spotted pixel is electrically connected to the common line 103, thereby ensuring darkening of the second pixel. Success rate.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat de réseau de transistors en couches minces et un procédé de traitement d'assombrissement de pixels associé. Le réseau de transistors en couches minces comprend une ligne de données (102), une ligne de balayage (101), une ligne commune (103), un premier pixel et un pixel sur lequel un traitement d'assombrissement a été effectué. Le pixel sur lequel un traitement d'assombrissement a été effectué comprend un deuxième transistor en couches minces (105) et une deuxième électrode de pixel (107). Le deuxième transistor en couches minces (105) est déconnecté de la ligne de données (102). Une couche d'isolation (201) est disposée entre la deuxième électrode de pixel (107) et la ligne commune (103). La deuxième électrode de pixel (107) est reliée électriquement à la ligne commune (103).
PCT/CN2014/086626 2014-08-26 2014-09-16 Substrat de réseau de transistors en couches minces et procédé de traitement d'assombrissement de pixels associé Ceased WO2016029517A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410426119.5 2014-08-26
CN201410426119.5A CN104201151B (zh) 2014-08-26 2014-08-26 薄膜晶体管阵列基板及其像素暗点化处理方法

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WO2016029517A1 true WO2016029517A1 (fr) 2016-03-03

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WO (1) WO2016029517A1 (fr)

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CN102707467A (zh) * 2012-06-18 2012-10-03 深圳市华星光电技术有限公司 液晶面板的亮点修补方法以及经亮点修补后的液晶面板
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CN111933582A (zh) * 2020-08-17 2020-11-13 京东方科技集团股份有限公司 像素暗点化处理方法、阵列基板及其制作方法及显示装置
CN111933582B (zh) * 2020-08-17 2024-06-11 京东方科技集团股份有限公司 像素暗点化处理方法、阵列基板及其制作方法及显示装置

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