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WO2016082763A1 - Procédé d'accès mémoire, dispositif pertinent et système - Google Patents

Procédé d'accès mémoire, dispositif pertinent et système Download PDF

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Publication number
WO2016082763A1
WO2016082763A1 PCT/CN2015/095567 CN2015095567W WO2016082763A1 WO 2016082763 A1 WO2016082763 A1 WO 2016082763A1 CN 2015095567 W CN2015095567 W CN 2015095567W WO 2016082763 A1 WO2016082763 A1 WO 2016082763A1
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Prior art keywords
memory
mapping relationship
virtual address
request message
cpu
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English (en)
Chinese (zh)
Inventor
阮元
陈明宇
张立新
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a method, related apparatus, and system for memory access.
  • the central processing unit when the central processing unit (CPU) initiates a memory access, it first accesses its internal private cache (cache). At this time, the CPU first sends the access request to the internal memory management of the CPU.
  • a memory management unit MMU
  • the MMU searches for a real address corresponding to the virtual address in the translation lookaside buffer (TLB) according to the virtual address information in the access request, that is, a physical address, and the CPU passes the physical address.
  • TLB translation lookaside buffer
  • the CPU passes the physical address.
  • Accessing the private cache when a cache miss occurs, that is, after the CPU fails to access the private cache, the CPU sends the memory access request to the memory controller (MC), and accesses the physical address through the MC. RAM.
  • the MMU and the TLB are located on the critical path of the CPU accessing the private cache, when the MMU and the TLB have problems, such as the MMU cannot find the real address (TLB miss) corresponding to the virtual address through the TLB, the CPU cannot access the CPU. Private cache.
  • the page fault interrupt processing is bound to the processor hardware. Once the MMU cannot find the real address corresponding to the virtual address from the TLB and the memory, the page fault interrupt is triggered, and the processor spends a lot of time processing the page fault interrupt.
  • the prior art proposes an effective memory management technology: Virtual Indexed Virtual Tagged technology.
  • the main idea of the all-virtual cache is to remove hardware such as TLB and MMU from the critical path of the CPU to access the private cache.
  • the CPU directly uses the virtual address index cache. Only the cache miss sends the access request to the MMU.
  • the MMU virtualizes through the TLB. Real address translation, using real address access memory. This method can shorten the critical path of the CPU accessing the cache.
  • the TLB is not accessing the critical path of the cache, the TLB can be made very large, and the hit rate of the TLB is increased, thereby effectively reducing the number of TLB misses.
  • the full virtual cache technology effectively solves the above first problem, but after the page fault interrupt occurs, it is still processed by the CPU, causing the CPU to waste a lot of time in processing the page fault interrupt, when the CPU page fault interrupt processing is completed. After that, the memory requested to be accessed in the above access request can be accessed, resulting in low memory access efficiency.
  • Embodiments of the present invention provide a memory access method, related apparatus, and system, which solve the problem of low memory access efficiency in the prior art.
  • an embodiment of the present invention provides a method for memory access, where the method includes:
  • mapping relationship corresponding to the process from a preset mapping relationship set, where the mapping relationship is a correspondence between the virtual address and a memory controller MC corresponding to a memory that the process requests to access;
  • the mapping relationship is a function that uses the virtual address as a variable, or
  • the mapping relationship is L preset bit information of the virtual address, where L ⁇ 1.
  • the method further includes:
  • mapping relationship corresponding to the process with a preset mapping relationship set.
  • the MC corresponding to the memory that the process requests to access includes:
  • the method further includes:
  • the MC Sending, by the MC, an indication message to the MC according to the obtained number of pages that are allocated to the corresponding process by the MC, where the indication message is used to instruct the MC to migrate data of the page allocated to the process to the memory corresponding to the first MC.
  • the first MC is any MC other than the MC of all MCs;
  • the obtaining the updated mapping relationship corresponding to the process specifically includes:
  • an embodiment of the present invention provides a method for accessing a memory, where the method includes:
  • the memory controller MC sends a request message to the central processing unit CPU, where the request message is used to indicate that the idle physical page of the MC is lower than a preset value, wherein the CPU stores the number of pages allocated by all the MCs to the corresponding process;
  • the MC receives the indication message sent by the CPU, where the indication message is used to instruct the MC to migrate the data of the page allocated to the first process to the memory corresponding to the first MC, where the first MC is Any MC of the MC other than the MC;
  • the MC migrates the data allocated to the page of the first process to the memory corresponding to the first MC according to the indication message.
  • the method further includes:
  • an embodiment of the present invention provides a device for accessing a memory, where the device includes: a receiving unit, a first acquiring unit, a second acquiring unit, and a sending unit;
  • the receiving unit is configured to receive a memory access request message of the process, where the memory access request message includes information of a virtual address corresponding to the memory requested by the process;
  • the first acquiring unit is configured to acquire, according to the process, a mapping relationship corresponding to the process from a preset mapping relationship set, where the mapping relationship is that the virtual address corresponds to a memory requested by the process to access Correspondence relationship of the memory controller MC;
  • the second obtaining unit is configured to acquire, according to the information of the virtual address and the mapping relationship, an MC corresponding to a memory requested by the process to access;
  • the sending unit is configured to send the memory access request message to the MC.
  • the mapping relationship is a function that uses the virtual address as a variable, or
  • the mapping relationship is L preset bit information of the virtual address, where L ⁇ 1.
  • the first acquiring unit is further configured to:
  • the second obtaining unit is specifically configured to:
  • the receiving unit is further configured to: receive a request message sent by the MC, where the request message is used to indicate an idle physical page of the MC Below the preset value;
  • the sending unit is further configured to: send an indication message to the MC according to the number of pages that all the MCs are allocated to the corresponding process, where the indication message is used to instruct the MC to migrate data of the page allocated to the process In the memory corresponding to the first MC, wherein the first MC is any MC except the MC of all MCs;
  • the first acquiring unit is specifically configured to: obtain, according to the process, the first MC The updated mapping relationship corresponding to the process is taken.
  • an embodiment of the present invention provides a memory controller MC, where the MC includes: a sending unit, a receiving unit, and a migration unit;
  • the sending unit is configured to send a request message to the central processing unit CPU, where the request message is used to indicate that the idle physical page of the MC is lower than a preset value, where the CPU stores all MCs allocated to the corresponding process. Number of pages;
  • the receiving unit is configured to receive an indication message sent by the CPU, where the indication message is used to instruct the MC to migrate data of a page allocated to the first process to a memory corresponding to the first MC, where the The first MC is any MC other than the MC of all MCs;
  • the migrating unit is configured to migrate data allocated to the page of the first process to a memory corresponding to the first MC according to the indication message.
  • the sending unit is further configured to:
  • the response message is used to instruct the MC to complete migration of data allocated to a page corresponding to the first process.
  • an embodiment of the present invention provides a memory access system, where the system includes the memory access device according to any one of the third aspect to the third possible implementation manner of the third aspect, and The memory controller MC of the fourth aspect or the first possible implementation of the fourth aspect.
  • the embodiment of the present invention provides a memory access method, related device, and system.
  • the CPU allocates a mapping relationship corresponding to the process for the process.
  • the memory access device is configured according to The mapping relationship corresponding to the process and the virtual address information corresponding to the memory requested by the process, and calculating the memory controller corresponding to the memory accessed by the process, thereby solving the translation of the virtual real address by the memory controller, and
  • the CPU cannot send a memory access request to the correct MC.
  • FIG. 1 is a schematic diagram of a system for memory access
  • FIG. 2 is a schematic diagram of another system for memory access
  • 3 is a flow chart of a method for memory access
  • FIG. 5 is a flow chart of another method for memory access
  • FIG. 6 is a schematic diagram of a device for memory access
  • Figure 7 is a schematic view of a MC
  • FIG. 8 is a schematic diagram of another device for accessing a memory
  • Figure 9 is a schematic view of another MC
  • Figure 10 is a schematic diagram of another system for memory access.
  • the page fault interrupt processing is bound to the hardware of the CPU.
  • the MMU cannot find the real address corresponding to the virtual address carried in the access request of the process from the TLB and the memory, the page fault is triggered, and the CPU is triggered.
  • the processing of the page fault interrupt is performed.
  • the CPU interrupt processing is completed, the access request of the process is continued. Since the CPU processes the page fault interrupt for a long time, the memory access efficiency of the CPU is low.
  • a virtual address is also referred to as a virtual address
  • a real address is also referred to as a physical address.
  • a new memory access system is exemplarily described in conjunction with FIG. 1, in which, when a cache miss occurs, the CPU will The access request corresponding to the process is sent to the memory controller (MC), and the MC translates the virtual address carried by the access request into a physical address according to the search TLB, so that the CPU accesses the memory corresponding to the MC according to the physical address. space.
  • the MC cannot find the page table entry corresponding to the virtual address from the TLB, the MC searches for the page table entry corresponding to the virtual address from its corresponding memory.
  • the CPU divides the memory into multiple physical memory pages, and the address of each page is a page table entry.
  • the correspondence between the virtual address and the page table entry is stored in the TLB and the memory, and the virtual address is indexed to
  • the page table entry corresponding to the virtual address can obtain the physical address corresponding to the virtual address, that is, the address of the physical memory page, by using the page table entry.
  • the MC does not directly trigger the page fault interrupt, but determines the type of the page fault, and the page fault type includes a blank page page fault and There is a missing page for the data.
  • the blank page missing page means that the virtual address is not assigned a corresponding page, that is, the virtual address is accessed for the first time, and the corresponding page has not been allocated.
  • the existing page missing data indicates that the virtual address has been assigned a corresponding page, but the page corresponding to the virtual address is not used for a long time, and therefore, the data of the page corresponding to the virtual address is replaced with the idle position.
  • the memory manager maintains page allocation information, where the information of the virtual address of the allocated page is recorded in the page allocation information. If the page allocation information records that the virtual address has been allocated the page, the memory manager determines that the page missing type is The data is out of page. If there is no allocation record of the virtual address in the page allocation information, the memory manager determines that the page fault type is a blank page page fault.
  • the MC determines that the virtual address is accessed for the first time.
  • the MC allocates a corresponding blank page to the virtual address of the process through a preset policy, and adds the page entry of the virtual address to the TLB and the memory.
  • the processing caused by the page fault interrupted when the blank page is missed or the existing data is missing is avoided in the prior art. Less efficient problem.
  • each memory controller has an independent memory space.
  • the CPU cannot obtain the physical address corresponding to the virtual address information of the access request after the cache miss occurs. Therefore, the CPU cannot determine the physical address of the memory space corresponding to the physical address of the virtual address. The CPU cannot send an access request to the correct MC.
  • the embodiment of the present invention provides another system for accessing a memory, in which one CPU corresponds to multiple MCs, and specifically, an MC judging module may be added to the CPU of the system.
  • the MC judging module is configured to receive a memory access request message after the CPU generates a cache miss, and send the memory access request to the correct MC according to the memory access request message.
  • the MC judging module may be located in each processor core of the CPU in the system shown in FIG. 2, or a plurality of processor cores may share one MC judging module.
  • a separate device may be added to the system, and the function of the device is the same as that of the MC judging module.
  • the embodiment of the present invention does not limit this.
  • an embodiment of the present invention provides a method for accessing a memory.
  • the execution body of the method is a device for accessing a memory.
  • the device for accessing the memory may be a CPU, or may be different from the CPU.
  • the independent device is not limited in this embodiment of the present invention.
  • the method includes:
  • the processor When a process of the processor needs to access the memory, the processor sends a memory access request message of the process, or when a processor is a multi-core processor, the processor shown in FIG. 2, in the processor A processor core, such as processor core 1, sends a memory access request of a process, and after a cache miss occurs, the memory access device receives a memory access request message of the process.
  • the access request message includes information that the process requests access to the virtual address corresponding to the memory.
  • the mapping relationship is the correspondence between the virtual address and the memory controller MC corresponding to the memory requested by the process.
  • a CPU corresponding to a memory access system of multiple MCs multiple MCs can work in parallel, improving the efficiency of memory access.
  • the operating system allocates a mapping relationship corresponding to the process for each process when the process is established.
  • the mapping relationship is a correspondence between a virtual address carried in a memory access request message of the process and a memory controller corresponding to the memory requested by the process.
  • the memory access device stores a mapping relationship set, where the mapping relationship set includes a mapping relationship between the process and the process. After the device receives the memory access request message of the process, the device may index from the mapping relationship set to the mapping relationship corresponding to the process according to the process.
  • the mapping relationship may be a function in which a virtual address is a variable, or the mapping relationship is L preset bit information of a virtual address in a memory access request of the process, where L ⁇ 1.
  • one physical CPU corresponds to four MCs, and the ID numbers of the four MCs are 00, 01, 02, and 03, respectively.
  • the first mapping relationship is a function that uses a virtual address as a variable, for example, the process is process 1, and when the process 1 is created, the operating system allocates a mapping for the process 1.
  • the relationship is crc16 (Cyclic Redundancy Check), and crc16 selects the generator polynomial x 16 +x 15 +x 2 +1.
  • the mapping relationship represents the calculation of the virtual address corresponding to process 1 crc16, and the result is The upper two are the IDs of the target MC.
  • the operating system allocates the mapping relationship to the process 2 It is vaddr15-14, which is used to indicate the 15th and 14th bits of the virtual address in the access request of the process with the process number 2 as the ID of the target MC.
  • the device After the device obtains the mapping relationship corresponding to the process, the device calculates the process according to the information about the virtual address corresponding to the memory requested by the process and the mapping relationship carried in the memory access request message.
  • the MC corresponding to the memory requested to access.
  • the mapping relationship is a function related to a virtual address
  • the device brings the virtual address in the memory access request message into the function to calculate the MC.
  • the function is crc16
  • the virtual address carried in the memory access request of process 1 is virtual address 1
  • the virtual address 1 is calculated by crc16
  • the upper two bits of the obtained result are 01, which is
  • the MC selected in Process 1 is the MC with ID number 01.
  • mapping relationship is the L preset bit information of the virtual address, such as vaddr15-14
  • the virtual address carried in the memory access request of process 2 is virtual address 2
  • the virtual address 2 is taken.
  • the 15th and 14th bits, the result is 00
  • the MC selected for the process 2 is the MC with the ID number 00.
  • the device sends a memory access request message of the process to the MC, so that the MC obtains a physical address corresponding to the virtual address by searching for a TLB according to the virtual address information in the memory access request message. . So that the processor accesses the memory corresponding to the physical address.
  • An embodiment of the present invention provides a method for accessing a memory.
  • the process is assigned a mapping relationship corresponding to the process, where the virtual relationship corresponds to the memory requested by the process.
  • Correspondence of the memory controller MC Correspondence of the memory controller MC.
  • the process obtains the mapping relationship corresponding to the process from the mapping relationship set, and the virtual address information carried in the memory access request of the process according to the mapping relationship And calculating, by the MC corresponding to the memory requested by the process, to send the memory access request of the process to the correct MC.
  • the embodiment of the present invention A method for accessing a memory is also provided.
  • the execution body of the method is a CPU. Referring to FIG. 4, the method includes:
  • the MC when the remaining idle physical page of the MC is lower than a preset value, the MC sends a request message to the CPU, where the request message is used to indicate that the idle physical page of the MC is lower than a preset value, requesting the location
  • the CPU reduces the load of the MC, such as migrating data allocated to a part of the MC to other MCs with lower load.
  • Step 402 Send an indication message to the MC according to the obtained number of pages that all the MCs allocate to the corresponding process, where the indication message is used to instruct the MC to migrate data of the page allocated to the process to the first MC.
  • the first MC is any MC except the MC of all MCs.
  • the CPU stores the number of pages allocated by all the MCs to the corresponding process, and after receiving the request message sent by the MC, the CPU receives the request message sent by the MC, and then sends the request message to the MC.
  • Sending an indication message the indication message is used to instruct the MC to migrate data allocated to the page of the process to a memory corresponding to the first MC.
  • the CPU corresponds to four MCs, and the ID numbers of the four MCs are 00, 01, 02, and 03, respectively.
  • the MC corresponding to the process 1 is the MC with the ID number of 00. After the load of the MC is large, that is, the number of remaining free physical pages is less than the preset value, the MC sends a request message to the CPU.
  • the CPU stores the number of pages allocated to the corresponding process by each MC.
  • the MC with the ID number 00 has four processes, which are processes 1-4, and the number of allocated pages is 50, 45, 30, and 20 respectively.
  • the MC with ID number 01 has three processes, which are processes 5-7, and the number of allocated pages is 25, 20, 15, and 10;
  • the MC with ID number 02 has two processes, which are process 8 respectively.
  • -9 the number of allocated pages is 20 and 15 respectively;
  • the MC with ID number 03 corresponds to 1 process, and for process 10, the number of allocated pages is 15.
  • the MC After the MC receives the request message sent by the MC with the ID number 00, it determines that the number of pages allocated by the MC with the ID number 00 to the process 1 is the largest, and the ID number is 03. The load of the MC is minimal.
  • the MC that the CPU determines the ID number of 00 migrates the data of the page allocated to the process 1 to the MC whose ID number is 03.
  • the MC whose ID number is 03 is the first MC. .
  • the CPU reassigns an updated mapping relationship to the process 1 according to the process 1 and the MC whose ID number is 03, and replaces the mapping relationship corresponding to the process in the preset mapping relationship set.
  • the mapping relationship for the update is
  • the step 404 and the steps 401-403 have no determined sequence, and the step 404 may be performed first, and then the steps 401-403 may be performed, or the steps 401-403 may be performed first, and then the step 404 is performed, and the implementation of the present invention does not limited.
  • the CPU obtains the updated mapping relationship corresponding to the process 1 according to the process 1, and acquires the first MC according to the virtual address information in the memory access request of the process 1 and the updated mapping relationship.
  • the detailed technical features of the steps 404-407 can be referred to the foregoing steps 301-304, which are not described in detail in the embodiments of the present invention.
  • An embodiment of the present invention provides a method for accessing a memory.
  • a mapping relationship corresponding to the process is assigned to the process.
  • the mapping relationship is a correspondence between the virtual address and the memory controller MC corresponding to the memory requested by the process.
  • the CPU determines that the MC migrates the data of the page allocated for the process to the first MC, and allocates an updated mapping relationship to the process, when receiving the memory access request message of the process.
  • the process obtains the updated mapping relationship corresponding to the process from the mapping relationship set, and calculates the process request access according to the updated mapping relationship and the virtual address information carried in the memory access request of the process.
  • the first MC corresponding to the memory, so that not only the memory access request of the process is sent to the correct MC, but also the adjustment of the MC load is implemented.
  • an embodiment of the present invention further provides a method for memory management, where the execution subject of the method is an MC, and the method includes:
  • the memory controller MC sends a request message to the central processing unit CPU, where the request message is used to indicate that the idle physical page of the MC is lower than a preset value, where the CPU stores all the pages allocated by the MC to the corresponding process. number.
  • the MC receives an indication message sent by the CPU, where the indication message is used to instruct the MC to migrate data of a page allocated to the first process to a memory corresponding to the first MC, where the first MC is any MC other than the MC of all MCs.
  • the MC migrates data allocated to the page of the first process to a memory corresponding to the first MC according to the indication message.
  • the MC migrates the data of the page allocated to the first process to the memory corresponding to the first MC
  • the MC sends a response message to the CPU, where the response message is used to indicate that the MC is complete.
  • a migration of the data that is allocated to the page corresponding to the first process so that the CPU acquires an updated mapping relationship corresponding to the first process according to the response message, and according to the updated mapping relationship and The virtual address information corresponding to the memory requested by the first process is sent, and the memory access request message of the first process is sent to the first MC.
  • Embodiments of the present invention provide a method for accessing a memory, in which the method
  • a CPU corresponds to multiple memory controllers, and one of the memory controllers has a large load
  • the MC sends a request message to the CPU, and the CPU determines, according to the request message, to migrate the page allocated by the MC to a process to The other is called the idle MC, which solves the problem of unbalanced MC load.
  • the embodiment of the present invention further provides a memory access device.
  • the device includes: a receiving unit 601, a first obtaining unit 602, a second obtaining unit 603, and a sending unit 604;
  • the receiving unit 601 is configured to receive a memory access request message of the process, where the memory access request message includes information of a virtual address corresponding to the memory requested by the process;
  • the first obtaining unit 602 is configured to acquire, according to the process, a mapping relationship corresponding to the process from a preset mapping relationship set, where the mapping relationship is that the virtual address corresponds to a memory requested by the process to access Corresponding relationship of the memory controller MC;
  • the second obtaining unit 603 is configured to acquire, according to the information of the virtual address and the mapping relationship, an MC corresponding to the memory requested by the process to access;
  • the sending unit 604 is configured to send the memory access request message to the MC.
  • mapping relationship is a function that uses the virtual address as a variable, or
  • the mapping relationship is L preset bit information of the virtual address, where L ⁇ 1.
  • the first obtaining unit 602 is further configured to:
  • the second obtaining unit 603 is specifically configured to:
  • the receiving unit 601 is further configured to: receive a request message sent by the MC, where the request message is used to indicate that an idle physical page of the MC is lower than a preset value;
  • the sending unit 604 is further configured to: send an indication message to the MC according to the number of pages that all the MCs are allocated to the corresponding process, where the indication message is used to indicate The MC migrates the data of the page allocated to the process to the memory corresponding to the first MC, where the first MC is any MC except the MC of all the MCs;
  • the first obtaining unit 602 is specifically configured to: acquire an updated mapping relationship corresponding to the process according to the process and the first MC.
  • the embodiment of the present invention provides a device for accessing a memory.
  • the device may be a CPU or an independent device.
  • the CPU allocates a mapping relationship corresponding to the process to the process.
  • the device After receiving the memory access request message of the process, the device obtains the mapping relationship corresponding to the process from the mapping relationship set by the process, and according to the mapping relationship and the virtual information carried in the memory access request of the process
  • the address information is used to calculate the MC corresponding to the memory requested by the process to send the memory access request of the process to the correct MC.
  • the embodiment of the present invention further provides an MC, in conjunction with FIG. 7, the MC includes: a sending unit 701, a receiving unit 702, and a migration unit 703;
  • the sending unit 701 is configured to send a request message to the central processing unit CPU, where the request message is used to indicate that the idle physical page of the MC is lower than a preset value, where the CPU stores all MCs allocated to the corresponding process. Number of pages;
  • the receiving unit 702 is configured to receive an indication message sent by the CPU, where the indication message is used to instruct the MC to migrate data of a page allocated to the first process to a memory corresponding to the first MC, where The first MC is any MC of the MC except the MC;
  • the migrating unit 703 is configured to migrate the data of the page allocated to the first process to the memory corresponding to the first MC according to the indication message.
  • the sending unit 701 is further configured to:
  • the response message is used to instruct the MC to complete migration of data allocated to a page corresponding to the first process.
  • the embodiment of the present invention provides an MC.
  • the CPU sends a request message to the CPU, and the CPU determines, according to the request message, that the page allocated by the MC for one process is migrated to another MC that is idle. Thereby solving the problem of unbalanced MC load.
  • the embodiment of the present invention further provides a memory access device, in conjunction with FIG. 8, the device includes: a receiver 801, a processor 802, a bus 803, a memory 804, and a transmitter 805;
  • the receiver 801 is configured to receive a memory access request message of a process, where the memory access request message includes information of a virtual address corresponding to a memory requested by the process;
  • the processor 802 is configured to acquire, by using the bus 803, an instruction in the memory 804, to obtain, according to the process, a mapping relationship corresponding to the process from a preset mapping relationship set, where the mapping relationship is Corresponding relationship between the virtual address and the memory controller MC corresponding to the memory requested by the process;
  • the transmitter 805 is configured to send the memory access request message to the MC.
  • mapping relationship is a function that uses the virtual address as a variable, or
  • the mapping relationship is L preset bit information of the virtual address, where L ⁇ 1.
  • the processor 802 is further configured to: obtain an updated mapping relationship corresponding to the process;
  • the receiver 801 is further configured to: receive a request message sent by the MC, where the request message is used to indicate that an idle physical page of the MC is lower than a preset value;
  • the transmitter 805 is further configured to: send an indication message to the MC, where the indication message is used to instruct the MC to migrate data allocated to a page of the process to a memory corresponding to the first MC, where The first MC is any MC of the MC except the MC;
  • the processor 802 is specifically configured to: according to the process and the first MC, Obtain an updated mapping relationship corresponding to the process.
  • the implementation of the present invention provides a memory access device.
  • the CPU allocates a mapping relationship corresponding to the process to the process, where the mapping relationship is that the virtual address corresponds to the memory requested by the process.
  • the memory controller MC Correspondence of the memory controller MC.
  • the device After receiving the memory access request message of the process, the device obtains the mapping relationship corresponding to the process from the mapping relationship set by the process, and according to the mapping relationship and the virtual information carried in the memory access request of the process The address information is used to calculate the MC corresponding to the memory requested by the process to send the memory access request of the process to the correct MC.
  • an embodiment of the present invention further provides an MC, where the MC includes: a transmitter 901, a receiver 902, and a processor 903;
  • the transmitter 901 is configured to send a request message to the central processing unit CPU, where the request message is used to indicate that the idle physical page of the MC is lower than a preset value, where the CPU stores all MCs allocated to the corresponding process. Number of pages;
  • the receiver 902 is configured to receive an indication message sent by the CPU, where the indication message is used to instruct the MC to migrate data of a page allocated to the first process to a memory corresponding to the first MC, where The first MC is any MC of the MC except the MC;
  • the processor 903 is configured to migrate, according to the indication message, data allocated to a page of the first process to a memory corresponding to the first MC.
  • the embodiment of the present invention provides an MC.
  • the CPU sends a request message to the CPU, and the CPU determines, according to the request message, that the page allocated by the MC for one process is migrated to another MC that is idle. Thereby solving the problem of unbalanced MC load.
  • an embodiment of the present invention further provides a system for memory access, including a memory access device as shown in FIG. 6 and a plurality of MCs as shown in FIG. 7; or, the system includes FIG.
  • the device for memory access shown may be a CPU or a stand-alone device other than a CPU.
  • the system further includes a CPU.
  • An embodiment of the present invention provides a system for accessing a memory.
  • a CPU corresponds to multiple MCs.
  • the CPU allocates a mapping relationship corresponding to the process, and the memory access device stores one. a mapping relationship set, after the memory access device receives the memory access request message of the process, indexes the mapping relationship corresponding to the process from the mapping relationship set, and passes the mapping relationship, and the virtual memory corresponding to the memory requested by the process request.
  • the address information is obtained by the MC corresponding to the process, and the memory access request of the process is sent to the MC, so that the correct MC is selected for the memory access request message of the process.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne un procédé d'accès mémoire, et un dispositif pertinent et système, qui permettent de résoudre le problème dans l'art antérieur de faible efficacité de l'accès mémoire. Le procédé comprend les étapes suivantes : recevoir un message de demande d'accès mémoire d'un processus, le message de demande d'accès mémoire comprenant des informations sur une adresse virtuelle correspondant à une mémoire à laquelle le processus demande d'accéder ; acquérir une relation de mappage correspondant au processus à partir d'une relation de mappage prédéfinie établie selon le processus, la relation de mappage étant une corrélation entre l'adresse virtuelle et un contrôleur de mémoire (MC) correspondant à la mémoire à laquelle le processus demande d'accéder ; acquérir le MC correspondant à la mémoire à laquelle le processus demande d'accéder en fonction des informations sur l'adresse virtuelle et de la relation de mappage ; et envoyer le message de demande d'accès mémoire au MC. Le procédé est applicable au domaine technique des ordinateurs.
PCT/CN2015/095567 2014-11-28 2015-11-25 Procédé d'accès mémoire, dispositif pertinent et système Ceased WO2016082763A1 (fr)

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