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WO2016072005A1 - Cellule solaire - Google Patents

Cellule solaire Download PDF

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Publication number
WO2016072005A1
WO2016072005A1 PCT/JP2014/079521 JP2014079521W WO2016072005A1 WO 2016072005 A1 WO2016072005 A1 WO 2016072005A1 JP 2014079521 W JP2014079521 W JP 2014079521W WO 2016072005 A1 WO2016072005 A1 WO 2016072005A1
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Prior art keywords
layer
crystalline
polarity
heavily doped
polar
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English (en)
Japanese (ja)
Inventor
敬司 渡邉
峰　利之
克矢 小田
真 三浦
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar battery cell.
  • Sunlight is composed of light in a wide wavelength range, and light that can be absorbed by the solar battery cell is light having energy equal to or higher than the band gap of the semiconductor material of the power generation layer. Electron-hole pairs are generated by the energy of the absorbed light, and electrons and holes are collected in separate electrodes, creating a potential difference between the electrodes and generating power. This is the operation principle of the battery cell.
  • surplus energy exceeding the band gap hereinafter referred to as Eg is dissipated as heat in a general solar battery cell.
  • multi-exciton generation is a phenomenon in which electron-hole pairs are further generated by surplus energy when the surplus energy is twice or more Eg (hereinafter referred to as 2Eg).
  • Patent Document 1 discloses a method of using multi-exciton generation in a crystalline silicon (hereinafter referred to as crystalline Si) solar battery cell.
  • crystalline Si crystalline silicon
  • the internal quantum efficiency is More than 1 phenomenon was observed.
  • the internal quantum efficiency represents the number of electrons and holes generated from one photon absorbed inside the solar battery cell and collected by the electrode. Therefore, an internal quantum efficiency exceeding 1 indicates that multi-exciton generation occurs inside the solar battery cell.
  • multi-exciton generation is a phenomenon that occurs due to high-energy light.
  • high-energy light is absorbed near the surface of a solar battery cell.
  • a high-quality surface passivation film is necessary for use.
  • a low-quality surface passivation film that is, when there are many recombination levels at the interface between the surface passivation film and the power generation layer, electrons and holes generated by multi-exciton generation are collected at the electrode. There is a high probability of disappearing by recombination before being done.
  • a SiO 2 film formed by a thermal oxidation method is used as a high-quality passivation film.
  • Non-Patent Document 1 describes a mixed crystal of Si and Ge (hereinafter referred to as crystalline Si 1-x Ge x .
  • x is a composition ratio of Ge and takes a value of 0 ⁇ x ⁇ 1.
  • the calculation results of ⁇ and Eg are described in FIG. According to this, both ⁇ ⁇ and Eg monotonously decrease with respect to x, and furthermore, the value of ⁇ ⁇ -2Eg monotonously decreases with respect to x.
  • x ⁇ 0.68 in ⁇ ⁇ -2Eg> is 0, x> in 0.68 ⁇ ⁇ -2Eg ⁇ 0.
  • Non-Patent Document 2 describes a method using a composition gradient buffer layer as a method of forming a crystalline Si 1-x Ge x film on a crystalline Si substrate.
  • Non-Patent Document 2 by using the composition graded buffer layer, on a crystalline Si substrate, directly, as compared with the case of forming a crystalline Si 1-x Ge x film, the crystalline Si 1-x Ge x film It is possible to reduce the crystal defect density.
  • Patent Document 2 describes a method using a Ge buffer layer as a method of forming a crystalline Ge film on a crystalline Si substrate. According to this, a Ge buffer layer is first formed on a crystalline Si substrate, and the Ge buffer layer is lattice-relaxed by applying heat treatment. Thereafter, a crystalline Ge layer is formed on the Ge buffer layer. According to Patent Document 2, it is possible to form a crystalline Ge layer having a low crystal defect density on a crystalline Si substrate by using a Ge buffer layer.
  • Patent Document 3 describes the diffusion coefficient of phosphorus in crystalline Si 1-x Ge x . According to this, the higher the Ge composition x of the crystalline Si 1-x Ge x , the larger the diffusion coefficient of phosphorus, and in particular, the diffusion coefficient of phosphorus in crystalline Ge is the diffusion coefficient of phosphorus in crystalline Si. 10 5 times or more.
  • the first problem relates to a method for forming a crystalline Si 1-x Ge x film.
  • the composition gradient buffer is increased as the Ge composition x of the crystalline Si 1-x Ge x film is increased. It is necessary to form a thick layer. Since the composition gradient buffer layer is a film having a high defect density, there is a high probability that carriers passing through the composition gradient buffer layer will recombine during solar cell operation.
  • the composition gradient buffer layer is formed thick, the crystal defect density of the crystalline Si 1-x Ge x film formed thereon increases with the Ge composition x. For this reason, carrier recombination inside the crystalline Si 1-x Ge x film during solar cell operation is more likely to occur as the Ge composition x is higher. Therefore, when a solar cell using a crystalline Si 1-x Ge x film having a high Ge composition x as a power generation layer using a composition gradient buffer layer, there is a problem that the carrier recombination probability is high.
  • the second problem relates to a method of forming a selective emitter for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge.
  • the selective emitter refers to an emitter formed locally only on the lower part of the surface electrode among the emitters formed on the light receiving surface (hereinafter referred to as surface) side of the solar battery cell.
  • surface the light receiving surface
  • the higher the doping concentration of the emitter the higher the carrier recombination probability inside the emitter, while the higher the doping concentration of the emitter, the lower the contact resistance between the emitter and the emitter and the electrode. To do.
  • the higher the doping concentration of the emitter the lower the potential energy of the selected emitter region for the electrons, thereby improving the carrier collection efficiency.
  • an emitter having a relatively low doping concentration is formed on the entire surface, and the doping concentration is relatively low only in the lower part of the surface electrode that is shielded by the surface electrode and does not receive light.
  • a technique of reducing the contact resistance between the emitter and the electrode is often used by forming a high selective emitter so as to cover the contact hole.
  • FIG. 10 shows the results of experiments conducted by the present inventors prior to the present invention.
  • the vertical axis represents the internal quantum efficiency at a wavelength of 290 nm of the crystalline Si solar cell, and the horizontal axis represents the surface phosphorous concentration of the selected emitter. It is a graph.
  • the internal quantum efficiency is the number of electron-hole pairs collected by the electrode per photon absorbed inside the solar battery cell. That is, the internal quantum efficiency exceeds 1 when multi-exciton generation occurs and the resulting electron-hole pairs are collected at the electrode.
  • the surface phosphorus concentration of the emitter formed on the entire surface other than the selected emitter is 3.5 ⁇ 10 18 cm ⁇ 3 .
  • the data with the lowest surface phosphorous concentration of the selected emitter represents the characteristics of the solar cell in which the emitter of the same concentration is formed on the entire surface without the selected emitter.
  • the internal quantum efficiency does not exceed 1, and the internal quantum efficiency exceeds 1 by forming a selective emitter having a higher phosphorus concentration.
  • the cause is considered to be that the carrier collection efficiency is improved by forming the selective emitter.
  • the data in FIG. 10 means that it is necessary to form a selective emitter in order to utilize multi-exciton production in a solar cell.
  • the internal quantum efficiency exceeds 1 when the surface phosphor concentration of the selective emitter is 8 ⁇ 10 18 cm ⁇ 3 or more and 7 ⁇ 10 19 cm ⁇ 3 or less.
  • the width of the selective emitter of the crystalline Ge layer is larger than the width of the selective emitter of crystalline Si and therefore larger than the width of the contact hole.
  • the width of the selective emitter of the crystalline Ge layer becomes larger than the width of the surface electrode, and a part of the selective emitter may be formed in a region that is not shielded by the surface electrode.
  • the composition of Ge using the composition gradient buffer layer is as follows.
  • a solar cell using a crystalline Si 1-x Ge x film having a high x as a power generation layer is produced, there is a problem that the carrier recombination probability is high.
  • a selective emitter is formed for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, a part of the selective emitter is shielded by the surface electrode due to the difference in phosphorus diffusion coefficient. There is a problem that a loss due to carrier recombination occurs in a region that is not formed.
  • a typical object of the present invention is to realize a highly efficient solar cell by making use of multi-exciton generation and reducing carrier recombination loss at the same time.
  • a solar cell a first polar crystalline Si substrate, a Ge buffer layer formed on the surface of the first polar crystalline Si substrate, and a crystalline Ge layer formed on the surface of the Ge buffer layer
  • a second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, and a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer
  • a passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, a second polar highly doped crystalline Si layer formed in the same plane as the second polar crystalline Si layer, A surface electrode formed on the surface of the second polarity highly doped crystal Si layer, and the second polarity highly doped crystal Si at the interface between the second polarity highly doped crystal Si layer and the surface electrode
  • the width of the layer is such that the heavily doped crystalline Si layer of the second polarity is connected to the second polarity.
  • Si 1-x Ge x is larger than
  • a solar cell a first polar crystalline Si substrate, a Ge buffer layer formed on the surface of the first polar crystalline Si substrate, and a crystalline Ge layer formed on the surface of the Ge buffer layer
  • a solar cell a first polar crystalline Si substrate, an insulating film formed on the surface of the first polar crystalline Si substrate, a crystalline Ge layer formed on the surface of the insulating film, A second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer, A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, and a surface electrode formed on the surface of the second polar crystalline Si layer, wherein the second polar crystalline Si layer is The first polar crystalline Si substrate and the crystalline Ge layer are in contact with each other.
  • a high-efficiency solar cell can be obtained by simultaneously using multi-exciton generation and reducing carrier recombination loss. Can be realized.
  • FIG.2 It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (d). It is a top view which shows the manufacturing method of a photovoltaic cell following FIG.2 (e). It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.2 (f). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (g). It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (h). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (i). It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.2 (j).
  • FIG.4 It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.4 (d). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (e). It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.4 (f). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (g). It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.4 (h). It is a top view which shows the photovoltaic cell which concerns on Example 3 of this invention. It is sectional drawing which shows the photovoltaic cell which concerns on Example 3 of this invention.
  • FIG. 6 is a top view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge.
  • FIG. 6 is a top view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge.
  • FIG. 6 is a cross-sectional view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge. It is a graph which shows the relationship between the internal quantum efficiency in wavelength 290nm, and the surface phosphorus density
  • a solar battery cell according to Example 1 of the present invention will be described with reference to FIGS.
  • FIG. 1A and FIG. 1B are a top view and a cross-sectional view, respectively, showing the solar battery cell according to the first embodiment.
  • the top view of FIG. 1A is hatched in the same manner as the cross-sectional view for easy understanding of the correspondence with the cross-sectional view of FIG. .
  • the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 were formed on the crystalline Si substrate 11. It is a solar battery cell, and has a front electrode 21 and a back electrode 22 as electrodes.
  • the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 each have a concentration of a dopant such as phosphorus or boron in the crystalline Ge layer. 13, higher than the dopant concentration inside the crystalline Si 1-x Ge x layer 14 and the crystalline Si layer 15.
  • the heavily doped crystal Ge layer 33 is characterized in that the width in the planar direction is smaller than the width of the surface electrode 21.
  • the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the surface electrode 21 is larger than the width of the opening of the passivation layer 16.
  • the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the heavily doped crystal Si 1-x Ge x layer 32 is as follows. It is characterized in that it is smaller than the width of the heavily doped crystalline Si layer 31 at the interface. The effects brought about by these features are described below.
  • FIG. 1A and FIG. 1B the structure in the case where the surface electrode 21 is formed in a straight line when viewed from above is shown, as in a general solar battery cell.
  • the surface electrode 21 may have a different top surface shape.
  • the passivation layer 16 is patterned, and in the structure of the first embodiment, the surface electrode 21 and the heavily doped crystalline Si layer 31 are formed in the opening where the passivation layer 16 does not exist. And are connected.
  • the shape of the upper surface of the opening where the passivation layer 16 does not exist is arbitrary, and may be linear when viewed from the upper surface, or there may be a plurality of circular openings when viewed from the upper surface.
  • the top surface shape of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 is arbitrary, and may be linear when viewed from above. Alternatively, there may be a plurality of circular openings as viewed from the top.
  • crystalline Si substrate 11 and the back electrode 22 are connected, but a back surface field (BSF) layer is provided at the interface between the crystalline Si substrate 11 and the back electrode 22 as in a general solar battery cell.
  • BSF back surface field
  • a back contact passivation film may be further added to form a point contact structure.
  • the conductivity type of the semiconductor constituting the solar battery cell of Example 1 will be described. The following p-type and n-type may be reversed.
  • the crystalline Si substrate 11 is p-type, and the four layers of the crystalline Si layer 15, the highly doped crystalline Ge layer 33, the highly doped crystalline Si 1-x Ge x layer 32, and the highly doped crystalline Si layer 31 are n-type. It is.
  • the two layers of the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14 may be both n-type or i-type, or the two layers may be n-type on the surface side and i-type on the substrate side, and 2 There may be an n-type and i-type interface on either side of the layer.
  • the crystalline Si layer 31 can have a single crystal structure, a polycrystal structure, a microcrystal structure, or the like.
  • the material of the passivation layer 16 is an insulator such as SiO 2 , SiN (silicon nitride), amorphous Si, SiC (silicon carbide), CdS, or a laminated structure of these insulators.
  • the material of the front electrode 21 and the back electrode 22 is a metal such as Ag, Al, Ti, Pd, Ni, or Cu, or a laminated structure of these metals.
  • the passivation layer 16 it is particularly desirable to use SiO 2 as the passivation layer 16.
  • SiO 2 the interface between the crystalline Si and SiO 2, compared with the interface between the crystalline Si 1-x Ge x and SiO 2, because the interface recombination is suppressed.
  • the effect of the first embodiment will be described by taking the case of using the above materials as an example.
  • a highly efficient solar battery cell can be realized by using both the use of multi-exciton generation and the reduction of carrier recombination loss.
  • the locations where multi-exciton generation can occur are the crystalline Si substrate 11, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15. .
  • it is effective to reduce the value of ⁇ ⁇ -2Eg in the band structure, and in the crystalline Si 1-x Ge x , ⁇ ⁇ -2Eg The value of decreases monotonically with respect to x.
  • the crystal Si 1-x Ge x layer 14 is used as a main generation layer for multi-exciton generation, thereby improving the use efficiency of multi-exciton generation compared to the crystal Si solar cell. can do.
  • the crystal Si 1-x Ge x layer 14, to the main generating layer Maruchiekishiton generated light having a higher energy 2Eg crystal Si 1-x Ge x, as many crystal Si 1-x Ge It is necessary to absorb the inside of the x layer 14, as will be described later. This is because the film thicknesses of the crystalline Si 1-x Ge x layer 14 and the crystalline Si layer 15 and the crystalline Si 1-x Ge x layer 14 This is possible by appropriately selecting the Ge composition x.
  • the first carrier recombination loss is a loss due to recombination at the interface between the crystalline Si layer 15 and the passivation layer 16.
  • the crystalline Si 1-x Ge x / SiO 2 interface state density is higher than the crystalline Si / SiO 2 interface state density, and as a result, the crystalline Si 1-x Ge x solar cell has There is a problem that it is difficult to form a high-quality surface passivation film.
  • the crystalline Si layer 15 exists between the passivation layer 16 and the crystalline Si 1-x Ge x layer 14. For this reason, surface passivation is performed at the crystalline Si / SiO 2 interface, and a high-quality surface passivation film can be formed.
  • Recombination loss second carrier the interior of the crystal Si 1-x Ge crystal Si during the formation of the x layer 14 1-x Ge x layer 14, and the crystal Si 1-x Ge x layer 14 and the crystal Si substrate 11 It is a recombination loss due to a crystal defect generated in a region between.
  • a method for forming the crystalline Si 1-x Ge x layer 14 applying the method of using the composition graded buffer layer, when the crystal Si 1-x Ge x layer 14 of the Ge composition x is high, the recombination The loss is great. Therefore, in the solar battery cell of Example 1, the Ge buffer layer 12 is used to form the crystalline Ge layer 13 on the crystalline Si substrate 11, and then the crystalline Si 1-x on the crystalline Ge layer 13.
  • a Ge x layer 14 is formed. According to this method, the crystalline Ge layer 13 having a low crystal defect density can be formed. Therefore, when the Ge composition x of the crystalline Si 1-x Ge x layer 14 is high, the crystal defect density of the crystalline Si 1-x Ge x layer 14 formed on the crystalline Ge layer 13 can also be reduced. Moreover, since the film thickness of the Ge buffer layer 12 is smaller than the film thickness of the composition gradient buffer layer as compared with the method using the composition gradient buffer layer described above, carrier recombination inside the Ge buffer layer 12 is This is suppressed more than the carrier recombination inside the composition gradient buffer layer.
  • the third carrier recombination is a recombination loss inside the selective emitter.
  • three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31 form a selective emitter.
  • a selective emitter is formed for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, a part of the selective emitter becomes a surface electrode due to a difference in diffusion coefficient of phosphorus. It is formed in a region that is not shielded, and loss due to carrier recombination occurs.
  • the selective emitter is formed in a region shielded by the surface electrode 21 by performing multi-step dopant implantation using a plurality of masks having different opening widths when forming the selective emitter. Details of the manufacturing method will be described later, but the outline is as follows. First, as a first step, a selective emitter having a depth extending over three layers of a heavily doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31 is formed with a narrow opening width. It is formed using a mask. At this time, the opening width of the mask is set so that the width of the heavily doped crystal Ge layer 33 among the three layers is smaller than the width of the surface electrode 21.
  • a selective emitter is formed only in the surface region of the heavily doped crystal Si layer 31 using a mask having a wide opening width.
  • the opening width of the mask is set so that the width of the heavily doped crystal Si layer 31 is larger than the width of the opening of the passivation layer 16.
  • the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the heavily doped crystal Si 1-x Ge x layer 32 is obtained. Is smaller than the width of the heavily doped crystalline Si layer 31 at the interface between the heavily doped crystalline Si layer 31 and the surface electrode 21. Since the selective emitter formed by the above method is formed in a region shielded by the surface electrode 21, unlike the structure shown in FIG. 9, there is no increase in carrier recombination loss inside the selective emitter.
  • the recombination loss at the interface between the crystalline Si layer 15 and the passivation layer 16 the recombination loss due to crystal defects generated when the crystalline Si 1-x Ge x layer 14 is formed, and It is possible to reduce three of the recombination losses inside the selective emitter.
  • the first parameter is the Ge composition x of the crystalline Si 1-x Ge x layer 14. In determining the value of x, it is necessary to consider two points: improvement in utilization efficiency of multi-exciton generation and formation conditions of the crystalline Si 1-x Ge x layer 14.
  • the value of ⁇ ⁇ -2Eg is 0 or more and as small as possible.
  • the value of x is preferably in the range of 0 ⁇ x ⁇ 0.68, and in particular, the value of x is preferably as large as possible within the above range.
  • Example 1 conditions for forming the crystalline Si 1-x Ge x layer 14 will be described.
  • the lattice constant between the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14 is changed. It is desirable that the difference is small. For this reason, epitaxial growth can be easily performed when the value of x is large. From the above, it is desirable that the range is 0 ⁇ x ⁇ 0.68, and it is particularly desirable that the value of x is as large as possible within the above range.
  • the second parameter is the film thickness of the crystalline Si 1-x Ge x layer 14.
  • the thickness of the determination of the crystal Si 1-x Ge x layer 14 consideration of the two points of the light absorption in the crystal Si 1-x Ge x layer 14, the formation conditions of the crystal Si 1-x Ge x layer 14 There is a need to.
  • the crystalline Si 1-x Ge x layer 14 is a main generation layer for multi-exciton generation. For this reason, it is desirable that the high energy light used for generating multi-exciton is absorbed by the emitter layer 12 as much as possible. For example, light having energy higher than 2 eV, the thickness of the crystal Si 1-x Ge x layer 14 only required to absorb crystal Si 1-x Ge x layer 14, the light absorption coefficient, estimated to 2 ⁇ m It is.
  • the film thickness of the crystalline Si 1-x Ge x layer 14 is desirably 2 ⁇ m or less in terms of solar cell characteristics, and particularly within the above range, the film thickness of the crystalline Si 1-x Ge x layer 14 Is desirably as large as possible, but ultimately it is necessary to determine the film thickness of the crystalline Si 1-x Ge x layer 14 in consideration of the formation conditions.
  • the third parameter is the film thickness of the crystalline Si layer 15.
  • the thickness of the crystal Si layer 15 the light absorption in the crystal Si 1-x Ge x layer 14, is necessary to consider two points and diffusion of Ge from the crystal Si 1-x Ge x layer 14 is there.
  • the thickness of the crystalline Si layer 15 is smaller than the thickness of the crystalline Si 1-x Ge x layer 14 for the purpose of light absorption. This can be said to be an outstanding feature with respect to the structure disclosed in the above-described prior art document, which the structure of the first embodiment has.
  • the film thickness of the crystalline Si layer 15 is desirably 7 nm or more.
  • the film thickness of the crystalline Si layer 15 is desirably as small as possible within the above range.
  • FIG. 2A to FIG. 2L are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the first embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 1 is demonstrated based on Fig.2 (a)-FIG.2 (l).
  • a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, and a crystalline Si layer 15 are formed in this order on the surface of the crystalline Si substrate 11.
  • the formation method of the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 is preferably performed by an epitaxial growth method to reduce crystal defects.
  • the layer may be formed by other film forming methods such as a CVD method.
  • the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 is an emitter doped over the entire surface.
  • the doping may be performed during the film formation, or may be performed by a method such as ion implantation, gas phase diffusion, or solid phase diffusion after the film formation.
  • a mask 34 is formed on the surface of the crystalline Si layer 15.
  • the opening of the mask 34 is performed by lithography and etching or laser processing. Alternatively, a method in which the mask 34 is not initially formed in the opening portion of the mask 34 by a screen printing method or the like may be used.
  • FIG. 2A A top view of the structure after forming the mask 34 is shown in FIG. 2A, and a cross-sectional view is shown in FIG. 2B.
  • a heavily doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31 are formed.
  • a top view of the structure after formation is shown in FIG. 2C, and a cross-sectional view is shown in FIG.
  • Formation of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 can be performed by a diffusion method such as ion implantation or vapor phase diffusion. .
  • a diffusion method such as ion implantation or vapor phase diffusion.
  • activation after dopant implantation is performed by heat treatment or laser treatment.
  • FIG. 2C and FIG. 2D show the state after activation of the dopant.
  • the diffusion coefficient of the dopant varies depending on the Ge composition x of the crystalline Si 1-x Ge x , and in particular, the higher the Ge composition x, the larger the diffusion coefficient of phosphorus. Therefore, as shown in FIG. Further, among the three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31, the width of the heavily doped crystal Ge layer 33 is the largest, The width of the heavily doped crystal Si layer 31 is the smallest.
  • FIG. 2 (e) A top view of the structure after formation is shown in FIG. 2 (e), and a cross-sectional view is shown in FIG. 2 (f).
  • the mask 35 can be removed by a process such as ashing if the mask 35 is a resist, or by a process such as etching if the mask 35 is an insulating film.
  • the mask 35 to be re-formed can use the same material and formation method as the mask 34 used for the first time.
  • the heavily doped crystalline Si layer 31 is formed on the surface portion of the crystalline Si layer 15 using the mask 35.
  • a top view of the structure after formation is shown in FIG. 2G, and a cross-sectional view is shown in FIG.
  • the heavily doped crystalline Si layer 31 and the heavily doped crystalline Si 1-x Ge x are formed.
  • the width of the heavily doped crystal Si layer 31 at the interface with the layer 32 is smaller than the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the surface electrode 21.
  • the highly doped crystal Si layer 31 is formed when the above-described three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31 are formed. Similarly to the above, it can be carried out by an ion implantation method or a diffusion method such as vapor phase diffusion. However, in forming the heavily doped crystalline Si layer 31 this time, for example, the heat treatment for activating the dopant is shortened so that the dopant does not diffuse into the crystalline Si 1-x Ge x layer 14 and the crystalline Ge layer 13. It is necessary to use means such as.
  • the passivation layer 16 is formed by a thermal oxidation method, a plasma oxidation method, a CVD method, or the like. As described above, in order to form a high-quality surface passivation film, it is desirable to form the passivation layer 16 by a thermal oxidation method. However, if the thermal oxidation method is used, the passivation layer 16 is also formed on the back surface side of the crystalline Si substrate 11. 16 is formed. On the other hand, for example, when the plasma CVD method is used, the passivation layer 16 is not formed on the back side of the crystalline Si substrate 11.
  • a back electrode 22 is formed on the back side of the crystalline Si substrate 11.
  • a top view of the structure after formation is shown in FIG. 2 (i), and a cross-sectional view is shown in FIG. 2 (j).
  • the back electrode 22 is formed by a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
  • a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
  • the passivation layer 16 when the passivation layer 16 is formed also on the back surface side of the crystalline Si substrate 11, the crystalline Si substrate 11 in the passivation layer 16 is formed before the back surface electrode 22 is formed. It is necessary to remove the area on the back side of the.
  • the opening of the passivation layer 16 may be formed by a patterning method using lithography and etching, or a patterning method using an etching paste.
  • the width of the opening of the passivation layer 16 needs to be smaller than the width at the outermost surface of the heavily doped crystal Si layer 31. If the width of the opening of the passivation layer 16 is larger than the width at the outermost surface of the heavily doped crystalline Si layer 31, and as a result, the opening of the passivation layer 16 also exists above the crystalline Si layer 15, The crystalline Si layer 15, which is a layer having a relatively low doping concentration, and the surface electrode 21 are in direct contact, and carrier recombination loss occurs at the contact interface.
  • the surface electrode 21 is formed.
  • a top view of the structure after formation is shown in FIG. 2 (k), and a cross-sectional view is shown in FIG. 2 (l).
  • the surface electrode 21 is formed by a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
  • an opening is formed in the passivation layer 16 and then the surface electrode 21 is formed.
  • the opening is not formed in the passivation layer 16, and baking is performed after the surface electrode 21 is formed.
  • the surface electrode 21 and the heavily doped crystal Si layer 31 may be electrically connected to each other by a method using a so-called fire-through.
  • the shape seen from the upper surface of the opening of the passivation layer 16 is the same as the shape seen from the upper surface of the surface electrode 21.
  • the method of forming the opening in the passivation layer 16 it is possible to reduce the contact area between the surface electrode 21 and the heavily doped crystal Si layer 31.
  • the above is the method for manufacturing the solar battery cell of Example 1.
  • heat treatment, plasma treatment, etc. may be added as appropriate to improve the crystallinity and film quality of each film or to improve the quality of the interface with the adjacent film.
  • Example 2 of the present invention will be described with reference to FIGS. In the second embodiment, differences from the first embodiment will be mainly described.
  • FIG. 3A and FIG. 3B are a top view and a cross-sectional view showing the solar battery cell according to the second embodiment.
  • 3A is a top view
  • FIG. 3B is a cross-sectional view.
  • a Ge buffer layer 12 a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, a crystalline Si layer 15, and a passivation layer 16 are formed on a crystalline Si substrate 11, Furthermore, it is a solar cell in which a highly doped crystalline Si layer 31 in contact with a plurality of layers among the above layers is formed, and has a front electrode 21 and a back electrode 22 as electrodes.
  • FIG. 3B shows a structure in which the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are all patterned. Only the surface side of the Si layer 15 and the crystalline Si 1-x Ge x layer 14 is patterned, and other regions may not be patterned. Further, as shown in FIG.
  • FIG. 3B shows a case where the shape of the opening is a quadrangle, but an opening having another shape such as a round shape or a triangle may be formed.
  • the first point is that the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are not patterned in the first embodiment, whereas the first embodiment 2 indicates that any of the four layers is patterned.
  • the second point is that, in the first embodiment, the selective emitter is composed of three layers of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31. In contrast, in the second embodiment, the selective emitter is composed of only the heavily doped crystal Si layer 31.
  • the number of times of patterning associated with the formation of the selective emitter can be reduced as compared with the case of the first embodiment.
  • the selective emitter can be formed in a deeper region with respect to the surface of the solar battery cell.
  • the first effect the reduction in the number of times of patterning associated with the formation of the selective emitter, will be described.
  • patterning is performed twice using a mask 34 having different opening widths in order to form a selective emitter. Further, after forming the selective emitter, patterning for forming an opening of the passivation layer 16 is also necessary.
  • a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer are used to form a selective emitter by using a manufacturing method described later.
  • the second embodiment the number of times of patterning necessary for manufacturing the solar battery cell can be reduced as compared with the case of the first embodiment, so that the manufacturing at a lower cost is possible.
  • the formation depth of the selective emitter is determined by the reach distance of the dopant by the ion implantation method or the diffusion method. Specifically, the higher the ion implantation energy, the higher the diffusion and activation temperatures, and the longer the time, the more selective emitters are formed in deeper regions. However, if these parameters are changed, the width of the formed selective emitter is also changed, so that it is difficult to control only the depth of the selected emitter.
  • an opening is formed by patterning in at least one layer in order from the layer closest to the surface.
  • the depth of the opening can be controlled over a relatively wide range by using dry etching or wet etching having a different etching rate depending on the crystal orientation. Since the heavily doped crystal Si layer 31 serving as the selective emitter is formed along the shape of the opening, the depth of the opening determines the formation depth of the selective emitter.
  • a selective emitter can be formed in a deeper region than in the first embodiment, and as a result, carrier recombination can be reduced.
  • ⁇ Solar cell manufacturing method> 4 (a) to 4 (j) are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the second embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 2 is demonstrated based on Fig.4 (a)-FIG.4 (j).
  • FIG. 4A shows a top view of the structure after formation
  • FIG. 4B shows a cross-sectional view thereof.
  • FIG. 4C A top view of the structure after formation is shown in FIG. 4C, and a cross-sectional view is shown in FIG. 4D.
  • FIG. 4D shows a structure in which the opening reaches the surface side of the crystalline Si substrate 11. The opening can be formed by dry etching, wet etching, laser processing, or the like.
  • the crystalline Si substrate 11 has a (100) plane
  • the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are utilized by utilizing the difference in etching rate depending on the plane orientation.
  • crystalline Si a method of performing anisotropic etching with an alkaline solution is known.
  • crystal Ge a method of performing anisotropic etching with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and hydrofluoric acid is known.
  • FIG. 4E shows a top view of the structure after formation
  • FIG. 4F shows a cross-sectional view.
  • the highly doped crystal Si layer 31 is formed by a CVD method, an epitaxial growth method, or the like.
  • FIG. 4 (f) shows a structure in which the heavily doped crystal Si layer 31 is formed only on the front surface side, but depending on the method of forming the heavily doped crystal Si layer 31, a high concentration is also formed on the back surface side. Doped crystal Si layer 31 may be formed. In that case, it is necessary to remove the heavily doped crystalline Si layer 31 on the back side.
  • the passivation layer 16 on the back surface side is removed, and further, the front surface electrode 21 and the back surface electrode 22 are formed.
  • a top view of the structure after formation is shown in FIG. 4G, and a cross-sectional view is shown in FIG. 4H. Removal of the passivation layer 16 and formation of the front electrode 21 and the back electrode 22 are performed in the same manner as in the first embodiment.
  • a mask 34 is formed.
  • the width of the mask 34 is desirably larger than the width of the openings formed in the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15.
  • the surface electrode 21 and the heavily doped crystalline Si layer 31 thereunder are removed by etching using the mask 34.
  • a top view of the structure after removal is shown in FIG. 4 (i), and a cross-sectional view is shown in FIG. 4 (j).
  • dry etching In order to simultaneously remove the surface electrode 21 and the heavily doped crystalline Si layer 31 below the surface electrode 21, it is desirable to use dry etching. At that time, it is necessary to select conditions such as etching gas so that the passivation layer 16 below the heavily doped crystal Si layer 31 to be removed is not completely etched.
  • the solar cells shown in FIGS. 3 (a) and 3 (b) are formed. As described above, the solar battery cell of Example 2 can be manufactured.
  • Example 3 of the present invention will be described with reference to FIGS. In the third embodiment, differences from the second embodiment will be mainly described.
  • FIG. 5A and FIG. 5B are a top view and a cross-sectional view showing the solar battery cell according to the third embodiment.
  • FIG. 5A is a top view
  • FIG. 5B is a cross-sectional view.
  • a Ge buffer layer 12 a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, a crystalline Si layer 15, and a passivation layer 16 are formed on a crystalline Si substrate 11, An opening is formed with respect to the above-described layer, and the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 are formed on the sidewall of the opening.
  • the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 are: They are formed at positions in contact with the Ge buffer layer 12 or the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15 or the crystalline Si substrate 11, respectively.
  • the selective emitter is composed of only the heavily doped crystal Si layer 31.
  • the selective emitter is the heavily doped crystal Ge layer 33, the heavily doped crystal.
  • the crystal Si 1-x Ge x layer 32 and the highly doped crystal Si layer 31 are composed of three layers.
  • the depth of the opening formed for the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 as in the second embodiment. Therefore, for example, when the opening is formed only in two layers of the crystalline Si layer 15 and the passivation layer 16, the selective emitter is formed in the side portion of the crystalline Si layer 15. Only the heavily doped crystal Si layer 31 is provided.
  • Example 3 since wet etching can be used when processing the surface electrode 21 as described later, the case of Example 2 in which dry etching is used when processing the surface electrode 21 is used. In comparison, the damage introduced into the passivation layer 16 is reduced. Thereby, the recombination loss at the interface between the passivation layer 16 and the crystalline Si layer 15 can be reduced.
  • a method for manufacturing the solar battery cell of Example 3 will be described.
  • ⁇ Solar cell manufacturing method> 6 (a) to 6 (f) are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the third embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 3 is demonstrated based on Fig.6 (a)-FIG.6 (f).
  • the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 are formed on the surface of the crystalline Si substrate 11. These are formed in order, and openings are formed by patterning the above layers.
  • a top view of the structure after formation is shown in FIG. 6A, and a cross-sectional view is shown in FIG. 6B.
  • FIG. 6C A top view of the structure after formation is shown in FIG. 6C, and a cross-sectional view is shown in FIG. 6D.
  • the passivation layer 16 on the surface side can be used as a mask.
  • an ion beam is incident on the wafer in an oblique direction at the time of ion implantation.
  • FIG. 6E A top view of the structure after formation is shown in FIG. 6E, and a cross-sectional view is shown in FIG. 6F.
  • FIG. 6E and FIG. 6F show the structure after the surface electrode 21 is patterned.
  • a method using dry etching is desirable. Only the surface electrode 21 needs to be removed, and therefore wet etching can be used. As described above, when the surface electrode 21 is processed by wet etching, damage introduced into the passivation layer 16 is reduced as compared with dry etching.
  • the solar battery cell of Example 3 can be manufactured.
  • Example 4 of the present invention will be described with reference to FIGS. In the fourth embodiment, differences from the first embodiment will be mainly described.
  • FIG. 7A and FIG. 7B are a top view and a cross-sectional view showing the solar battery cell according to the fourth embodiment.
  • FIG. 7A is a top view
  • FIG. 7B is a cross-sectional view.
  • a buried oxide film 36, a crystalline Ge layer 13, and a crystalline Si 1-x Ge x layer 14 are formed on a crystalline Si substrate 11, and an opening is formed with respect to the above layer.
  • the solar cell is formed and further has a crystalline Si layer 15 and a passivation layer 16 formed on the opening, and has a front electrode 21 and a back electrode 22 as electrodes.
  • FIG. 7B shows a structure in which a buried oxide film 36 and a crystalline Si layer 15 are formed between the crystalline Si substrate 11 and the crystalline Ge layer 13. That is, a structure is shown in which the width of the opening of the buried oxide film 36 is larger than the width of the opening of the crystalline Ge layer 13 when the opening is formed. In order to reduce the series resistance of the solar battery cell, it is desirable that the width of the opening of the buried oxide film 36 is larger than the width of the opening of the crystalline Ge layer 13 as shown in FIG. The width of the opening of the oxide film 36 may be equal to or smaller than the width of the opening of the crystalline Ge layer 13.
  • the solar cell of the fourth embodiment since the Ge buffer layer 12 in the structure of the first embodiment is not necessary to form the crystalline Ge layer 13, the carriers generated inside the solar cell are Ge. It becomes possible to avoid recombination loss associated with passing through the buffer layer 12.
  • the solar cell of the fourth embodiment also uses the same method as in the first, second, and third embodiments in the inside of the selected emitter. It is possible to reduce the recombination loss at.
  • the manufacturing method of the photovoltaic cell of Example 4 will be described.
  • ⁇ Solar cell manufacturing method> 8A to 8N are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the fourth embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 3 is demonstrated based on FIG. 8A-FIG. 8N.
  • a Germanium On Insulator substrate (hereinafter referred to as a GeOI substrate) in which a buried oxide film 36 and a crystalline Ge layer 13 are formed in this order on a crystalline Si substrate 11 may be used. good.
  • the GeOI substrate is manufactured by a method such as the Smart Cut method using epitaxial growth of a crystalline Ge film, bonding of the substrates, and peeling.
  • FIG. 8A shows a top view after formation
  • FIG. 8B shows a cross-sectional view. Formation of the crystalline Si 1-x Ge x layer 14 can be performed by the same method as in the first embodiment.
  • openings are formed in the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14.
  • the opening can be formed by dry etching, wet etching, laser processing, or the like.
  • an opening is formed in the buried oxide film 36.
  • FIG. 8C shows a top view after formation
  • FIG. 8D shows a cross-sectional view.
  • the opening is preferably formed by wet etching. The reason for this is that if wet etching is used, unlike the methods such as dry etching and laser processing, side etching is performed on the buried oxide film 36 to reduce the width of the opening of the buried oxide film 36 to the crystalline Ge layer 13. This is because the width of the opening of the crystalline Si 1-x Ge x layer 14 can be made larger. Increasing the width of the opening of the buried oxide film 36 increases the contact area between the crystalline Si layer 15 and the crystalline Si substrate 11 to be formed thereafter, so that the series resistance of the solar cell can be reduced. it can.
  • FIG. 8E shows a top view after formation
  • FIG. 8F shows a cross-sectional view.
  • the crystalline Si layer 15 can be formed by an epitaxial growth method, a CVD method, or the like, as in the first embodiment.
  • FIG. 8G shows a top view after formation
  • FIG. 8H shows a cross-sectional view.
  • FIG. 8 (i) A top view of the structure after formation is shown in FIG. 8 (i), and a cross-sectional view is shown in FIG. 8 (j).
  • 8 (i) and 8 (j) show the structure after the surface electrode 21 is patterned.
  • the patterning of the surface electrode 21 can be performed by a method such as dry etching or wet etching.
  • the width of the region of the passivation layer 16 that is not removed is the opening of the crystalline Si 1-x Ge x layer 14. It is desirable to be larger than the width of.
  • the surface electrode 21 has a crystalline Si 1-x Ge x layer. This is because it is necessary to be formed so as to straddle the ends of the 14 openings, which increases the risk of disconnection.
  • the solar battery cell of Example 4 can be manufactured.
  • Example 5 of the present invention will be described with reference to FIG.
  • the fifth embodiment is an example of a solar battery system using the solar battery cells described in the first, second, third, and fourth embodiments.
  • FIG. 11 is a configuration diagram illustrating a solar battery system using the solar battery cells according to the fifth embodiment.
  • the fifth embodiment is a solar battery system using the solar battery cells of the first, second, third, and fourth embodiments.
  • the solar cell system includes a solar cell panel 41, a connection box 42, a current collection box 43, a power conditioner 44, and a transformer 45.
  • the solar battery panel 41 is a solar battery panel in which a plurality of the solar battery cells described in Examples 1, 2, 3, and 4 are arranged.
  • the solar cell panel 41 is a panel that generates electric power by sunlight.
  • the connection box 42 is a connection box that transmits the electric power generated by the solar cell panel 41 to the current collection box 43.
  • the current collection box 43 is a current collection box that collects the electric power transmitted from the connection box 42 and transmits it to the power conditioner 44.
  • the power conditioner 44 is a converter that converts the electric power transmitted from the current collection box 43 from direct current to alternating current and transmits the electric power to the transformer 45.
  • the transformer 45 is a transformer that transforms the voltage of the AC power transmitted from the power conditioner 44 and transmits it to the commercial power system 46.
  • three power conditioners 44 and a current collection box 43 are connected to one transformer 45 connected to the commercial power system 46. Further, a three-system connection box 42 and a solar cell panel 41 are connected to each one-system power conditioner 44 and current collection box 43.
  • the electric power generated by the solar cell panel 41 is transmitted to the connection box 42 and collected by the current collection box 43. Thereafter, the power conditioner 44 converts the voltage from direct current to alternating current, collectively transforms the voltage with the transformer 45, and connects to the commercial power system 46.
  • the said structure is a structural example of the mega solar system with many panel numbers especially in a solar cell system. In the case of a residential system with a relatively small number of panels, it is directly connected to the power conditioner 44 from the connection box 42.
  • the solar cell system of Example 5 can be realized.
  • the solar cell system of Example 5 it is possible to increase the efficiency of solar power generation by taking advantage of the effect of the solar cell structure.

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  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne une cellule solaire qui est conçue de telle sorte que la cellule solaire comporte : un substrat de Si cristallin doté d'une première polarité (11); une couche tampon de Ge (12) formée sur une surface du substrat de Si cristallin doté de la première polarité (11); une couche de Ge cristallin (13) formée sur une surface de la couche tampon de Ge (12); une couche de Si1-xGex cristallin dotée d'une seconde polarité (14) formée sur une surface de la couche de Ge cristallin (13); une couche de Si cristallin dotée de la seconde polarité (15) formée sur une surface de la couche de Si1-xGex cristallin dotée de la seconde polarité (14); une couche de passivation (16) formée sur une surface (15) de la couche de Si cristallin dotée de la seconde polarité, ladite couche de passivation étant constituée d'un matériau isolant; une couche de Si cristallin dopée à concentration élevée dotée de la seconde polarité (31) formée à l'intérieur d'un même plan dans lequel est formée la couche de Si cristallin dotée de la seconde polarité (15); et une électrode de surface (21) formée sur une surface de la couche de Si cristallin dopée à concentration élevée dotée de la seconde polarité (31). La cellule solaire est également conçue de telle sorte que la largeur de la couche de Si cristallin dopée à concentration élevée dotée de la seconde polarité (31) au niveau de l'interface entre la couche de Si cristallin dopée à concentration élevée dotée de la seconde polarité (31) et l'électrode de surface (21) est supérieure à la largeur de la couche de Si cristallin dopée à concentration élevée dotée de la seconde polarité (31) au niveau de l'interface entre la couche de Si cristallin dopée à concentration élevée dotée de la seconde polarité (31) et la couche de Si1-xGex cristallin dotée de la seconde polarité (14). En conséquence, l'invention fournit une cellule solaire très efficace, permettant à la fois une utilisation de génération multiexciton et une réduction de perte de recombinaison des porteurs.
PCT/JP2014/079521 2014-11-07 2014-11-07 Cellule solaire Ceased WO2016072005A1 (fr)

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Citations (5)

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JP2006073833A (ja) * 2004-09-02 2006-03-16 Sharp Corp 太陽電池セルおよびその製造方法
WO2010075606A1 (fr) * 2008-12-29 2010-07-08 Shaun Joseph Cunningham Dispositif photo-voltaïque amélioré
WO2010094919A2 (fr) * 2009-02-19 2010-08-26 Iqe Silicon Compounds Limited Cellule photovoltaïque
WO2011012382A2 (fr) * 2009-07-31 2011-02-03 International Business Machines Corporation Structure basée sur une tranche de silicium pour cellules solaires à hétérostructure
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JP2006073833A (ja) * 2004-09-02 2006-03-16 Sharp Corp 太陽電池セルおよびその製造方法
WO2010075606A1 (fr) * 2008-12-29 2010-07-08 Shaun Joseph Cunningham Dispositif photo-voltaïque amélioré
WO2010094919A2 (fr) * 2009-02-19 2010-08-26 Iqe Silicon Compounds Limited Cellule photovoltaïque
WO2011012382A2 (fr) * 2009-07-31 2011-02-03 International Business Machines Corporation Structure basée sur une tranche de silicium pour cellules solaires à hétérostructure
US20110120538A1 (en) * 2009-10-23 2011-05-26 Amberwave, Inc. Silicon germanium solar cell

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M.WOLF: "Solar cell efficiency and carrier multiplication in Sil-xGex alloys", JOURNAL OF APPLIED PHYSICS, vol. 83, no. 8, 1998, pages 4213 - 4221, XP012045017, DOI: doi:10.1063/1.367177 *
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