WO2016049245A1

WO2016049245A1 - Passivated contact solar cells and methods for manufacturing

Info

Publication number: WO2016049245A1
Application number: PCT/US2015/051809
Authority: WO
Inventors: Atul Gupta; Ajeet Rohatgi; Vijay Nag YELUNDUR
Original assignee: Suniva Inc
Current assignee: Suniva Inc
Priority date: 2014-09-24
Filing date: 2015-09-24
Publication date: 2016-03-31
Anticipated expiration: 2017-03-24

Abstract

A device having passivated contacts and capable of withstanding processing temperatures above 700°C is disclosed, together with a solar cell having passivated contacts and being capable of converting solar energy to electrical energy with an efficiency of at least 20%. Also disclosed herein are methods of making the disclosed device and the solar cell.

Description

PASSIVATED CONTACT SOLAR CELLS AND METHODS FOR

MANUFACTURING

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of United States Provisional Application No. 62/054,662, filed September 24, 2014, which is hereby incorporated herein by reference in its entirety.

FIELD OF INVENTION

[0002] This disclosure relates generally to semiconductor devices, and more particularly to solar cells and methods for manufacturing solar cells.

BACKGROUND

[0003] Solar cells are devices that can convert solar radiation to electrical energy. On a clear day, the sun provides approximately one thousand watts of energy per square meter almost everywhere on the planet's surface. Various solar cell structures have been described over the last few decades of research; however, to date, photovoltaic or solar cells typically have a relative low overall efficiency. The performance or efficiency of a solar cell is typically described as a product of three (3) interdependent electrical parameters, namely short circuit current density (Jsc), open circuit voltage (Voc) and fill factor (FF). Efforts to maximize Jsc have been focused on maximizing adsorption of sunlight within the cell by minimizing reflection from the exposed cell surface, maximizing light trapped within the cell by improving reflectance from the back, maximizing the creation of free carriers though improved bulk material properties, and minimizing recombination of photo-generated charge carriers throughout the device. While these improvements also help increase the open circuit voltage of the solar cells, the voltage potential of most solar cells is fundamentally limited by

recombination within the device. Additionally, development of efficient solar cells is further limited due to metal contacts, used to conduct the charge from the solar cell to external loads. By their very nature, such solar cells suffer from the infinite recombination rate of carriers at the interface of the metal contact and semiconductor substrate. Thus, to approach the theoretical limit of solar cell efficiency, carrier-selective contacts capable of withstanding high processing temperatures, with low minority carrier recombination and efficient majority carrier transport, are needed.

[0004] Accordingly, there remains a need in the solar cell industry for solar cells and methods for manufacturing solar cells that address the aforementioned deficiencies and /or inadequacies. This need and other needs are satisfied by the various aspects of the present disclosure.

SUMMARY OF THE INVENTION

[0005] In accordance with the purposes of the invention, as embodied and broadly described herein, the invention provides a device having a front side and a back side opposite to the front side, comprising: a) a silicon substrate, wherein at least a portion of the substrate is textured; b) a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the front side; c) a second heavily doped polycrystalline silicon layer superposed on the silicon substrate on the back side and having a doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer; d) a first dielectric layer interposed between the first heavily doped polycrystalline silicon layer and the silicon substrate; and e) and a first metal contact positioned on the front side and a second metal contact positioned on the back side.

[0006] In further aspects, the invention also relates to a solar cell having a front side and a back side opposite to the front side comprising: a) a silicon substrate textured on the front side; b) an emitter layer comprising a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the front side, wherein the emitter layer forms a front junction with the silicon substrate; c) a first dielectric layer interposed between the emitter layer and the silicon substrate; d) a first metal contact making an electrical connection to the emitter layer on the front side of the solar cell; e) a second metal contact making an electrical connection to the substrate on the back side of the solar cell; and f) and the first metal contact and the second metal contact being configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%.

[0007] In yet further aspects, the invention is also directed to a method of forming a device having a front side and a back side opposite to the front side comprising: a) providing a silicon substrate; b) texturing at least a portion of the silicon substrate; c) forming a first dielectric layer on the front side of the silicon substrate; d) forming a first heavily doped polycrystalline silicon layer and a second heavily doped polycrystalline silicon layer, wherein the first heavily doped polycrystalline silicon layer has a thickness of greater than about 20 nm to about 5 μιη, and wherein the first heavily doped polycrystalline silicon forms a junction with the front side of the substrate; e) forming at least one coating layer, wherein the at least one coating layer comprises: i) an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the front side; ii) a back reflector positioned over the second heavily doped polycrystalline silicon layer on the back side; or iii) a combination thereof; f) forming at least one metal contact comprising: iv) the at least one first metal contact is formed on at least a portion of the front side; and v) the at least one second metal contact is formed on at least a portion of the back side; and g) configuring the at least one first and the at least one second metal contacts to allow an external electrical circuit to be powered by the device.

[0008] While aspects of the present invention can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience only, and one of skill in the art would understand that each aspect of the present invention can be described and claimed in any statutory class. Unless otherwise expressly stated, it is no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or description that the steps are to be limited to a specific order, it is no way intended that an order be inferred in any respect.

[0009] Additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or can be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying figures, which are incorporated in and constitute a part of this specification, illustrate several aspects and together with the description serve to explain the principles of the invention. [0011] FIG. 1 illustrates a cross-sectional view of a passivated contact device, in accordance with an exemplary aspect of the present invention.

[0012] FIG. 2 illustrates a flow chart for one aspect of a solar cell fabrication process.

[0013] FIG. 3 illustrates a flow chart for another aspect of a solar cell fabrication process.

DETAILED DESCRIPTION

[0014] The present invention can be understood more readily by reference to the following detailed description of the invention.

[0015] Before the present compounds, compositions, articles, systems, devices, and/or methods are disclosed and described, it is to be understood that they are not limited to specific synthetic methods unless otherwise specified, or to particular reagents unless otherwise specified, as such can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, exemplary methods and materials are now described.

[0016] Moreover, it is to be understood that unless expressly stated otherwise, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect.

[0017] All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

A. DEFINITIONS

[0018] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. As used in the specification and in the claims, the term "comprising" can include the aspects "consisting of and "consisting essentially of." Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. In this specification and in the claims which follow, reference will be made to a number of terms which shall be defined herein.

[0019] As used in the specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a solar cell" includes two or more solar cells.

[0020] As used herein, the term "combination" is inclusive of devices, cells, alloys, layers, and the like.

[0021] As used herein, the terms "about" and "at or about" mean that the amount or value in question can be the value designated some other value approximately or about the same. It is generally understood, as used herein, that it is the nominal value indicated up to ±10% variation unless otherwise indicated or implied. The term is intended to convey that similar values promote equivalent results or effects recited in the claims. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art. In general, an amount, size, formulation, parameter or other quantity or characteristic is "about" or "approximate" whether or not expressly stated to be such. It is understood that where "about" is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0022] Ranges can be expressed herein as from "about" one particular value, and/or to "about" another particular value. When such a range is expressed, another aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent 'about,' it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as "about" that particular value in addition to the value itself. For example, if the value "10" is disclosed, then "about 10" is also disclosed. It is also understood that each unit between two particular units are also disclosed. For example, if 10 and 15 are disclosed, then 1 1, 12, 13, and 14 are also disclosed. [0023] The terms "first," "second," "first part," "second part," and the like, where used herein, do not denote any order, quantity, or importance, and are used to distinguish one element from another, unless specifically stated otherwise.

[0024] As used herein, the terms "optional" or "optionally" means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0025] Moreover, it is to be understood that unless otherwise expressly stated, it is in no way intended that any method set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not actually recite an order to be followed by its steps or it is not otherwise specifically stated in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible non-express basis for interpretation, including: matters of logic with respect to arrangement of steps or operational flow; plain meaning derived from grammatical organization or punctuation; and the number or type of aspects described in the specification.

[0026] Disclosed are materials to be used in the preparation of components of the invention, the components of the invention themselves, and methods for the manufacture and use of such components. These and other materials are disclosed herein, and it is understood that when combinations, subsets, interactions, groups, etc. of these materials are disclosed that while specific reference of each various individual and collective combinations and permutation of these materials cannot be explicitly disclosed, each is specifically contemplated and described herein. For example, if a particular component is disclosed and discussed and a number of modifications that can be made to a number of materials including the components are discussed, specifically contemplated is each and every combination and permutation of the components and the modifications that are possible unless specifically indicated to the contrary. Thus, if a class of materials A, B, and C are disclosed as well as a class of materials D, E, and F and an example of a combination materials, A-D is disclosed, then even if each is not individually recited each is individually and collectively contemplated meaning combinations, A-E, A-F, B-D, B-E, B-F, C-D, C-E, and C-F are considered disclosed.

Likewise, any subset or combination of these is also disclosed. Thus, for example, the subgroup of A-E, B-F, and C-E would be considered disclosed. This concept applies to all aspects of this application including, but not limited to, steps in methods of making and using the compositions of the invention. Thus, if there are a variety of additional steps that can be performed it is understood that each of these additional steps can be performed with any specific aspect or combination of aspects of the methods of the invention.

[0027] As used herein, the term or phrase "sufficient," "sufficient thickness," "sufficient amount," or "conditions sufficient to" refers to such thickness, amount or condition that is capable of performing the function or property for which a sufficient thickness or amount is expressed. As will be pointed out below, the exact thickness, amount, or particular condition required can vary from one aspect to another, depending on recognized variables such as the materials employed and the processing conditions observed; however, it should be understood that an appropriate effective thickness, amount, or condition could be readily determined by one of ordinary skill in the art in possession of this disclosure using only routine

experimentation.

[0028] As used herein, the term "substantially," when used in reference to a composition, refers to more than about 98% by weight, more than about 98.5% by weight, more than about 99 % by weight, more than about 99.5 % by weight, or more than about 99.9 % by weight, based on the total weight of the composition, of a specified feature or component.

[0029] It is understood that the devices disclosed herein have certain functions. Disclosed herein are certain structural requirements for performing the disclosed functions and it is understood that there are a variety of structures that can perform the same function that are related to the disclosed structures, and that these structures will typically achieve the same result.

B. DEVICE

[0030] Solar energy is an ideal resource because it is clean and reliable. Solar cells are devices that convert solar energy into electrical energy. These devices are also often called photovoltaic (PV) cells. Solar cells are manufactured from a wide variety of semiconductors. One common semiconductor material frequently used in solar cells is crystalline silicon. A typical solar cell comprises at least three main elements: (1) a substrate; (2) a semiconductor junction; and (3) conductive contacts. Semiconductors, such as silicon, can be doped with a charge carrier, which can be an n-type or a p-type dopant. When an n-type silicon and a p-type silicon are formed in contact with one another, the region in the solar cell where they meet is referred to as a semiconductor junction, or "p-n junction." The semiconductor can absorb light, and the light energy can be transferred to the valence electron of an atom in a silicon layer, allowing the valence electron to escape its bound state and leave a hole. These photo-generated electrons and holes are separated by the electric field associated with the p-n junction. The conductive contacts allow current to flow from the solar cell to an external circuit.

[0031] The device described herein can comprise a first surface and an opposing second surface. In one exemplary and non-limiting aspect, the first surface can be located on a front side of the device. In such an aspect, the first surface can comprise a front surface. In a further exemplary and non-limiting aspect, the second surface can be located opposite to the first surface, for example, on a back side of the device. In such an exemplary aspect, the second surface is a back surface. It should be understood that the invention is not intended to be limited by any specific geometry or orientation of the device or a portion thereof, and that, in some aspects, the terms first surface, second surface, and the like, can refer to surfaces other than as described herein. It should also be understood that when the terms front side or back side are used herein, no specific geometry is implied and that the terms first surface and second surface can be used interchangeably.

[0032] As briefly described above, the present disclosure relates, in one aspect, to a device having a front side and a back side opposite to the front side, comprising: (a) a silicon substrate, wherein at least a portion of the substrate is textured; (b) a first heavily doped polycrystalline silicon layer having a first doping type superposed on the silicon substrate on the front side; (c) a second heavily doped polycrystalline silicon layer superposed on the silicon substrate on the back side and having a second doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer; (d) a first dielectric layer interposed between the first heavily doped polycrystalline silicon layer and the silicon substrate; and e) a first metal contact positioned on the front side and a second metal contact positioned on the back side.

[0033] FIG. 1 schematically illustrates a cross-section of a passivated contact device 100 in accordance with an aspect of the present invention. The device 100 comprises an absorber layer or a silicon substrate 101, having a front side (an exemplary first surface) 102 and a back side (an exemplary second surface) 103 opposite to the front side. In one aspect, the silicon substrate 101 is a crystalline silicon. In another aspect, the silicon substrate 101 can comprise a monocrystalline silicon. In yet another aspect, the silicon substrate 101 can comprise a multicrystalline silicon. In one aspect, the silicon substrate 101 can comprise an n-type doped silicon or a p-type doped silicon. In yet another aspect, the silicon substrate 101 is an n-type silicon. In a further aspect, the silicon substrate 101 is a p-type silicon. In a yet further aspect, at least a portion of the silicon substrate 101 is textured.

[0034] In some aspects, fabrication of a high-efficiency silicon solar cell can require the presence of textured surfaces capable of reducing reflectance, since optical losses due to reflectance of incident solar radiation are one of the most important factors limiting cell efficiency.

[0035] In one aspect, the device schematically shown on FIG.1 satisfies at least one of conditions (l)-(3): (1) the at least a portion of the silicon substrate 101 can be textured on the front side to form a front side 102 that is textured; (2) the at least a portion of the silicon substrate 101 can be textured to form a back side 103 that is textured; (3) the at least a portion of the substrate 101 can be textured on the front side 102 and the back side 103. In one aspect, when at least a portion of the front side 102 is textured, at least a portion of the back side 103 is planarized. In another aspect, the back side 103 is planarized.

[0036] In some aspects, the textured substrate comprises a plurality of atomically smooth facets. In other aspects, the atomically smooth facets can comprise a plurality of pyramid shaped structures on the surface of the textured substrate. In one aspect, such pyramid shaped structures are randomly formed pyramids. In another aspect, such pyramid shaped structures can be ordered in a predetermined pattern.

[0037] In some aspects, the n-type silicon substrate comprises a long lifetime n-type silicon wafer having a thickness of about 100 μιη to about 250 μιη, including exemplary values of about 110 μιη, about 120 μιη, about 130 μιη, about 140 μιη, about 150 μιη, about 160 μιη, about 170 μιη, about 180 μιη, about 190 μιη, about 200 μιη, about 210 μιη, about 220 μιη, about 230 μιη, and about 240 μιη, as measured from the back side surface 103 to a tip of the textured front side surface of the substrate 102.

[0038] In some aspects, and as illustrated in FIG. 1, the device can further comprise a first heavily doped polycrystalline silicon 105 having a first polarity on the first surface of the silicon substrate. In one aspect, the first heavily doped polycrystalline silicon can have a doping type comprising an n-type or a p-type. In another aspect, the first heavily doped polycrystalline silicon 105 has an n-type doping. In yet another aspect, the first heavily doped polycrystalline silicon 105 has a p-type doping. In a further aspect, the first heavily doped polycrystalline silicon 105 has a doping type of an opposite polarity to the silicon substrate. In a further aspect, the first heavily doped polycrystalline silicon 105 has a doping type of the same polarity as the silicon substrate. In another aspect, the first heavily doped polycrystalline silicon 105 can further comprise carbon. In one aspect, the first heavily doped polycrystalline silicon layer has an active dopant concentration greater than about lxlO¹⁹ at/cm³, or greater than about lxlO²⁰ at/cm³. In another aspect, the active dopant concentration is about 2xl0²¹ at/cm³ or less. In some aspects, the first heavily doped polycrystalline silicon can have a sheet resistance of from about 40 Ohm/sq to about 1000 Ohm/sq, including exemplary values of about 50 Ohm/sq, about 75 Ohm/sq, about 100 Ohm/sq, about 125 Ohm/sq, about 150 Ohm/sq, about 170 Ohm/sq, about 200 Ohm/sq, about 220 Ohm/sq, about 250 Ohm/sq, about 270 Ohm/sq, about 300 Ohm/sq, about 320 Ohm/sq, about 350 Ohm/sq, about 400 Ohm/sq, about 500 Ohm/sq, about 600 Ohm/sq, about 700 Ohm/sq, and about 800 Ohm/sq. In another aspect, the first heavily doped polycrystalline silicon layer forms a front side pn junction with the silicon substrate. In yet another aspect, the first heavily doped polycrystalline silicon layer is compatible with high temperatures required in the manufacturing of the silicon based devices. In a further aspect, the band structure of the first heavily doped polycrystalline silicon layer is substantially identical to the silicon substrate. In some aspects, the first heavily doped polycrystalline silicon layer exhibits an indirect bandgap. As one of ordinary skill in the art would readily appreciate, the indirect bandgap of the first heavily doped polycrystalline silicon layer can enable the use of a thicker layer without significant losses due to absorption in the first heavily doped polycrystalline silicon layer. In some aspects, the first heavily doped polycrystalline silicon layer can serve as a front surface field forming a high-low junction. In some aspects, where the first heavily doped polycrystalline silicon layer comprises the carbon doping, the first heavily doped polycrystalline silicon layer has a larger bandgap than the substrate. In such exemplary aspects, the disclosed device allows more light to pass through the first heavily doped polycrystalline silicon layer with absorption losses therein.

[0039] In some aspects, the device can comprise a second heavily doped polycrystalline silicon layer 106 having a second polarity on the second surface of the silicon substrate. In one aspect, the second heavily doped polycrystalline silicon layer 106 can have a doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer. In another aspect, the second heavily doped polycrystalline silicon can comprise an n-type or a p-type dopants. In another aspect, the second heavily doped polycrystalline silicon 106 has an n-type doping, when the first heavily doped polycrystalline silicon 105 has a p-type doping. In yet another aspect, the second heavily doped polycrystalline silicon 106 has a p-type doping, when the first heavily doped polycrystalline silicon 105 has an n-type doping.

[0040] In some aspects, the thickness of the first heavily doped polycrystalline silicon layer is greater than about 20 nm to about 5 μιη, including exemplary values of about 50 nm, about 100 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 450 nm, about 500 nm, about 550 nm, about 600 nm, about 650 nm, about 700 nm, about 750 nm, about 800 nm, about 850 nm, about 900 nm, about 950 nm, about 1 μιη, about 1.5 μιη, about 2 μιη, about 2.5 μιη, about 3 μιη, about 3.5 μιη, about 4 μιη, and about 4.5 μιη. In one aspect, the thickness of the of the first heavily doped polycrystalline silicon can be determined by one of ordinary skill in the art to ensure a lateral conductivity sufficient to enable higher efficiency in the cell while being sufficiently thin to minimize carrier absorption. In one aspect, the thickness can be determined by a sheet resistance of the polycrystalline silicon layer. In some aspects, the sheet resistance of the first heavily doped polycrystalline silicon layer is from about 40 Ohm/sq to about 200 Ohm/sq if the first heavily doped polycrystalline silicon has an opposite polarity to the substrate and, from about 40 Ohm/sq to about 1,000 Ohm/sq if the first heavily doped polycrystalline silicon has the same polarity as the substrate.

[0041] In other aspects, the thickness of the second heavily doped polycrystalline silicon layer can be same or thinner than the thickness of the first heavily doped polycrystalline silicon layer. In some aspects, the thickness of the second heavily doped polycrystalline silicon layer is about 10 nm or greater to about 1 μιη or less, including exemplary values of about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, about 50 nm, about 55 nm, about 60 nm, about 65 nm, about 70 nm, about 75 nm, about 80 nm, about 85 nm, about 90 nm, about 95 nm, about 100 nm, 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 450 nm, about 500 nm, about 550 nm, about 600 nm, about 650 nm, about 700 nm, about 750 nm, about 800 nm, about 850 nm, about 900 nm, and about 950 nm. [0042] In some aspects, the device can further comprise a first dielectric layer 104 that is interposed between the first heavily doped polycrystalline silicon 105 and the silicon substrate 101. In certain aspects, the first dielectric layer can comprise a chemical oxide layer or a thermal oxide layer. In other aspects, the first dielectric layer can be deposited by the methods described below.

[0043] In certain aspects, the first dielectric layer comprises a tunneling dielectric layer. As one of ordinary skill in the art would readily appreciate the first dielectric layer 104 needs to be sufficiently thin to allow selective transport of holes or electrons through the dielectric layer. In one aspect, the first dielectric layer 104 can exhibit passivation qualities. In some aspects, the first dielectric layer has a thickness from about 0.5 to about 3.5 nm, including exemplary values of about 0.6 nm, about 0.7 nm, about 0.8 nm, about 0.9 nm, about 1.0 nm, about 1.1 nm, about 1.2 nm, about 1.3 nm, about 1.4 nm, about 1.5 nm, about 1.6 nm, about 1.7 nm, about 1.8 nm, about 1.9 nm, about 2.0 nm, about 2.1 nm, about 2.2 nm, about 2.3 nm, about 2.4 nm, about 2.5 nm, about 2.6 nm, about 2.7 nm, about 2.8 nm, about 2.9 nm, about 3.0 nm, about 3.1 nm, about 3.2 nm, about 3.3 nm, and about 3.4 nm. In further aspects, the first dielectric layer 104 has a bandgap at least about 0.2 eV larger than the silicon substrate 101. In some aspects, the first dielectric layer 104 has a bandgap at least about 0.5 eV, at least about 1 eV, at least about 1.5 eV, at least about 2 eV, at least about 2.5 eV, at least about 3 eV, at least about 3.5 eV, at least about 4 eV, at least about 4.5 eV, at least about 5 eV, at least about 5.5. eV, at least about 6 eV, at least about 6.5 eV, at least about 7 eV, at least about 7.5 eV, at least about 8 eV, at least about 8.5 eV, at least about 9 eV, at least about 9.5 eV, or about 10 eV larger than the silicon substrate. In some aspects, the first dielectric layer 104 can comprise a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy), an aluminum oxide film (AlOx), a hafnium oxide film (HfOx), or a combination thereof.

[0044] In some aspects, the device of the current invention can further comprise a second dielectric layer 104a interposed between the second heavily doped polycrystalline silicon layer and the silicon substrate. In one aspect, the second dielectric layer is the same as or different from the first dielectric layer.

[0045] In certain aspects, the larger bandgap of the first dielectric layer 104 and/or the second dielectric layer 104a introduces positive offsets in the conduction and/or valence bands relative to the silicon substrate 101. In some aspects, the offsets in the valence and conduction bands can provide effective barriers to minority carrier transport across the dielectric layer while selectively allowing majority carrier transport (in the heavily doped poly crystalline silicon layers across the dielectric layer). This selective nature of carrier transport enables excellent surface passivation characteristics for the absorber layer and can significantly reduce recombination current densities in the junctions to allow formation of a device exhibiting high cell open circuit voltages. Without wishing to be bound by theory, the inventive device can eliminate the negative effects of having photo-generated carrier recombination in the first and the second heavily doped polycrystalline silicon layers surrounding the silicon substrate by preventing the photo-generated carriers from crossing over to the regions having a higher dopant concentration.

[0046] In certain aspects, the first and/or the second dielectric layers can be "optically transparent." In one aspect, as used herein, the term "optically transparent" refers to the substantially low absorption of photons. In further aspects, the first 104 and the second dielectric 104a layers interposed between the silicon substrate 101 and the first 105 and the second 106 heavily doped polycrystalline silicon layers, respectively, are stable at high temperature processes and can withstand a processing temperature of at least about 700 °C, at least about 750 °C, at least about 800 °C, at least about 850 °C, at least about 900 °C, at least about 950 °C, or at least about 1,000 °C. In other aspects, the first and the second dielectric layer exhibit very few atomic defects and/or electrical states within the bandgap. In other aspects, the first and/or the second dielectric layers are not optically transparent.

[0047] In certain aspects, and as illustrated in FIG. 1, the device can further comprise at least one coating layer. In some aspects, the device can further comprise a first coating and a second coating. In certain aspects, the first coating can be disposed on the first surface. In other aspects, the second coating can be disposed on the second surface.

[0048] In some aspects, the at least one coating layer can be an antireflective coating 107 that is positioned over the first heavily doped polycrystalline silicon layer on the front side. In one aspect, the antireflective coating helps improve solar radiation collection efficiency. In another aspect, the antireflective coating 107 comprises a film that is selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O₂), aluminum oxide (AlOx), and titanium oxide (T1O₂) films. In some aspects, the antireflective coating 107 is a silicon nitride film. In other aspects, the silicon nitride film exhibits a refractive index of from about 1.9 to about 2.3, including exemplary values of about 1.95, about 2.0, about 2.05, about 2.1, about 2.15, about 2.2, and about 2.25. In further aspects, the antireflective film can comprise a graded index silicon nitride film. In yet further aspects, the antireflective coating comprises titanium oxide with a refractive index of from about 2.1 to about 2.4, including exemplary values of about 2.15, about 2.2, about 2.25, about 2.3, and about 2.35. In one aspect, the antireflective film has a thickness of from about 40 nm to about 90 nm, including exemplary values of about 45 nm, about 50 nm, about 55 nm, about 60 nm, about 65 nm, about 70 nm, about 75 nm, about 80 nm, and about 85 nm.

[0049] In other aspects, the at least one coating layer comprises a back reflector film 107a positioned over the second heavily doped polycrystalline silicon layer on the back side. In one aspect, the back reflector 107a comprises a film that is selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O₂), aluminum oxide (AlOx), titanium oxide (T1O₂), graphene, carbon nanotubes, and a transparent conductive oxide (TCO). In some aspects, the transparent conductive oxide layer can comprise indium tin oxide (ITO), fluorine doped ZnO (FTO), aluminum doped zinc oxide (AZO), indium gallium oxide (IGO), or any combination thereof. In other aspects, the at least one coating layer positioned over the second heavily doped polycrystalline silicon layer on the back side does not comprise a transparent conductive oxide (TCO). In one aspect, the back reflector film has a thickness from about 30 nm to about 200 nm, including exemplary values of about 40 nm, about 50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about 100 nm, about 110 nm, about 120 nm, about 130 nm, about 140 nm, about 150 nm, about 160 nm, about 170 nm, about 180 nm, and about 190 nm.

[0050] In certain aspects, the inventive device comprises at least two coating layers, wherein the two coating layers comprise an antireflective coating and a back reflector.

[0051] In a further aspect and as illustrated in FIG. 1, the device comprises at least one first metal contact 108 making an electrical connection with the first heavily doped polycrystalline silicon layer. In one aspect, the at least one first metal contact is screen printed. In some aspects, the at least one first metal contact 108 comprises a pattern with gridlines to collect the current from the contact layer and transport to the interconnect points that connect one cell to the next in a panel. In one aspect, the at least one first metal contact is silver (Ag). In yet another aspect, the at least one first metal contact is aluminum (Al). In yet another aspect, the at least one first metal contact is an alloy of aluminum and silver. In yet another aspect, the at least one first metal contact has a size sufficient to minimize the sum of resistive and optical power losses in the panel. In a further aspect, the at least one first metal contact comprises a substantially rectangular grid pattern with thin gridlines having width of from about 30 μιη to about 150 μιη. In another aspect, the at least one first metal contact comprises a substantially rectangular grid pattern with thing gridlines spaced from about 0.3 mm to about 2.5 mm apart ending in perpendicularly oriented busbars. In yet another aspect, the width of the

perpendicularly oriented busbars can be from about 0.1 mm to about 3 mm. In a yet further aspect, the at least one first metal contact can comprise an array or a wire capable of carrying the current away from the gridlines to the next cell. In one aspect, the array or the wire capable of carrying current away from the gridline to the next cell comprises a copper ribbon. In a further aspect, the interconnect points that connect one cell to the next in a panel can comprise a copper ribbon. In yet another aspect, the copper ribbon has a rectangular cross-section.

[0052] In another aspect, the device can comprise at least one second metal contact 108a. In one aspect, the at least one second metal contact is the same as or different from a first metal contact comprising silver metal (Ag), aluminum metal (Al), or Ag/Al metal alloys as a conducting material. In yet another aspect, the second metal contact can comprise copper. In a further aspect, the at least one second metal contact can be screen printed or deposited by physical vapor deposition (PVD) techniques that can include but are not limited to sputtering, evaporation, and the like; or electrochemical deposition techniques that can include but are not limited to electroplating, electroless plating, light induced plating, and the like; or any combination of thereof.

[0053] In certain aspect, the device disclosed herein is a solar cell. In some aspects, the solar cell is having a front side and a back side opposite to the front side comprising: a) a silicon substrate textured on the front side; b) an emitter layer comprising a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the front side, wherein the emitter layer forms a front junction with the silicon substrate; c) a first dielectric layer interposed between the emitter layer and the silicon substrate; d) a first metal contact making an electrical connection to the emitter layer on the front side of the solar cell; e) a second metal contact making an electrical connection to the substrate on the back side of the solar cell; and f) the first metal contact and the second metal contact being configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%. [0054] In some aspects, the front side emitter has an emitter saturation current of less than about 100 fA/cm², less than about 80 fA/cm² _; less than about 60 fA/cm², less than about 40 fA/cm², less than about 30 fA/cm², less than about 20 fA/cm², less than about 10 fA/cm², less than about 5 fA/cm², less than about 2 fA/cm², or less than about 1 fA/cm². In some aspects, the emitter dopant profile can be a substantially uniform profile with a peak doping

20 21 / 3

concentration of from about 1x10 to about 1x10 at cm with electrically active carrier

20 20 3

concentrations from about 1x10 to about 6x10 at/cm , and a junction depth less than about 0.5 μιη, less than about 0.4 μιη, less than about 0.3 μιη, less than about 0.2 μιη, or less than about 0.15 μιη. In some aspects, the emitter profile can be a Gaussian profile with a peak doping concentration at the surface of from about lxlO²⁰ to about lxlO²¹ at/cm³ and a junction depth of about 1 μιη. In another aspect, the front side emitter has a sheet resistance of about 10 Ohm/sq to about 500 Ohm/sq. In yet another aspect, the front side emitter has a sheet resistance of less than about 200 Ohm/sq, including exemplary values of less than about 150 Ohm/sq, less than about 140 Ohm/sq, less than about 130 Ohm/sq, less than about 120 Ohm/sq, less than about 1 10 Ohm/sq, less than about 100 Ohm/sq, less than about 90 Ohm/sq, less than about 80 Ohm/sq, less than about 70 Ohm/sq, less than about 60 Ohm/sq, less than about 50 Ohm/sq, less than about 40 Ohm/sq, less than about 30 Ohm/sq, and less than about 20 Ohm/sq.

[0055] In some aspects, the solar cell disclosed herein does not comprise transparent conductive layers (TCO). In some aspects, the first dielectric layer interposed between the emitter layer and the silicon layer comprises a tunnel oxide. In one aspect, the tunnel oxide layer does not hinder majority charge carrier transport across its barrier, providing the solar cell fill factors (FFs) above about 80%. In a further aspect, the inventive solar cell structure allows a cell Voc higher than about 670 mV.

[0056] In some aspects, the solar cell disclosed herein comprises a first metal contact and a second metal contact that are configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%, including exemplary values of at least about 20.1%, at least about 20.2 %, at least about 20.3 %, at least about 20.4%, at least about 20.5 %, at least about 20.6%, at least about 20.7%, at least about 20.8%, at least about 20.9%, at least about 21.0%, at least about 21.1%, at least about 21.2 %, at least about 21.3 %, at least about 21.4%, at least about 21.5 %, at least about 21.6%, at least about 21.7%, at least about 21.8%, at least about 21.9%, at least about 22.0%, at least about 22.1%, at least about 22.2 %, at least about 22.3 %, at least about 22.4%, at least about 22.5 %, at least about 22.6%, at least about 22.7%, at least about 22.8%, at least about 22.9%, at least about 23.0%, at least about 23.1%, at least about 23.2 %, at least about 23.3 %, at least about 23.4%, at least about 23.5 %, at least about 23.6%, at least about 23.7%, at least about 23.8%, at least about 23.9%, at least about 24.0%, at least about 24.1%, at least about 24.2 %, at least about 24.3 %, at least about 24.4%, at least about 24.5 %, at least about 24.6%, at least about 24.7%, at least about 24.8%, at least about 24.9%, at least about 25.0%, at least about 25.1%, at least about 25.2 %, at least about 25.3 %, at least about 25.4%, at least about 25.5 %, at least about 25.6%, at least about 25.7%, at least about 25.8%, at least about 25.9%, at least about 26.0%, at least about 26.1%, at least about 26.2 %, at least about 26.3 %, at least about 26.4%, at least about 26.5 %, at least about 26.6%, at least about 26.7%, at least about 26.8%, at least about 26.9%, at least about 27.0%, at least about 27.1%, at least about 26.2 %, at least about 26.3 %, at least about 26.4%, at least about 26.5%, at least about 26.6%, at least about 26.7%, at least about 26.8%, at least about 26.9%, at least about 27.0%, at least about 27.1%, at least about 27.2 %, at least about 27.3 %, at least about 27.4%, at least about 27.5 %, at least about 27.6%, at least about 27.7%, at least about 27.8%, at least about 27.9%, at least about 28.0%, at least about 28.1%, at least about 28.2 %, at least about 28.3 %, at least about 28.4%, at least about 28.5 %, at least about 28.6%, at least about 28.7%, at least about 28.8%, at least about 28.9%, at least about 29.0%, at least about 29.1%, at least about 29.2%, at least about 29.3%, and about 29.4%.

C. PROCESSES

[0057] Also disclosed herein is a process comprising: forming a device having a front side and a back side opposite to the front side comprising: a) providing a silicon substrate; b) texturing at least a portion of the silicon substrate; c) forming a first dielectric layer on the front side of the silicon substrate; d) forming a first heavily doped polycrystalline silicon layer and a second heavily doped polycrystalline silicon layer, wherein the first heavily doped polycrystalline silicon layer has a thickness of greater than about 20 nm to about less than about 1 μιη, and wherein the first heavily doped polycrystalline silicon forms a junction with the front side of the substrate; e) forming at least one coating layer, wherein the at least one coating layer comprises: i) an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the front side; ii) a back reflector positioned over the second heavily doped polycrystalline silicon layer on the back side; or iii) a combination thereof; f) forming at least one metal contact comprising: iv) at least one first metal contact is formed on at least a portion of the front side; and v) at least one second metal contact is formed on at least a portion of the back side; and g) configuring the at least one first and the at least one second metal contacts to allow an external electrical circuit to be powered by the device.

[0058] FIG. 2 schematically illustrates an exemplary process for the fabrication of the device 100 shown in FIG. 1. In one aspect, a silicon substrate is provided. As one of ordinary skill in the art would readily appreciate, approximately 75% of the cost of manufacturing silicon solar cells is in the cost of the silicon wafer itself. Thus, the more wafer that can be sliced from an ingot, the more cost savings may be realized. In some aspects of this invention, the device 100 can be manufactured utilizing the silicon substrate having a thickness of about 100 μιη to about 250 μιη, including exemplary values of about 110 μιη, about 120 μιη, about 130 μιη, about 140 μιη, about 150 μιη, about 160 μιη, about 170 μιη, about 180 μιη, about 190 μιη, about 200 μιη, about 210 μιη, about 220 μιη, about 230 μιη, and about 240 μιη. It is understood that in order to ensure reproducibility of the manufacturing process and to remove undesired impurities and defects, the provided silicon substrate can undergo any cleaning procedure commonly known to one of ordinary skill in the art. In one aspect, the undesirable defects can be the result of a sawing process used by the wafer vendor to slice the substrate from its ingot. In another aspect, undesired impurities can include without limitation dust, water marks, metal impurities, organic residues, and the like.

[0059] In one aspect, the provided silicon substrate is a crystalline substrate 200. In another aspect, the silicon substrate is a monocrystalline silicon substrate. In yet another aspect, the silicon substrate is a multicrystalline silicon substrate. In a further aspect, the silicon substrate can comprise an n-type or a p-type silicon substrate.

[0060] In certain aspects, to increase an amount of light captured by the device, the at least a portion of the silicon substrate is textured 201. In one aspect, texturing can be present on the first surface or a portion thereof. In yet in another aspect, texturing can be present on the second surface or a portion thereof. In yet another aspect, texturing can be present on at least a portion of the first and at least a portion of the second surface. In certain aspects, the texturing of the at least a portion of the silicon substrate is performed on a front side, back side, or a combination thereof. In another aspect, the texturing of the at least a portion of the silicon substrate is performed on the front side. In yet another aspect, at least a portion of the silicon substrate on the back side is substantially planarized.

[0061] In some aspects, texturing the silicon substrate comprises exposing at least a portion of the silicon substrate to a liquid capable of forming a textured silicon substrate, a plasma etching process, a laser etching process, a mechanical etching process, or any combination thereof. In certain aspects, texturing can be performed in a liquid capable of forming a textured silicon substrate. In this aspect, at least a portion of an outer silicon layer is removed from the silicon substrate surface. Upon removal the outer silicon layer, a clean contaminant- free silicon surface is exposed. In some aspects, the liquid can comprise an alkaline solution. In an exemplary aspect, the alkaline solution comprises a solution of potassium hydroxide and isopropyl alcohol. In other aspects, etching in an alkaline solution can result in formation of random crystallographic grain orientations and high selectivity of etching along specific directions on the silicon surface. In yet other aspects, the liquid comprises an acid solution. In one aspect, when texturing comprises the use of an acid solution comprising, for example, a mixture of hydrofluoric acid and nitric acid (HF-HNO₃), the resulting textured surface can comprise randomly distributed grains of different

crystallographic orientation. In yet another aspect, precise control of a processing temperature can be useful.

[0062] In one aspect, texturing can comprise use of plasma etching. In another aspect, such plasma etching can comprise a reactive ion etching (RIE) or inductively coupled plasma (ICP) etching technique. In yet another aspect, texturing can comprise a mechanical etching technique.

[0063] In another aspect, texturing can be accomplished by the use of a laser etching technique. As one of ordinary skill in the art would appreciate, a coherent and monochromatic laser beam focused on a small spot can produce high power densities that allow evaporation and removal of the thin material layer in the form of neutral atoms and molecules, positive and negative ions from material surface exposed to laser radiation and thus, forming a

contaminant-free textured surface.

[0064] In some aspects, a sacrificial layer can be deposited on the silicon substrate prior to texturing. In another aspect, such a sacrificial layer can be an oxide layer that can be removed by any previously described texturing technique. In some aspects, texturing forms a uniform or substantially uniform surface. In yet another aspect, texturing forms an atomically smooth or substantially atomically smooth surface.

[0065] In further aspects, the first dielectric layer can be formed on the front side of the silicon substrate. In one aspect, the first dielectric layer can be positioned on the textured substrate surface. In another aspect, the first dielectric layer can be formed by methods comprising chemical oxidation of at least a portion of the silicon substrate, or deposition via atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). In yet another aspect, the first dielectric layer is a tunnel oxide. In one aspect, the chemical oxidation of the silicon substrate can be performed by immersing at least a portion of the silicon substrate in an oxidizing environment at temperatures elevated above 25 °C. In some aspects, the first dielectric layer can comprise aluminum oxide (AlOx), hafnium oxide (HfOx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy) films.

[0066] In one aspect, the oxidizing environment can include, but is not limited to, hydrogen peroxide, sulfuric acid, nitric acid, ozone, ozonated water, and the like. In one aspect, the first dielectric layer has a thickness sufficiently low to allow selective tunneling of holes or electrons through the dielectric layer to the contact layer that will be subsequently deposited on the other side of the dielectric layer. Without wishing to be bound by theory, it is understood that since tunneling probability decreases exponentially with increasing thickness, and good passivation requires a minimum thickness to provide a stable process, the first dielectric layer thickness can be determined by one of ordinary skill in the art based on the specific needs of a given device and/or process. In another aspect, the thickness of the first dielectric layer is from about 0.5 to about 3.5 nm, including exemplary values of about 0.6 nm, about 0.7 nm, about 0.8 nm, about 0.9 nm, about 1.0 nm, about 1.1 nm, about 1.2 nm, about 1.3 nm, about 1.4 nm, about 1.5 nm, about 1.6 nm, about 1.7 nm, about 1.8 nm, about 1.9 nm, about 2.0 nm, about 2.1 nm, about 2.2 nm, about 2.3 nm, about 2.4 nm, about 2.5 nm, about 2.6 nm, about 2.7 nm, about 2.8 nm, about 2.9 nm, about 3.0 nm, about 3.1 nm, about 3.2 nm, about 3.3 nm, and about 3.4 nm. In some exemplary aspects and as illustrated in FIG. 2, the method can further comprise forming a second dielectric layer, wherein the second dielectric layer is formed on the back side of the silicon substrate, 202. In some exemplary aspects, the second dielectric layer can be formed simultaneously with the first dielectric layer. In other exemplary aspects, the second dielectric layer is formed separately from the first dielectric layer. In some aspects, the second dielectric layer is the same as or different from the first dielectric layer. [0067] In one aspect, deposition of undoped silicon layers on both sides 203 of the silicon substrate 101 can be performed to provide layers that will subsequently be converted into contact layers. In one aspect, forming the first and the second heavily doped polycrystalline silicon layers further comprises depositing a first undoped layer on the front side and a second undoped silicon layer on the back side. In some aspects, the first and the second undoped silicon layers are deposited simultaneously or separately. In yet further aspects, the first and the second undoped silicon layers are deposited using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or any combination thereof. In aspects where the first and the second undoped silicon layers are deposited simultaneously on both sides of the substrate, low pressure chemical vapor deposition (LPCVD) can be used to deposit the layers. In other aspects, where the first and the second undoped silicon layers are deposited sequentially, plasma enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD) can be utilized. In some aspects, when the films are deposited by PECVD or APCVD, hydrogenation of the tunnel oxide layers is possible during the deposition.

[0068] In some aspects, the first undoped silicon layer can be positioned on the first dielectric layer. In other aspects, the second undoped silicon layer can be positioned on the second dielectric layer. In some aspects, the first undoped polycrystalline silicon layer has a thickness greater than about 20 nm to about 5 μιη. In some aspects, the thickness of the first undoped polycrystalline silicon layer can be sufficient to exhibit a desirable lateral conductivity in order to enable higher efficiency in the cells. Without wishing to be bound by theory, it is speculated that higher cell efficiency can be achieved, in part, by minimizing power loss due to the resistance in the contact layers to the grid, especially on the front side since the metal gridlines are limited in coverage area, to minimize shading losses. In another aspect, the thickness of the first undoped polycrystalline silicon layer can be sufficiently thin to minimize carrier absorption within the top contact layer. In some aspects, to achieve the highest efficiency cells, all or substantially all of the incident light can be absorbed in the silicon substrate. In other aspects, the thickness of the second undoped polycrystalline silicon layer can be same as or different from the thickness of the first undoped polycrystalline silicon layer. [0069] In further aspects, the methods described herein can further comprise doping the first and/or the second undoped silicon layers to form a first heavily doped polycrystalline silicon layer 204 having a first polarity and a second heavily doped polycrystalline silicon layer 205 having a second (opposing) polarity. It is understood that to maximize tunneling probability of the carriers to the contacts, high doping levels are desirable. It is also understood that the first and the second undoped silicon layers, when doped, can advantageously have an opposite doping polarity. In some aspects, the first heavily doped polycrystalline silicon layer 204 can have a doping type that has same polarity as the silicon substrate. In other aspects, the first heavily doped polycrystalline silicon layer 204 can have a doping type that has an opposite polarity to the silicon substrate. In one aspect, when the silicon substrate is n-type, the first heavily doped polycrystalline silicon layer 204 can be a p-type doped, and the second heavily doped polycrystalline silicon layer 205 can be an n-type doped. In one aspect, the p- type doping is achieved by introducing group III elements including boron (B), aluminum (Al), gallium (Ga), or indium (In) as doping elements. In one aspect, boron (B) atoms are used as the dopant element. In another aspect, the n-type doping is achieved by introducing group V elements, including phosphorous (P), arsenic (As), antimony (Sb) atoms, as a doping agent. In one aspect phosphorus (P) atoms are used as the dopant element.

[0070] In one aspect, doping can be accomplished through single side doping techniques, such as an ion implantation or a doped glass deposition (APCVD or PECVD), enabling different dopant types to be placed into/onto the contact layers. In another aspect, doping can be performed via ion implantation. In one aspect, the active dopant concentration in the first heavily doped polycrystalline silicon layer is greater than about lxlO¹⁹ at/cm³. In another aspect, a dose of the ion implantation needed to form a heavily doped layers is equal to or greater than about lxlO¹⁵ at/cm² to less than or equal to about 2xl0¹⁶ at/cm².

[0071] In another aspect, doping comprises doped glass deposition. In yet another aspect, such a doped glass deposition can be performed by plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or a combination thereof.

[0072] In one aspect, the doping level of the second undoped polycrystalline silicon can be the same or different than the doping level of the first undoped silicon layer. In yet another aspect, doping of the second undoped layer is performed simultaneously with doping of the first undoped layer.

[0073] In one aspect, the methods described herein can further comprise annealing 206 of the contact layers comprising the first and the second heavily doped polycrystalline silicon layers having opposite polarity. In one aspect, annealing can comprise diffusing and activating dopants. In yet another aspect, annealing can be performed in a tube furnace. In a further aspect, annealing can be performed by a laser or a flash lamp. In a yet further aspect, annealing can be performed at a temperature equal to or greater than about 700 °C, including exemplary values of greater than about 750 °C, greater than about 800 °C, greater than about 850 °C, greater than about 900 °C, greater than about 950 °C, and greater than about 1000 °C. In some aspects, the temperature greater than about 800 °C can be desired so as to achieve a sufficient activation of the dopants within the contact layers. In one aspect, at annealing temperatures above about 1,000 °C, the dopants can diffuse at least partially into the silicon substrate, potentially leading to performance degradation of the cell due to increased recombination. In some aspects, a passivating oxide can be grown during the annealing on top of the doped contact layers.

[0074] In certain aspects, as demonstrated in FIG. 3, the doping can be performed simultaneously (i.e., in-situ) with the deposition of the first and/or the second undoped silicon layers to form the first and the second heavily doped layers. In one exemplary aspect (FIG. 3), the polysilicon deposition can be done with in-situ doping of the first polarity on at least a first surface (303), when the steps 304-311 are substantially similar to the steps 205-212. In-situ doping, if performed, can be performed using any suitable technique known in the art. In other aspects, the in-situ doped silicon layers can be subsequently annealed to increase conductivity of the layers. In one aspect, an amorphous silicon layer is doped in-situ and subsequently annealed to allow recrystallization of at least a portion of amorphous silicon into a large grain polycrystalline silicon exhibiting optical and conductive properties substantially identical to optical and conductive properties of monocrystalline silicon.

[0075] In one aspect, the doping of the first doped polycrystalline silicon layer can be n or p type, wherein the doping of the second doped polycrystalline silicon layer can be p or n type, to allow formation of the disclosed device having opposite polarities. In certain aspects, the desired of polarity of each doped polycrystalline silicon layer can be achieved via a single side doping techniques followed by the annealing process.

[0076] As one of ordinary skill in the art would readily appreciate a successful annealing process can allow accomplishment of multiple effects that include but are not limited to a dopant activation or crystallization of at least a portion of the deposited silicon layers. In certain aspects, a passivating oxide can be grown on the surface of the polycrystalline silicon during the annealing step.

[0077] In certain aspects, the methods of the present invention can further comprise the deposition of at least one coating layer. In some aspects, the at least one coating layer is a first coating layer deposited on the first surface of the silicon substrate 207. In another aspect, at least one coating can comprise a second coating layer deposited on the second surface of the silicon substrate 208. In one aspect, at least one coating layer can comprise an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the front side and can be selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O₂), aluminum oxide (AlOx), or titanium oxide (T1O₂).

[0078] In another aspect, at least one coating layer can comprise a back reflector positioned over the second heavily doped polycrystalline silicon layer on the back side and can be selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O₂), aluminum oxide (AlOx), titanium oxide (T1O₂), graphene, carbon nanotubes, or a transparent conductive oxide (TCO). In some aspects, the TCO, if used, can comprise indium tin oxide (ITO), fluorine doped ZnO (FTO), aluminum doped zinc oxide (AZO), indium gallium oxide (IGO), or any combination thereof. In yet another aspect, the at least one coating layer does not comprise a transparent conductive oxide (TCO). In certain aspects, an antireflective coating can exhibit a refractive index about 1.9 to about 2.3. In other aspects, a graded index SiNx layer or T1O₂ or any materials known in the art having a refractive index of about 2.1 to about 2.4 can also be used. In some aspects, the thickness of the antireflective coating can be about 40 to about 90 nm.

[0079] In one aspect, the methods can further comprise forming at least two coating layers, wherein the two coating layers comprise an antireflective coating and a back reflector. In certain aspects, the at least two coating layers can be deposited in a single machine, or via a single step or technique, with multiple chambers for front and back layers or via double side deposition process as low pressure plasma chemical vapor deposition (LPCVD).

[0080] In some aspects, the methods can further comprise forming at least one metal contact. In one aspect, at least one metal contact formed on at least a portion of the front side can be a first metal contact. In another aspect, at least one metal contact formed on at least a portion of the back side can be a second metal contact. In yet another aspect, at least one metal contact formed both on the at least a portion of the front side and at least a portion of the back side can be a first metal contact and a second metal contact.

[0081] In one aspect, at least one first metal contact can be formed by screen printing using a metal paste on the first surface of the antireflection layer 207. In another aspect, at least one first metal contact can be formed by screen printing using a metal paste 209 on the front surface of the antireflection layer 207. In some aspects, the metal paste can comprise a silver paste. In other aspects, the metal paste can comprise a silver/aluminum paste. As one of ordinary skill in the art would readily appreciate, the silver paste can be selected because of its high electrical conductivity to limit shadowing effects that can lower solar cell efficiency. Various commercial silver pastes are available for this purpose, and can be easily accessible to one of ordinary skill in the art. As silver paste is not transparent, it can be desirable to limit the dimensions of the metal contact to a limited area. In certain aspects, the gridlines are printed to have widths of less than about 200 μιη, for example in the range of from about 30 to about70 μιη range. In one aspect, at least one first metal contact is making an electrical connection with the first heavily doped polycrystalline silicon layer.

[0082] In some aspects, the printed gridlines are capable of collecting the current from the contact layer and transporting it to the interconnect points that connect one cell to the next in a panel. In a yet further aspect, the at least one first metal contact can comprise an array or a wire capable of carrying the current away from the gridlines to the next cell. In one aspect, the array or the wire capable of carrying current away from the gridline to the next cell comprises a copper ribbon. In a further aspect, the interconnect points that connect one cell to the next in a panel can comprise a copper ribbon. In yet another aspect, the copper ribbon has a rectangular cross-section.

[0083] In other aspects, at least one second contact is formed on the second coating layer on the second surface 208. In one aspect, at least one second contact comprises a pattern that is same as or different from one or more of the first metal contacts. In one aspect, a second contact is formed by screen printing. In one aspect, screen printing is performed using a the metal paste 210. In other aspects, a second metal contact can be formed by physical vapor deposition, sputtering, or evaporation. In one aspect, a second metal contact can also comprise copper, aluminum, or any metal alloys thereof. In one aspect, the metal alloys can comprise substantially aluminum. In yet another aspect, the metal alloys can comprise substantially copper. In another aspect, the metal alloys can comprise both aluminum and copper. In a further aspect, the metal alloys can comprise any metals that can form an alloy with copper. In a yet further aspect, the metal alloys can comprise any metals that can for an alloy with aluminum. In a still further aspect, the metal alloys can comprise any metals that can form an alloy with both copper and aluminum. As one of ordinary skill in the art would appreciate, when a second metal contact comprising copper, aluminum, or any metal alloys thereof is not formed by a screen printing process, additional processing steps such as the development of vias can be utilized.

[0084] In some aspects, the methods disclosed herein can further comprise firing 211 the first and second metal contacts at a temperature equal to or greater than about 700 °C.

[0085] In certain aspects, solar cells can be manufactured by the methods described herein. In some aspects, such solar cells can be tested 212 and sorted. The cells having substantially identical characteristics, including but not limited to a current, a voltage, and a cell efficiency can be connected to form a panel having a plurality of the tested solar cells. In some aspect, the panel can be deployed into a photovoltaic (PV) system.

[0086] Without further elaboration, it is believed that one skilled in the art can, using the description herein, utilize the present invention. The following examples are included to provide addition guidance to those skilled in the art of practicing the claimed invention. The examples provided are merely representative of the work and contribute to the teaching of the present invention. Accordingly, these examples are not intended to limit the invention in any manner.

[0087] While aspects of the present invention can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience only and one of skill in the art will understand that each aspect of the present invention can be described and claimed in any statutory class. Unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state that steps are to be limited to a specific order, no order is to be inferred.

[0088] Throughout this application, various publications are referenced. The disclosures of these publications in their entireties are hereby incorporated by reference into this application in order to more fully describe the state of the art to which this application pertains. The references disclosed are also individually and specifically incorporated by reference herein for the material contained in them that is discussed in the sentence in which the reference is relied upon. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publications provided herein can be different from the actual publication dates, which can require independent confirmation.

Claims

CLAIMS What is claimed is:

1. A device having a first surface and an opposing second surface, comprising:

a) a silicon substrate, wherein at least a portion of the substrate is textured; b) a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the first surface;

c) a second heavily doped polycrystalline silicon layer superposed on the silicon substrate on the second surface and having a doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer; d) a first dielectric layer interposed between the first heavily doped

polycrystalline silicon layer and the silicon substrate; and e) a first metal contact positioned on the first surface and a second metal contact positioned on the second surface.

2. The device of claim 1, further comprising a second dielectric layer interposed

between the second heavily doped polycrystalline silicon layer and the silicon substrate.

3. The device of claim 1, wherein the silicon substrate is a crystalline silicon.

4. The device of claim 1, wherein the silicon substrate is an n-type doped silicon.

5. The device of claim 1, wherein the silicon substrate is a p-type doped silicon.

6. The device of claim 3, wherein the silicon substrate is a monocrystalline silicon.

7. The device of claim 3, wherein the silicon substrate is a multicrystalline silicon.

8. The device of claim 1, wherein at least one of conditions (1)- (3) is satisfied:

(1) the at least a portion of the substrate is textured on the first surface;

(2) the at least a portion of the substrate is textured on the second surface; and

(3) the at least a portion of the substrate is textured on the first surface and the second surface.

9. The device of claim 1, wherein the textured substrate comprises a plurality of atomically smooth facets.

10. The device of claim 1, wherein the first heavily doped polycrystalline silicon layer forms a first surface junction with the silicon substrate.

11. The device of claim 4, wherein the first heavily doped polycrystalline silicon has a doping type of an opposite polarity to the silicon substrate.

12. The device of claim 1, wherein the first heavily doped polycrystalline silicon layer has an active dopant concentration greater than about lxlO¹⁹ at/cm³.

13. The device of claim 1, wherein the first heavily doped polycrystalline silicon layer is p-doped.

14. The device of claim 1, wherein the first dielectric layer has a thickness about 0.5 to about 3.5 nm.

15. The device of claim 1 or 14, wherein the first dielectric layer having a bandgap at least about 0.2 eV larger than the silicon substrate.

16. The device of claim 1, wherein the first dielectric layer comprises a chemical oxide layer, or a thermal oxide layer.

17. The device of claim 16, wherein the first dielectric layer is a tunneling oxide layer.

18. The device of claims 16 or 17, wherein the first dielectric layer comprises SiOx, SiOxNy, AlOx, or HfOx.

19. The device of claim 2, wherein the second dielectric layer is the same as or different from the first dielectric layer.

20. The device of claim 1 further comprises at least one coating layer.

21. The device of claim 19, wherein the at least one coating layer is an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the first surface and is selected from the group consisting of SiNx, Si02, AlOx, and Ti02.

22. The device of claim 19, wherein the at least one coating layer is a back reflector positioned over the second heavily doped polycrystalline silicon layer on the second surface and is selected from the group consisting of SiNx, Si02, AlOx, Ti02, graphene, carbon nanotubes, and a transparent conductive oxide (TCO).

23. The device of claim 21 , wherein the TCO comprises indium tin oxide (ITO), fluorine doped ZnO (FTO), aluminum doped zinc oxide (AZO), indium gallium oxide (IGO), or any combination thereof.

24. The device of claim 19, wherein the at least one coating layer does not comprise a transparent conductive oxide (TCO).

25. The device of claim 1, wherein the device comprises at least two coating layers, and wherein the two coating layers comprise an antireflective coating and a back reflector.

26. The device of claim 1, where the at least one first metal contact making an electrical connection with the first heavily doped polycrystalline silicon layer.

27. The device of claim 1, wherein the at least one first metal contact comprises silver, aluminum, or a silver/aluminum alloy.

28. The device of claim 1, wherein the at least one first metal contact is screen printed.

29. The device of claim 1, wherein the at least one second metal contact is the same as or different from a first contact metal contact.

30. The device of claim 1, wherein the second metal contact comprises copper,

aluminum, or any metal alloys thereof.

31. The device of claim 1, wherein the at least one second metal contact is deposited by PVD.

32. A solar cell having a first surface and an opposing second surface comprising:

a) a silicon substrate textured on the first surface;

b) an emitter layer comprising a first heavily doped polycrystalline silicon layer; superposed on the silicon substrate on the first surface, the emitter layer forming a front junction with the silicon substrate;

c) a first dielectric layer interposed between the emitter layer and the silicon substrate;

d) a first metal contact making an electrical connection to the emitter layer on the first surface of the solar cell;

e) a second metal contact making an electrical connection to the substrate on the second surface of the solar cell; and

f) the first metal contact and the second metal contact being configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%.

33. A method of forming a device having a first surface and an opposing second surface comprising:

a) providing a silicon substrate;

b) texturing at least a portion of the silicon substrate;

c) forming a first dielectric layer on the first surface of the silicon substrate; d) forming a first heavily doped polycrystalline silicon layer and a second heavily doped polycrystalline silicon layer, wherein the first heavily doped polycrystalline silicon layer has a thickness of greater than about 20 nm to about 5 μηι, and wherein the first heavily doped polycrystalline silicon forms a junction with the first surface of the substrate;

e) forming at least one coating layer, wherein the at least one coating layer comprises:

i) an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the first surface;

ii) a back reflector positioned over the second heavily doped

polycrystalline silicon layer on the second surface; or

iii) a combination thereof;

f) forming at least one metal contact comprising:

iv) the at least one first metal contact is formed on at least a portion of the first surface; and

v) the at least one second metal contact is formed on at least a portion of the second surface; and

g) configuring the at least one first and the at least one second metal contacts to allow an external electrical circuit to be powered by the device.

34. The method of claim 33, wherein the silicon substrate is a crystalline substrate.

35. The method of claim 34, wherein the silicon substrate is a monocrystalline silicone.

36. The method of claim 33, wherein the silicon substrate is a multicrystalline silicon.

37. The method of claim 35 or 36, wherein the silicon substrate is an n-type.

38. The method of claim 35 or 36, wherein the silicon substrate is a p-type.

39. The method of claim 33, wherein the texturing of the at least a portion of the silicon substrate is performed on a first surface, second surface, or a combination thereof.

40. The method of claim 39, wherein the texturing of the at least a portion of the silicon substrate is performed on the first surface.

41. The method of claim 40, wherein the at least a portion of the silicon substrate on the second surface is substantially planarized.

42. The method of claim 33, wherein the texturing of the at least a portion the silicon substrate comprises exposing the at least a portion of the silicon substrate to a liquid capable of forming a textured silicon substrate, a plasma etching, a mechanical etching, a laser etching, or any combination thereof.

43. The method of claim 33, wherein a sacrificial layer is deposited on the silicon substrate prior to the texturing.

44. The method of claim 43, wherein the sacrificial layer is an oxide layer.

45. The method of claim 33, wherein the texturing forms a surface exhibiting a

substantially atomic smoothness.

46. The method of claim 33, wherein the first dielectric layer is formed on the first

surface of the silicon substrate.

47. The method of claim 46, wherein the first dielectric layer is superposed on the

textured substrate surface.

48. The method of claim 33, wherein the first dielectric layer is exhibiting a band gap at least about 0.2 eV larger than the silicon substrate.

49. The method of claim 33, wherein the first dielectric layer is a tunnel oxide.

50. The method of claim 33, wherein the first dielectric layer has a thickness about 0.5 to about 2.5 nm.

51. The method of claim 33, wherein the first dielectric layer is formed by chemical oxidation of at least a portion of the silicon substrate.

52. The method of claim 33, wherein the first dielectric layer is formed by depositing via atomic layer deposition or plasma-enhanced chemical vapor deposition.

53. The method of claim 52, wherein the first dielectric layer comprises aluminum oxide (AlOx), hafnium oxide (HfOx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy).

54. The method of claim 33, further comprising forming a second dielectric layer,

wherein the second dielectric layer is formed on the second surface of the silicon substrate.

55. The method of claim 54, wherein the second dielectric layer is formed simultaneously with the first dielectric layer.

56. The method of claim 54, wherein the second dielectric layer is formed separately from the first dielectric layer.

57. The method of claim 54, wherein the second dielectric layer is the same as or

different from the first dielectric layer.

58. The method of claim 33, wherein the forming of the first and the second heavily doped polycrystalline silicon layers further comprises depositing a first undoped layer on the first surface and a second undoped silicon layer on the second surface.

59. The method of claim 58, wherein the first and the second undoped silicon layers are deposited simultaneously or separately.

60. The method of claim 58, wherein the depositing is low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, or any combination thereof.

61. The method of claim 58, wherein the first undoped silicon layer is superposed on the first dielectric layer.

62. The method of claim 58, wherein the second undoped silicon layer is superposed on the second dielectric layer.

63. The method of claim 61, further comprising doping the first undoped silicon layer to form the first heavily doped polycrystalline silicon layer.

64. The method of claim 63, wherein the doping is an ion implantation.

65. The method of claim 64, wherein a dose of the ion implantation is equal to or greater than about lxlO¹⁵ at/cm² to less than or equal to 2xl0¹⁶ at/cm².

66. The method of claim 63, wherein the doping is doped glass deposition.

67. The method of claim 66, wherein the doped glass deposition is performed by plasma enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition.

68. The method of claim 63, wherein an active dopant concentration in the first heavily doped polycrystalline silicon layer is greater than about lxlO¹⁹ at/cm³.

69. The method of claim 63, wherein a doping type is an opposite polarity to the silicon substrate.

70. The method of claim 63, wherein a doping type is same polarity as the silicon

substrate.

71. The method of claim 58, further comprising doping of the second undoped silicon layer to form the second heavily doped polycrystalline silicon layer.

72. The method of claim 63 or 71, wherein the doping is the same as or different from the doping of the first undoped silicon layer.

73. The method of claim 72, wherein the doping of the second undoped layer is

performed simultaneously with the doping of the first undoped layer.

74. The method of claim 73, wherein a doping type is an opposite polarity to the first heavily doped polycrystalline silicon layer.

75. The method of claim 33, further comprising annealing the first heavily doped polycrystalline silicon layer and the second heavily doped polycrystalline silicon layer.

76. The method of claim 75, wherein the annealing comprises diffusing and activating of dopants.

77. The method of claim 75, wherein the annealing is performed in a tube furnace.

78. The method of claim 75, wherein the annealing is performed by a laser or a flash lamp.

79. The method of claim 75, wherein the annealing is performed at a temperature equal to or greater than 700 °C.

80. The method of claim 33, wherein the at least one coating layer is an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the first surface and is selected from the group consisting of silicon nitride (SiNx), silicon oxide (Si02), aluminum oxide (AlOx), or titanium oxide (Ti02).

81. The method of claim 33, wherein the at least one coating layer is a back reflector positioned over the second heavily doped polycrystalline silicon layer on the second surface and is selected from the group consisting of silicon nitride (SiNx), silicon oxide (Si02), aluminum oxide (AlOx), titanium oxide (Ti02), graphene, carbon nanotubes, or a transparent conductive oxide (TCO).

82. The method of claim 81, wherein the TCO comprises indium tin oxide (ITO),

fluorine doped ZnO (FTO), aluminum doped zinc oxide (AZO), indium gallium oxide (IGO), or any combination thereof.

83. The method of claim 33, wherein the at least one coating layer does not comprise a transparent conductive oxide (TCO);

84. The method of claim 33, further comprising forming at least two coating layers, and wherein the two coating layers comprise an antireflective coating and a back reflector.

85. The method of claim 33, wherein the at least one first metal contact making an

electrical connection with the first heavily doped polycrystalline silicon layer.

86. The device of claim 33, wherein the at least one first metal contact comprises silver, aluminum, or a silver/aluminum alloy.

87. The method of claim 33, wherein the at least one first metal contact is an array.

88. The method of claim 33, wherein the at least one first metal contact is a wire.

89. The method of claim 33, wherein the at least one first metal contact is formed by screen printing.

90. The method of claim 89, wherein forming the at least one first metal contact by

screen printing further comprises firing the at least one first metal contact at a temperature equal to above 700 °C.

91. The method of claim 33, wherein the at least one second metal contact comprises copper, aluminum, or any metal alloys thereof.

92. The method of claim 33, wherein the at least one second metal contact is an array.

93. The method of claim 33, wherein the at least one second metal contact is a wire.

94. The method of claim f), wherein the at least one second metal contact is screen

printed.

95. The method of claim 94, further comprises firing the at least one second metal

contact at a temperature equal to above 700 °C.

96. The method of claim 33, wherein the at least one second metal contact is deposited by plasma vapor deposition.

97. A device formed by the method of claims 33-96.

98. A solar cell prepared by the method of claims 33-96.

99. The solar cell of claim 98, wherein the solar cell exhibiting efficiency greater than at least 20 %.

100. The solar cell of claim 98, wherein the solar cell exhibiting efficiency greater than at least 23 %.