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WO2016046984A1 - Dispositif à semi-conducteur au carbure de silicium - Google Patents

Dispositif à semi-conducteur au carbure de silicium Download PDF

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Publication number
WO2016046984A1
WO2016046984A1 PCT/JP2014/075720 JP2014075720W WO2016046984A1 WO 2016046984 A1 WO2016046984 A1 WO 2016046984A1 JP 2014075720 W JP2014075720 W JP 2014075720W WO 2016046984 A1 WO2016046984 A1 WO 2016046984A1
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WIPO (PCT)
Prior art keywords
silicon carbide
insulating layer
type silicon
semiconductor device
layer
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Ceased
Application number
PCT/JP2014/075720
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English (en)
Japanese (ja)
Inventor
俊一 中村
昭彦 菅井
徹人 井上
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Priority to JP2015504450A priority Critical patent/JP5784860B1/ja
Priority to PCT/JP2014/075720 priority patent/WO2016046984A1/fr
Publication of WO2016046984A1 publication Critical patent/WO2016046984A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation

Definitions

  • the present invention relates to a silicon carbide semiconductor device using silicon carbide.
  • the semiconductor device may be destroyed due to the parasitic bipolar transistor operation.
  • a deep P body as described above is disclosed in, for example, Patent Document 1, Patent Document 2, and the like.
  • silicon carbide has a small diffusion coefficient of impurities, a deep P body cannot be formed by diffusing impurities. Further, it is difficult to form a deep P body only by ion implantation. Since it is difficult to form a deep P body as described above, in the silicon carbide semiconductor device, by deepening the P body, the electric field strength applied to the gate insulating film can be reduced, or by deepening the P body. It is difficult to suppress the operation of the parasitic bipolar transistor.
  • Japanese Patent Laid-Open No. 11-330091 Japanese Unexamined Patent Publication No. 63-128757 (see, for example, FIG. 2)
  • the present invention has been made in view of the above points, and provides a silicon carbide semiconductor device having high avalanche resistance as a result of suppressing parasitic bipolar transistor operation in the silicon carbide semiconductor device.
  • a silicon carbide semiconductor device includes: A first conductivity type silicon carbide layer; A plurality of second conductivity type silicon carbide layers provided in the horizontal direction on the first conductivity type silicon carbide layer; A first conductivity type source region formed in the second conductivity type silicon carbide layer; An insulating layer provided on the first conductivity type silicon carbide layer located between adjacent second conductivity type silicon carbide layers; With The insulating layer is located on the second conductivity type silicon carbide layer and the source region, and on the second conductivity type silicon carbide layer, and not on the source region.
  • An insulating layer, A gate electrode is provided in the first insulating layer; No gate electrode is provided in the second insulating layer, In the horizontal direction, the second insulating layer is disposed next to the first insulating layer, Second distance L 2 between the second conductivity type silicon carbide layer located below the second insulating layer, a first distance between the second conductivity type silicon carbide layer located below the first insulating layer It is longer than L 1.
  • the first insulating layer and the second insulating layer may be alternately arranged.
  • the second insulating layer is arranged next to a certain first insulating layer, and another first insulating layer is arranged next to the second insulating layer, and the first insulating layer and the A second insulating layer may be disposed.
  • the thickness obtained by subtracting the thickness of the gate electrode from the thickness of the first insulating layer and the thickness of the second insulating layer may be the same.
  • a plurality of the insulating layers are provided, Each of the horizontal distances between the adjacent insulating layers may be equal.
  • a plurality of the first insulating layer and the second insulating layer are provided, Each of the horizontal distances between the adjacent first insulating layer and the second insulating layer may be equal.
  • the second distance L 2 may be equal to or less than 2 times 1.25 times or more of the first distance L 1.
  • the portion of the second conductivity type silicon carbide layer that contacts the source electrode may have a higher impurity concentration than the portion of the second conductivity type silicon carbide layer that does not contact the source electrode.
  • the impurity concentration in the first conductivity type source region may be higher than the impurity concentration in the first conductivity type silicon carbide layer.
  • the second insulating layer is disposed next to the first insulating layer in the horizontal direction. For this reason, when a large voltage is applied to the silicon carbide semiconductor device, the electric field may be concentrated on the second insulating layer having no gate electrode therein instead of the first insulating layer having the gate electrode provided therein. it can. For this reason, the electric field strength applied to the gate insulating film located below the gate electrode can be relaxed, and a large avalanche resistance can be obtained.
  • FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment of the present invention.
  • 2 (a) to 2 (c) are cross-sectional views showing steps of manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention.
  • 3 (a) to 3 (c) are cross-sectional views illustrating steps for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention, and are cross-sectional views illustrating steps subsequent to FIG. 2 (c).
  • FIG. FIG. 4 is an upper plan view of the silicon carbide semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a silicon carbide semiconductor device according to the second embodiment of the present invention.
  • FIG. 6 is an upper plan view of the silicon carbide semiconductor device according to the second embodiment of the present invention.
  • the silicon carbide semiconductor device of the present embodiment is, for example, a planar gate type vertical MOSFET.
  • the planar gate type vertical MOSFET will be described as a silicon carbide semiconductor device.
  • this is merely an example of the semiconductor device, and other devices having a MOS gate such as an insulated gate bipolar transistor (IGBT). It should be noted that it can also be applied to structures.
  • IGBT insulated gate bipolar transistor
  • the silicon carbide semiconductor device of the present embodiment includes a high concentration n-type silicon carbide semiconductor substrate 11 (first conductivity type silicon carbide substrate) and a high concentration n-type silicon carbide semiconductor substrate.
  • a high concentration n-type silicon carbide semiconductor substrate 11 first conductivity type silicon carbide substrate
  • a high concentration n-type silicon carbide semiconductor substrate On the low-concentration n-type silicon carbide layer 12 (corresponding to the “first-conductivity-type silicon carbide layer” in the claims) and the low-concentration n-type silicon carbide layer 12.
  • a low concentration p-type silicon carbide region 13 which is provided in the horizontal direction and constitutes the P body.
  • the silicon carbide semiconductor device of the present embodiment has a high concentration n-type source region 17 formed in the low concentration p-type silicon carbide region 13 (the “first conductivity type source” in the claims). And a high-concentration p-type silicon carbide region 18 formed in the low-concentration p-type silicon carbide region 13.
  • the silicon carbide semiconductor device of the present embodiment includes insulating layers 21 and 22 provided on n-type silicon carbide layer 12 positioned between adjacent p-type silicon carbide regions 13 and 18. Yes. Note that the low-concentration p-type silicon carbide region 13 and the high-concentration p-type silicon carbide region 18 of the present embodiment correspond to the “second conductivity type silicon carbide layer” in the claims.
  • the insulating layers 21 and 22 described above are formed on the plurality of first insulating layers 21 located on the low-concentration p-type silicon carbide region 13 and the n-type source region 17 and on the high-concentration p-type silicon carbide region 18. And a plurality of second insulating layers 22 not located on the source region. That is, the first insulating layer 21 is provided on the n-type silicon carbide layer 12 positioned between the adjacent low-concentration p-type silicon carbide regions 13, while the second insulating layer 22 is adjacent to the adjacent high-concentration silicon carbide region 12. It is provided on the n-type silicon carbide layer 12 located between the p-type silicon carbide regions 18 having a concentration.
  • the gate electrode 31 made of, for example, polysilicon is provided in the first insulating layer 21, but the gate electrode 31 is not provided in the second insulating layer 22.
  • the first insulating layer 21 is disposed next to the second insulating layer 22.
  • the second insulating layer 22 is the first insulating layer 22.
  • the first insulating layer 21 and the second insulating layer 22 are alternately arranged on both sides of the insulating layer 21.
  • each of the distance of the horizontal direction between the adjacent 1st insulating layer 21 and the 2nd insulating layer 22 is equal.
  • positioned next to the 1st insulating layer 21 is not the 1st insulating layer 21 but the 2nd insulating layer 22 on the one side or both sides of the 1st insulating layer 21.
  • the second insulating layer 22 is disposed on one side of the first insulating layer 21.
  • the first insulating layer 21 is disposed on the other side of 21 (see the second embodiment described later).
  • the first insulating layer 21 and the second insulating layer 22 are alternately disposed as in the present embodiment. Will be.
  • a source electrode 32 is provided on the insulating layers 21 and 22, the high-concentration n-type source region 17, and the high-concentration p-type silicon carbide region 18.
  • a drain electrode 36 is provided on the back surface of the high-concentration n-type silicon carbide semiconductor substrate 11.
  • the second distance L 2 between the adjacent p-type silicon carbide regions 18 located below the second insulating layer 22 is equal to the adjacent p-type silicon carbide located below the first insulating layer 21. It is longer than the first distance L 1 between the region 13, and has a L 2> L 1.
  • the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. 1 to 3A to 3C relating to the present embodiment and FIG. 5 relating to the second embodiment, the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. This is because they are merely schematic representations of the arrangement. Actually, the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. In the present embodiment, the width of the first insulating layer 21 and the width of the second insulating layer 22 are the same length.
  • the second distance L 2 between the adjacent p-type silicon carbide regions 18 located below the second insulating layer 22 is equal to the adjacent p-type silicon carbide located below the first insulating layer 21. It is preferable that the first distance L 1 between the regions 13 is, for example, 1.25 times or more and 2 times or less.
  • the portions of p-type silicon carbide regions 13 and 18 that are in contact with source electrode 32 have impurities compared to the portions of p-type silicon carbide regions 13 and 18 that are not in contact with source electrode 32.
  • the concentration is high. That is, the portion of the p-type silicon carbide regions 13 and 18 that contacts the source electrode 32 becomes the high-concentration p-type silicon carbide region 18 and does not contact the source electrode 32 of the p-type silicon carbide regions 13 and 18.
  • the portion is a low-concentration p-type silicon carbide region 13.
  • the impurity concentration in the n-type source region 17 is higher than the impurity concentration in the n-type silicon carbide layer 12.
  • FIG. 4 is an upper plan view of first insulating layer 21 and second insulating layer 22 of the silicon carbide semiconductor device according to the present embodiment as viewed from above. As shown in FIG. 4, in the present embodiment, the first insulating layer 21 and the second insulating layer 22 have a stripe shape. "Manufacturing process"
  • FIGS. 2 (a)-(c) and FIGS. 3 (a)-(c). An example of the manufacturing process of the silicon carbide semiconductor device of the present embodiment having the above-described configuration will be described mainly with reference to FIGS. 2 (a)-(c) and FIGS. 3 (a)-(c). .
  • n-type silicon carbide semiconductor substrate 11 is prepared (see FIG. 2A).
  • a low-concentration n-type silicon carbide layer 12 is formed by epitaxial growth on the high-concentration n-type silicon carbide semiconductor substrate 11 (see FIG. 2A).
  • a mask made of, for example, an oxide film is laminated on the entire surface of the low-concentration n-type silicon carbide layer 12.
  • an opening is provided at a predetermined portion of the mask, and p-type impurity ions are implanted through the opening to form a low-concentration p-type silicon carbide region 13 (see FIG. 2B). ).
  • the low-concentration p-type silicon carbide region 13 is formed in a stripe shape (see FIG. 4), and the p-type silicon carbide region will be located below the second insulating layer 22 to be formed later.
  • second distance L 2 between the 13 is longer than the first distance L 1 between the p-type silicon carbide region 13 to be positioned below the first insulating layer 21 to be later formed.
  • a mask made of, for example, an oxide film is laminated on the entire surface of the low concentration n-type silicon carbide layer 12 and the low concentration p-type silicon carbide region 13.
  • an opening is provided in a predetermined portion of the mask, and p-type impurity ions are implanted through the opening, thereby forming a high-concentration p-type silicon carbide region 18 (FIG. 2C). reference).
  • the high-concentration p-type silicon carbide region 18 is formed in the p-type silicon carbide region 13 located below the second insulating layer 22 and is adjacent to the high-concentration p-type silicon carbide region 18. the distance between the region 18 becomes the second distance L 2.
  • a mask made of an oxide film or the like is laminated on the entire surface of the low-concentration n-type silicon carbide layer 12, the high-concentration p-type silicon carbide region 18, and the low-concentration p-type silicon carbide region 13. .
  • an opening is provided at a predetermined portion of the mask, and n-type impurity ions are implanted through the opening to form a high-concentration n-type source region 17 (see FIG. 2C). ).
  • the high-concentration n-type source region 17 is formed adjacent to the high-concentration p-type silicon carbide region 18.
  • activation annealing is performed in an atmosphere of an inert gas such as argon.
  • an oxide film is formed on the entire surface of the low-concentration n-type silicon carbide layer 12, the high-concentration n-type silicon carbide layer 17 and the high-concentration p-type silicon carbide region 18 shown in FIG. 29 are stacked.
  • polysilicon is stacked on the surface of the oxide film 29, and then patterned to leave only the polysilicon at the location to be the gate electrode 31 (see FIG. 3A).
  • an oxide film is stacked on the entire surface of the oxide film 29 and the gate electrode 31, and then patterned to leave only the oxide film where the first insulating layer 21 and the second insulating layer 22 are disposed (FIG. 3 (b)). Thereby, the first insulating layer 21 and the second insulating layer 22 are formed.
  • a source electrode 32 is laminated on the entire surface of the first insulating layer 21, the second insulating layer 22, the high concentration n-type silicon carbide layer 17 and the high concentration p-type silicon carbide region 18, and the high concentration
  • a drain electrode 36 is provided on the back surface of the n-type silicon carbide semiconductor substrate 11 (see FIG. 3C).
  • a silicon carbide semiconductor device is manufactured as described above.
  • the second distance L 2 between the p-type silicon carbide regions 18 located below the second insulating layer 22 is the p-type carbonized located below the first insulating layer 21. Since it is longer than the first distance L 1 between the silicon regions 13, the number of electric lines of force that flow from below between the p-type silicon carbide regions 18 located below the second insulating layer 22. Is greater than the number of lines of electric force flowing from below between the p-type silicon carbide regions 13 located below the first insulating layer 21. As described above, in the aspect of the present embodiment, breakdown is most likely to occur due to the lines of electric force flowing from below between the p-type silicon carbide regions 18 located below the second insulating layer 22. Become.
  • the high-concentration p-type silicon carbide region 18 located below the second insulating layer 22 is used before the electric field of the gate insulating film 21a below the gate electrode 31 is increased.
  • An avalanche breakdown can occur, and an avalanche current can flow into the source electrode 32 without passing below the n-type source region 17. Therefore, the voltage drop in the low-concentration p-type silicon carbide region 13 due to the avalanche current is reduced, the operation of the parasitic bipolar transistor is suppressed, and the avalanche breakdown resistance can be improved.
  • the electric field strength applied to the gate insulating film 21a below the gate electrode 31 can be relaxed, and the avalanche breakdown resistance can be improved. According to the present embodiment, it is not necessary to narrow the interval between the p-type silicon carbide regions or deepen the p-type silicon carbide regions as in the prior art.
  • the second insulating layer 22 is disposed next to the first insulating layer 21 in the horizontal direction. For this reason, the electric field can be concentrated on the p-type silicon carbide region 18 located below the second insulating layer 22 instead of the p-type silicon carbide region 13 located below the first insulating layer 21.
  • the first insulating layers 21 and the second insulating layers 22 are alternately arranged in the horizontal direction, and the second insulating layers 22 are always arranged on both sides of the first insulating layer 21. It will be.
  • the electric field is more reliably concentrated on the second insulating layer 22 not including the gate electrode 31 instead of the first insulating layer 21 including the gate electrode 31. Can do. Therefore, the electric field strength applied to the gate insulating film 21a can be more reliably alleviated, and the avalanche breakdown resistance can be more reliably improved.
  • the crystal defect region can be reduced, and an increase in leakage current can be suppressed.
  • the second distance L 2 preferably is equal to or less than 2 times 1.25 times the first distance L 1. If the first distance L 1 is assumed to be 2 [mu] m, it is preferable that the second distance L 2 has a 2.5 [mu] m ⁇ 4.0 .mu.m. Second distance when the length and the length of the first distance L 1 L 2 has become too close length, the second insulating layer does not contain a gate electrode 31 instead of the first insulating layer 21 includes a gate electrode 31 The second distance L 2 is preferably 1.25 times or more of the first distance L 1 because the effect of concentrating the electric field on 22 is difficult to obtain.
  • the second distance L 2 is less than twice the first distance L 1.
  • the thickness obtained by subtracting the thickness of the gate electrode 31 from the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 are the same. This is a result of forming the first insulating layer 21 and the second insulating layer 22 by the same method as described above. Thus, the manufacturing method can be simplified by forming the first insulating layer 21 and the second insulating layer 22 in the same manner.
  • the horizontal distances between the first insulating layer 21 and the second insulating layer 22 adjacent to each other are equal. For this reason, even if a large voltage is applied to the silicon carbide semiconductor device, the generated electric field can be evenly concentrated on each second insulating layer 22. For this reason, the electric field strength applied to the gate insulating film 21a can be relaxed reliably and without unevenness.
  • the portion that contacts the source electrode 32 is a high-concentration p-type silicon carbide region 18. For this reason, in this high-concentration p-type silicon carbide region 18, sufficient ohmic contact with the source electrode 32 can be obtained. Further, since the impurity concentration in the n-type source region 17 is high, sufficient ohmic contact with the source electrode 32 can be obtained also in the n-type source region 17.
  • the first insulating layer 21 and the second insulating layer 22 are alternately arranged.
  • the second insulating layer 22 is arranged next to a certain first insulating layer 21 in the horizontal direction as described in the second embodiment. A description will be given using a mode in which the first insulating layer 21 and the second insulating layer 22 are arranged at a period in which another first insulating layer 21 is arranged next to the second insulating layer 22.
  • the other configurations are substantially the same as those in the first embodiment.
  • the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • a second insulating layer 22 is disposed next to a certain first insulating layer 21 (for example, the second first insulating layer 21 from the left in FIGS. 5 and 6), and Next to the second insulating layer 22, another first insulating layer 21 (for example, the rightmost first insulating layer 21 in FIGS. 5 and 6) is arranged at a period, and the first insulating layer 21 and the second insulating layer Layer 22 is disposed. That is, the first insulating layer 21, the second insulating layer 22, the first insulating layer 21, the first insulating layer 21, the second insulating layer 22, the first insulating layer 21, and so on are repeated in order from the left. Will be.
  • one second insulating layer 22 is necessarily arranged next to each first insulating layer 21.
  • the electric field can be concentrated on the second insulating layer 22 not including the gate electrode 31 instead of the first insulating layer 21 including the gate electrode 31.
  • the electric field intensity concerning each gate insulating film 21a can be relieved, and it can be expected to improve the avalanche breakdown resistance.
  • the number of second insulating layers 22 can be reduced. As described above, since the gate electrode 31 is not provided in the second insulating layer 22, it becomes a useless region for flowing current. In this regard, according to the present embodiment, since the area occupied by the second insulating layer 22 can be reduced, it is possible to reduce a useless area for flowing current.
  • Silicon carbide semiconductor substrate (first conductivity type silicon carbide substrate) 12 n-type silicon carbide layer (first conductivity type silicon carbide layer) 13 p-type silicon carbide region (second conductivity type silicon carbide layer) 17 n-type source region (source region of first conductivity type) 18 High-concentration p-type silicon carbide region (second conductivity type silicon carbide layer) 21 First insulating layer 21a Gate insulating film 22 Second insulating layer 31 Gate electrode 32 Source electrode 36 Drain electrode

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Abstract

La présente invention est pourvue : d'une couche de carbure de silicium d'un premier type de conductivité 12 ; d'une pluralité de couches de carbure de silicium d'un second type de conductivité 13 qui sont disposées dans la direction horizontale sur la couche de carbure de silicium du premier type de conductivité 12 ; de zones de source du premier type de conductivité 17 qui sont formées dans les couches de carbure de silicium du second type de conductivité 13, respectivement. Des premières couches isolantes 21 sont disposées sur les couches de carbure de silicium du second type de conductivité 13 et les zones de source 17, et des secondes couches isolantes 22 sont disposées dans des zones qui se trouvent sur les couches de carbure de silicium du second type de conductivité 13 et qui ne sont pas positionnées sur les zones de source 17, respectivement. Une électrode de grille 31 est utilisée dans chacune des premières couches isolantes 21, mais n'est pas utilisée dans aucune des secondes couches isolantes 22. Dans la direction horizontale, les secondes couches isolantes 22 sont disposées adjacentes aux premières couches isolantes 21. Une seconde distance L2 entre les couches de carbure de silicium du second type de conductivité, positionnées au-dessous des secondes couches isolantes 22, est plus grande qu'une première distance L1 entre les couches de carbure de silicium du second type de conductivité, positionnées au-dessous des premières couches isolantes 21.
PCT/JP2014/075720 2014-09-26 2014-09-26 Dispositif à semi-conducteur au carbure de silicium Ceased WO2016046984A1 (fr)

Priority Applications (2)

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JP2015504450A JP5784860B1 (ja) 2014-09-26 2014-09-26 炭化ケイ素半導体装置
PCT/JP2014/075720 WO2016046984A1 (fr) 2014-09-26 2014-09-26 Dispositif à semi-conducteur au carbure de silicium

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281662A (ja) * 1989-04-21 1990-11-19 Mitsubishi Electric Corp 半導体装置
JPH04767A (ja) * 1990-04-02 1992-01-06 Fuji Electric Co Ltd Ｍｏｓ型半導体素子
JP2000294770A (ja) * 1999-04-09 2000-10-20 Rohm Co Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02281662A (ja) * 1989-04-21 1990-11-19 Mitsubishi Electric Corp 半導体装置
JPH04767A (ja) * 1990-04-02 1992-01-06 Fuji Electric Co Ltd Ｍｏｓ型半導体素子
JP2000294770A (ja) * 1999-04-09 2000-10-20 Rohm Co Ltd 半導体装置

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