[go: up one dir, main page]

WO2015122242A1 - Élément de conversion photoélectrique à jonction arrière et système de génération d'énergie photovoltaïque solaire - Google Patents

Élément de conversion photoélectrique à jonction arrière et système de génération d'énergie photovoltaïque solaire Download PDF

Info

Publication number
WO2015122242A1
WO2015122242A1 PCT/JP2015/051340 JP2015051340W WO2015122242A1 WO 2015122242 A1 WO2015122242 A1 WO 2015122242A1 JP 2015051340 W JP2015051340 W JP 2015051340W WO 2015122242 A1 WO2015122242 A1 WO 2015122242A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
silicon substrate
photoelectric conversion
conversion element
amorphous semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2015/051340
Other languages
English (en)
Japanese (ja)
Inventor
和也 辻埜
神川　剛
真臣 原田
直城 小出
親扶 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of WO2015122242A1 publication Critical patent/WO2015122242A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
    • H02S10/00—PV power plants; Combinations of PV energy systems with other systems for the generation of electric power
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/219—Arrangements for electrodes of back-contact photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a back junction type photoelectric conversion element and a photovoltaic power generation system.
  • photoelectric conversion elements have attracted attention.
  • As the photoelectric conversion element there is a back contact type photoelectric conversion element.
  • the back junction type photoelectric conversion element is disclosed in, for example, JP-T-2012-519375. In this publication, irregularities are formed on the entire front and back surfaces.
  • the short-circuit current can be increased.
  • the open circuit voltage decreases. As a result, conversion efficiency may be reduced.
  • An object of the present invention is to provide a back junction type photoelectric conversion element capable of suppressing a decrease in open-circuit voltage and increasing conversion efficiency even when unevenness is formed on the back surface. .
  • a back junction photoelectric conversion element includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode.
  • the first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate.
  • the second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed on the back side of the silicon substrate.
  • the first electrode is formed in contact with the first semiconductor layer.
  • the second electrode is formed in contact with the second semiconductor layer. Irregularities are formed on the back surface of the silicon substrate and in the region where the first semiconductor layer is formed.
  • the average surface roughness Ra is 0.75 nm or less.
  • the back junction type photoelectric conversion element according to the embodiment of the present invention, it is possible to increase the conversion efficiency by suppressing the reduction of the open circuit voltage.
  • FIG. 2 is a cross-sectional view for explaining a method of manufacturing the back junction photoelectric conversion element shown in FIG. 1, in which an intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer are formed on the entire light receiving surface of a silicon substrate.
  • FIG. 5 is a cross-sectional view showing a state in which an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on a part of the back surface of the silicon substrate. It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG. 1, Comprising: The intrinsic
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of a back junction photoelectric conversion element according to Comparative Example 2.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of a back junction photoelectric conversion element according to Comparative Example 3.
  • FIG. It is sectional drawing which shows an example of schematic structure of the back junction type photoelectric conversion element by the 2nd Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG.
  • FIG. 8 Comprising: A texture structure is formed in the whole light-receiving surface of a silicon substrate, and unevenness
  • FIG. 9 is a cross-sectional view for explaining a manufacturing method of the back junction type photoelectric conversion element shown in FIG. 8 and showing a state in which an n-type diffusion region and a p-type diffusion region are formed on the back surface side of the silicon substrate. It is. It is sectional drawing for demonstrating the manufacturing method of the back junction type photoelectric conversion element shown in FIG.
  • a back junction photoelectric conversion element includes a silicon substrate, a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode.
  • the first semiconductor layer has a first conductivity type and is formed on the back side of the silicon substrate.
  • the second semiconductor layer has a second conductivity type opposite to the first conductivity type, and is formed on the back side of the silicon substrate.
  • the first electrode is formed in contact with the first semiconductor layer.
  • the second electrode is formed in contact with the second semiconductor layer. Irregularities are formed on the back surface of the silicon substrate and in the region where the first semiconductor layer is formed.
  • the average surface roughness Ra is 0.75 nm or less.
  • the short circuit current can be increased by forming irregularities on the back surface of the silicon substrate. This is because light absorption increases when light on the long wavelength side is reflected and returned into the silicon substrate.
  • the back junction type photoelectric conversion element irregularities are formed in a region of the back surface of the silicon substrate where the first semiconductor layer in contact with the first electrode is formed. Therefore, the short circuit current can be increased.
  • the average surface roughness Ra is 0.75 nm or less in the region where the second semiconductor layer in contact with the second electrode is formed on the back surface of the silicon substrate.
  • the oxygen concentration at the interface between the silicon substrate and the second semiconductor layer is 1.2 ⁇ 10 20 cm ⁇ 3 or less. Therefore, surface recombination in the region can be reduced. As a result, it is possible to suppress a decrease in the open circuit voltage.
  • the average surface roughness Ra of the region where the second semiconductor layer in contact with the second electrode is formed on the back surface of the silicon substrate is 0.40 nm or less.
  • the oxygen concentration at the interface between the silicon substrate and the second semiconductor layer is 8 ⁇ 10 19 cm ⁇ 3 or less. As a result, surface recombination in the region can be further reduced.
  • the first semiconductor layer may be the first diffusion region
  • the second semiconductor layer may be the second diffusion region.
  • the first diffusion region is a region formed in the silicon substrate and in which the first conductivity type impurity is diffused.
  • the second diffusion region is a region formed in the silicon substrate and diffused with the second conductivity type impurity. Even with such a back junction type photoelectric conversion element, the conversion efficiency can be improved.
  • the back junction photoelectric conversion element may further include an intrinsic amorphous semiconductor layer.
  • the intrinsic amorphous semiconductor layer is formed in contact with the back surface of the silicon substrate and is made of an intrinsic amorphous semiconductor.
  • the first semiconductor layer is a first amorphous semiconductor layer
  • the second semiconductor layer is a second amorphous semiconductor layer.
  • the first amorphous semiconductor layer is formed in contact with the intrinsic amorphous semiconductor layer and is made of an amorphous semiconductor containing an impurity of the first conductivity type.
  • the second amorphous semiconductor layer is formed in contact with the intrinsic amorphous semiconductor layer and is made of an amorphous semiconductor containing a second conductivity type impurity. Even with such a back junction type photoelectric conversion element, the conversion efficiency can be improved.
  • the photoelectric conversion element 10 includes a silicon substrate 12, intrinsic amorphous semiconductor layers 14 and 16 as intrinsic amorphous semiconductor layers, an n-type amorphous semiconductor layer 18 as a first semiconductor layer, and a second semiconductor layer.
  • a p-type amorphous semiconductor layer 20 an electrode 22 as a first electrode, an electrode 24 as a second electrode, an intrinsic amorphous semiconductor layer 26, an n-type amorphous semiconductor layer 28, a reflection A prevention film 30.
  • the silicon substrate 12 is an n-type single crystal silicon substrate.
  • the thickness of the silicon substrate 12 is, for example, 100 to 300 ⁇ m.
  • the specific resistance of the silicon substrate 12 is, for example, 1.0 to 10.0 ⁇ ⁇ cm.
  • a texture structure 32 is formed on the light receiving surface of the silicon substrate 12. Thereby, the light incident on the silicon substrate 12 can be confined and the light use efficiency can be improved.
  • the plane orientation of the silicon substrate 12 is preferably (100). Thereby, formation of the texture structure 32 becomes easy.
  • the light receiving surface of the silicon substrate 12 is covered with an intrinsic amorphous semiconductor layer 26.
  • the intrinsic amorphous semiconductor layer 26 is made of, for example, i-type amorphous silicon (a-Si).
  • the thickness of the intrinsic amorphous semiconductor layer 26 is, for example, 2 to 25 nm.
  • the intrinsic amorphous semiconductor layer 26 is covered with an n-type amorphous semiconductor layer 28.
  • the n-type amorphous semiconductor layer 28 is made of, for example, amorphous silicon containing an n-type impurity (for example, phosphorus).
  • the thickness of the n-type amorphous semiconductor layer 28 is, for example, 2 to 50 nm.
  • the n-type amorphous semiconductor layer 28 is covered with an antireflection film 30.
  • the antireflection film 30 is made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. In consideration of passivation of the surface of the n-type amorphous semiconductor layer 28, the antireflection film 30 is preferably made of silicon nitride or silicon oxynitride. The thickness of the antireflection film 30 is, for example, 80 to 300 nm.
  • the back surface of the silicon substrate 12 is covered with intrinsic amorphous semiconductor layers 14 and 16.
  • the intrinsic amorphous semiconductor layers 14 and 16 are made of, for example, i-type amorphous silicon (a-Si).
  • the intrinsic amorphous semiconductor layer 14 is formed on a part of the back surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layer 16 is formed adjacent to the region where the intrinsic amorphous semiconductor layer 14 is formed on the back surface of the silicon substrate 12. That is, the intrinsic amorphous semiconductor layers 14 and 16 are formed on the entire back surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layers 14 and 16 have a thickness of 2 to 10 nm, for example.
  • the n-type amorphous semiconductor layer 18 is made of amorphous silicon containing an n-type impurity (for example, phosphorus).
  • the thickness of the n-type amorphous semiconductor layer 18 is, for example, 2 to 50 nm.
  • the p-type amorphous semiconductor layer 20 is made of amorphous silicon containing a p-type impurity (for example, boron).
  • the thickness of the p-type amorphous semiconductor layer 20 is, for example, 2 to 50 nm.
  • the electrode 22 is formed in contact with the n-type amorphous semiconductor layer 18. Thereby, the electrode 22 is electrically connected to the n-type amorphous semiconductor layer 18.
  • the electrode 22 includes a transparent conductive layer 22A and a metal layer 22B.
  • the transparent conductive layer 22A is formed in contact with the n-type amorphous semiconductor layer 18.
  • the transparent conductive layer 22A is made of indium tin oxide (ITO), for example.
  • the metal layer 22B is formed in contact with the transparent conductive layer 22A.
  • the metal layer 22B is made of, for example, silver.
  • the electrode 24 is formed in contact with the p-type amorphous semiconductor layer 20. Thereby, the electrode 24 is electrically connected to the p-type amorphous semiconductor layer 20.
  • the electrode 24 includes a transparent conductive layer 24A and a metal layer 24B.
  • the transparent conductive layer 24 ⁇ / b> A is formed in contact with the p-type amorphous semiconductor layer 20.
  • the transparent conductive layer 24A is made of indium tin oxide (ITO), for example.
  • the metal layer 24B is formed in contact with the transparent conductive layer 24A.
  • the metal layer 24B is made of silver, for example.
  • irregularities 34 are formed in a region overlapping the n-type amorphous semiconductor layer 18 on the back surface of the silicon substrate 12. Therefore, on the surface of the intrinsic amorphous semiconductor layer 14, irregularities 34 ⁇ / b> A corresponding to the irregularities 34 formed on the back surface of the silicon substrate 12 are formed. Further, on the surface of the n-type amorphous semiconductor layer 18, irregularities 34 ⁇ / b> B corresponding to the irregularities 34 formed on the back surface of the silicon substrate 12 are formed.
  • the unevenness 34 has, for example, a texture structure.
  • the unevenness 34 may have regularity or may be random.
  • the height difference of the unevenness 34 may be the same as or different from the height difference of the texture structure 32.
  • the ratio of the formation region of the unevenness 34 to the entire back surface of the silicon substrate 12 is preferably 20 to 80%. In this case, the short circuit current can be increased.
  • the height difference of the irregularities 34 is preferably 1 to 10 ⁇ m. In this case, the short circuit current can be increased.
  • the average surface roughness Ra of the region where the irregularities 34 are not formed on the back surface of the silicon substrate 12 is 0.75 nm or less, and preferably 0.40 nm or less.
  • the average surface roughness Ra is an index for quantifying the surface unevenness (height difference) measured by an atomic force microscope (AFM), and is defined by the following equation.
  • Z (i) is a height difference (surface height) at a certain measurement point
  • Ze is an average value of the height difference (surface height).
  • Ra is defined as described above. However, even if “the average surface roughness Ra of the region where the unevenness 34 is not formed is 0.75 nm or less” is described, the unevenness In all the regions where 34 is not formed, Ra is not completely 0.75 nm or less. For example, there may be a case where a part of the abnormality is formed. However, the abnormal part is very small in area. Therefore, the effects described in the embodiments of the present invention are not affected. Even if the average surface roughness Ra of the region where the unevenness 34 is not formed is described as 0.75 nm or less, the average surface roughness is 90% or more of the total area of the region where the unevenness 34 is not formed. If is within the stated range, there will be no problem.
  • a silicon substrate 12 having a texture structure 32 on the entire light-receiving surface and having irregularities 34 on a part of the back surface is prepared. Specifically, it is as follows.
  • the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate to be obtained later varies depending on the mixing ratio of the hydrofluoric acid solution and the processing time.
  • hydrofluoric acid for example, hydrofluoric acid (HF) is 8.3% by weight, nitric acid (HNO 3 ) is 50.0%, and water (H 2 O) is 41.7% by weight. .
  • the etching time is, for example, 1 minute.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film is patterned by photolithography.
  • the silicon oxide film remains only on a part of the back surface of the silicon substrate.
  • the silicon substrate is wet etched.
  • the texture structure 32 is formed on the entire light receiving surface, and the unevenness 34 is formed on a part of the back surface.
  • the solution used for the wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water.
  • KOH potassium hydroxide
  • IPA isopropyl alcohol
  • the proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight.
  • the proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight.
  • the temperature of the solution is, for example, 80 to 90 ° C.
  • the etching time is, for example, 10 to 60 minutes.
  • the texture 32 on the light receiving surface and the unevenness on the back surface are formed at the same time.
  • they can be formed separately as follows.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon substrate is wet etched.
  • the texture structure 32 is formed in the whole light-receiving surface.
  • the solution used for wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water.
  • KOH potassium hydroxide
  • IPA isopropyl alcohol
  • the proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight.
  • the proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight.
  • the temperature of the solution is, for example, 80 to 90 ° C.
  • the etching time is, for example, 10 to 60 minutes.
  • a silicon oxide film is formed on the light receiving surface of the silicon substrate on which the texture structure 32 is formed by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film on the back surface is patterned by photolithography.
  • the silicon oxide film remains only on a part of the light receiving surface and the back surface of the silicon substrate.
  • the silicon substrate is wet etched.
  • corrugation 34 is formed in a part of back surface.
  • the solution used for wet etching is, for example, potassium hydroxide (KOH) and isopropyl alcohol (IPA) dissolved in water.
  • the proportion of potassium hydroxide in the solution is, for example, 1 to 5% by weight.
  • the proportion of isopropyl alcohol in the solution is, for example, 1 to 10% by weight.
  • the temperature of the solution is, for example, 80 to 90 ° C.
  • the etching time is, for example, 10 to 60 minutes.
  • the conditions of the composition, concentration, temperature, and time of the solution at this time may be the same as those in the above-described wet etching of the light receiving surface, but may be different. If they are different, irregularities different from the texture of the light receiving surface can be formed.
  • the texture structure 32 formed on the entire light receiving surface and the unevenness 34 formed on a part of the back surface it remains on a part of the back surface of the silicon substrate 12 or a part of the light receiving surface and the back surface.
  • the silicon oxide film is removed by wet etching using 5.2 wt% hydrofluoric acid. Thereby, the target silicon substrate 12 is obtained.
  • the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate is 0.26 nm.
  • an intrinsic amorphous semiconductor layer 26 and an n-type amorphous semiconductor layer 28 are formed on the light receiving surface of the silicon substrate 12, and intrinsic non-existence is formed on a part of the back surface of the silicon substrate 12.
  • a crystalline semiconductor layer 16 and a p-type amorphous semiconductor layer 20 are formed. Specifically, it is as follows.
  • the intrinsic amorphous semiconductor layer 26 and the n-type amorphous semiconductor layer 28 are formed on the light receiving surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layer 26 and the n-type amorphous semiconductor layer 28 can be formed by, for example, a plasma CVD method.
  • an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer are formed on the back surface of the silicon substrate 12.
  • the intrinsic amorphous semiconductor layer and the p-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
  • the intrinsic amorphous semiconductor layer and the p-type amorphous semiconductor layer are patterned by photolithography. As a result, the region where the irregularities 34 are formed is exposed on the back surface of the silicon substrate 12, and the other region is covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20.
  • the intrinsic amorphous semiconductor layer 14 and the region not covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20 on the back surface of the silicon substrate 12 are formed.
  • An n-type amorphous semiconductor layer 18 is formed. Specifically, it is as follows.
  • an intrinsic amorphous semiconductor layer and an n-type amorphous semiconductor layer that cover the back surface of the silicon substrate 12 and the p-type amorphous semiconductor layer 20 are formed.
  • the intrinsic amorphous semiconductor layer and the n-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
  • the intrinsic amorphous semiconductor layer and the n-type amorphous semiconductor layer are patterned by photolithography.
  • the intrinsic amorphous semiconductor layer 14 and the n-type amorphous semiconductor layer are formed on the back surface of the silicon substrate 12 in a region not covered with the intrinsic amorphous semiconductor layer 16 and the p-type amorphous semiconductor layer 20. 18 is formed.
  • an antireflection film 30 is formed on the n-type amorphous semiconductor layer 28.
  • the antireflection film 30 can be formed by, for example, a plasma CVD method.
  • electrodes 22 and 24 are formed as shown in FIG. 2E. Specifically, it is as follows.
  • a transparent conductive layer covering the n-type amorphous semiconductor layer 18 and the p-type amorphous semiconductor layer 20 is formed.
  • the transparent conductive layer can be formed by sputtering, for example.
  • the metal layer can be formed by sputtering or vapor deposition, for example.
  • the transparent conductive layer and the metal layer are patterned by photolithography. Thereby, the electrodes 22 and 24 are formed, and the target photoelectric conversion element 10 is obtained.
  • FIG. 3 shows a photoelectric conversion element 10A according to an application example of the first embodiment.
  • unevenness 34 is formed in a region of the back surface of the silicon substrate 12 where the p-type amorphous semiconductor layer 20 overlaps when viewed from the thickness direction of the silicon substrate 12.
  • the average surface roughness Ra of the region where the unevenness 34 is not formed on the back surface of the silicon substrate 12 is 0.75 nm or less. Also in the photoelectric conversion element 10A, as in the first embodiment, it is possible to improve conversion efficiency while suppressing a decrease in open-circuit voltage.
  • the photoelectric conversion characteristics of the photoelectric conversion element 10 according to the first embodiment and the photoelectric conversion element 10A according to the application example of the first embodiment were evaluated using a solar simulator.
  • a photoelectric conversion element (Example 1) having an average surface roughness Ra of 0.26 nm and a photoelectric conversion element (average surface roughness Ra of 0.40 nm) ( Example 2), a photoelectric conversion element (Example 3) having an average surface roughness Ra of 0.53 nm, a photoelectric conversion element (Example 4) having an average surface roughness Ra of 0.75 nm, and an average surface A photoelectric conversion element (Comparative Example 1) having a roughness Ra of 1.02 nm was prepared.
  • a photoelectric conversion element (Example 5) having an average surface roughness Ra of 0.26 nm was prepared.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 8.3% by weight for hydrofluoric acid (HF), 50.0% for nitric acid (HNO 3 ), and 41.7% by weight for water (H 2 O).
  • the etching time was 1 minute.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid is 3.9% by weight for hydrofluoric acid (HF) and 55% for nitric acid (HNO 3 ). . 3% and water (H 2 O) was 40.8% by weight.
  • the etching time was 2 minutes.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 2.0% by weight for hydrofluoric acid (HF), 57.6% for nitric acid (HNO 3 ), and 40.4% by weight for water (H 2 O).
  • the etching time was 3 minutes.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 0.4% by weight for hydrofluoric acid (HF), 59.5% for nitric acid (HNO 3 ), and 40.1% by weight for water (H 2 O).
  • the etching time was 5 minutes.
  • the conditions for etching the silicon substrate with a hydrofluoric acid solution were as follows.
  • the mixing ratio of hydrofluoric acid was 0.3% by weight for hydrofluoric acid (HF), 43.8% for nitric acid (HNO 3 ), and 55.9% by weight for water (H 2 O).
  • the etching time was 30 minutes.
  • the concentration profile of oxygen atoms in the vicinity of the interface between the intrinsic amorphous semiconductor layer and the silicon substrate was measured using SIMS (Secondary Ion Mass Spectrometer). .
  • FIG. 4 shows oxygen atom concentration profiles of Example 2 and Example 4 measured by SIMS.
  • the concentration of oxygen atoms had a peak at the interface between the intrinsic amorphous semiconductor layer and the silicon substrate.
  • the oxygen concentration also had a peak at the interface in the other examples and comparative examples.
  • the relationship between the value of the oxygen concentration at the peak and the average surface roughness Ra of the substrate is shown in FIG. As shown in FIG. 5, the oxygen concentration was low when Ra was small. When Ra was 0.75 nm or less, the oxygen concentration was 1.2 ⁇ 10 20 cm ⁇ 3 or less, and particularly when Ra was 0.40 nm or less, the oxygen concentration was lowered to 8 ⁇ 10 19 cm ⁇ 3 or less.
  • the photoelectric conversion characteristics of the photoelectric conversion elements shown in FIGS. 6 and 7 were evaluated.
  • the unevenness 34 is not formed on the back surface of the silicon substrate 12 as compared with the photoelectric conversion element 10.
  • the average surface roughness Ra of the back surface was 0.26 nm.
  • the photoelectric conversion element 70 shown in FIG. 7, as compared with the photoelectric conversion element 10, the unevenness 34 was formed on the entire back surface.
  • the cell area was 2 cm ⁇ 2 cm. Irradiation light was light equivalent to AM1.5.
  • Table 1 shows the evaluation results. In Table 1, the case of Comparative Example 2 is standardized.
  • Example 4 As can be seen from Table 1, in Examples 1 to 5, compared to Comparative Example 1, since the decrease in open-circuit voltage was suppressed, the conversion efficiency was improved. In Example 4, the conversion efficiency was improved as compared with Comparative Example 1. In Example 3, since the average surface roughness Ra was smaller than that in Example 4, the conversion efficiency was further improved. In Example 2, since the average surface roughness Ra was smaller than that in Example 3, the conversion efficiency was further improved. In Example 1, since the average surface roughness Ra was smaller than that in Example 2, the conversion efficiency was further improved.
  • the photoelectric conversion element 50 includes a silicon substrate 52, an antireflection film 54, a passivation film 56, a passivation film 58, an electrode 60, and an electrode 62.
  • the silicon substrate 52 is an n-type single crystal silicon substrate.
  • the thickness and specific resistance of the silicon substrate 52 are the same as those of the silicon substrate 12.
  • a texture structure 68 is formed on the light receiving surface of the silicon substrate 52.
  • the silicon substrate 52 includes an n-type diffusion region 64 as a first semiconductor layer and a p-type diffusion region 66 as a second semiconductor layer.
  • the impurity concentration of the n-type diffusion region 64 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the depth dimension (vertical dimension in FIG. 8) of the n-type diffusion region 64 is, for example, 0.3 to 1.0 ⁇ m.
  • the impurity concentration of the p-type diffusion region 66 is, for example, 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the depth dimension (vertical dimension in FIG. 8) of the p-type diffusion region 66 is, for example, 0.3 to 1.0 ⁇ m.
  • the light receiving surface of the silicon substrate 52 is covered with an antireflection film 54.
  • the antireflection film 54 is, for example, a silicon nitride film.
  • the thickness of the silicon nitride film is, for example, 80 to 300 nm.
  • the passivation film 56 is formed in contact with the p-type diffusion region 66.
  • the region where the p-type diffusion region 56 is formed on the back surface of the silicon substrate 52 is covered with the passivation 56.
  • the passivation film 56 is, for example, a silicon nitride film or a silicon oxynitride film.
  • the thickness of the passivation film 56 is, for example, 5 to 100 nm.
  • the passivation film 58 is formed in contact with the n-type diffusion region 64.
  • the region excluding the region where the p-type diffusion region 56 is formed on the back surface of the silicon substrate 52 is covered with the passivation 58.
  • the passivation film 58 is, for example, a silicon nitride film or a silicon oxynitride film.
  • the thickness of the passivation film 58 is, for example, 10 to 200 nm.
  • the electrode 60 is formed in contact with the n-type diffusion region 64. As a result, the electrode 60 is electrically connected to the n-type diffusion region 64.
  • the electrode 60 is made of, for example, silver.
  • the electrode 62 is formed in contact with the p-type diffusion region 66. Thereby, the electrode 62 is electrically connected to the p-type diffusion region 66.
  • the electrode 62 is made of silver, for example.
  • unevenness 70 is formed in a region other than the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate 52.
  • the unevenness 70 has, for example, a texture structure.
  • the unevenness 70 may have regularity or may be random.
  • the height difference of the unevenness 70 may be the same as or different from the height difference of the texture structure 68.
  • the ratio of the formation region of the unevenness 70 to the entire back surface of the silicon substrate 52 is preferably 20 to 80%. In this case, the short circuit current can be increased.
  • the height difference of the unevenness 70 is preferably 1 to 10 ⁇ m. In this case, the short circuit current can be increased.
  • the average surface roughness Ra of the region where the p-type diffusion region 66 is formed is 0.75 nm or less, and preferably 0.40 nm or less.
  • a silicon substrate 52 having a texture structure 68 on the entire light receiving surface and having irregularities 70 on a part of the back surface is prepared. Specifically, it is as follows.
  • a silicon substrate having a predetermined thickness is prepared by the method described in the first embodiment.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film is patterned by photolithography.
  • the silicon oxide film remains only on a part of the back surface of the silicon substrate.
  • the region where the silicon oxide film remains is a region where the p-type diffusion region 66 is formed later.
  • the silicon substrate is wet etched. Thereby, the texture structure 68 is formed on the entire light receiving surface, and the unevenness 70 is formed on a part of the back surface.
  • the texture 32 on the light receiving surface and the unevenness on the back surface are formed at the same time.
  • they can be formed separately as follows.
  • a silicon oxide film is formed on the back surface of the silicon substrate by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon substrate is wet etched. Thereby, the texture structure 32 is formed in the whole light-receiving surface.
  • a silicon oxide film is formed on the light receiving surface of the silicon substrate on which the texture structure 32 is formed by sputtering or the like.
  • the film thickness of the silicon oxide film is, for example, 100 to 1000 nm.
  • the silicon oxide film on the back surface is patterned by photolithography. As a result, the silicon oxide film remains only on a part of the light receiving surface and the back surface of the silicon substrate. At this time, the region where the silicon oxide film remains on the back surface is a region where the p-type diffusion region 66 is formed later. In this state, the silicon substrate is wet etched. Thereby, the unevenness
  • the conditions of the composition, concentration, temperature, and time of the solution at this time may be the same as those in the above-described wet etching of the light receiving surface, but may be different. If they are different, irregularities different from the texture of the light receiving surface can be formed.
  • an n-type diffusion region 64 and a p-type diffusion region 66 are formed on the back side of the silicon substrate 52. Specifically, it is as follows.
  • a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52.
  • an etching paste is printed on the silicon oxide film formed on the back surface of the silicon substrate 52.
  • Examples of a method for printing the etching paste include a screen printing method.
  • the silicon substrate 52 on which the etching paste is printed is heated. As a result, only the portion where the etching paste is printed is removed from the silicon oxide film formed on the back surface of the silicon substrate 52. Thereafter, the silicon substrate 52 is immersed in water and subjected to ultrasonic cleaning or the like. Thereby, the etching paste is removed.
  • boron as a p-type impurity is vapor-phase diffused.
  • a p-type diffusion region 66 is formed in a portion of the silicon substrate 52 that is not covered with the silicon oxide film.
  • the silicon oxide film formed on the light receiving surface and the back surface of the silicon substrate 52 and the BSG (Boron Silicate Glass) film formed by vapor-diffusing boron are removed using an aqueous hydrogen fluoride solution or the like.
  • the hydrogen fluoride aqueous solution at this time for example, a 5.2 wt% hydrofluoric acid aqueous solution can be used.
  • a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52.
  • the silicon oxide film formed on the back surface of the silicon substrate 52 is etched.
  • an etching method for example, there is a method using an etching paste.
  • phosphorus as an n-type impurity is vapor-phase diffused.
  • an n-type diffusion region 64 is formed in a portion of the silicon substrate 52 that is not covered with the silicon oxide film.
  • the silicon oxide film formed on the light receiving surface and the back surface of the silicon substrate 52, the PSG (Phosphorus Silicate Glass) film formed by vapor phase diffusion of phosphorus, and the like are removed using a hydrogen fluoride aqueous solution or the like.
  • a hydrogen fluoride aqueous solution for example, a 5.2 wt% hydrofluoric acid aqueous solution can be used.
  • the average surface roughness Ra of the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate is 0.75 nm or less.
  • the region where the p-type diffusion region 66 is formed on the back surface of the silicon substrate 52 is covered with the passivation film 56, and the other region is covered with the passivation film 58. Specifically, it is as follows.
  • a thermal oxidation process is performed on the silicon substrate 52.
  • a silicon oxide film is formed on the light receiving surface and the back surface of the silicon substrate 52.
  • the silicon oxide film formed on the back surface of the silicon substrate 52 is etched.
  • an etching method for example, there is a method using an etching paste.
  • a passivation film 58 that covers the back surface of the silicon substrate 52 and the passivation film 56 is formed.
  • the passivation film 58 can be formed by, for example, a plasma CVD method.
  • the silicon oxide film formed on the light receiving surface of the silicon substrate 52 is removed using a hydrogen fluoride aqueous solution or the like. 9C, the light receiving surface of the silicon substrate 52 is exposed, and the back surface of the silicon substrate 52 is covered with the passivation films 56 and 58.
  • an antireflection film 54 is formed on the light receiving surface of the silicon substrate 52.
  • the antireflection film 54 can be formed by, for example, a plasma CVD method or the like.
  • electrodes 60 and 62 are formed. Specifically, it is as follows.
  • a part of the passivation films 56 and 58 is removed by etching to form a contact hole.
  • the etching method include a method using an etching paste.
  • the average surface roughness Ra of the region where the n-type diffusion region 64 is formed in the back surface of the silicon substrate 52 is 0.75 nm, and the region where the n-type diffusion region 64 is formed in the back surface of the silicon substrate 52
  • the unevenness 70 may be formed in a region other than the above.
  • the photoelectric conversion element according to the embodiment of the present invention has high conversion efficiency. Therefore, the photoelectric conversion module and the photovoltaic power generation system including the photoelectric conversion element according to the embodiment of the present invention can also have high conversion efficiency.
  • FIG. 10 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the present embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1013 and 1014.
  • a plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series.
  • FIG. 10 an arrangement in which the photoelectric conversion elements 1001 are connected in series is illustrated, but the arrangement and connection method are not limited thereto, and the photoelectric conversion elements 1001 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • the photoelectric conversion element according to the embodiment of the present invention is used for each of the plurality of photoelectric conversion elements 1001, the photoelectric conversion element according to the embodiment of the present invention is used. Note that the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 can be any integer of 2 or more.
  • the cover 1002 is composed of a weatherproof cover and covers the plurality of photoelectric conversion elements 1001.
  • the output terminal 1013 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1014 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • FIG. 11 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • solar power generation system 2000 includes a photoelectric conversion module array 2001, a connection box 2002, a power conditioner 2003, a distribution board 2004, and a power meter 2005.
  • the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000.
  • the solar power generation system 2000 can be added with a function generally called “Home Energy Management System (HEMS)”. As a result, it is possible to contribute to power saving for each individual house while monitoring the power usage status of each room.
  • HEMS Home Energy Management System
  • connection box 2002 is connected to the photoelectric conversion module array 2001.
  • the power conditioner 2003 is connected to the connection box 2002.
  • the distribution board 2004 is connected to the power conditioner 2003 and the electrical equipment 2011.
  • the power meter 2005 is connected to the distribution board 2004 and the grid connection.
  • the photoelectric conversion module array 2001 generates sunlight by converting sunlight into electricity, and supplies the DC power to the connection box 2002.
  • connection box 2002 receives DC power generated by the photoelectric conversion module array 2001 and supplies DC power to the power conditioner 2003.
  • the power conditioner 2003 converts the DC power received from the connection box 2002 into AC power and supplies it to the distribution board 2004.
  • a part of the DC power received from the connection box 2002 may be supplied to the distribution board 2004 as it is without being converted into AC power.
  • Distribution board 2004 supplies at least one of AC power received from power conditioner 2003 and commercial power received via power meter 2005 to electrical equipment 2011.
  • the distribution board 2004 supplies the AC power received from the power conditioner 2003 to the electrical equipment 2011 when the AC power received from the power conditioner 2003 is larger than the power consumption of the electrical equipment 2011.
  • the distribution board 2004 supplies the surplus AC power to the grid connection via the power meter 2005.
  • the distribution board 2004 uses the AC power received from the grid connection and the AC power received from the power conditioner 2003 to the electrical equipment. To 2011.
  • the power meter 2005 measures the power in the direction from the grid connection to the distribution board 2004 and measures the power in the direction from the distribution board 2004 to the grid connection.
  • FIG. 12 is a schematic diagram showing an example of the configuration of the photoelectric conversion module array 2001 shown in FIG. Referring to FIG. 12, photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 and output terminals 2013 and 2014.
  • the plurality of photoelectric conversion modules 1000 are arranged in an array and connected in series.
  • FIG. 12 illustrates an arrangement in which the photoelectric conversion modules 1000 are connected in series, the arrangement and connection method are not limited to this, and the photoelectric conversion modules 1000 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • the number of photoelectric conversion modules 1000 included in the photoelectric conversion module array 2001 can be any integer of 2 or more.
  • the output terminal 2013 is connected to the photoelectric conversion module 1000 located at one end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the output terminal 2014 is connected to the photoelectric conversion module 1000 located at the other end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the solar power generation system of the present embodiment is not limited to the above description as long as it includes the photoelectric conversion element according to the embodiment of the present invention, and can take any configuration.
  • FIG. 13 is a schematic diagram illustrating another example of the configuration of the photovoltaic power generation system.
  • the photovoltaic power generation system shown in FIG. 13 is a larger scale photovoltaic power generation system than the photovoltaic power generation system shown in FIG.
  • the photovoltaic power generation system shown in FIG. 13 also includes the photoelectric conversion element according to the embodiment of the present invention.
  • solar power generation system 4000 includes a plurality of subsystems 4001, a plurality of power conditioners 4003, and a transformer 4004.
  • the plurality of power conditioners 4003 are each connected to the subsystem 4001.
  • the number of the power conditioners 4003 and the subsystems 4001 connected thereto can be any integer of 2 or more.
  • the transformer 4004 is connected to a plurality of power conditioners 4003 and grid interconnection.
  • Each of the plurality of subsystems 4001 includes a plurality of module systems 3000.
  • the number of module systems 3000 in the subsystem 4001 can be any integer greater than or equal to two.
  • Each of the plurality of module systems 3000 includes a plurality of photoelectric conversion module arrays 2001, a plurality of connection boxes 3002, and a current collection box 3004.
  • the number of the junction box 3002 in the module system 3000 and the photoelectric conversion module array 2001 connected to the junction box 3002 can be any integer of 2 or more.
  • the current collection box 3004 is connected to a plurality of connection boxes 3002.
  • the power conditioner 4003 is connected to a plurality of current collection boxes 3004 in the subsystem 4001.
  • the plurality of photoelectric conversion module arrays 2001 of the module system 3000 convert sunlight into electricity to generate DC power, and supply the DC power to the current collection box 3004 via the connection box 3002.
  • a plurality of current collection boxes 3004 in the subsystem 4001 supplies DC power to the power conditioner 4003.
  • the plurality of power conditioners 4003 convert DC power into AC power and supply the AC power to the transformer 4004.
  • the transformer 4004 converts the voltage level of AC power received from the plurality of power conditioners 4003 and supplies it to the grid interconnection.
  • the photovoltaic power generation system 4000 only needs to include the photoelectric conversion element according to the embodiment of the present invention, and all the photoelectric conversion elements included in the photovoltaic power generation system 4000 are the photoelectric conversion elements according to the embodiment of the present invention. Not necessarily. For example, all of the photoelectric conversion elements included in one subsystem 4001 are the photoelectric conversion elements according to the embodiment of the present invention, and part or all of the photoelectric conversion elements included in another subsystem 4001 are the implementation of the present invention. In some cases, the photoelectric conversion element may not be a photoelectric conversion element.

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

La présente invention porte sur un élément de conversion photoélectrique à jonction arrière qui est apte à augmenter l'efficacité de conversion par suppression de la diminution de la tension en circuit ouvert même dans des cas où la surface arrière de ce dernier comporte des renfoncements et des saillies. Cet élément de conversion photoélectrique (10) comporte un substrat au silicium (12), une première couche semi-conductrice (18), une seconde couche semi-conductrice (20), une première électrode (22) et une seconde électrode (24). La première couche semi-conductrice (18) a un premier type de conductivité, et est formée sur le côté de surface arrière du substrat au silicium (12). La seconde couche semi-conductrice (20) a un second type de conductivité qui est opposé au premier type de conductivité, et est formée sur le côté de surface arrière du substrat au silicium (12). La première électrode (22) est formée en contact avec la première couche semi-conductrice (18). La seconde électrode (24) est formée en contact avec la seconde couche semi-conductrice (20). Une région de la surface arrière du substrat au silicium (12), où la première couche semi-conductrice (18) est formée, comporte des renfoncements et des saillies. Une autre région de la surface arrière du substrat au silicium (12), où la seconde couche semi-conductrice (20) est formée, a une rugosité de surface moyenne (Ra) de 0,75 nm ou moins.
PCT/JP2015/051340 2014-02-13 2015-01-20 Élément de conversion photoélectrique à jonction arrière et système de génération d'énergie photovoltaïque solaire Ceased WO2015122242A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-025842 2014-02-13
JP2014025842 2014-02-13

Publications (1)

Publication Number Publication Date
WO2015122242A1 true WO2015122242A1 (fr) 2015-08-20

Family

ID=53799990

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/051340 Ceased WO2015122242A1 (fr) 2014-02-13 2015-01-20 Élément de conversion photoélectrique à jonction arrière et système de génération d'énergie photovoltaïque solaire

Country Status (1)

Country Link
WO (1) WO2015122242A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106087070A (zh) * 2016-07-11 2016-11-09 吕铁铮 一种金刚线硅片重结晶湿法制绒的方法
CN110797420A (zh) * 2018-07-17 2020-02-14 精工爱普生株式会社 光电转换元件、光电转换模块以及电子设备
TWI772432B (zh) * 2017-09-13 2022-08-01 日商鐘化股份有限公司 太陽能電池、太陽能電池之製造方法、及太陽能電池模組
JP2025515821A (ja) * 2022-09-08 2025-05-20 江蘇微導納米科技股▲ふん▼有限公司 電荷蓄積構造および電荷蓄積構造を製造する方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012521078A (ja) * 2009-03-17 2012-09-10 アイメック プラズマテクスチャ方法
WO2012132615A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Dispositif de conversion photoélectrique, et procédé de fabrication de celui-ci
JP2013128095A (ja) * 2011-12-16 2013-06-27 Lg Electronics Inc 太陽電池及びその製造方法
WO2013096500A1 (fr) * 2011-12-21 2013-06-27 Sunpower Corporation Cellule à contact arrière à hétérojonction polysilicium hybride
JP2013187287A (ja) * 2012-03-07 2013-09-19 Sharp Corp 光電変換素子
JP2014007284A (ja) * 2012-06-25 2014-01-16 Mitsubishi Electric Corp 太陽電池セルの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012521078A (ja) * 2009-03-17 2012-09-10 アイメック プラズマテクスチャ方法
WO2012132615A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Dispositif de conversion photoélectrique, et procédé de fabrication de celui-ci
JP2013128095A (ja) * 2011-12-16 2013-06-27 Lg Electronics Inc 太陽電池及びその製造方法
WO2013096500A1 (fr) * 2011-12-21 2013-06-27 Sunpower Corporation Cellule à contact arrière à hétérojonction polysilicium hybride
JP2013187287A (ja) * 2012-03-07 2013-09-19 Sharp Corp 光電変換素子
JP2014007284A (ja) * 2012-06-25 2014-01-16 Mitsubishi Electric Corp 太陽電池セルの製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106087070A (zh) * 2016-07-11 2016-11-09 吕铁铮 一种金刚线硅片重结晶湿法制绒的方法
CN106087070B (zh) * 2016-07-11 2018-11-09 湖南筱豪新能源有限公司 一种金刚线硅片重结晶湿法制绒的方法
TWI772432B (zh) * 2017-09-13 2022-08-01 日商鐘化股份有限公司 太陽能電池、太陽能電池之製造方法、及太陽能電池模組
CN110797420A (zh) * 2018-07-17 2020-02-14 精工爱普生株式会社 光电转换元件、光电转换模块以及电子设备
CN110797420B (zh) * 2018-07-17 2023-09-26 精工爱普生株式会社 光电转换元件、光电转换模块以及电子设备
JP2025515821A (ja) * 2022-09-08 2025-05-20 江蘇微導納米科技股▲ふん▼有限公司 電荷蓄積構造および電荷蓄積構造を製造する方法

Similar Documents

Publication Publication Date Title
US8569614B2 (en) Solar cell and method of manufacturing the same
CN105826411B (zh) 单晶硅双面太阳电池及其制备方法
US9806210B2 (en) Photoelectric conversion element
US20150349156A1 (en) Solar battery cell and method of manufacturing the same
JP6529437B2 (ja) 光電変換素子、光電変換モジュール、並びに、太陽光発電システム
EP2538447B1 (fr) Cellule solaire et son procédé de fabrication
JP6423373B2 (ja) 光電変換素子およびそれを備えた太陽電池モジュール
US9761743B2 (en) Photoelectric conversion element
WO2015122242A1 (fr) Élément de conversion photoélectrique à jonction arrière et système de génération d'énergie photovoltaïque solaire
JP2014011246A (ja) 太陽電池素子および太陽電池モジュール
WO2015122257A1 (fr) Élément de conversion photoélectrique
US20150372165A1 (en) Photoelectric converting element
US20160247949A1 (en) Photoelectric conversion element, photoelectric conversion module, and solar photovoltaic power generation system
KR101198438B1 (ko) 양면 수광형 국부화 에미터 태양전지 및 그 제조 방법
US10658526B2 (en) Photovoltaic device
US8445311B2 (en) Method of fabricating a differential doped solar cell
KR20120077710A (ko) 양면 수광형 국부화 에미터 태양전지 및 그 제조 방법
JP6389639B2 (ja) 光電変換素子
KR101251857B1 (ko) 양면 수광형 태양전지 제조 방법
JP6198813B2 (ja) 光電変換素子、光電変換モジュールおよび太陽光発電システム
KR101251878B1 (ko) 양면 수광형 태양전지 제조 방법
US20120132244A1 (en) Solar cell module with current control and method of fabricating the same
WO2015178305A1 (fr) Élément de conversion photoélectrique, et procédé de fabrication de celui-ci
WO2015178307A1 (fr) Élément de conversion photoélectrique
KR101251856B1 (ko) 양면 수광형 태양전지 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15749252

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15749252

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP