[go: up one dir, main page]

WO2015104084A1 - Dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées et procédé de fabrication correspondant - Google Patents

Dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées et procédé de fabrication correspondant Download PDF

Info

Publication number
WO2015104084A1
WO2015104084A1 PCT/EP2014/075092 EP2014075092W WO2015104084A1 WO 2015104084 A1 WO2015104084 A1 WO 2015104084A1 EP 2014075092 W EP2014075092 W EP 2014075092W WO 2015104084 A1 WO2015104084 A1 WO 2015104084A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
region
substrate
transistor device
mosfet transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2014/075092
Other languages
German (de)
English (en)
Inventor
Christian Tobias Banzhaf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of WO2015104084A1 publication Critical patent/WO2015104084A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 

Definitions

  • the present invention relates to a trench MOSFET transistor device, a substrate for a trench MOSFET transistor device and a corresponding manufacturing method.
  • Substrates comprising a silicon carbide layer are finding increasing use for standard components.
  • power semiconductors which block voltages of more than 1.2 kV are realized as a trench metal-oxide-semiconductor field-effect transistor (trench MOSFET) using such substrates.
  • trench MOSFET trench metal-oxide-semiconductor field-effect transistor
  • Such power semiconductors find, for example, in electromobile applications, ie
  • Automotive vehicles with batteries such as lithium-ion cell based batteries or in photovoltaic systems use.
  • microelectromechanical systems can be realized with such substrates.
  • a substrate (n-doped 4H-) for example, a substrate (n-doped 4H-
  • SiC substrate whose silicon carbide layer has a hexagonal crystal structure.
  • a trench is patterned perpendicular to the substrate surface in a dry chemical plasma etching process.
  • the ditch is going through
  • FIG. 7 is a schematic cross-sectional view of a trench type MOSFET transistor device known from JP2010-258385 A.
  • reference numeral 1 denotes a silicon carbide substrate, which is a
  • Front V and a back R has.
  • the reverse side R has the substrate 1 which has a basic doping of the n + type, a drain terminal portion 1 a n + -type.
  • the back R is on the drain connection area 1 a a
  • Drain metallization 10 is provided.
  • an epitaxial drift region 1 b includes the n "type in.
  • On the front side V is provided in connection to the drift region 1 b is a p-doped region 1c, which is formed for example by epitaxy or implantation.
  • From the A trench G extends into the interior of the substrate 1 as far as into the drift region 1b in the interior of the trench G.
  • a gate dielectric layer 3 is deposited in the interior of the trench G and a gate metallization 30 is provided on the side of the trench G in the p-doped region 1c is an n + -type source region 5 with a source metallization 20. Will become a
  • FIG. 8 shows a schematic cross-sectional representation of a trench MOSFET transistor device described in DE 10 2013 209 256.3.
  • an additional p + -doped separation region 1d is provided between adjacent trenches G to reduce the stress of the gate dielectric 3 specifically in the lower corners of the trench G, and thus a sufficient blocking capability of the transistor device to ensure.
  • this requires ion implantation with high ion energy in order to achieve a sufficiently deep extension of the p + separation region 1 d into the interior of the substrate 1, preferably to at least the depth extent of the trench G or even more deeper.
  • Such an implantation is very time-consuming, because multiple ionized ions must be used, whereby only a very small implantation current comes about.
  • such an implantation requires very high acceleration voltages, which only a few implantation devices or production environments can provide.
  • such a large collision energy leads to
  • the present invention provides a trench MOSFET transistor device according to claim 1, a substrate for a trench MOSFET transistor device according to claim 6 and a corresponding manufacturing method according to claim 10.
  • Dry etch processes which structure narrow trenches with a high aspect ratio at a lower etching rate than wide trenches with a low
  • the deep implantation for the separation regions which takes place in the narrow trenches according to the invention, can separate adjacent trenches with gate structures in such a way that a field can no longer act on the gate dielectric, since it is about the
  • the body diode can be designed as a pure pn diode.
  • the inventive trench MOSFET transistor device the corresponding substrate for a trench MOSFET transistor device and the corresponding
  • Manufacturing processes make it possible to minimize the cost of further process steps and at the same time greatly increase the quality of the component.
  • a source metallization is provided on the front side of the substrate and the second trench with a
  • the buried doped separation region can advantageously be electrically connected.
  • a buried third doping region of the second conductivity type is provided below the first trench. This allows the short circuit risk to be further reduced.
  • a plurality of spaced-apart second trenches having the second depth extension are arranged from the front side in the first doping region laterally from the source connection region, below which a contiguous buried second doping region of the second conductivity type is arranged with the third depth extension.
  • the substrate is a
  • Silicon carbide substrate Such a substrate is of good short-circuit strength.
  • 1 is a schematic cross-sectional view of a trench MOSFET
  • Fig. 2a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the first embodiment of the present invention in successive stages of manufacture; 3 is a schematic cross-sectional view of a trench MOSFET
  • Fig. 4a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the second embodiment of the present invention in successive stages of manufacture; a schematic cross-sectional view of a trench MOSFET transistor device according to a third embodiment of the present invention;
  • FIG. 6a), b) show schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the third embodiment of the present invention in successive stages of manufacture;
  • FIG. 7 is a schematic cross-sectional view of a trench MOSFET transistor device known from JP2010-258385 A;
  • FIG. 8 shows a schematic cross-sectional representation of a trench MOSFET transistor device described in DE 10 2013 209 256.3.
  • FIG. 1 is a schematic cross-sectional view of a trench MOSFET transistor device according to a first embodiment of the present invention.
  • the first embodiment in contrast to the known trench MOSFET
  • Transistor device shown in FIG. 7 or FIG. 8 a buried, preferably annular, separation region I provided in the substrate 1, which are of the p + -type and has been generated by an ion implantation in the narrow trenches G '.
  • the buried separation region I adjoins that of the front side V of the
  • Substrate 1 outgoing narrow trench G ' which has a smaller depth extension T' than a depth extension T of the trench G for the gate structure is.
  • the separation region I adjoining the underside of the trench G ' in turn, has a depth extent T "which is at least as great as the depth extent T of the trench G (see FIG. 2a), b)).
  • the narrow trench G ' is filled with a metallization region 20a which corresponds to the source metallization 20, whereby the separation region I is set to the same potential as the source region 5.
  • the metallization region 20a for the trench G 'could also be realized with a different metallization which is then in electrical contact with the source metallization 20. Due to the fact that for the production of the separation region I, which is carried out by implantation of the unfilled narrow trench G ', a lower implantation depth and thus a lower implantation energy is necessary, the damage to the crystal structure in the region of the separation region I is much lower than in the prior art and can thus be healed much easier, for example in a corresponding Anneal polish.
  • FIG. 2a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the first embodiment of the present invention in successive stages of manufacture.
  • the silicon carbide substrate 1 is patterned to make the trenches G and G 'in a single anisotropic plasma etching step AE using a mask M, taking advantage of the ARDE effect.
  • the depth extent T of the trench G for the gate structure is low
  • the ratio of the depth extents T '/ T can be adjusted accordingly.
  • the mask M for the plasma etching step is replaced by a mask M 'for the implantation of the separation region I, which in particular protects the gate G for the gate structure.
  • the implantation step IS which is carried out to produce the separation region I, only the region below the trench G 'is implanted and thus the p + -type separation region I is produced, which has the depth extent T "which is at least as great as that Depth extension T of the trench G.
  • the remaining process steps for producing the trench MOSFET transistor device according to FIG. 1 are carried out in a known manner, as known, for example, from JP 2010/258385 A.
  • FIG. 3 shows a schematic cross-sectional view of a trench MOSFET transistor device according to a second embodiment of the present invention.
  • an additional p + -type separation region 11 below the trench G for the second embodiment is provided.
  • Gate structure provided. This additionally reduces field effects at the lower corners of the trench G.
  • the representation according to FIG. 4a) corresponds to the representation according to FIG. 2a). Still referring to Fig. 4b), in the second embodiment, however, the mask M for the plasma etching step after the simultaneous formation of the trenches G, G 'is left on the front side V of the substrate 1, followed by the implantation step IS, simultaneously the separation region I below the narrow trench G 'and the separation region 11 below the trench G for the
  • the further masking step is omitted, which leads to a further simplification of the method.
  • 5 shows a schematic cross-sectional representation of a trench MOSFET
  • Transistor device according to a third embodiment of the present invention.
  • the third embodiment relates to the case in which the p + -doped separation region ⁇ should have a greater width extension.
  • a plurality of adjacent narrow trenches GT, G2 ', G3' are provided, through which the implantation step IE can take place. Due to the lateral extent of the implantation region, a laterally widened contiguous separation region ⁇ thus forms in the periphery of the trench G for the gate structure.
  • the trenches G1 ', G2', G3 ' are filled with corresponding metallization regions 20a', 20a ", 20a '", which correspond to either the source metallization 20 or a separate one
  • Metallization in electrical contact with the source metalization are 20.
  • an additional separation region 11 is provided below the trench G for the gate structure.
  • the third embodiment is the same as the second embodiment.
  • 6a), b) are schematic cross-sectional views of a substrate for a trench MOSFET transistor device according to the third embodiment of the present invention in successive stages of manufacture.
  • Gate structure also in the third embodiment simultaneously with the trenches GT, G2 ', G3' for the implantation of the separation region ⁇ produced.
  • the mask M1 used in this case can, as shown in FIG. 6b), also be used for the ion implantation step IS, in which the contiguous p + -type separation region ⁇ below the trenches GT, G2 ', G3' simultaneously with the additional separation region 11 below the trench G for the gate structure.

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées et un procédé de fabrication correspondant. Le dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées comprend : un substrat (1) d'un premier type de conductivité (n+) pourvu d'une face avant (V) et d'une face arrière (R) ; une zone de drain (1a) du premier type de conductivité (n+) au niveau de la face arrière (R) du substrat (1) ; une zone de dérive (1b) du premier type de conductivité (n-) raccordée à la zone de drain (la) ; une première zone de dopage (1c) du deuxième type de conductivité (p) raccordée à la zone de dérive (1b) ; et une zone de source (5) du premier type de conductivité (n+) au niveau de la face avant (V) du substrat (1) ; une première tranchée (G) présentant une première étendue en profondeur (T), laquelle tranchée est formée à partir de la face avant (V) du substrat (1) dans la zone de source (5), la première zone de dopage (1c) et la zone de dérive (1b) et dans laquelle une structure de grille (3, 30) est située, de sorte qu'à la suite de l'application d'une tension, une zone de canal (K) peut être formée dans la première zone de dopage (1c) entre la zone de dérive (1b) et la zone de source (5) ; une deuxième tranchée (G' ; G1', G2', G3') présentant une deuxième étendue en profondeur (Τ') inférieure à la première étendue en profondeur (T), laquelle tranchée est disposée à partir de la face avant (V) dans la première zone de dopage (1c) à côté de la zone de source (5) ; et une deuxième zone de dopage (I ; I') du deuxième type de conductivité (p+) enterrée au-dessous de la deuxième tranchée (G' ; G1', G2', G3'), ladite tranchée présentant une troisième étendue en profondeur (T") au moins aussi importante que la première étendue en profondeur (T).
PCT/EP2014/075092 2014-01-13 2014-11-20 Dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées et procédé de fabrication correspondant Ceased WO2015104084A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014200429.2A DE102014200429A1 (de) 2014-01-13 2014-01-13 Trench-MOSFET-Transistorvorrichtung, Substrat für Trench-MOSFET-Transistorvorrichtung und entsprechendes Herstellungsverfahren
DE102014200429.2 2014-01-13

Publications (1)

Publication Number Publication Date
WO2015104084A1 true WO2015104084A1 (fr) 2015-07-16

Family

ID=51945876

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2014/075092 Ceased WO2015104084A1 (fr) 2014-01-13 2014-11-20 Dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées et procédé de fabrication correspondant

Country Status (2)

Country Link
DE (1) DE102014200429A1 (fr)
WO (1) WO2015104084A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3264470A1 (fr) 2016-06-29 2018-01-03 ABB Schweiz AG Mosfet de puissance à tranchée à canal court
WO2019053199A1 (fr) 2017-09-15 2019-03-21 Ascatron Ab Concept pour dispositifs de puissance au carbure de silicium
US11114557B2 (en) 2017-09-15 2021-09-07 Ii-Vi Delaware, Inc. Integration of a Schottky diode with a MOSFET
US11158706B2 (en) 2017-09-15 2021-10-26 II-VI Delaware, Inc Feeder design with high current capability
US11342423B2 (en) 2017-09-15 2022-05-24 Ii-Vi Delaware, Inc. Method for manufacturing a grid
WO2023231502A1 (fr) * 2022-06-02 2023-12-07 中芯越州集成电路制造(绍兴)有限公司 Dispositif dmos à tranchée et son procédé de fabrication

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250120133A1 (en) * 2023-10-06 2025-04-10 Wolfspeed, Inc. Gate trench power semiconductor devices having deep support shields and methods of fabricating such device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047045A1 (fr) * 1996-06-06 1997-12-11 Cree Research, Inc. Transistor a effet de champ metal-isolant semi-conducteur en carbure de silicium
DE102005020075A1 (de) * 2005-04-29 2006-11-09 Infineon Technologies Ag Verfahren zum Herstellen einer Grabenstrukturhalbleitereinrichtung
US20100117142A1 (en) * 2008-11-10 2010-05-13 Wei-Chieh Lin Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter
EP2276066A1 (fr) * 2008-03-26 2011-01-19 Rohm Co., Ltd. Dispositif a semi-conducteur et son procede de fabrication
US20130181229A1 (en) * 2012-01-13 2013-07-18 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5463725B2 (ja) 2009-04-28 2014-04-09 富士電機株式会社 炭化珪素半導体装置およびその製造方法
DE102013209256A1 (de) 2013-05-17 2014-11-20 Robert Bosch Gmbh Metall-Oxid-Halbleiter-Feldeffekttransistor und Verfahren zur Herstellung eines Metall-Oxid-Halbleiter-Feldeffekttransistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047045A1 (fr) * 1996-06-06 1997-12-11 Cree Research, Inc. Transistor a effet de champ metal-isolant semi-conducteur en carbure de silicium
DE102005020075A1 (de) * 2005-04-29 2006-11-09 Infineon Technologies Ag Verfahren zum Herstellen einer Grabenstrukturhalbleitereinrichtung
EP2276066A1 (fr) * 2008-03-26 2011-01-19 Rohm Co., Ltd. Dispositif a semi-conducteur et son procede de fabrication
US20100117142A1 (en) * 2008-11-10 2010-05-13 Wei-Chieh Lin Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter
US20130181229A1 (en) * 2012-01-13 2013-07-18 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing same

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3264470A1 (fr) 2016-06-29 2018-01-03 ABB Schweiz AG Mosfet de puissance à tranchée à canal court
WO2018002048A1 (fr) 2016-06-29 2018-01-04 Abb Schweiz Ag Transistor mosfet de puissance à tranchée à canal court
US11581431B2 (en) 2017-09-15 2023-02-14 Ii-Vi Delaware, Inc. Integration of a Schottky diode with a MOSFET
US11652099B2 (en) 2017-09-15 2023-05-16 Ii-Vi Delaware, Inc. Concept for silicon for carbide power devices
US11158706B2 (en) 2017-09-15 2021-10-26 II-VI Delaware, Inc Feeder design with high current capability
US11276681B2 (en) 2017-09-15 2022-03-15 Ii-Vi Delaware, Inc. Concept for silicon carbide power devices
US11342423B2 (en) 2017-09-15 2022-05-24 Ii-Vi Delaware, Inc. Method for manufacturing a grid
US11575007B2 (en) 2017-09-15 2023-02-07 Ii-Vi Delaware, Inc. Feeder design with high current capability
WO2019053199A1 (fr) 2017-09-15 2019-03-21 Ascatron Ab Concept pour dispositifs de puissance au carbure de silicium
US11114557B2 (en) 2017-09-15 2021-09-07 Ii-Vi Delaware, Inc. Integration of a Schottky diode with a MOSFET
US12249630B2 (en) 2017-09-15 2025-03-11 Ii-Vi Delaware, Inc. Method for manufacturing a grid
US11869940B2 (en) 2017-09-15 2024-01-09 Ii-Vi Delaware, Inc. Feeder design with high current capability
US11876116B2 (en) 2017-09-15 2024-01-16 Ii-Vi Delaware, Inc. Method for manufacturing a grid
US11984497B2 (en) 2017-09-15 2024-05-14 Ii-Vi Advanced Materials, Llc Integration of a Schottky diode with a MOSFET
US12034001B2 (en) 2017-09-15 2024-07-09 Ii-Vi Advanced Materials, Llc Concept for silicon carbide power devices
WO2023231502A1 (fr) * 2022-06-02 2023-12-07 中芯越州集成电路制造(绍兴)有限公司 Dispositif dmos à tranchée et son procédé de fabrication

Also Published As

Publication number Publication date
DE102014200429A1 (de) 2015-07-16

Similar Documents

Publication Publication Date Title
DE102013007685B4 (de) Siliziumkarbid-halbleiterbauelement und verfahren zu dessen herstellung
WO2015104084A1 (fr) Dispositif à transistor à effet de champ à semi-conducteur à oxyde métallique et à tranchées et procédé de fabrication correspondant
DE102010042971B4 (de) Transistorbauelement mit einer Feldelektrode
DE102012217073B4 (de) Vertikales mikroelektronisches Bauelement
DE102009028485B4 (de) Verfahren zur Herstellung einer Halbleiterstruktur mit vertikalen Dielektrikumsschichten und Halbleiterbauelement
DE4212829A1 (de) Verfahren zur herstellung von metall-oxid-halbleiter-feldeffekttransistoren
DE102008023474A1 (de) Halbleitervorrichtung mit Super-Junction-Struktur und Verfahren zu deren Fertigung
DE102015109538B3 (de) Transistor mit verbessertem Lawinendurchbruchsverhalten und Verfahren zur Herstellung
DE102009002813B4 (de) Verfahren zur Herstellung eines Transistorbauelements mit einer Feldplatte
DE112007002739B4 (de) Verfahren zur Herstellung eines Halbleiterbauelements mit Isolationsgraben und Kontaktgraben
DE102004024885A1 (de) Halbleiterbauelement und Verfahren zu dessen Herstellung
DE112015003603T5 (de) Split-Gate-Halbleitervorrichtung mit L-förmigem Gate
DE102010046213B3 (de) Verfahren zur Herstellung eines Strukturelements und Halbleiterbauelement mit einem Strukturelement
DE112013005837T5 (de) Halbleitervorrichtung mit einem vertikalen Mosfet mit Super-Junction-Struktur und Verfahren zur Herstellung davon
EP3042391A1 (fr) Procédé permettant de produire un substrat, substrat, transistor à effet de champ métal-oxyde-semi-conducteur pourvu d'un substrat, système microélectromécanique pourvu d'un substrat, et véhicule automobile
WO2015150268A1 (fr) Procédé de fabrication d'un substrat, substrat, transistor à effet de champ à grille métal-oxyde possédant un substrat, et système micro-électromécanique possédant un substrat
DE102011010248B3 (de) Ein Verfahren zum Herstellen eines Halbleiterbausteins
DE102016100128A1 (de) LDMOS-Hochspannungstransistor und Verfahren zu dessen Herstellung
DE102005035153A1 (de) Halbleiterbauelement mit hoher Durchbruchsspannung und niedrigem Durchlasswiderstand
DE102019201453A1 (de) Halbleiter-Bauelement, Leistungsschalter, Steuergerät sowie Verfahren zur Herstellung eines Halbleiter-Bauelements
EP1670052B1 (fr) Méthode de fabrication d'un dispositif semi-conducteur comportant une structure semi-conductrice à PMOSFET à tenue en tension et une structure semi-conductrice à NMOSFET
DE102004014928A1 (de) Hochvolttransistor und Verfahren zu seiner Herstellung
DE102013213007B4 (de) Halbleiterbauelement, Trench-Feldeffekttransistor, Verfahren zur Herstellung eines Trench-Feldeffekttransistors und Verfahren zur Herstellung eines Halbleiterbauelements
DE102009023420B3 (de) Verfahren zur Herstellung einer Halbleitervorrichtung und Halbleitervorrichtung (z.B. Doppelgate-Transistor)
EP1734582B1 (fr) Circuit intégré et méthode pour fabriquer un circuit intégré

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14802018

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14802018

Country of ref document: EP

Kind code of ref document: A1