[go: up one dir, main page]

WO2015102253A1 - Appareil et procédé pour traiter une valeur numérique - Google Patents

Appareil et procédé pour traiter une valeur numérique Download PDF

Info

Publication number
WO2015102253A1
WO2015102253A1 PCT/KR2014/012102 KR2014012102W WO2015102253A1 WO 2015102253 A1 WO2015102253 A1 WO 2015102253A1 KR 2014012102 W KR2014012102 W KR 2014012102W WO 2015102253 A1 WO2015102253 A1 WO 2015102253A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital value
bit sequence
grouping
groups
puf
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2014/012102
Other languages
English (en)
Korean (ko)
Inventor
김동규
최병덕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ICTK Co Ltd
Original Assignee
ICTK Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ICTK Co Ltd filed Critical ICTK Co Ltd
Priority to EP14876633.0A priority Critical patent/EP3091470B1/fr
Priority to JP2016544534A priority patent/JP2017508173A/ja
Priority to US15/109,317 priority patent/US10872172B2/en
Priority to EP19155303.1A priority patent/EP3503079A1/fr
Priority to CN201480076501.6A priority patent/CN106030605B/zh
Publication of WO2015102253A1 publication Critical patent/WO2015102253A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]

Definitions

  • It relates to the security field, and more particularly, to a device and a method for determining the randomness of a digital value generated by a physically unclonable function (PUF) and processing the digital value to improve the randomness as needed.
  • PAF physically unclonable function
  • PUFs Physically Unclonable Functions
  • PUF may be referred to as Physical One-Way Function practically impossible to be duplicated (POWF) or Physical Random Function (PRF).
  • PWF Physical One-Way Function practically impossible to be duplicated
  • PRF Physical Random Function
  • PUF Physical Uplink Detection Function
  • PUF may be used to provide a unique key to distinguish devices from one another.
  • Korean Patent Registration No. 10-1139630 (hereinafter '630 patent) has been presented a method for implementing the PUF.
  • a process variation of a semiconductor is used to probabilistically determine whether an inter-layer contact or via is generated between conductive layers or conductive nodes of the semiconductor.
  • a method for generating a PUF has been presented.
  • One of the embodiments presented in the '630 patent is to design a small size of the via to be formed between the conductive layers so that the vias are formed randomly and when they are not. Thus, random digital values were generated that were not possible to artificially guess.
  • the individual bit values included in the digital value are not biased to '0' or '1' so that they are true random numbers. It is preferable.
  • a digital value processing device for processing a first digital value generated by a physically unclonable function (PUF) to generate a second digital value with greatly improved entropy.
  • PAF physically unclonable function
  • the apparatus may include: a grouping unit generating a plurality of groups by grouping a first bit sequence included in the first digital value; And a processor configured to calculate a second bit sequence from the plurality of groups by performing a logical operation to generate a second digital value including the second bit sequence.
  • the logical operation may be an Exclusive Or (XOR) logical operation.
  • the apparatus may further include a determining unit configured to read the first bit sequence and determine whether the first digital value has a predetermined level of randomness.
  • the randomness of the predetermined level may satisfy a condition that the P-value calculated for the first bit sequence exceeds a predetermined threshold.
  • the determiner may read the first bit sequence to determine a parameter associated with the grouping.
  • the parameter may be the number of generated groups.
  • the determination unit may include: a reading unit that reads the first bit sequence and calculates a ratio of '1' and '0' included in the first bit sequence; And a calculator configured to calculate the parameter such that the P-value of the second bit sequence calculated using the ratio satisfies a condition exceeding a predetermined threshold.
  • a digital value processing method in which a digital value processing device generates a second digital value with greatly improved entropy by processing a first digital value generated by a PUF.
  • the method may further include: a grouping unit of generating a plurality of groups by grouping a first bit sequence included in a first digital value generated by a physically unclonable function (PUF) by a grouping unit of the device; And a processing unit of performing a logical operation to calculate a second bit sequence from the plurality of groups to generate a second digital value including the second bit sequence.
  • PAF physically unclonable function
  • the logical operation may be an Exclusive Or (XOR) logical operation.
  • the method may further include a determining step of determining, by the determination unit of the device, whether the first digital value has a predetermined level of randomness by reading the first bit sequence. have.
  • the randomness of the predetermined level may satisfy a condition that the P-value calculated for the first bit sequence exceeds a predetermined threshold.
  • the method may further include a determining step of determining, by the determining unit of the device, the parameter related to the grouping by reading the first bit sequence.
  • the parameter may be the number of generated groups.
  • the determining step may include: calculating a ratio of '1' and '0' included in the first bit sequence by reading the first bit sequence; And calculating the parameter such that a P-value of the second bit sequence calculated using the ratio satisfies a condition exceeding a predetermined threshold.
  • FIG. 1 is a block diagram of a digital value processing apparatus according to an embodiment.
  • FIG. 2 is a conceptual diagram illustrating a detailed configuration and operation of a determination unit according to an embodiment.
  • FIG. 3 is a conceptual diagram illustrating a detailed configuration and operation of a determination unit according to an embodiment.
  • FIG. 4 is a conceptual diagram illustrating an operation of a grouping unit and a processing unit, according to an exemplary embodiment.
  • FIG. 5 is a flowchart illustrating a digital value processing method according to an embodiment.
  • FIG. 6 is a flowchart illustrating a digital value processing method according to an embodiment.
  • FIG. 1 is a block diagram of a digital value processing apparatus 100 according to an embodiment.
  • the digital value processing apparatus 100 processes the first digital value A generated by the PUF to generate a second digital value B with greatly improved entropy and / or randomness.
  • the first digital value A generated by the PUF is received.
  • the digital value A may include m bit sequences a 1 to a m .
  • m is a natural number.
  • the determination unit 110 determines a parameter to process the m bit sequence to ensure the randomness.
  • the processing may be performed by grouping m bit sequences into n, and calculating n bit sequences by performing a logical operation on the bit sequences included in each group.
  • n is a natural number.
  • the calculated n bit sequences may be referred to as a second digital value B.
  • the parameter determined by the determination unit 110 may be the number i of the bit sequences included in one group when the grouping is performed. i is a natural number.
  • the digital value B can be a value which is greatly improved in randomness or entropy.
  • each of the m bit sequences a 1 to a m included in the first digital value A provided by the PUF is '1' is p, and the probability that it is '0' is q. Then, the sum of p and q is 1, and each of p and q is a real number of 0 or more and 1 or less.
  • the grouping unit 120 groups m bit sequences by i to generate n or more groups. If the digital value B including the random sequence to be generated is n bits, i may be a natural number selected by the determiner 110 among values of (m / n) or less.
  • the processor 130 generates a digital value of 1 bit by performing a logical operation on the i bit sequence included in one group.
  • One bit from each of the n groups may be generated to generate n bits of digital values.
  • the logical operation may be an eXclusive OR (XOR) operation calculated by inputting the i bit sequences.
  • XOR eXclusive OR
  • Equation 1 As the value of i increases, the probability that the bit value determined as the output of the XOR operation is '1' converges to 50%. Therefore, even if the probability that each of the i input bit values included in one group is '1' is not 50%, as the value of i is increased, the output of the XOR operation rapidly approaches 50%, so that entropy is greatly increased.
  • FIG. 2 is a conceptual diagram illustrating a detailed configuration and operation of the determination unit 110 according to an embodiment.
  • the determiner 110 receives the first digital value A from the PUF 201.
  • the digital value A generated by the PUF 201 may include m bit sequences a 1 to a m . Where m is a natural number.
  • the PUF 201 may include m vias formed between conductive layers of the semiconductor.
  • the bit sequences a 1 to a m may be determined as digital values '1' or '0' depending on whether each of the m vias shorts or fails between the conductive layers of the semiconductor.
  • the probability that each of the bit sequences a 1 to a m becomes '1' is p, and the probability that it becomes '0' is q.
  • the reading unit 210 reads the bit sequences a 1 to a m included in the digital value A generated by the PUF 201. Through this reading process, the number of '1' and the number of '0' included in the bit sequences a 1 to a m may be counted. When a count is made, p may be a ratio of the number of sequences having a value of '1' among m bit sequences.
  • the calculation unit 220 determines whether the bit sequences a 1 to a m pass a predetermined randomness test by using the count of '1' and the number of '0'.
  • the calculator 220 calculates and / or predicts a P-Value according to NIST 800-22 in advance with respect to the digital value A generated by the PUF 201 so that the digital value A passes the frequency test. You can determine if you can.
  • the failure rate can be predicted in advance, and the grouping to be used by the grouping unit 120 and the processing unit 130 of FIG. 1 to pass the test. You can also determine the size.
  • the P-Value according to NIST 800-22 is calculated as follows.
  • the calculation unit 220 is applied to the bit sequence a k in accordance with Equation 2 For obtaining the X k, it calculates a value by adding the S m X k.
  • the process is a sequence of bits k is the case of "1" in case the X value k to "1", and a bit sequence k '0' by converting the X k value to '1', and then, a bit sequence of m It is the process of calculating the S m value which adds all the calculated X k values for these fields.
  • the S m value is positive; conversely, if the bit sequence contains more '0' than '1', the S m value is negative.
  • NIST 800-22 proposes a decision rule that determines that digital value A is a random sequence when the calculated P-value is larger than a certain threshold.
  • the threshold may be, for example, 0.1 or 0.01, and may be set differently according to the level of randomness required.
  • the calculation unit 220 may check the randomness of the digital value A provided by the PUF 201 through this calculation.
  • a bit sequence having a probability of '1' p may be grouped by i, and the bit sequence of 1 bit may be calculated for each group by performing an XOR operation on the i bit sequences of each group. Then, n bits of the second digital value B are generated by the n groups.
  • Equation 1 the probability that each of the n bit sequences included in the second digital value B is '1' to be.
  • the P-value when generating the second bit sequence B of n bits can be calculated in advance by grouping the given first bit sequences by i and performing XOR operation on each group.
  • the calculation unit 220 calculates a grouping size i necessary to pass a randomness test, for example, the NIST 800-22. You can also pay. This process will be described in more detail with reference to FIG. 3.
  • 3 is a conceptual diagram illustrating a detailed configuration and operation of the determination unit 110 according to an embodiment.
  • the reading unit 210 counts '1' of the bit sequences a 1 to a m . p can be calculated.
  • the P-value may be calculated by substituting n and the calculated p into Equation 5. Then, the group size i for passing the random test according to the given decision rule can be calculated.
  • the group size i is calculated. As such, it may be determined that at least n * i via holes should be formed in one PUF.
  • FIG. 4 is a conceptual diagram illustrating an operation of the grouping unit 120 and the processing unit 130 according to an embodiment.
  • the grouping unit 120 groups the bit sequences included in the first digital value A into n to generate groups A 1 to A n .
  • Each group contains i bit sequences.
  • the processor 130 calculates one digital bit b k by performing an XOR operation on i bit sequences included in each group. For example, b 1 is calculated using the i bit sequence included in the group A 1 as an input of an XOR operation.
  • n bits of the second digital value B are generated through the n groups.
  • the second digital value B has a very high entropy. Therefore, it is suitable for use in the field of security.
  • FIG. 5 is a flowchart illustrating a digital value processing method according to an embodiment.
  • the reading unit 210 of FIG. 1 reads the first digital value A provided by the PUF 201.
  • the first digital value A may include m bit sequences.
  • the calculator 220 may calculate a P-value of the first digital value A using Equations 2 to 4 below.
  • the calculator 220 compares the calculated P-value with a threshold value according to a predetermined decision rule, for example, 0.1 or 0.01, to determine whether the first digital value A can pass the random test.
  • a predetermined decision rule for example, 0.1 or 0.01
  • the failure rate can be predicted in advance, and the grouping to be used by the grouping unit 120 and the processing unit 130 of FIG. 1 to pass the test. You can also determine the size.
  • FIG. 6 is a flowchart illustrating a digital value processing method according to an embodiment.
  • step 610 it is determined whether the first digital value A passes the given random test. If the random test passes when only the n-bit sequence included in the digital value A itself is selected, the second digital value B may be determined as the predetermined and / or randomly selected n bits.
  • step 610 if it is determined in step 610 that the random test does not pass, then in step 620 a grouping size i for generating a random sequence of n bits may be determined.
  • the grouping size i may be determined as a minimum natural number at which the P-value calculated according to Equation 5 becomes larger than the threshold.
  • the grouping unit 120 groups the bit sequences included in the first digital value A by i to generate n groups. Examples of grouped results are as A 1 to A n described with reference to FIG. 4.
  • the processor 130 performs an XOR operation on the i bit sequences of each group to calculate a bit sequence of 1 bit for each group. Then, n bits of the second digital value B are generated by the n groups.
  • the second digital generated by the digital value processing apparatus 100 does not have a 50% probability that the individual bit sequence of the first first digital value A generated by the PUF is '1'.
  • the value B can be randomized by greatly improving entropy.
  • the apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components.
  • the devices and components described in the embodiments may be, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable arrays (FPAs), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions.
  • the processing device may execute an operating system (OS) and one or more software applications running on the operating system.
  • the processing device may also access, store, manipulate, process, and generate data in response to the execution of the software.
  • OS operating system
  • the processing device may also access, store, manipulate, process, and generate data in response to the execution of the software.
  • processing device includes a plurality of processing elements and / or a plurality of types of processing elements. It can be seen that it may include.
  • the processing device may include a plurality of processors or one processor and one controller.
  • other processing configurations are possible, such as parallel processors.
  • the software may include a computer program, code, instructions, or a combination of one or more of the above, and configure the processing device to operate as desired, or process it independently or collectively. You can command the device.
  • Software and / or data may be any type of machine, component, physical device, virtual equipment, computer storage medium or device in order to be interpreted by or to provide instructions or data to the processing device. Or may be permanently or temporarily embodied in a signal wave to be transmitted.
  • the software may be distributed over networked computer systems so that they may be stored or executed in a distributed manner.
  • Software and data may be stored on one or more computer readable recording media.
  • the method according to the embodiment may be embodied in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium.
  • the computer readable medium may include program instructions, data files, data structures, etc. alone or in combination.
  • the program instructions recorded on the media may be those specially designed and constructed for the purposes of the embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts.
  • Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks.
  • Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like.
  • the hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Complex Calculations (AREA)

Abstract

L'invention concerne un appareil pour tester le caractère aléatoire d'une valeur numérique et traiter celle-ci. La valeur numérique peut comprendre des premières séquences de bits générées par une fonction ne pouvant pas être clonée physiquement (PUF). Une unité de groupement groupe les premières séquences de bits pour générer une pluralité de groupes, et une unité de traitement peut calculer une seconde séquence de bits provenant de la pluralité de groupes au moyen d'opérations logiques.
PCT/KR2014/012102 2013-12-31 2014-12-10 Appareil et procédé pour traiter une valeur numérique Ceased WO2015102253A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP14876633.0A EP3091470B1 (fr) 2013-12-31 2014-12-10 Appareil et procédé pour traiter une valeur numérique
JP2016544534A JP2017508173A (ja) 2013-12-31 2014-12-10 デジタル値処理装置及び方法
US15/109,317 US10872172B2 (en) 2013-12-31 2014-12-10 Apparatus and method for processing digital value
EP19155303.1A EP3503079A1 (fr) 2013-12-31 2014-12-10 Appareil et procédé pour traiter un nombre aléatoire utilisant des pufs
CN201480076501.6A CN106030605B (zh) 2013-12-31 2014-12-10 数字值处理装置及方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020130168558A KR102198499B1 (ko) 2013-12-31 2013-12-31 디지털 값 처리 장치 및 방법
KR10-2013-0168558 2013-12-31

Publications (1)

Publication Number Publication Date
WO2015102253A1 true WO2015102253A1 (fr) 2015-07-09

Family

ID=53493560

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2014/012102 Ceased WO2015102253A1 (fr) 2013-12-31 2014-12-10 Appareil et procédé pour traiter une valeur numérique

Country Status (7)

Country Link
US (1) US10872172B2 (fr)
EP (2) EP3091470B1 (fr)
JP (1) JP2017508173A (fr)
KR (1) KR102198499B1 (fr)
CN (1) CN106030605B (fr)
TW (1) TWI640896B (fr)
WO (1) WO2015102253A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110569676A (zh) * 2018-06-05 2019-12-13 英飞凌科技股份有限公司 用于转换输入比特序列的加密设备和方法
US11283632B2 (en) 2017-12-28 2022-03-22 Mitsubishi Heavy Industries, Ltd. Integrated circuit, control device, information distribution method, and information distribution system

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3032421A4 (fr) 2013-07-26 2017-04-19 ICTK Co. Ltd. Dispositif et procédé de test du caractère aléatoire
KR102836787B1 (ko) * 2016-11-16 2025-07-18 삼성전자주식회사 난수 생성기의 랜덤성 시험 장치 및 방법
WO2019011607A1 (fr) * 2017-07-10 2019-01-17 Intrinsic Id B.V. Génération d'une clé sécurisée à partir d'une fonction physique non clonable sollicitée
FR3069677A1 (fr) * 2017-07-27 2019-02-01 Stmicroelectronics (Crolles 2) Sas Dispositif de generation d'un nombre aleatoire
CN107943450A (zh) * 2017-11-17 2018-04-20 上海众人网络安全技术有限公司 随机数生成方法、装置、计算机设备及计算机可读介质
CN110018810B (zh) * 2018-01-10 2021-05-18 力旺电子股份有限公司 随机码产生器
US20210026602A1 (en) * 2019-07-25 2021-01-28 PUFsecurity Corporation Entropy Generator and Method of Generating Enhanced Entropy Using Truly Random Static Entropy
CN112764977B (zh) * 2019-11-05 2024-08-27 深圳宏芯宇电子股份有限公司 存储控制器以及测试数据产生方法
WO2022212375A1 (fr) * 2021-03-31 2022-10-06 Tokyo Electron Limited Procédé de conception de cellule standard automatisée

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110055649A1 (en) * 2009-08-25 2011-03-03 Farinaz Koushanfar Testing security of mapping functions
KR101139630B1 (ko) 2010-12-09 2012-05-30 한양대학교 산학협력단 식별키 생성 장치 및 방법
JP2012105056A (ja) * 2010-11-10 2012-05-31 Nec Corp デバイス固有情報生成装置、デバイス固有情報生成方法および認証装置
US20130147511A1 (en) * 2011-12-07 2013-06-13 Patrick Koeberl Offline Device Authentication and Anti-Counterfeiting Using Physically Unclonable Functions
EP2615571A1 (fr) * 2012-01-16 2013-07-17 Gemalto SA Procédé de génération d'un identifiant pour un appareil électronique

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003131867A (ja) * 2001-08-15 2003-05-09 Syst Kogaku Kk 乱数生成装置
JP3604674B2 (ja) * 2001-09-26 2004-12-22 株式会社東芝 乱数生成回路
TWI258698B (en) * 2004-04-06 2006-07-21 Ind Tech Res Inst Static floating-point processor suitable for embedded digital signal processing and shift control method thereof
WO2005124537A1 (fr) * 2004-06-18 2005-12-29 Fujitsu Limited Dispositif de génération de nombre aléatoire, méthode de génération, méthode d’évaluation de générateur et méthode d’utilisation de nombre aléatoire
JP2009519537A (ja) * 2005-12-14 2009-05-14 エヌエックスピー ビー ヴィ 物理的トークンに対するキー抽出パラメータのチップ上評価
GB2448245B (en) * 2005-12-23 2009-11-04 Ingenia Holdings Optical authentication
TW200807425A (en) * 2006-06-05 2008-02-01 Renesas Tech Corp Semiconductor device, unique ID of semiconductor device and method for verifying unique ID
JP4950924B2 (ja) * 2008-03-19 2012-06-13 日本電信電話株式会社 カオスレーザ発振器と、それを用いた超高速物理乱数生成装置とその方法と、そのプログラムと記録媒体
US8121825B2 (en) * 2008-04-30 2012-02-21 Synopsys, Inc. Method and apparatus for executing a hardware simulation and verification solution
CN102783028B (zh) * 2010-01-15 2016-02-03 三菱电机株式会社 比特列生成装置以及比特列生成方法
US20120183135A1 (en) * 2011-01-19 2012-07-19 Verayo, Inc. Reliable puf value generation by pattern matching
EP3206330B1 (fr) * 2011-08-16 2018-12-26 ICTK Holdings Co., Ltd. Appareil et procédé d'authentification entre dispositifs sur la base de puf sur communications machine-machine
US8525169B1 (en) * 2012-08-10 2013-09-03 International Business Machines Corporation Reliable physical unclonable function for device authentication
CN103188075B (zh) * 2013-02-01 2016-01-06 广州大学 一种密钥和真随机数发生器及生成密钥和真随机数的方法
US10333708B1 (en) * 2017-02-03 2019-06-25 Amazon Technologies, Inc. Hybrid random-number generator
US10581841B2 (en) * 2017-02-13 2020-03-03 Zentel Japan Corporation Authenticated network

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110055649A1 (en) * 2009-08-25 2011-03-03 Farinaz Koushanfar Testing security of mapping functions
JP2012105056A (ja) * 2010-11-10 2012-05-31 Nec Corp デバイス固有情報生成装置、デバイス固有情報生成方法および認証装置
KR101139630B1 (ko) 2010-12-09 2012-05-30 한양대학교 산학협력단 식별키 생성 장치 및 방법
US20130147511A1 (en) * 2011-12-07 2013-06-13 Patrick Koeberl Offline Device Authentication and Anti-Counterfeiting Using Physically Unclonable Functions
EP2615571A1 (fr) * 2012-01-16 2013-07-17 Gemalto SA Procédé de génération d'un identifiant pour un appareil électronique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications", NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY (NIST
See also references of EP3091470A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11283632B2 (en) 2017-12-28 2022-03-22 Mitsubishi Heavy Industries, Ltd. Integrated circuit, control device, information distribution method, and information distribution system
CN110569676A (zh) * 2018-06-05 2019-12-13 英飞凌科技股份有限公司 用于转换输入比特序列的加密设备和方法
CN110569676B (zh) * 2018-06-05 2023-12-05 英飞凌科技股份有限公司 用于转换输入比特序列的加密设备和方法

Also Published As

Publication number Publication date
EP3091470A1 (fr) 2016-11-09
TW201539243A (zh) 2015-10-16
EP3091470A4 (fr) 2017-01-11
EP3503079A1 (fr) 2019-06-26
US20160335458A1 (en) 2016-11-17
EP3091470B1 (fr) 2019-02-06
US10872172B2 (en) 2020-12-22
JP2017508173A (ja) 2017-03-23
TWI640896B (zh) 2018-11-11
CN106030605A (zh) 2016-10-12
KR102198499B1 (ko) 2021-01-05
KR20150078817A (ko) 2015-07-08
CN106030605B (zh) 2020-07-07

Similar Documents

Publication Publication Date Title
WO2015102253A1 (fr) Appareil et procédé pour traiter une valeur numérique
WO2015102359A1 (fr) Appareil et procédé pour générer une valeur numérique aléatoire
Dofe et al. Hardware security assurance in emerging IoT applications
US10121011B2 (en) Apparatus, method and article of manufacture for partially resisting hardware trojan induced data leakage in sequential logics
Koteshwara et al. Key-based dynamic functional obfuscation of integrated circuits using sequentially triggered mode-based design
Kodýtek et al. Improved ring oscillator PUF on FPGA and its properties
WO2015012667A1 (fr) Dispositif et procédé de test du caractère aléatoire
WO2012077856A1 (fr) Dispositif et procédé de génération d'une clé d'identification
CN103650407A (zh) 用于检查n中取m码的方法
WO2016204863A1 (fr) Renforcement de la sécurité des communications de gestion d'énergie et protection contre les attaques par voie auxiliaire
US11968306B2 (en) PUF key transfer
US8955160B2 (en) Method for detecting abnormalities in a cryptographic circuit protected by differential logic, and circuit for implementing said method
WO2017126900A1 (fr) Appareil de génération de clé d'identification et son procédé de gestion
WO2017165296A1 (fr) Système, procédé et support accessible par ordinateur pour verrouillage logique résistant aux attaques de satisfaisabilité
CN105678083A (zh) 一种具有单比特频数检测和块内频数检测的快速检测方法
CN114706556A (zh) 多熵源真随机数生成器、控制方法、介质、设备及终端
KR20140037153A (ko) 랜덤 출력 비트 시퀀스의 생성 방법
WO2015053441A1 (fr) Appareil et procédé de génération de clé d'identification
CN116318629A (zh) 一种数据加密装置
CN107220545A (zh) 一种硬件加密系统、方法及服务器
CN113268745B (zh) 基于Camellia加密算法的软PUF
US20140223568A1 (en) Method for securely checking a code
Zhang et al. Invariance checking based Trojan detection method for three-dimensional integrated circuits
Jagadeesh et al. Lightweight signature scheme to protect intellectual properties of Internet of things applications in system on chip field-programmable gate arrays
US12395361B2 (en) Device encrypted authentication method based on strong physical unclonable function and device encrypted authentication system using the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14876633

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2016544534

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 15109317

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2014876633

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014876633

Country of ref document: EP