WO2015198367A1 - Test circuit for integrated circuit, information processing device, and test method for integrated circuit - Google Patents

Abstract

This test circuit for an integrated circuit comprises a test control unit which supplies scan-in data to an integrated circuit via a first signal line and receives scan-out data from the integrated circuit via a second signal line, said test control unit comprising: a signal control unit which controls the integrated circuit so that the scan-in data is returned through the integrated circuit, and which supplies the original scan-in data to the integrated circuit via the first signal line; and a determination unit which receives, from the signal control unit, the original scan-in data to be supplied to the integrated circuit, receives the returned version of the scan-in data from the integrated circuit via the second signal line, and compares the original scan-in data with the returned version to determine whether the returned version is valid.

Description

Integrated circuit test circuit, information processing apparatus, and integrated circuit test method

The present invention relates to an integrated circuit test circuit, an information processing apparatus, and an integrated circuit test method.

With high integration of LSI (Large Scale Integration) and high density of printed circuit boards, testing of LSIs and printed circuit boards has become difficult. For this reason, for example, an integrated circuit corresponding to a test method standardized by JTAG (Joint Test Action Group) as IEEE 1149.1 has become widespread. Hereinafter, IEEE1149.1 is also referred to as JTAG. An integrated circuit corresponding to JTAG has an interface signal terminal called TAP (Test Access Port), a TAP controller, a scan instruction register, a plurality of scan data registers, and the like.

The TAP controller receives, for example, an interface signal TMS (Test Mode Select) for selecting a test mode and outputs a control signal for controlling an instruction register and a data register. The instruction register is used, for example, to select a data register to be scanned. The data register executes a scan operation based on, for example, control signals from the TAP controller and the instruction register.

This will test the integrated circuit. For example, in the scan operation, the value (logical value) of the interface signal TDI (Test Data In) is sequentially written into the data register (scan-in). The values written in the data register by the scan-in are sequentially read out from the data register as the interface signal TDO (Test （Data Out) (scan-out). For example, the integrated circuit test apparatus compares the value written in the data register by scan-in with the value read from the data register by scan-out to determine the presence or absence of an error.

In this type of test, it is difficult to determine whether the circuit that realizes the original function of the integrated circuit is abnormal or the test circuit is abnormal. For this reason, a boundary scan test circuit has been proposed in which an additional circuit having a control output pin for confirming a control signal output from the TAP controller from the outside is added (for example, see Patent Document 1). For example, the user confirms whether the state transition of the TAP controller is normal by observing the control output pin of the additional circuit with a tester or the like.

Japanese Patent Laid-Open No. 7-72203

If the error check function for the signal line for the interface signal between the integrated circuit test apparatus and the integrated circuit is not provided, it may take a long time to detect the error of the test interface (for example, the signal line for the interface signal). There is. For example, an integrated circuit test apparatus detects an error by executing scan-out after executing scan-in. In this case, since two steps of scan-in and scan-out are executed, it takes time until an error in the test interface is found. In the method of observing the control output pin of the additional circuit, the number of terminals of the integrated circuit or the like increases.

In one aspect, the integrated circuit test circuit, the information processing apparatus, and the integrated circuit test method disclosed herein are intended to reduce the time of error detection of the test interface.

According to one aspect, the test circuit of the integrated circuit has a test control unit that supplies scan-in data to the integrated circuit via the first signal line and receives scan-out data from the integrated circuit via the second signal line. The test control unit controls the integrated circuit so that the scan-in data is folded back by the integrated circuit, and supplies the scan-in data to the integrated circuit via the first signal line and the integrated circuit. The scan-in data is received from the signal control unit, the return data of the scan-in data is received from the integrated circuit via the second signal line, and the scan-in data and the return data are compared to determine whether the return data is correct. And a determination unit.

According to another aspect, the information processing apparatus includes an integrated circuit and a test circuit that tests the integrated circuit. The test circuit supplies scan-in data to the integrated circuit via the first signal line, and scans the integrated circuit. A test control unit configured to receive out-data from the integrated circuit via the second signal line; the test control unit controls the integrated circuit so that the scan-in data is folded back by the integrated circuit; A signal control unit supplied to the integrated circuit via the line, scan-in data supplied to the integrated circuit is received from the signal control unit, and return data of the scan-in data is received from the integrated circuit via the second signal line. A determination unit that compares the data and the return data to determine whether the return data is correct;

According to another aspect, in the integrated circuit test method, the integrated circuit is controlled so that the scan-in data is folded back by the integrated circuit, and the scan-in data is transferred from the test control unit to the integrated circuit via the first signal line. Then, the return data of the scan-in data is transferred from the integrated circuit to the test control unit via the second signal line, and the scan-in data held in the test control unit is compared with the return data transferred to the test control unit. Then, it is determined whether the return data is correct.

The integrated circuit test circuit, the information processing apparatus, and the integrated circuit test method disclosed in the present disclosure can reduce the error detection time of the test interface.

1 is a diagram illustrating an embodiment of an integrated circuit test circuit, an information processing apparatus, and an integrated circuit test method; FIG. FIG. 2 is a diagram illustrating an example of a determination circuit illustrated in FIG. 1. It is a figure which shows an example of the state transition of the TAP controller shown in FIG. FIG. 2 is a diagram illustrating an example of operation of the test circuit illustrated in FIG. 1. It is a figure which shows an example of the time chart of each signal shown in FIG. It is a figure which shows another example of the time chart of each signal shown in FIG. It is a figure which shows another example of the time chart of each signal shown in FIG.

Hereinafter, embodiments will be described with reference to the drawings. The broken-line arrows in FIGS. 1 and 2 show an example of the flow of data and control signals. Further, the same reference numerals as those attached to the signals transmitted to the signal lines are used for the signal lines connecting the integrated circuit 100 and the test control apparatus 200. Similarly, the same reference numerals as those attached to the signals transmitted to the terminals are used for the terminals (double circles in FIG. 1) of the integrated circuit 100 and the test control apparatus 200. The terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored.

FIG. 1 shows an embodiment of an integrated circuit test circuit, an information processing apparatus, and an integrated circuit test method. The information processing apparatus 10 according to this embodiment includes an integrated circuit 100 such as an LSI (Large Scale Integration) corresponding to a test method standardized by JTAG (Joint Test Action Group) as IEEE1149.1. Hereinafter, IEEE1149.1 is also referred to as JTAG.

For example, the information processing apparatus 10 includes an integrated circuit 100 including a test circuit compatible with JTAG, a test control apparatus 200 that controls a test circuit compatible with JTAG, and a system control apparatus 300 that controls the test control apparatus 200. is doing. Further, the test circuit 20 of the integrated circuit 100 includes, for example, a test control device 200 and a test circuit provided in the integrated circuit 100.

The integrated circuit 100 includes, for example, interface signal terminals TCK (Test ClocK), TMS (Test Mode Reselect), TRST (Test Data Re In), TDI (Test Data In), and TDO (Test Data Out) is provided. For example, the terminals TCK, TMS, TRST, TDI, and TDO of the integrated circuit 100 are connected to the terminals TCK, TMS, TRST, TDI, and TDO of the test control device 20 through the signal lines TCK, TMS, TRST, TDI, and TDO. Yes. In FIG. 1, the description of a circuit that realizes the original function of the integrated circuit 100 is omitted to make the drawing easier to see.

For example, the integrated circuit 100 includes a TAP controller 110, an instruction register 120, a data register 130, a selector 150, a selector control circuit 160, a flip-flop 170, and a loopback control circuit 180 as a part of the test circuit 20. Hereinafter, the instruction register 120 is also referred to as IR (Instruction-Register) 120, and the data register 130 is also referred to as DR (Data-Register) 130.

The test clock TCK, which is one of interface signals, is transmitted to the terminal TCK. The test clock TCK is, for example, a clock signal (test clock) that synchronizes the operation of the state machine in the integrated circuit 100. Hereinafter, the test clock TCK is also referred to as a signal TCK. In FIG. 1, in order to make the drawing easier to see, a part of a signal line to which a clock such as the signal TCK is transmitted is omitted.

The test mode select TMS, which is one of interface signals, is transmitted to the terminal TMS. The test mode select TMS is a signal for controlling the state transition of the TAP controller 110. That is, the test mode select TMS is a signal for selecting a test mode. For example, the test mode select TMS is read at the rising edge of the test clock TCK. Hereinafter, test mode select TMS is also referred to as signal TMS.

A test reset TRST, which is one of interface signals, is transmitted to the terminal TRST. The test reset TRST is a signal for resetting the state machine of the TAP controller 110. Hereinafter, the test reset TRST is also referred to as a signal TRST. In IEEE1149.1, the test reset TRST is an option signal.

The data TDI, which is one of interface signals, is transmitted to the terminal TDI. The data TDI is data scanned into the integrated circuit 100, for example. For example, the data TDI is read at the rising edge of the test clock TCK. Hereinafter, the data TDI is also referred to as scan-in data TDI or signal TDI.

The data TDO which is one of the interface signals is transmitted to the terminal TDO. The data TDO is, for example, scan-out data from the integrated circuit 100. For example, the data TDO is output at the falling edge of the test clock TCK. Hereinafter, the data TDO is also referred to as scan-out data TDO or a signal TDO.

The TAP controller 110 is a synchronous state machine controlled by signals TCK, TMS, and TRST. For example, the TAP controller 110 receives signals TCK, TMS, and TRST from the test control apparatus 200 and outputs control signals for controlling the instruction register 120 and the data register 130. For example, the TAP controller 110 executes a state transition according to the value of the test mode select TMS at the rising edge of the test clock TCK. In accordance with each state, the operation of the JTAG circuit (the test circuit 20 included in the integrated circuit 100) is determined.

The instruction register 120 is used, for example, for selecting a data register 130 (any one of the data registers 134, 136, 138, and 138) to be scanned. For example, the instruction register 120 receives control signals such as signals CAPTUREIR, UPDATATEIR, IRACK, and IRBCK from the TAP controller 110, and receives data TDI indicating an instruction code and the like from the test control device 200. Then, the instruction register 120 outputs a set instruction code, for example. Here, for example, the signals IRACK and IRBCK are scan clocks for executing scan shift. Hereinafter, the signals IRACK and IRBCK are also referred to as scan clocks IRACK and IRBCK.

For example, the instruction register 120 includes a shift register in which scan shift is executed and a flip-flop that holds the value of the shift register. That is, the instruction register 120 is a scannable register. For example, when the state of the TAP controller 110 transitions to the Capture IR state, a user-defined fixed value is set in the shift register.

Also, when the state of the TAP controller 110 transitions to the Shift IR state, the value of the data TDI is sequentially transmitted to the shift register by a shift operation. Thereby, an instruction code or the like is set in the shift register. When the state of the TAP controller 110 transitions to the Update IR state, the value of the shift register is set in the flip-flop, and the value of the flip-flop is transmitted to the integrated circuit 100.

Note that in addition to the essential instructions defined in IEEE1149.1, user-defined instructions can be set in the instruction register 120 of this embodiment. For example, in this embodiment, a UR scan-in instruction (for example, IR = 1100) and a UR scan-in instruction with loopback (for example, IR = 1110) are implemented as user-defined instructions. The UR scan-in instruction with loopback is, for example, an instruction for outputting the return data of the scan-in data TDI to the terminal TDO of the integrated circuit 100 during the period when the scan-in data TDI is written in the data register 138.

The data register 130 performs a scan operation based on control signals from the TAP controller 110 and the instruction register 120, for example. For example, the data register 130 includes a plurality of scanable data registers 132, 134, 136, 138, a data register control circuit 140, and a selector 142.

The data register 132 is a boundary scan register. Hereinafter, the data register 132 is also referred to as a boundary scan register 132 or BS (BoundaryBoundScan register) 132. The BS 132 is a shift register provided at each terminal of the integrated circuit 100, for example. For example, the test control apparatus 200 can perform reading and writing with respect to each terminal of the integrated circuit 100 by causing the BS 132 to perform a scanning operation.

The data register 134 is a register that holds information such as an ID (IDentification) of a device (for example, the integrated circuit 100). Hereinafter, the data register 134 is also referred to as an IDCODE register 134 or IDCODE (ID CODE register) 134.

The data register 136 is a bypass register. Hereinafter, the data register 136 is also referred to as a bypass register 136 or BYPS (BYPaSs register) 136. The BYPS 136 is, for example, a one-stage shift register. For example, the BYPS 136 sequentially receives the data TDI and sequentially outputs the received data TDI as data TDO. For example, when connecting a plurality of devices to the scan chain, the test control apparatus 200 can perform access by the scan operation at high speed by bypassing a device that is not an access target by the BYPS 136.

The data register 138 is a user-defined register. Hereinafter, the data register 138 is also referred to as a user register 138 or a UR (User Register) 136. The UR 136 is used, for example, when accessing the inside of the integrated circuit 100 by a scanning operation.

The data register control circuit 140 receives a control signal such as a signal SHIFTDR from the TAP controller 110 and receives a control signal indicating an instruction code or the like from the instruction register 120, for example. The data register control circuit 140 supplies the scan clock to the data registers 132 to 138 that execute the scan operation and controls the selector 142 based on the control signals received from the TAP controller 110 and the instruction register 120.

For example, when the UR 138 performs a scan operation, the data register control circuit 140 supplies the scan clocks URACK and URBCK (hereinafter also referred to as signals URACK and URBCK) to the UR 138. Further, the data register control circuit 140 controls the selector 142 so that an output signal of the UR 138 (hereinafter also referred to as a scan-out signal) is transmitted to the selector 150.

The selector 142 is controlled by the data register control circuit 140 and selects one of the scan-out signals of the data registers 132-138. For example, when the UR 138 performs a scan operation, the selector 142 selects a scan-out signal of the UR 138 and outputs the selected scan-out signal to the selector 150. As a state of the selector 142, there may be a state where none of the output signals of the data registers 132-138 is selected.

The selector control circuit 160 receives a control signal such as a signal SHIFTDR from the TAP controller 110 and receives a control signal indicating an instruction code or the like from the instruction register 120, for example. The selector control circuit 160 controls the selector 150 based on control signals received from the TAP controller 110 and the instruction register 120.

For example, the selector control circuit 160 selects the output signal LBDO of the flip-flop 170 in a cycle when a predetermined condition is satisfied, in addition to the selection control for realizing the operation specified in IEEE1149.1. 150 is controlled. The predetermined condition is, for example, when the control signal from the IR 120 indicates a UR scan-in instruction with loopback (for example, IR = 1101) and the control signal SHIFTDR from the TAP controller 110 is asserted in the previous cycle. .

The selector 150 is controlled by the selector control circuit 160, for example, and selects any one of the output signals (scanout signals) of the IR 120, the DR 130 (more specifically, the selector 142) and the flip-flop 170 as the data TDO. Then, the selector 150 outputs the data TDO (selected scan-out signal) to the outside of the integrated circuit 100 via the terminal TDO.

For example, the selector 150 selects the output signal of the DR 130 when the control signal from the IR 120 indicates a UR scan-in command (IR = 1100) and the control signal SHIFTDR from the TAP controller 110 is asserted. Further, for example, when the control signal from the IR 120 indicates the UR scan-in instruction with loopback (IR = 1110) and the control signal SHIFTDR from the TAP controller 110 is asserted, the selector 150 performs the signal in the next cycle. Select LBDO. The signal LBDO is an output signal of the flip-flop 170, and is loopback data of the data TDI.

It should be noted that as the state of the selector 150, there may be a state in which none of the output signals of the IR 120, the DR 130, and the flip-flop 170 is selected.

The loopback control circuit 180 receives a control signal such as a signal SHIFTDR from the TAP controller 110 and receives a control signal indicating an instruction code and the like from the instruction register 120, for example. The loopback control circuit 180 controls the scan shift of the flip-flop 170 based on the control signals received from the TAP controller 110 and the instruction register 120.

For example, when the UR scan-in instruction with loopback is set and the control signal SHIFTDR is asserted, the loopback control circuit 180 supplies the scan clock to the flip-flop 170 in the next cycle. Thereby, the scan shift of the flip-flop 170 is controlled.

The flip-flop 170 is an example of a flip-flop that outputs scan-in data as loopback data in synchronization with a test clock. The flip-flop 170 is, for example, a 1-bit long scan shift register. For example, the flip-flop 170 is a D-type flip-flop circuit that operates in synchronization with a scan clock (for example, a clock that is the same as or similar to the signals URACK and URBCK). The flip-flop 170 sequentially receives the data TDI from the test control device 200 via the terminal TDI, and sequentially outputs the received data TDI to the selector 150 as a signal LBDO.

As described above, the flip-flop 170 provided in the integrated circuit 100 outputs the signal LBDO to the test control device 200 via the selector 150, the terminal TDO, and the like as the data TDI folded data (data TDO).

The system control device 300 is connected to the test control device 200 by, for example, a control bus. For example, the system control device 300 executes a read / write request and data transfer to a register (for example, IR 120, DR 130, etc.) in the integrated circuit 100 via the control bus and the test control device 200.

The test control apparatus 200 supplies scan-in data to the integrated circuit 100 via a first signal line (for example, signal line TDI), and scan-out data from the integrated circuit 100 to a second signal line (for example, signal line TDO). It is an example of the test control part received via. For example, the test control device 200 controls the test circuit in the integrated circuit 100 in accordance with a command from the system control device 300. The test control device 200 includes a signal control circuit 210 and a determination circuit 220.

The signal control circuit 210 is an example of a signal control unit that controls the integrated circuit so that the scan-in data is folded back by the integrated circuit, and supplies the scan-in data to the integrated circuit via the first signal line. For example, the signal control circuit 210 controls the integrated circuit 100 using the signals TCK, TMS, TRST, and TDI so that the scan-in data TDI is turned back by the integrated circuit 100.

For example, the signal control circuit 210 outputs signals TCK, TMS, TRST, and TDI to the integrated circuit 100 via the signal lines TCK, TMS, TRST, and TDI in response to a request from the system control device 300. Further, the signal control circuit 210 receives the signal TDO (scan-out data TDO) from the integrated circuit 100 via the signal line TDO.

Furthermore, the signal control circuit 210 outputs the signal TDI (scan-in data TDI) and the delay valid signal DEN to the determination circuit 220 and receives the mismatch signal ESIG from the determination circuit 220. For example, when the UR scan-in instruction with loopback is set in the IR 120, the signal control circuit 210 asserts the delay valid signal DEN while outputting the scan-in data TDI to the UR 138.

The determination circuit 220 is an example of a determination unit that compares the scan-in data with the return data of the scan-in data to determine whether the return data is correct. For example, the determination circuit 220 receives the scan-in data TDI and the delay valid signal DEN from the signal control circuit 210, and receives data TDO from the integrated circuit 100 through the signal line TDO as the return data of the scan-in data TDI. Then, the determination circuit 220 compares the scan-in data TDI and the return data TDO to determine whether the return data TDO is correct.

For example, the determination circuit 220 asserts the mismatch signal ESIG when the scan-in data TDI and the return data TDO do not match in the determination period based on the delay valid signal DEN (when the return data TDO is abnormal). That is, the mismatch signal ESIG is negated when the scan-in data TDI and the return data TDO match (when the return data TDO is correct).

For example, when the scan-in data TDI and the loopback data TDO do not match, the test control device 200 uses a test interface such as terminals TCK, TMS, TRST, TDI, TDO, signal lines TCK, TMS, TRST, TDI, TDO, etc. It is determined that there is an abnormality. Note that the return data TDO of the scan-in data TDI reaches the determination circuit 220 during the period when the scan-in data TDI is written in the UR 138, for example.

That is, the determination circuit 220 receives the return data TDO during a period in which the scan-in data TDI is written to the data register in the integrated circuit 200, and determines whether the return data TDO is correct. Therefore, the determination circuit 220 can determine whether or not the return data TDO of the scan-in data TDI is correct before the value written in the UR 138 (the value of the scan-in data TDI) is read. Therefore, the test control apparatus 200 can shorten the error detection time of the test interface without adding a terminal for error detection of the test interface from the TAP (terminals TCK, TMS, TRST, TDI, TDO).

As described above, the test circuit 20 of the integrated circuit 100 includes the test control device 200, the TAP controller 110, the IR 120, the DR 130, the selector 150, the selector control circuit 160, the flip-flop 170, and the loop back control circuit 180. Note that the test circuit 20 may be defined except for the test circuit in the integrated circuit 100. That is, the test control apparatus 200 is also an aspect of the test circuit 20.

Further, the configurations of the test circuit 20 and the information processing apparatus 10 of the integrated circuit 100 are not limited to this example. For example, the system control device 300 may be provided in the test control device 200. Alternatively, the system control apparatus 300 may be provided outside the information processing apparatus 10.

Also, for example, when the signal transmission time constraint is satisfied, the flip-flop 170 and the loopback control circuit 180 may be omitted. In this case, for example, the selector 150 receives the signal TDI from the terminal TDI instead of the signal LBDO. Alternatively, the selectors 142 and 150 may output the output signal of the BYPS 136 to the test control apparatus 200 as the return data TDO of the scan-in data TDI when the flip-flop 170 or the like is omitted.

Further, for example, the selector control circuit 160 outputs the loopback data TDO (for example, the signal LBDO) of the scan-in data TDI to the terminal TDO based on the value set in a register other than the instruction register 120 in the integrated circuit 100. It may be determined whether or not. Alternatively, the selector control circuit 160 may determine whether to output the loopback data TDO (for example, the signal LBDO) of the scan-in data TDI to the terminal TDO based on the input signal supplied to the integrated circuit 100. .

FIG. 2 shows an example of the determination circuit 220 shown in FIG. The determination circuit 220 includes, for example, a delay circuit 222 and a coincidence determination circuit 224.

The delay circuit 222 is an example of a timing adjustment unit that outputs the scan-in data TDI received from the signal control circuit 210 after being delayed by a predetermined number of cycles in synchronization with the test clock (test clock TCK). For example, the delay circuit 222 receives the test clock TCK, the scan-in data TDI, and the delay valid signal DEN from the signal control circuit 210, and delays the scan-in data TDI and the delay valid signal DEN. Then, the delay circuit 222 outputs the signals DENdd and TDIdd obtained by delaying the signals TDI and DEN to the coincidence determination circuit 224.

The delay amounts of the signals TDI and DEN are, for example, delay amounts corresponding to the time until the scan-in data TDI output from the test control device 200 reaches the test control device 200 via the flip-flop 170, the selector 150, and the like. is there. For example, the delay circuit 222 includes flip-flops DFF1, DFF2, DFF3, and DFF4. The flip-flops DFF1 to DFF4 are, for example, D-type flip-flop circuits that operate in synchronization with the test clock TCK.

The input terminal D of the flip-flop DFF1 receives the delay valid signal DEN, and the output terminal Q of the flip-flop DFF1 is connected to the input terminal D of the flip-flop DFF2. That is, the flip-flop DFF1 outputs the signal DENd obtained by delaying the delay valid signal DEN to the input terminal D of the flip-flop DFF2. The output terminal Q of the flip-flop DFF2 is connected to the input of the AND circuit AND1 of the coincidence determination circuit 224. That is, the flip-flop DFF2 outputs the signal DENdd obtained by delaying the signal DENd to the AND circuit AND1.

The input terminal D of the flip-flop DFF3 receives the scan-in data TDI, and the output terminal Q of the flip-flop DFF3 is connected to the input terminal D of the flip-flop DFF4. That is, the flip-flop DFF3 outputs a signal TDId obtained by delaying the scan-in data TDI to the input terminal D of the flip-flop DFF4. The output terminal Q of the flip-flop DFF4 is connected to the input of the exclusive OR circuit EXOR1 of the coincidence determination circuit 224. That is, the flip-flop DFF4 outputs the signal TDIdd obtained by delaying the signal TDId to the exclusive OR circuit EXOR1.

The coincidence determination circuit 224 is an example of a comparison unit that compares the scan-in data TDI and the return data TDO. For example, the coincidence determination circuit 224 receives the return data TDO of the scan-in data TDI from the integrated circuit 100 via the signal line TDO or the like, and receives the test clock TCK from the signal control circuit 210. Further, the coincidence determination circuit 224 receives from the delay circuit 222 a signal DENdd obtained by delaying the delay effective signal DEN by two stages of flip-flops and a signal TDIdd obtained by delaying the scan-in data TDI by two stages of flip-flops.

Then, the coincidence determination circuit 224 compares the scan-in data TDI after timing adjustment with the return data TDO during the period when the signal DENdd (delay effective signal DEN after timing adjustment) received from the delay circuit 222 is asserted. For example, the coincidence determination circuit 224 asserts the disagreement signal ESIG when the scan-in data TDI after the timing adjustment does not coincide with the return data TDO. In this case, the test control apparatus 200 determines that there is an error in the test interface. Further, the coincidence determination circuit 224 negates the non-coincidence signal ESIG when the scan-in data TDI after the timing adjustment coincides with the return data TDO.

For example, the coincidence determination circuit 224 includes a flip-flop DFF5, an exclusive OR circuit EXOR1, and an AND circuit AND1. The flip-flop DFF5 is, for example, a D-type flip-flop circuit that operates in synchronization with the test clock TCK. The input terminal D of the flip-flop DFF5 receives the return data TDO, and the output terminal Q of the flip-flop DFF5 is connected to the input of the exclusive OR circuit EXOR1. That is, the flip-flop DFF5 outputs a signal TDOd obtained by delaying the loopback data TDO to the exclusive OR circuit EXOR1.

The exclusive OR circuit EXOR1 calculates the exclusive OR of the signal TDIdd and the signal TDOd and outputs the calculation result to the AND circuit AND1. For example, the exclusive OR circuit EXOR1 outputs a signal having a logical value “0” to the AND circuit AND1 when the signal TDIdd and the signal TDOd match, and when the signal TDIdd and the signal TDOd do not match, A signal having a logical value “1” is output to the AND circuit AND1.

The AND circuit AND1 calculates a logical product of the operation result of the exclusive OR circuit EXOR1 (exclusive OR of the signal TDAdd and the signal TDOd) and the signal DENdd, and uses the operation result as the mismatch signal ESIG to the signal control circuit 210. Output to. For example, the AND circuit AND1 negates the mismatch signal ESIG when the signal DENdd is negated or when the signal TDidd and the signal TDOd match. In addition, for example, the AND circuit AND1 asserts the mismatch signal ESIG when the signal DENdd is asserted and the signal TDDD and the signal TDOd do not match.

Note that the configuration of the determination circuit 220 is not limited to this example. For example, when the flip-flop 170 shown in FIG. 1 is omitted, one of the flip-flops DFF1 and DFF2 and one of the flip-flops DFF3 and DFF4 may be omitted. In this case, the coincidence determination circuit 224 generates a signal (signal DENd) obtained by delaying the delay effective signal DEN by one flip-flop and a signal (signal TDId) obtained by delaying the scan-in data TDI by one flip-flop. Received from delay circuit 222.

FIG. 3 shows an example of state transition of the TAP controller 110 shown in FIG. In FIG. 3, the state of the test mode select TMS when the test clock TCK rises will be simply referred to as the state of the test mode select TMS.

The Test Logic Reset state ST1 is a state in which the test logic cannot be used and the normal operation of the system logic can be used. For example, when the signal TRST is asserted, the state of the TAP controller 110 returns to the state ST1. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Run Test Idle state ST2. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 is maintained at the state ST1.

Run Test Idle state ST2 is an internal test execution state or an intermediate state during a scan operation (between scan operations). When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 is maintained in the state ST2. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Select DR Scan state ST3.

In the Select DR Scan state ST3, the scan sequence of the data register 130 is selected. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Capture DR state ST5. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Select IR Scan state ST4.

In the Select IR Scan state ST4, the scan sequence of the instruction register 120 is selected. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Capture IR state ST11. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Test Logic Reset state ST1.

In the Capture DR state ST5, the internal state of the integrated circuit 100 is set in the shift register of the data register 130. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Shift DR state ST6. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Exit DR state ST7.

In the Shift DR state ST6, the data register 130 is connected between the terminal TDI and the terminal TDO. The data register 130 shifts the data bit by bit to the terminal TDO in synchronization with the rising edge of the test clock TCK. Thus, the scan shift of the data register 130 is executed. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 is maintained in the state ST6. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Exit DR state ST7.

In Exit DR state ST7, the scan is terminated. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Pause DR state ST8. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Updata DR state ST10.

In Pause DR state ST8, the scan shift operation in the serial path between the terminal TDI and the terminal TDO is suspended. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 is maintained at the state ST8. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Exit2 DR state ST9.

In Exit2 DR state ST9, the scan is terminated. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Shift DR state ST6. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Updata DR state ST10.

In the Updata DR state ST10, the value of the data register 130 (for example, any of the data registers 132, 134, 136, and 138) is transmitted to the integrated circuit 100. For example, when BS 132 is selected, the value of BS 132 is set to the terminal of integrated circuit 100. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Run Test Idle state ST2. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Select DR Scan state ST3.

In the Capture IR state ST11, a fixed pattern defined by the device (for example, the integrated circuit 100) is set in the shift register of the instruction register 120. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Shift IR state ST12. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Exit IR state ST13.

In the Shift IR state ST12, the shift register of the instruction register 120 is connected between the terminal TDI and the terminal TDO. The shift register of the instruction register 120 shifts the data bit by bit to the terminal TDO in synchronization with the rising edge of the test clock TCK. In this way, the scan shift of the shift register of the instruction register 120 is executed. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 is maintained at the state ST12. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Exit IR state ST13.

In Exit IR state ST13, the scan is terminated. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Pause IR state ST14. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Updata IR state ST16.

In Pause IR state ST14, the scan shift operation in the serial path between the terminal TDI and the terminal TDO is suspended. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 is maintained at the state ST14. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Exit2 IR state ST15.

In Exit2 IR state ST15, the scan is terminated. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Shift IR state ST12. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Updata IR state ST16.

In the Updata IR state ST16, the value of the shift register of the instruction register 120 is held in the flip-flop of the instruction register 120. That is, the data scanned into the shift register of the instruction register 120 is latched by the flip-flop of the instruction register 120. The value of the flip-flop of the instruction register 120 is transmitted to the inside of the integrated circuit 100. When the state of the test mode select TMS is the logical value “0”, the state of the TAP controller 110 transitions to the Run Test Idle state ST2. When the state of the test mode select TMS is the logical value “1”, the state of the TAP controller 110 transitions to the Select DR Scan state ST3.

For example, the test control apparatus 200 changes the state of the TAP controller 110 to the Shift IR state ST12, the Shift DR state ST6, etc., and accesses the instruction register 120 and the data register 130. An example of an access procedure for the instruction register 120 and the data register 130 is shown below.

First, the test control apparatus 200 controls the signals TCK, TMS, TRST, etc., and changes the state of the TAP controller 110 to the state ST12 via the states ST1, ST2, ST3, ST4, ST11. Then, in the state ST12, the test control device 200 outputs the value set in the instruction register 120 to the terminal TDI of the integrated circuit 100 in synchronization with the test clock TCK. Note that the value of the instruction register 120 is output to the terminal TDO of the integrated circuit 100 via the selector 150.

Then, the test control apparatus 200 changes the state of the TAP controller 110 from the state ST12 to the state ST16 via the state ST13. As a result, the instruction code set in the instruction register 120 is output from the instruction register 120 to the data register control circuit 140 and the like.

Next, the test control apparatus 200 changes the state of the TAP controller 110 from the state ST16 through the state ST2 or directly from the state ST16 to the state ST3. As a result, the state of the TAP controller 110 transitions from the IR read / write sequence (states ST4, ST11-ST13, ST16, etc.) to the DR read / write sequence (states ST3, ST5-ST7, ST10, etc.).

The data register 130 to be read / written is selected based on the value (instruction code) of the instruction register 120 set in the IR read / write sequence, for example. The test control apparatus 200 changes the state of the TAP controller 110 from the state ST3 to the state ST6 through the state ST5.

In the state ST6, the test control device 200 outputs the value set in the data register 130 to the terminal TDI of the integrated circuit 100 in synchronization with the test clock TCK. Note that the value of the data register 130 (any one of the data registers 132 to 138) selected by the selectors 142 and 150 is output to the terminal TDO of the integrated circuit 100. Thereafter, the test control apparatus 200 changes the state of the TAP controller 110 from the state ST6 to the state ST2 via the states ST7 and ST10. As described above, the test control device 200 can access the instruction register 120 and the data register 130 using the signals TCK, TMS, TRST, TDI, and TDO.

FIG. 4 shows an example of the operation of the test circuit 20 shown in FIG. That is, FIG. 4 shows one form of a test method for the integrated circuit 100. The operation of FIG. 4 may be realized only by hardware, or may be realized by controlling the hardware by software. In FIG. 4, the operation of the test control device 200 in the test circuit 20 will be mainly described.

In step S100, the signal control circuit 210 of the test control apparatus 200 sets the UR scan-in instruction with loopback in the instruction register 120. For example, the test control apparatus 200 sets an instruction code (for example, 1101) indicating a UR scan-in instruction with loopback in the instruction register 120 in the IR read / write sequence described with reference to FIG. Thereafter, the test control apparatus 200 changes the state of the TAP controller 110 to the DR read / write sequence. As described above, the signal control circuit 210 controls the integrated circuit 100 so that the scan-in data TDI is turned back by the integrated circuit 100.

In step S200, the signal control circuit 210 of the test control apparatus 200 sequentially supplies the scan-in data TDI to the integrated circuit 100. As a result, the scan-in data TDI is sequentially written into the UR 138, and the return data LBDO of the scan-in data TDI is sequentially output from the flip-flop 170.

In step S300, the test control apparatus 200 sequentially acquires the return data LBDO of the scan-in data TDI from the integrated circuit 100 as the scan-out data TDO. For example, the test control device 200 sequentially receives the output signal LBDO of the flip-flop 170 in the integrated circuit 100 from the integrated circuit 100.

In step S400, the determination circuit 220 of the test control apparatus 200 compares the scan-in data TDI supplied to the integrated circuit 100 in step S200 with the return data TDO acquired in step S300. For example, the determination circuit 220 adjusts the comparison timing of the scan-in data TDI and the return data TDO according to the delay of the return data TDO, and compares the scan-in data TDI after timing adjustment with the return data TDO after timing adjustment. .

In step S500, the determination circuit 220 of the test control apparatus 200 determines whether or not the scan-in data TDI and the return data TDO match. When the scan-in data TDI and the return data TDO match (Yes in step S500), the operation of the test control device 200 proceeds to step S600. On the other hand, when the scan-in data TDI and the return data TDO do not match (No in step S500), the operation of the test control apparatus 200 moves to step S700.

In step S600, the determination circuit 220 of the test control device 200 negates the mismatch signal ESIG. In this case, the test control apparatus 200 determines that there is no abnormality in the test interface.

In step S700, the determination circuit 220 of the test control apparatus 200 asserts the mismatch signal ESIG. In this case, the test control apparatus 200 determines that there is an abnormality in the test interface. That is, the test control device 200 detects an error in the test interface.

As described above, it is possible to determine whether or not the return data TDO of the scan-in data TDI is correct before the value (the value of the scan-in data TDI) written in the test control device 200 and the UR 138 is read. Therefore, the test control apparatus 200 can shorten the time for detecting an error in the test interface. Note that the operation of the test circuit 20 is not limited to this example.

FIG. 5 shows an example of a time chart of each signal shown in FIG. A period T3-T10 in FIG. 5 corresponds to the IR write sequence (scan-in to the IR 120). IR (SHIFT) in FIG. 5 indicates the value of the shift register of IR 120, and IR (FF) indicates the value of the flip-flop of IR 120 (instruction code set in IR 120).

For example, among the IR120 shift registers, the value of the register that receives data TDI corresponds to the leftmost value of IR (SHIFT), and the value of the register that outputs data TDO is the rightmost value of IR (SHIFT). Corresponds to the value of. In FIG. 5, the description will be made assuming that the bit length of the shift register of IR 120 is 4 bits. The bit length of the IR120 shift register is not limited to 4 bits. In addition, Select DR in the figure indicates Select DR Scan state ST3, and Select IR indicates Select IR Scan state ST4.

In the period T0-T1, the state of the TAP controller 110 is the Run Test Idle state ST2. As shown in FIG. 3, the state of the TAP controller 110 changes according to the state of the test mode select TMS when the test clock TCK rises. For example, when the TAP controller 110 detects in the Run Test Idle state ST2 that the test mode select TMS at the rising edge of the test clock TCK is a logical value “1”, the TAP controller 110 transitions to the Select DR Scan state ST3 (period T2 ).

In the period T2-T4, the state of the TAP controller 110 transits from the Select DR Scan state ST3 to the Select IR Scan state ST4 to the Capture IR state ST11 under the control of the test mode select TMS. In the Capture IR state ST11 (period T4), a predetermined fixed value (0001 in the example of FIG. 5) is set in the shift register of the IR 120.

For example, in the period T4, the TAP controller 110 outputs a one-shot pulse to the IR 120 in synchronization with the falling edge of the test clock TCK as the signal CAPTUREIR. As a result, a predetermined fixed “0001” is set in the shift register of the IR 120 in synchronization with the rising edge of the signal CAPTUREIR. Thereafter, the state of the TAP controller 110 transitions from the Capture IR state ST11 to the Shift IR state ST12 since the test mode select TMS at the rising edge of the test clock TCK is the logical value “0” (period T5).
In the period T5-T8, the state of the TAP controller 110 is maintained in the Shift IR state ST12. In the period T9, the state of the TAP controller 110 changes from the Shift IR state ST12 to the Exit IR state ST13 because the test mode select TMS at the rising edge of the test clock TCK is the logical value “1”. For example, the scan shift of the IR 120 shift register is executed in the Shift IR state ST12, and the scan shift of the IR 120 shift register is completed in the Exit IR state ST13.

For example, the TAP controller 110 outputs the scan clock IRACK to the IR 120 in synchronization with the rising edge of the test clock TCK, and outputs the scan clock IRBCK to the IR 120 in synchronization with the falling edge of the test clock TCK. The scan clocks IRACK and IRBCK are supplied to the IR 120, for example, from the next cycle (period T6) in which the transition is made to the Shift IR state ST12 to the cycle of the Exit IR state ST13 (period T9).

Each shift register of IR120 outputs, for example, the value held (the value received at the input terminal when the clock IRACK rises) to the next stage in synchronization with the rise of the clock IRBCK. Of the shift registers of IR 120, the last stage register outputs the held value to selector 150 in synchronization with the rising edge of clock IRBCK.

In the example of FIG. 5, serial data “1011” of the instruction code “1101” indicating the UR scan-in instruction with loopback is supplied to the terminal TDI as data TDI in synchronization with the test clock TCK. As a result, the instruction code “1011” indicating the UR scan-in instruction with loopback is set in the shift register of the IR 120 by the period T9.

Further, from the middle of the period T5 to the middle of the period T9, the selector 150 selects the output signal of the IR 120 as the data TDO to be output to the terminal TDO. Therefore, the rightmost value of IR (SHIFT) is output as data TDO in each of the periods T5-T9.

In the period T9, since the state of the TAP controller 110 is the Exit IR state ST13, the scan-in to the shift register of the IR 120 is completed. Further, since the test mode select TMS at the rising edge of the test clock TCK is the logical value “1”, the state of the TAP controller 110 transitions from the Exit IR state ST13 to the Updata IR state ST16 (period T10).

In the period T10, since the state of the TAP controller 110 is the Updata IR state ST16, the value of the IR120 shift register is held in the IR120 flip-flop. For example, in the period T10, the TAP controller 110 outputs a one-shot pulse to the IR 120 in synchronization with the falling edge of the test clock TCK as the signal UPDATEIR.

Thereby, the value “1101” of the shift register of the IR 120 is set in the flip-flop of the IR 120 in synchronization with the rising edge of the signal UPDATEIR. That is, the UR scan-in instruction with loopback is set in the IR 120.

Thus, in the IR write sequence, the data scanned into the IR 120 shift register is latched in the IR 120 flip-flop. The value of the IR 120 flip-flop is transmitted to the integrated circuit 100.

FIG. 6 shows another example of a time chart of each signal shown in FIG. 6 corresponds to a DR write sequence (scan-in to UR 138) executed after the IR write sequence (period T3-T10 in FIG. 5) shown in FIG. Therefore, in FIG. 6, the operation based on the UR scan-in instruction with loopback is executed. The meanings of IR (FF) and Select DR in FIG. 6 are the same as or similar to those in FIG. Further, UR in FIG. 6 indicates the value of UR138.

For example, among the registers of UR138, the value of the register that receives data TDI corresponds to the leftmost value of UR, and the value of the register that outputs data TDO corresponds to the rightmost value of UR. Yes. In FIG. 6, UR138 will be described as a 4-bit shift register. The bit length of UR138 (shift register) is not limited to 4 bits.

In the period T10, the state of the TAP controller 110 is the Updata IR state ST16. In addition, an instruction code “1101” indicating a UR scan-in instruction with a loopback is set in the IR 120. As shown in FIG. 3, the state of the TAP controller 110 changes according to the state of the test mode select TMS when the test clock TCK rises. For example, when the TAP controller 110 detects that the test mode select TMS at the rising edge of the test clock TCK is the logical value “1” in the Updata IR state ST16, the TAP controller 110 transits to the Select DR Scan state ST3 (period T11). .

During the period T11-T13, the state of the TAP controller 110 transitions from the Select DR Scan state ST3 to the Capture DR state ST5 to the Shift DR state ST6 under the control of the test mode select TMS. In the Shift DR state ST6, the signal SHIFTDR is asserted. For example, the TAP controller 110 asserts the signal SHIFTDR during the Shift DR state ST6.

In the period T13-T16, the state of the TAP controller 110 is maintained in the Shift DR state ST6. In the period T17, the state of the TAP controller 110 changes from the Shift DR state ST6 to the Exit DR state ST7 because the test mode select TMS at the rising edge of the test clock TCK is the logical value “1”. For example, the UR 138 scan shift is executed in the Shift DR state ST6, and the UR 138 scan shift ends in the Exit DR state ST7.

For example, the data register control circuit 140 and the loopback control circuit 180 control the scan shift operations of the UR 138 and the flip-flop 170 based on the values of the signals SHIFTDR and IR 120 received from the TAP controller 110, respectively. First, the scan shift operation of the UR 138 will be described.

For example, the data register control circuit 140 supplies the scan clocks URACK and URBCK to the UR 138 from the next cycle (period T14) in which the signal SHIFTDR is asserted to the cycle (period T17) in which the signal SHIFTDR is negated. For example, the data register control circuit 140 outputs the scan clock URACK to the UR 138 in synchronization with the rising edge of the test clock TCK, and outputs the scan clock URBCK to the UR 138 in synchronization with the falling edge of the test clock TCK.

Each register of the UR 138 outputs, for example, a held value (value received at the input terminal when the clock URACK rises) to the next stage in synchronization with the rise of the clock URBCK. Note that the last-stage register of the UR 138 outputs the held value to the selector 142 in synchronization with the rising edge of the clock URBCK.

In the example of FIG. 6, serial data “1001” is supplied to the terminal TDI as data TDI in synchronization with the test clock TCK. Thereby, the scan-in data “1001” is set in the UR 138 by the period T17. The selector 142 selects the output signal of the UR 138 as a signal to be output to the selector 150 based on the control of the data register control circuit 140.

Next, the scan shift operation of the flip-flop 170 will be described. Since the instruction code “1101” indicating the UR scan-in instruction with loopback is set in the IR 120, the loopback control circuit 180 supplies a scan clock that is the same as or similar to the scan clocks URACK and URBCK to the flip-flop 170. In FIG. 6, the scan clock supplied to the flip-flop 170 is also referred to as scan clocks URACK and URBCK.

For example, the loopback control circuit 180 outputs the scan clock URACK to the flip-flop 170 in synchronization with the rising edge of the test clock TCK. The loopback control circuit 180 outputs the scan clock URBCK to the flip-flop 170 in synchronization with the falling edge of the test clock TCK. For example, the flip-flop 170 outputs the value of the data TDI received at the input terminal at the rising edge of the clock URACK as the signal LBDO in synchronization with the rising edge of the clock URBCK.

The selector control circuit 160 controls the selector 150 based on the values of the signals SHIFTDR and IR 120 received from the TAP controller 110. For example, the selector control circuit 160 controls the selector 150 to select the output signal LBDO of the flip-flop 170 because the value of the IR 120 is the instruction code “1101” indicating the UR scan-in instruction with loopback.

Thereby, for example, the selector 150 outputs the output signal LBDO of the flip-flop 170 as data TDO to the terminal TDO in synchronization with the falling edge of the test clock TCK in the next cycle (period T14) in which the signal SHIFTDR is asserted. To do. The selector 150 continues to output the output signal LBDO of the flip-flop 170 as data TDO to the terminal TDO until the falling edge of the test clock TCK in the next cycle (period T18) in which the signal SHIFTDR is negated.

As a result, from the middle of the period T14 to the middle of the period T18, the loopback data LBDO of the data TDI is output from the integrated circuit 100 to the test controller 200 as the data TDO. In the UR scan-in instruction with loopback, since the selector 150 selects the output signal LBDO of the flip-flop 170, the value of the UR138 is not output to the terminal TDO.

The signal control circuit 220 of the test control apparatus 200 asserts the delay valid signal DEN while outputting the scan-in data “1001” as the data TDI (from the middle of the period T13 to the middle of the period T17).

The delay circuit 222 delays the delay valid signal DEN and the data TDI by two cycles in synchronization with the test clock TCK (signals DENdd and TDIdd in FIG. 6). For example, the delay circuit 222 delays the delay valid signal DEN using the flip-flops DFF1 and DFF2, and delays the data TDI using the flip-flops DFF3 and DFF4.

For example, the coincidence determination circuit 224 delays the data TDO by one cycle in synchronization with the test clock TCK (signal TDOd in FIG. 6). For example, the coincidence determination circuit 224 delays the delay valid signal DEN using the flip-flop DFF5. Then, when the signal DENdd obtained by delaying the delay valid signal DEN is asserted, the coincidence determination circuit 224 compares the value of the signal TDidd with the value of the signal TDOd (period T15-T18). In the example of FIG. 6, the value of the signal TDIdd and the value of the signal TDOd match in each of the periods T15 to T18, so the mismatch signal ESIG is negated. Note that if the value of the signal TDIdd and the value of the signal TDOd do not match, the mismatch signal ESIG is asserted.

For example, the test control apparatus 200 detects that a failure has occurred in the terminals TDI, TDO, signal lines TDI, TDO, etc., which are test interfaces, by detecting a mismatch between the value of the signal TDIdd and the value of the signal TDOd. It can be detected. Note that, for example, when a failure occurs in the signal lines TCK, TMS, and TRST, the loopback to the test control device 200 is not normally performed. Therefore, the failure of the signal lines TCK, TMS, and TRST is caused by the value of the signal TDAdd. And the value of the signal TDOd are detected as mismatches.

Thus, the test control apparatus 200 can detect an error in the test interface only by the DR write sequence (scan-in), for example. Therefore, in this embodiment, the procedure for detecting an error in the test interface can be simplified. Further, in this embodiment, the processing time required for detecting an error in the test interface can be shortened.

FIG. 7 shows another example of a time chart of each signal shown in FIG. A period T31 to T38 in FIG. 7 corresponds to the DR write sequence (scan-in to the UR 138). In the example of FIG. 7, the UR scan-in instruction is set in the IR 120 by the IR write sequence executed before the DR write sequence (IR = 1100). The IR write sequence for setting the UR scan-in instruction in IR 120 is the same as or similar to the IR write sequence shown in FIG. 5 except for serial data “0011” (instruction code “1100”) given as data TDI. For example, in FIG. 5, serial data “1011” of the instruction code “1101” is given as data TDI.

7 The meanings of IR (FF), UR, and Select DR in FIG. 7 are the same as or similar to those in FIG. Detailed description of the same or similar operations as those described in FIG. 6 is omitted. For example, the period T30 to T40 corresponds to the period T10 to T20 in FIG.

In the period T30, the state of the TAP controller 110 is the Updata IR state ST16. In addition, an instruction code “1100” indicating a UR scan-in instruction is set in the IR 120. The UR 138 holds data “1001” (for example, scan-in data set in the UR 138 by the DR write sequence in FIG. 6).

In the period T33-T36, for example, the data register control circuit 140 and the loopback control circuit 180 control the scan shift operations of the UR 138 and the flip-flop 170 based on the values of the signals SHIFTDR and IR 120 received from the TAP controller 110, respectively. The loopback control circuit 180 does not execute the scan shift operation of the flip-flop 170 because the instruction code “1100” indicating the UR scan-in instruction is set in the IR 120. Therefore, the scan shift operation of the UR 138 will be described focusing on the operation different from the operation of FIG.

For example, the data register control circuit 140 supplies the scan clocks URACK and URBCK to the UR 138 from the next cycle (period T34) in which the signal SHIFTDR is asserted to the cycle (period T37) in which the signal SHIFTDR is negated. Each register of the UR 138 outputs, for example, a held value (value received at the input terminal when the clock URACK rises) to the next stage in synchronization with the rise of the clock URBCK. Note that the last-stage register of the UR 138 outputs the held value to the selector 142 in synchronization with the rising edge of the clock URBCK.

In the example of FIG. 7, serial data “0110” is supplied to the terminal TDI as data TDI in synchronization with the test clock TCK. Thereby, the scan-in data “0110” is set in the UR 138 by the period T37. Further, the selector 142 selects the output signal of the UR 138 (the value of the register at the final stage of the UR 138) as a signal to be output to the selector 150 based on the control of the data register control circuit 140.

For example, since the value of the IR 120 is the instruction code “1100” indicating the UR scan-in instruction, the selector control circuit 160 selects the output signal of the DR 130 (the output signal of the UR 138 selected by the selector 142). 150 is controlled.

Thereby, for example, the selector 150 synchronizes with the falling edge of the test clock TCK in the cycle (period T33) in which the signal SHIFTDR is asserted, and the value of the last-stage register of the UR 138 (the rightmost value of the UR). The data TDO is output to the terminal TDO. Then, the selector 150 uses the value of the last-stage register of UR 138 (the rightmost value of UR) as data TDO until the falling edge of the test clock TCK in the cycle (period T37) in which the signal SHIFTDR is negated. Continue to output.

As a result, the data “1001” held in the UR 138 before the DR write sequence in FIG. 7 is executed is output as the data TDO from the integrated circuit 100 to the test control device 200 (period T33-T37). In the UR scan-in instruction, since the selector 150 selects the output signal of the DR 130, the output signal LBDO of the flip-flop 170 is not output to the terminal TDO.

The signal control circuit 220 of the test control apparatus 200 does not assert the delay valid signal DEN because the UR scan-in command is executed. That is, the delay valid signal DEN is negated. For this reason, the coincidence determination circuit 224 does not perform a comparison between the value of the signal TDIdd and the value of the signal TDOd. Therefore, the mismatch signal ESIG is negated in the UR scan-in instruction.

As described above, in the integrated circuit test circuit, the information processing apparatus, and the integrated circuit test method according to the embodiments shown in FIGS. 1 to 7, for example, the test control apparatus 200 integrates the scan-in data TDI through the signal line TDI. Supply to circuit 100. Then, the test control device 200 receives the return data of the scan-in data TDI as the scan-out data TDO from the integrated circuit 100 via the signal line TDO. Further, the determination circuit 222 of the test control device 200 compares the scan-in data TDI and the return data TDO to determine whether the return data TDO is correct.

Thereby, the test control apparatus 200 can detect an error in the test interface. For example, when the determination circuit 222 determines that the return data TDO is not correct, the test control apparatus 200 determines that a failure has occurred in the test interface. In this embodiment, since it is determined whether or not the return data TDO of the scan-in data TDI is correct, an error in the test interface can be detected only by scan-in of scan-in and scan-out.

As a result, in this embodiment, the procedure for detecting an error in the test interface can be simplified, and the processing time required for detecting the error in the test interface can be shortened. That is, in this embodiment, it is possible to shorten the time for detecting an error in the test interface.

From the above detailed description, the features and advantages of the embodiment will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

Claims (12)

An integrated circuit test circuit,
A test control unit for supplying scan-in data to the integrated circuit via a first signal line and receiving scan-out data from the integrated circuit via a second signal line;
The test control unit
A signal control unit that controls the integrated circuit so that the scan-in data is folded at the integrated circuit, and supplies the scan-in data to the integrated circuit via the first signal line;
The scan-in data to be supplied to the integrated circuit is received from the signal control unit, the return data of the scan-in data is received from the integrated circuit via the second signal line, and the scan-in data and the return data are received. A test circuit comprising: a determination unit that determines whether the return data is correct by comparison. The test circuit according to claim 1,
A flip-flop that is provided in the integrated circuit, receives the scan-in data, and outputs the scan-in data to the determination unit in synchronization with a test clock as the folded data;
The signal control unit supplies the test clock to the integrated circuit. An integrated circuit test circuit. The integrated circuit test circuit according to claim 2,
The determination unit
A timing adjustment unit that outputs the scan-in data received from the signal control unit with a predetermined number of cycles delayed in synchronization with the test clock; and
The scan-in data delayed by the predetermined number of cycles is received from the timing adjustment unit, the return data is received from the integrated circuit via the second signal line, and the scan-in data and the return data are received. An integrated circuit test circuit comprising: a comparison unit for comparison. The integrated circuit test circuit according to any one of claims 1 to 3,
The test circuit for an integrated circuit, wherein the determination unit receives the return data during a period in which the scan-in data is written to a data register in the integrated circuit, and determines whether the return data is correct. An integrated circuit, and a test circuit for testing the integrated circuit,
The test circuit includes a test control unit that supplies scan-in data to the integrated circuit via a first signal line and receives scan-out data from the integrated circuit via a second signal line,
The test control unit
A signal control unit that controls the integrated circuit so that the scan-in data is folded at the integrated circuit, and supplies the scan-in data to the integrated circuit via the first signal line;
The scan-in data to be supplied to the integrated circuit is received from the signal control unit, the return data of the scan-in data is received from the integrated circuit via the second signal line, and the scan-in data and the return data are received. An information processing apparatus comprising: a determination unit configured to determine whether the return data is correct by comparison. The information processing apparatus according to claim 5,
The integrated circuit includes a flip-flop that receives the scan-in data and outputs the scan-in data as the loop-back data to the determination unit in synchronization with a test clock;
The signal control unit supplies the test clock to the integrated circuit. The information processing apparatus according to claim 6,
The determination unit
A timing adjustment unit that outputs the scan-in data received from the signal control unit with a predetermined number of cycles delayed in synchronization with the test clock; and
The scan-in data delayed by the predetermined number of cycles is received from the timing adjustment unit, the return data is received from the integrated circuit via the second signal line, and the scan-in data and the return data are received. An information processing apparatus comprising: a comparison unit for comparing. The information processing apparatus according to any one of claims 5 to 7,
The information processing apparatus, wherein the determination unit receives the return data during a period in which the scan-in data is written to a data register in the integrated circuit, and determines whether the return data is correct. An integrated circuit test method comprising:
Controlling the integrated circuit such that scan-in data is folded at the integrated circuit;
Transferring the scan-in data from the test control unit to the integrated circuit via the first signal line;
Transfer back data of the scan-in data from the integrated circuit to the test control unit via a second signal line,
Comparing the scan-in data held in the test control unit with the return data transferred to the test control unit, it is determined whether or not the return data is correct. Test method. The method of testing an integrated circuit according to claim 9.
A test clock is transferred from the test control unit to the integrated circuit;
Transferring the scan-in data from the test control unit to the flip-flop in the integrated circuit via the first signal line;
A test method for an integrated circuit, wherein the output signal of the flip-flop that has received the scan-in data is transferred as the loopback data from the integrated circuit to the test control unit in synchronization with the test clock. The method of testing an integrated circuit according to claim 10.
The scan-in data held in the test control unit is delayed by a predetermined number of cycles in synchronization with the test clock,
An integrated circuit comprising: comparing the loop-back data transferred from the integrated circuit to the test control unit via the second signal line with the scan-in data delayed by the predetermined number of cycles. Testing method. 12. The integrated circuit test method according to claim 9, wherein:
During the period in which the scan-in data is written to the data register in the integrated circuit, the loopback data is transferred from the integrated circuit to the test control unit via the second signal line, and whether the loopback data is correct or not is determined. A method for testing an integrated circuit, characterized by: determining.

Images