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WO2015189955A1 - Procédé de fabrication de carte de circuit imprimé multicouche et carte de circuit imprimé multicouche - Google Patents

Procédé de fabrication de carte de circuit imprimé multicouche et carte de circuit imprimé multicouche Download PDF

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Publication number
WO2015189955A1
WO2015189955A1 PCT/JP2014/065608 JP2014065608W WO2015189955A1 WO 2015189955 A1 WO2015189955 A1 WO 2015189955A1 JP 2014065608 W JP2014065608 W JP 2014065608W WO 2015189955 A1 WO2015189955 A1 WO 2015189955A1
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WO
WIPO (PCT)
Prior art keywords
base material
core
substrate
conductive layer
core substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2014/065608
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English (en)
Japanese (ja)
Inventor
光昭 戸田
直之 齋藤
峰進 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meiko Electronics Co Ltd
Original Assignee
Meiko Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Electronics Co Ltd filed Critical Meiko Electronics Co Ltd
Priority to PCT/JP2014/065608 priority Critical patent/WO2015189955A1/fr
Priority to JP2016527565A priority patent/JPWO2015189955A1/ja
Priority to TW104115081A priority patent/TW201603676A/zh
Publication of WO2015189955A1 publication Critical patent/WO2015189955A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a substrate manufacturing method, and more particularly to a multilayer substrate manufacturing method and a multilayer substrate including a step of laminating and pressing a core base material on which a conductive layer is formed and an insulating base material.
  • a so-called multilayer substrate having a plurality of conductive layers formed as wiring patterns on both sides and inside of the substrate is known.
  • This multilayer substrate is manufactured by laminating an insulating base material and a metal film from both sides to a core substrate having a conductive layer on both sides and pressing it.
  • voids may be generated in the insulating base material.
  • Such a cavity is called void or blur. This void often occurs in a portion where there is no conductive layer on both surfaces of the core substrate, which is considered to be caused by the fact that the insulating base becomes thicker than the other portions after curing in this portion.
  • the part without the conductive layer becomes thick because the pressure is applied unevenly between the part with and without the conductive layer against the core substrate during pressing, and the part without the conductive layer becomes low pressure. is there. Such a phenomenon may impair the reliability quality of the substrate, such as inducing delamination during mounting reflow or reducing the resistance to insulation deterioration.
  • a method of laminating and pressing a convex member in which a convex portion is formed in a portion corresponding to a portion without a conductive layer is known (for example, see Patent Document 1).
  • pressure nonuniformity during pressing is suppressed, and voids and blurring are prevented from occurring.
  • the metal film is bent together with the film by using the vacuum during pressing, and the pressure is applied to this part by entering the part without the conductive layer. There is something to hang.
  • the above-described method of further laminating the film is in a state where the metal film is bent together with the film, and the flatness of the substrate surface is deteriorated. This will hinder the adhesion of the dry film, which is an etching resist, to the metal film in the future, resulting in a circuit failure due to the etching process.
  • the circuit since the circuit is formed of a bent metal film, it causes a wire bonding failure when mounting a component.
  • the present invention has been made in consideration of the above-described prior art, and an object of the present invention is to provide a method for manufacturing a multilayer substrate and a multilayer substrate that do not cause voids or blurring.
  • a core substrate forming step of forming a core substrate by forming a patterned first conductive layer on at least one surface of a flat core substrate, and the core substrate A laminating step of disposing an insulating base material made of an insulating material on both sides of the substrate and further disposing a metal film on the outer side thereof, and a pressing step of pressing the core substrate, the insulating base material, and the metal film against each other by vacuum pressurization
  • a method for manufacturing a multilayer substrate is provided.
  • the elastic modulus of the core base material is lower than the elastic modulus of the insulating base material to be laminated in the laminating step.
  • a smoothing treatment is performed to dispose a smoothing agent over the entire surface of the core base material, and the smoothing agent has OH in one molecule. All groups or OH-forming groups, azide groups, and triazine rings are included.
  • the insulating base material is disposed on both sides of the core base material, and the first conductive layer is formed in a product region formed by dividing both surfaces of the core base material for each product,
  • the product region is formed by being surrounded by a frame provided so as to protrude from the core base material, and the core base material has a waste region separated from the product region through the frame, Provides a multilayer substrate wherein the first conductive layer is not formed.
  • a plurality of locations are bent so that the core base material has a corrugated cross section, so that the core base material is uniformly subjected to pressure applied from above and below. That is, since the core base material receives the pressure uniformly, the insulating base material can be uniformly pressed over the entire area. For this reason, generation
  • the core base material is more uniformly affected by the pressure than the insulating base material when pressure is applied during the pressing process. To follow and change its shape. For this reason, an insulating base material is uniformly pressed in the whole area between a core base material and a press, and generation
  • the surface of the core base material is smoothed by arranging a smoothing agent over the entire surface of the core base material in the core substrate forming step. For this reason, an insulating base material comes into contact with the surface of a core base material in a press process, and becomes easy to flow, and an insulating base material spreads over the whole area of a core base material. For this reason, generation
  • the adhesiveness (plating adhesion) between the core base material and the first conductive layer may be reduced, but OH group or OH generating group in one molecule, It has been found that the use of a smoothing agent containing all of an azide group and a triazine ring improves the adhesion performance between the first conductive layer made of metal and the core substrate. For this reason, the roughening process of the core base material surface normally performed in order to improve adhesiveness with a 1st conductive layer becomes unnecessary.
  • FIG. 3 is a flowchart showing a method for manufacturing a multilayer substrate according to the present invention. It is a schematic plan view of a core substrate.
  • FIG. 2 is a cross-sectional view taken along the line AA in FIG. It is the schematic which shows a lamination process. It is the schematic which shows a press process. It is the schematic which shows a pattern formation process, and is the schematic of the multilayer substrate which concerns on this invention.
  • FIG. 1 will be described with reference to FIGS. 2 to 6.
  • FIG. 1 will be described with reference to FIGS. 2 to 6.
  • the method for manufacturing a multilayer substrate according to the present invention starts with a core substrate formation process (step S1).
  • the core substrate 1 as shown in FIGS. 2 and 3 is formed.
  • the first conductive layer 3 is formed on at least one surface (both surfaces in the illustrated example) of the flat core substrate 2.
  • the first conductive layer 3 is formed as a conductor pattern using, for example, an additive method or a subtractive method.
  • the patterned first conductive layer 3 is omitted.
  • the core substrate 1 is formed by having a plurality of product regions 4 (six in the example in the figure) product regions 4 to be product substrates in one core base material 2. Therefore, a plurality of product substrates can be obtained from the core substrate 1.
  • the area other than the product area 4 is a discarded area 6.
  • Each product area 4 is surrounded by a frame 5.
  • the frame 5 is provided so as to protrude from the core substrate 2, and plays a role of a boundary between each product region 4 and the disposal region 6.
  • the surface of the core substrate 2 is exposed.
  • the conductive layer 3 is formed as described above.
  • a double-sided section 12 in which the conductive layer 3 is not disposed on both sides and a single-sided section 13 in which the conductive layer 3 is not disposed only on one side are formed.
  • a lamination process is performed (step S2).
  • an insulating base material 7 made of an insulating material is disposed on both sides of the core substrate 1, and a metal film 8 is disposed on the outer side thereof.
  • the insulating base material 7 is a prepreg, for example, and this prepreg is formed from a thermosetting resin such as an epoxy resin.
  • the insulating base material 7 has a flat plate shape like the core base material 2. Note that a glass cloth (not shown) is embedded in the insulating base material 7 over substantially the entire area.
  • the glass cloth is a cloth woven with glass fiber yarns and has a sheet shape.
  • the metal film 8 is a copper foil.
  • the support plate 9 has a flat plate shape like the insulating substrate 7 and the core substrate 2, and is a rigid SUS (stainless steel) plate.
  • the core board 1 is laminated so that the support plate 9 is on the outermost side.
  • step S3 a pressing process is performed (step S3).
  • the core substrate 1, the insulating base material 7, and the metal film 8 are pressed against each other by vacuum pressurization.
  • the support plate 9 is pressed using a press machine (not shown), and the insulating base material 7 is caused to flow by heating.
  • the insulating base material 7 is spread all over the part of the core substrate 1 where the first conductive layer 3 is not present (the double-sided section 12 and the single-sided section 13) and every corner of the disposal region 6.
  • the core substrate 2 is bent at a plurality of locations so as to have a corrugated cross section. That is, the core substrate 2 is deformed.
  • the deformation of the core base material 2 is performed by transmitting a pressing force to the core base material 2 by pressing of a press. Due to the deformation of the core base material 2, the core base material 2 receives a uniform pressure with respect to the pressure applied from above and below. Since the core base material 2 receives the pressure uniformly, the insulating base material 7 can be uniformly pressurized over the entire area.
  • the insulating base material 7 flows by pressing from above and below, but the area where the surface of the core base material 2 is exposed, such as the discarded area 6, is a portion where the first conductive layer 8 and the frame 5 are located. Compared to low pressure. In this portion, the insulating base material 7 does not become consolidated, but the core base material 2 is deformed by the vacuum pressurization, so that a substantially uniform pressure is received in the pressing direction. For this reason, generation
  • the deformation of the core base material 2 in such a pressing process can be specifically realized as follows. That is, a material having an elastic modulus lower than the elastic modulus (tensile elastic modulus characteristic) of the insulating substrate 7 is used as the core substrate 2.
  • a material having an elastic modulus lower than the elastic modulus (tensile elastic modulus characteristic) of the insulating substrate 7 is used as the core substrate 2.
  • the core substrate 2 has considerable flexibility, and deformation in the pressing process is promoted.
  • the core base material 2 is more affected by the pressure than the insulating base material 7 when pressure is applied in the pressing process. To follow the pressure evenly and change its shape. For this reason, the insulating base material 7 is uniformly pressed in the whole area between the core base material 2 and a press machine, and generation
  • step S4 a pattern forming process is performed (step S4).
  • the second conductive layer 10 is formed by patterning the metal film 8 as shown in FIG. Specifically, first, the support plate 9 is removed, a mask of a predetermined circuit is formed on the exposed metal film 8 by a printing method or a photographic method, and then unnecessary portions are removed with an etching solution such as ferric chloride. The metal film 8 is removed. This is a so-called subtractive method. Thereby, the second conductive layer 10 is formed.
  • the multilayer substrate 11 is manufactured. That is, the multilayer substrate 11 is formed by disposing the insulating base material 7 on both sides of the core base material 2. On the surface of the core substrate 2, a plurality of product areas 4 and a discard area 6 are formed, and these are divided by a frame 5. In other words, the frame 5 functions as a boundary between the product area 4 and the discard area 6. A first conductive layer 3 as a conductor pattern is formed in the product region 4. Furthermore, a double-sided section 12 and a single-sided section 13 are formed in the product region 4. In the future, a part including the product region 4 in the frame 5 is cut from the multilayer substrate 11 as a product substrate. On the other hand, the first conductive layer 3 is not formed in the discarded region 6.
  • the multilayer substrate 11 has a structure in which only the side surface of the core substrate 1 is exposed and embedded in the insulating base material 7.
  • the core base material 2 of the core substrate 1 has a corrugated cross section, and the surface is bent with unevenness repeatedly.
  • both exposed surfaces of the insulating substrate 7 are smooth. That is, the front and back surfaces of the core substrate 2 and the front and back surfaces of the multilayer substrate 11 are not parallel but non-parallel. Thus, since it is non-parallel, the press from a press machine can be received uniformly at the time of a press process.
  • the core base material 2 since there is a part (double-sided section 12 or single-sided section 13) where the first conductive layer 3 is not formed in the product region 4, the core base material 2 is bent and is uniformly pressed in this part. Deform.
  • the ability to suppress the generation of voids in the double-sided section 12 and the single-sided section 13 in the product region 4 is also effective from the viewpoint of the yield of product substrates.
  • a smoothing process may be performed in which a smoothing agent is disposed on the entire surface of the core base material 2 before the first conductive layer 3 is formed.
  • the smoothing process in this way, the surface of the core substrate 2 is smoothed.
  • the insulating base material 7 becomes easy to flow in contact with the surface of the core base material 2 in the pressing step, and the insulating base material 7 spreads over the entire area of the core base material 2. For this reason, generation
  • the thickness of the substrate has been reduced, and the insulating base material 7 tends to use a glass having a high glass transition point and low fluidity in order to reduce warpage during curing.
  • the insulating base material 7 does not spread so as to closely follow the side surface of the first conductive layer 3.
  • the insulating substrate 7 can be spread over the entire surface of the core substrate 2.
  • the smoothing agent one containing all of OH group or OH generating group, azide group and triazine ring in one molecule is used.
  • a smoothing agent made of such a compound it has been found that the adhesion performance is improved without decreasing the adhesion (plating adhesion) between the first conductive layer 3 and the core substrate 2. Yes.
  • the roughening process of the surface of the core base material 2 normally performed in order to improve the adhesiveness of the 1st conductive layer 3 becomes unnecessary. That is, if the smoothing process is performed, the first conductive layer 3 can be formed by a simple manufacturing method such as a copper plating process.
  • R 1 is a hydrocarbon group
  • R 2 is a group containing an alkoxysilyl group
  • Q is N 3 or NR 3 (R 4 ) (R 3 and R 4 are hydrocarbon groups).
  • Examples of the compound represented by the chemical formula include 6-azido-2,4-bis (ethanolamino) -1,3,5-triazine, 6-azido-2,4-bis (hexanolamino) -1 , 3,5-triazine, 6-azido-2,4-bis (decanolamino) -1,3,5-triazine, 6-azido-2,4-bis (3,4-bishydroxyphenyl) amino) -1,3,5-triazine, 6-azido-2,4-bis (2,2-dihydroxymethyl) ethylamino-1,3,5-triazine, 6-azido-2,4-bis (trismethanolmethyl) ) Methylamino-1,3,5-triazine, 6-a

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention concerne un procédé de fabrication de carte de circuit imprimé multicouche comprenant les étapes suivantes : une étape de formation de carte de circuit imprimé centrale à laquelle une première couche conductrice à motifs est formée sur au moins une surface d'un substrat central plat, ce qui permet d'obtenir une carte de circuit imprimé centrale ; une étape de stratification à laquelle des substrats isolants comprenant chacun un matériau isolant sont disposés sur les deux côtés de la carte de circuit imprimé centrale et des films métalliques sont disposés sur les côtés extérieurs desdits substrats isolants ; une étape de pression à laquelle le vide est utilisé pour presser la carte de circuit imprimé centrale, les substrats isolants et les films métalliques l'un contre l'autre ; et une étape de formation des motifs à laquelle les films métalliques sont soumis à une formation des motifs de manière à former des secondes couches conductrices. À l'étape de pression, la carte de circuit imprimé centrale est déformée au niveau d'une pluralité de points de façon à donner une section transversale ondulée à ladite carte de circuit imprimé centrale.
PCT/JP2014/065608 2014-06-12 2014-06-12 Procédé de fabrication de carte de circuit imprimé multicouche et carte de circuit imprimé multicouche Ceased WO2015189955A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2014/065608 WO2015189955A1 (fr) 2014-06-12 2014-06-12 Procédé de fabrication de carte de circuit imprimé multicouche et carte de circuit imprimé multicouche
JP2016527565A JPWO2015189955A1 (ja) 2014-06-12 2014-06-12 多層基板の製造方法及び多層基板
TW104115081A TW201603676A (zh) 2014-06-12 2015-05-12 多層基板之製造方法及多層基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/065608 WO2015189955A1 (fr) 2014-06-12 2014-06-12 Procédé de fabrication de carte de circuit imprimé multicouche et carte de circuit imprimé multicouche

Publications (1)

Publication Number Publication Date
WO2015189955A1 true WO2015189955A1 (fr) 2015-12-17

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PCT/JP2014/065608 Ceased WO2015189955A1 (fr) 2014-06-12 2014-06-12 Procédé de fabrication de carte de circuit imprimé multicouche et carte de circuit imprimé multicouche

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JP (1) JPWO2015189955A1 (fr)
TW (1) TW201603676A (fr)
WO (1) WO2015189955A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243147A (ja) * 1999-02-16 2000-09-08 Nec Corp 異方性導電フィルム、これを用いた半導体装置及びその製造方法
JP2003229509A (ja) * 2002-02-01 2003-08-15 Cmk Corp 多層プリント配線板
JP2003347727A (ja) * 2002-05-30 2003-12-05 Hitachi Ltd 配線基板および両面実装半導体製品
JP2008244325A (ja) * 2007-03-28 2008-10-09 Japan Gore Tex Inc プリント配線基板およびボールグリッドアレイパッケージ
WO2012046651A1 (fr) * 2010-10-04 2012-04-12 株式会社いおう化学研究所 Procédé de formation de couche métallique et produit doté d'une couche métallique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000243147A (ja) * 1999-02-16 2000-09-08 Nec Corp 異方性導電フィルム、これを用いた半導体装置及びその製造方法
JP2003229509A (ja) * 2002-02-01 2003-08-15 Cmk Corp 多層プリント配線板
JP2003347727A (ja) * 2002-05-30 2003-12-05 Hitachi Ltd 配線基板および両面実装半導体製品
JP2008244325A (ja) * 2007-03-28 2008-10-09 Japan Gore Tex Inc プリント配線基板およびボールグリッドアレイパッケージ
WO2012046651A1 (fr) * 2010-10-04 2012-04-12 株式会社いおう化学研究所 Procédé de formation de couche métallique et produit doté d'une couche métallique

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Publication number Publication date
JPWO2015189955A1 (ja) 2017-04-20
TW201603676A (zh) 2016-01-16

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