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WO2015189878A1 - Cellule solaire et son procédé de fabrication - Google Patents

Cellule solaire et son procédé de fabrication Download PDF

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Publication number
WO2015189878A1
WO2015189878A1 PCT/JP2014/003159 JP2014003159W WO2015189878A1 WO 2015189878 A1 WO2015189878 A1 WO 2015189878A1 JP 2014003159 W JP2014003159 W JP 2014003159W WO 2015189878 A1 WO2015189878 A1 WO 2015189878A1
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WIPO (PCT)
Prior art keywords
semiconductor layer
amorphous semiconductor
electrode
layer
amorphous
Prior art date
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Ceased
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PCT/JP2014/003159
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English (en)
Japanese (ja)
Inventor
金子　哲也
宏 野毛
愛子 佐藤
公彦 斉藤
近藤　道雄
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National Institute of Advanced Industrial Science and Technology AIST
Fukushima University NUC
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National Institute of Advanced Industrial Science and Technology AIST
Fukushima University NUC
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Application filed by National Institute of Advanced Industrial Science and Technology AIST, Fukushima University NUC filed Critical National Institute of Advanced Industrial Science and Technology AIST
Priority to PCT/JP2014/003159 priority Critical patent/WO2015189878A1/fr
Priority to JP2016527498A priority patent/JPWO2015189878A1/ja
Publication of WO2015189878A1 publication Critical patent/WO2015189878A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar cell and a manufacturing method thereof. More specifically, the present invention relates to a solar cell having a back electrode type heterojunction structure and a manufacturing method thereof.
  • a solar cell having a heterojunction structure In a solar cell having a heterojunction structure, light is received from the main surface side of the n-type single crystal silicon substrate, and power is generated by generating excess carriers in the n-type single crystal silicon substrate. The electric power generated at this time can be taken out by the two electrodes which are electrically paired.
  • Japanese Patent Publication No. 2003-298078 discloses a solar cell having such a structure.
  • the documents ⁇ Meijun Lu, Ujjwal Das, Stuart Bowden, Steven Hegedus and RobertBirkmire, Opt'Optimization of interdigitated back contact silicon heterojunctionsolar cells: tailoring hetero-interface band structures while maintainingsurface passics , 326-338, 2011 discloses another example.
  • Japanese Patent Publication No. 2013-168605 discloses another example.
  • Japanese Patent Publication No. 2013-131586 discloses another example.
  • Japanese Patent Publication 2005-101151 discloses another example.
  • Another example is disclosed in International Patent Publication No. WO2010 / 113750.
  • Another example is disclosed in Japanese Patent Publication No. 2009-200267.
  • another example is disclosed in US Pat. No. US8525018.
  • the invention of the solar cell is disclosed below.
  • the solar cell A semiconductor substrate of one conductivity type having a light receiving surface and a back surface; An intrinsic first amorphous semiconductor layer disposed on the back surface of the semiconductor substrate and having a comb shape; A second amorphous semiconductor layer that is disposed on the first amorphous semiconductor layer and includes an impurity having a conductivity type different from that of the semiconductor substrate; A first electrode disposed on the entire surface of the second amorphous semiconductor layer; An intrinsic third amorphous semiconductor layer which is disposed on the back surface of the semiconductor substrate and has a comb shape which meshes with the first amorphous semiconductor layer and partially overlaps the first electrode in plan view; , A fourth amorphous semiconductor layer including an impurity disposed on the third amorphous semiconductor layer and including an impurity having the same conductivity type as the semiconductor substrate; And a second electrode disposed on the fourth amorphous semiconductor layer.
  • the manufacturing method of the solar cell is as follows: Forming an intrinsic first amorphous semiconductor layer on the back surface of the one-conductivity-type semiconductor substrate having a light-receiving surface; Forming a second amorphous semiconductor layer containing an impurity having a conductivity type different from that of the semiconductor substrate on the first amorphous semiconductor layer; Forming a first electrode on the second amorphous semiconductor layer; Etching the first amorphous semiconductor layer, the second amorphous semiconductor layer, and the first electrode into a comb shape on the back surface of the semiconductor substrate; Forming an intrinsic third amorphous semiconductor layer including the portion of the semiconductor substrate exposed by the etching on the back surface of the semiconductor substrate provided with the first electrode; Forming a fourth amorphous semiconductor layer containing an impurity having the same conductivity type as that of the semiconductor substrate on the third amorphous semiconductor layer; The third amorphous semiconductor layer and the fourth amorphous semiconductor layer are engaged
  • the first electrode is arranged on the entire surface of the second amorphous semiconductor layer, carriers can be efficiently taken out. improves.
  • a solar cell with high power generation efficiency can be easily manufactured with high accuracy.
  • FIG. 5 is composed of FIGS. 5A to 5J.
  • FIG. 5 is a schematic cross-sectional view showing the manufacturing method of the first embodiment of the solar cell.
  • FIG. 5A shows the state after the first electrode is formed.
  • FIG. 5B shows a state after the mask for etching the first electrode is formed.
  • FIG. 5C shows the state after the first electrode has been etched.
  • FIG. 5D shows the situation after the mask has been removed.
  • FIG. 5E shows a state after the fourth amorphous semiconductor layer is formed.
  • FIG. 5F shows a state after the mask for etching the fourth amorphous semiconductor layer is formed.
  • FIG. 5G shows a state after the fourth amorphous semiconductor layer is etched.
  • FIG. 5H shows the situation after the mask is removed.
  • FIG. 5I shows the state after the second electrode and the collector electrode are formed.
  • FIG. 5J shows the state after the antireflection layer is formed.
  • FIG. 6 is configured from FIGS. 6A to 6D.
  • FIG. 6 is a schematic cross-sectional view showing the manufacturing method of the second embodiment of the solar cell.
  • FIG. 6A shows the state after the first electrode has been etched.
  • FIG. 6B shows the state after the insulator layer 9 is formed.
  • FIG. 6C shows a state after the fourth amorphous semiconductor layer is etched.
  • FIG. 6D shows the state after the second electrode and the collector electrode are formed.
  • 1st Embodiment of a solar cell the relationship between the separation distance of an electrode and the conversion efficiency (relative value) of a solar cell when hole mobility (micro
  • Crystalline semiconductors include single crystal semiconductors and polycrystalline semiconductors.
  • Amorphous semiconductors include amorphous semiconductors and microcrystalline semiconductors.
  • An intrinsic amorphous semiconductor is an amorphous semiconductor that is not intentionally doped with impurities.
  • Intrinsic amorphous semiconductors include amorphous semiconductors containing impurities that are inherently contained in semiconductor raw materials or impurities that are naturally mixed in the manufacturing process.
  • the plan view means that the solar cell is viewed from the back side in a direction perpendicular to the surface of the semiconductor substrate unless otherwise specified.
  • FIG. 1 shows a first embodiment of a solar cell.
  • FIG. 2 shows a part of the back surface of the first embodiment of the solar cell. The reason why it is a part of the back surface is that a part of the comb shape is shown. Actually, the comb shape may have a larger number of comb teeth.
  • a direction S perpendicular to the substrate to be viewed in plan is indicated by an arrow.
  • the direction P in which light travels is indicated by a white arrow.
  • This solar cell is a solar cell having a back electrode type heterojunction structure.
  • the solar cell includes a semiconductor substrate 10, a first amorphous semiconductor layer 1, a second amorphous semiconductor layer 2, a first electrode 11, and a third amorphous semiconductor layer. 3, a fourth amorphous semiconductor layer 4, and a second electrode 12.
  • the semiconductor substrate 10 has a light receiving surface 10a and a back surface 10b.
  • the semiconductor substrate 10 is of one conductivity type.
  • the first amorphous semiconductor layer 1 is disposed on the back surface 10 b of the semiconductor substrate 10.
  • the first amorphous semiconductor layer 1 is an intrinsic amorphous semiconductor layer.
  • the first amorphous semiconductor layer 1 has a comb shape.
  • the second amorphous semiconductor layer 2 is disposed on the first amorphous semiconductor layer 1.
  • the second amorphous semiconductor layer 2 exhibits a conductivity type different from that of the semiconductor substrate 10.
  • the second amorphous semiconductor layer 2 is an amorphous semiconductor layer containing impurities.
  • the first electrode 11 is disposed on the entire surface of the second amorphous semiconductor layer 2.
  • the third amorphous semiconductor layer 3 is disposed on the back surface 10 b of the semiconductor substrate 10.
  • the third amorphous semiconductor layer 3 is an intrinsic amorphous semiconductor layer.
  • the third amorphous semiconductor layer 3 has a comb shape that meshes with the first amorphous semiconductor layer 1.
  • the third amorphous semiconductor layer 3 partially overlaps the first electrode 11 in plan view.
  • the fourth amorphous semiconductor layer 4 is disposed on the third amorphous semiconductor layer 3.
  • the fourth amorphous semiconductor layer 4 has the same conductivity type as that of the semiconductor substrate 10.
  • the fourth amorphous semiconductor layer 4 is an amorphous semiconductor layer containing impurities.
  • the second electrode 12 is disposed
  • the first collector electrode 5 is disposed on the first electrode 11.
  • a second collector electrode 6 is disposed on the second electrode 12.
  • the second electrode 12 is separated from the first electrode 11 in plan view.
  • the light receiving surface 10a is a surface that receives light.
  • the light receiving surface 10a is also called a light incident surface.
  • the light receiving surface 10a is defined as a main surface.
  • the back surface 10b is a surface opposite to the light receiving surface 10a.
  • the semiconductor substrate 10 is a thin-plate semiconductor substrate.
  • the semiconductor substrate 10 has a p-type or n-type conductivity type.
  • One conductivity type means either p or n.
  • the semiconductor substrate 10 is preferably n-type.
  • the semiconductor substrate 10 is made of crystalline silicon, a compound semiconductor, or other semiconductor material that can be formed into a plate shape. Examples of crystalline silicon include single crystal silicon and polycrystalline silicon. Examples of the compound semiconductor include GaAs and InP.
  • As the semiconductor substrate 10, an n-type single crystal silicon substrate is preferably used.
  • the thickness of the semiconductor substrate 10 is not particularly limited.
  • the thickness of the semiconductor substrate 10 is preferably 10 to 200 ⁇ m from the viewpoint of member cost and handling.
  • the semiconductor substrate 10 preferably has a texture structure on one or both sides of the semiconductor substrate 10 from the viewpoint of improving efficiency. Since the texture structure can sufficiently confine incident light, an improvement in efficiency can be expected.
  • the texture structure may be a minute uneven structure, for example.
  • the minute uneven structure may have periodicity.
  • the texture structure is not essential.
  • an intrinsic semiconductor corresponds to i-type.
  • the semiconductor containing impurities may be n-type or p-type.
  • n-type semiconductor substrate 10 a p-type semiconductor substrate 10 may be used, and in that case, the structure can be understood if n-type and p-type are interchanged in the following description.
  • the first amorphous semiconductor layer 1 is an i-type amorphous semiconductor layer.
  • the first amorphous semiconductor layer 1 has a comb shape in plan view.
  • the second amorphous semiconductor layer 2 is a p-type amorphous semiconductor layer.
  • the second amorphous semiconductor layer 2 has a comb shape in plan view.
  • the comb shape of the first amorphous semiconductor layer 1 and the comb shape of the second amorphous semiconductor layer 2 may coincide with each other.
  • the first electrode 11 is a p-type electrode.
  • the first electrode 11 constitutes a back electrode.
  • the first electrode 11 has a comb shape in plan view.
  • the comb shape of the second amorphous semiconductor layer 2 and the comb shape of the first electrode 11 may coincide with each other. That is, the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2, and the first electrode 11 can have the same comb shape.
  • the second amorphous semiconductor layer 2 is disposed on the entire surface of the first amorphous semiconductor layer 1. It can be said that the second amorphous semiconductor layer 2 covers the first amorphous semiconductor layer 1.
  • the first electrode 11 is disposed on the entire surface of the second amorphous semiconductor layer 2. It can be said that the first electrode 11 covers the second amorphous semiconductor layer 2.
  • the first electrode 11, the first amorphous semiconductor layer 1, and the second amorphous semiconductor layer 2 are aligned at the ends.
  • the first amorphous semiconductor layer 1 and the second amorphous semiconductor layer 2 do not protrude from the first electrode 11. Therefore, the contact area between the first electrode 11 and the second amorphous semiconductor layer 2 becomes larger.
  • holes that are minority carriers generated in the semiconductor substrate 10 can be efficiently extracted to the outside. . Thereby, the power generation efficiency is improved.
  • the third amorphous semiconductor layer 3 is an i-type amorphous semiconductor layer.
  • the third amorphous semiconductor layer 3 has a comb shape in plan view.
  • the fourth amorphous semiconductor layer 4 is an n-type amorphous semiconductor layer.
  • the fourth amorphous semiconductor layer 4 has a comb shape in plan view.
  • the comb shape of the third amorphous semiconductor layer 3 and the comb shape of the fourth amorphous semiconductor layer 4 may be the same.
  • the second electrode 12 is an n-type electrode.
  • the second electrode 12 constitutes a back electrode.
  • the second electrode 12 has a comb shape in plan view.
  • the comb shape of the second electrode 12 may be a comb shape having a narrower width than the comb shape of the fourth amorphous semiconductor layer 4. That is, the width of the comb-shaped comb teeth of the second electrode 12 is smaller than the width of the comb-shaped comb teeth of the third amorphous semiconductor layer 3 and the fourth a
  • the fourth amorphous semiconductor layer 4 is disposed on the entire surface of the third amorphous semiconductor layer 3. It can be said that the fourth amorphous semiconductor layer 4 covers the third amorphous semiconductor layer 3.
  • the third amorphous semiconductor layer 3 is placed on the first electrode 11.
  • the third amorphous semiconductor layer 3 and the first electrode 11 are in contact with each other.
  • the third amorphous semiconductor layer 3 is arranged so as to bridge adjacent comb teeth of the first electrode 11.
  • the fourth amorphous semiconductor layer 4 is placed on the first electrode 11 following the shape of the third amorphous semiconductor layer 3.
  • the fourth amorphous semiconductor layer 4 is arranged so as to bridge adjacent comb teeth of the first electrode 11.
  • the ends of the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4 are aligned.
  • the fourth amorphous semiconductor layer 4 has a flat portion 4a.
  • the flat portion 4 a is a flat portion of the fourth amorphous semiconductor layer 4 that is not placed on the first electrode 11.
  • the flat portion 4 a may be a portion where the surface of the fourth amorphous semiconductor layer 4 is formed in parallel with the surface of the semiconductor substrate 10. In the flat portion 4 a, there is no deformation of the fourth amorphous semiconductor layer 4 to be placed on the first electrode 11.
  • the second electrode 12 is preferably disposed on the flat portion 4a.
  • the second electrode 12 is preferably arranged so as not to protrude from the flat portion 4a.
  • the second electrode 12 does not have to be formed in a portion where the fourth amorphous semiconductor layer 4 is placed on the first electrode 11.
  • the first collector electrode 5 is disposed on the first electrode 11. Thereby, it becomes easy to take out an electric current.
  • the first collector electrode 5 is disposed on a portion of the first electrode 11 that is not covered with the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4.
  • the edge of the first collector electrode 5 is located inside the edge of the first electrode 11.
  • the first collector electrode 5 is not in contact with the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4. Thereby, the occurrence of leakage current is suppressed.
  • the first collector electrode 5 may have a comb shape.
  • the first collector electrode 5 can be configured as a p-type collector electrode.
  • the second collector electrode 6 is disposed on the second electrode 12. Thereby, it becomes easy to take out an electric current.
  • the second collector electrode 6 is preferably disposed on the entire surface of the second electrode 12.
  • the second collector electrode 6 may have a comb shape.
  • the comb shape of the second electrode 12 and the comb shape of the second collector electrode 6 may be the same shape.
  • the second collector electrode 6 can be configured as an n-type collector electrode.
  • the first electrode 11 and the first collector electrode 5 on the p-type second amorphous semiconductor layer 2 constitute a positive electrode.
  • the second electrode 12 and the second collector electrode 6 on the n-type fourth amorphous semiconductor layer 4 constitute a negative electrode.
  • the first amorphous semiconductor layer 1 and the third amorphous semiconductor layer 3 have a comb shape that meshes with each other.
  • the second amorphous semiconductor layer 2 and the fourth amorphous semiconductor layer 4 have a comb shape that meshes with each other.
  • the first electrode 11 and the second electrode 12 have a comb shape that meshes with each other.
  • the first collector electrode 5 and the second collector electrode 6 have a comb shape that meshes with each other.
  • a combination of the second amorphous semiconductor layer 2 and the first electrode 11 is defined as a p-type structure
  • the p-type structure and the n-type structure have a comb shape that meshes with each other.
  • the comb shape is a shape having a plurality of comb teeth extending linearly and a base portion connected to the plurality of comb teeth.
  • the interdigitated comb shape is a shape in which two comb-shaped comb teeth are arranged between one comb-shaped comb teeth. This shape may be a shape in which one comb-shaped comb tooth and the other comb-shaped comb tooth are alternately arranged.
  • the two comb-shaped bases can be arranged on opposite sides of each other.
  • a part of the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4 are part of the first amorphous semiconductor layer when viewed in plan.
  • the first amorphous semiconductor layer 2 and the first electrode 11 are overlapped. Therefore, there is no portion where the back surface 10b of the semiconductor substrate is directly exposed, and the surface recombination of carriers can be suppressed to improve efficiency.
  • FIG. 2 shows the comb shape.
  • FIG. 2 shows a comb shape in which the first collector electrode 5 and the second collector electrode 6 are engaged with each other.
  • the comb shape of the first collector electrode 5 includes a base portion 5B and a plurality of comb teeth 5A.
  • the comb shape of the second collector electrode 6 includes a base portion 6B and a plurality of comb teeth 6A.
  • Other layers of the comb shape will also be understood from this figure.
  • the interdigitated comb shapes partially overlap each other. Since the p-type amorphous semiconductor and the corresponding electrode, and the n-type amorphous semiconductor and the corresponding electrode are in a comb shape, the carriers generated by light reception are efficiently extracted to the outside. be able to.
  • the width of the comb teeth of the second amorphous semiconductor layer 2 is preferably larger than the width of the comb teeth of the fourth amorphous semiconductor layer 4. Thereby, minority carriers can be efficiently taken out over a wide area. Since the second amorphous semiconductor layer 2 has a conductivity type different from that of the semiconductor substrate 10, the efficiency is increased by increasing the area of the second amorphous semiconductor layer 2.
  • the second amorphous semiconductor layer 2 becomes n-type when the n-type semiconductor substrate 10 is used, and becomes p-type when the p-type semiconductor substrate 10 is used.
  • the width of the comb teeth is a length in a direction perpendicular to the direction in which the comb teeth extend. In FIG.
  • the width W5 of the comb teeth 5A of the first collector electrode 5 and the width W6 of the comb teeth 6A of the second collector electrode 6 are shown. 1 and 2, each layer (first electrode 11, second electrode 12, first amorphous semiconductor layer 1, second amorphous semiconductor layer 2, third amorphous system).
  • the width of the comb teeth of the semiconductor layer 3 and the fourth amorphous semiconductor layer 4) will be understood.
  • the width of the comb teeth of the second amorphous semiconductor layer 2 is preferably 1.2 times or more, more preferably 2 times or more than the width of the comb teeth of the fourth amorphous semiconductor layer 4. The above is more preferable.
  • the width of the comb teeth of the first electrode 11 is preferably larger than the width of the comb teeth of the second electrode 12.
  • the width of the comb teeth of the first collector electrode 5 is preferably larger than the width of the comb teeth of the second collector electrode 6.
  • FIG. 2 shows a relationship in which the width W5 of the comb teeth 5A of the first collector electrode 5 is larger than the width W6 of the comb teeth 6A of the second collector electrode 6.
  • the width of the comb teeth of the first electrode 11 is not particularly limited, but may be in the range of 100 to 5000 ⁇ m, for example.
  • the width of the comb teeth of the second electrode 12 is not particularly limited, but may be in the range of 10 to 1000 ⁇ m, for example.
  • the first electrode 11 and the second electrode 12 are separated from each other in plan view. That is, the first electrode 11 and the second electrode 12 do not overlap in plan view. It can be said that the comb teeth of the second electrode 12 are accommodated between the comb teeth of the first electrode 11.
  • the distance at which the first electrode 11 and the second electrode 12 are separated is indicated by a separation distance D.
  • the separation distance D is preferably larger than the total thickness of the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4. Thereby, the leak current is easily reduced.
  • the separation distance D between the first electrode 11 and the second electrode 12 is preferably 10 ⁇ m or more and 100 ⁇ m or less.
  • the separation distance D is 100 ⁇ m or less, the series resistance with respect to the majority carriers decreases, and thus the efficiency is further improved. Further, when the separation distance D is 10 ⁇ m or more, the leakage current between the electrodes is easily reduced.
  • Each amorphous semiconductor layer (first to fourth amorphous semiconductor layers) is preferably composed of a hydrogenated amorphous semiconductor containing silicon. This is common to all of i-type, p-type and n-type.
  • the amorphous semiconductor include amorphous silicon, amorphous silicon carbide, and amorphous silicon germanium.
  • the amorphous semiconductor layer is not limited to these materials, and may be composed of other amorphous semiconductors.
  • the amorphous semiconductor layer may be composed of other thin film semiconductors.
  • impurities in the p-type amorphous semiconductor layer examples include B (boron), Al, and Ga (gallium). This impurity is preferably a group III element. B (boron) is preferably used as the impurity.
  • impurities in the n-type amorphous semiconductor layer include P (phosphorus), As (arsenic), and Sb (antimony). This impurity is preferably a group V element. P (phosphorus) is preferably used as the impurity.
  • the first electrode 11 may be a transparent electrode.
  • the second electrode 12 may be a transparent electrode. These electrodes can be formed of, for example, a transparent metal oxide.
  • the first electrode 11 and the second electrode 12 can be made of, for example, ITO (indium tin oxide), SnO 2 (tin oxide), or ZnO (zinc oxide).
  • the first electrode 11 and the second electrode 12 may be formed of the same material or may be formed of different materials.
  • the first collector electrode 5 and the second collector electrode 6 may be made of metal.
  • the first collector electrode 5 and the second collector electrode 6 can be made of, for example, Ag (silver), Al (aluminum), Cu (copper), or Au (gold).
  • the first collector electrode 5 and the second collector electrode 6 are preferably made of Ag.
  • the first collector electrode 5 and the second collector electrode 6 may be formed of the same material or different materials.
  • the second electrode 12 may be made of metal. In that case, the second electrode 12 may have the function of a collecting electrode, and the second collecting electrode 6 may be omitted. Thereby, the layer structure becomes easier.
  • each amorphous semiconductor layer (first to fourth amorphous semiconductor layers) is not particularly limited, but may be in the range of 1 to 50 nm, for example.
  • the thickness of these amorphous semiconductor layers is about 10 nm.
  • the thicknesses of the first electrode 11 and the second electrode 12 are not particularly limited, but may be in the range of 10 to 200 nm, for example.
  • the thickness of these electrodes is about 70 nm.
  • the thickness of the first collector electrode 5 and the second collector electrode 6 is not particularly limited, but may be in the range of 100 to 1000 nm, for example.
  • the thickness of these collector electrodes is about 200 nm.
  • an intrinsic amorphous semiconductor layer 7 is preferably disposed on the light receiving surface 10 a (main surface) of the semiconductor substrate 10. Thereby, carrier recombination on the main surface side surface is suppressed, and the efficiency of power generation is improved.
  • the amorphous semiconductor layer 7 may be an i-type amorphous semiconductor layer.
  • the amorphous semiconductor layer 7 is defined as a main surface amorphous semiconductor layer.
  • the amorphous semiconductor layer 7 is preferably disposed on the entire main surface of the semiconductor substrate 10.
  • the amorphous semiconductor layer 7 functions as a passivation film.
  • the amorphous semiconductor layer 7 is preferably composed of a hydrogenated amorphous semiconductor containing silicon.
  • amorphous semiconductor examples include amorphous silicon, amorphous silicon carbide, amorphous silicon oxide, and amorphous silicon nitride.
  • the thickness of the amorphous semiconductor layer 7 is not particularly limited, but may be in the range of 1 to 50 nm, for example.
  • the thickness of the amorphous semiconductor layer 7 is about 10 nm.
  • An antireflection layer 8 is preferably disposed on the amorphous semiconductor layer 7. Thereby, reflection of light is suppressed and light becomes easy to enter.
  • the amorphous semiconductor layer 7 is preferably formed of a material that absorbs little incident light.
  • the antireflection layer 8 can be formed of, for example, silicon nitride.
  • the thickness of the antireflection layer 8 is not particularly limited, but may be, for example, in the range of 30 to 2000 nm. For example, the thickness of the antireflection layer 8 is about 70 nm.
  • a single layer having the functions of the amorphous semiconductor layer 7 and the antireflection layer 8 may be disposed on the light receiving surface 10 a of the semiconductor substrate 10.
  • silicon nitride or aluminum nitride can have such a function.
  • an additional layer may be provided between the amorphous semiconductor layer 7 and the antireflection layer 8.
  • the additional layer may be composed of, for example, an amorphous semiconductor layer doped with impurities forming the surface electric field layer, or a dielectric layer having a fixed charge.
  • the solar cell described above efficiently takes out minority carriers generated in the semiconductor substrate 10 by disposing the first electrode 11 over the entire surface of the second comb-shaped amorphous semiconductor layer 2. be able to.
  • the electrode can be formed with the maximum area allowed by the processing accuracy. Then, the influence of series resistance due to in-plane conduction in the amorphous semiconductor layer is reduced. Therefore, the conversion efficiency of the solar cell is improved.
  • FIG. 3 shows a second embodiment of the solar cell.
  • FIG. 4 shows a part of the back surface of the second embodiment of the solar cell. The reason why it is a part of the back surface is that a part of the comb shape is shown. Actually, the comb shape may have a larger number of comb teeth.
  • a direction S perpendicular to the substrate to be viewed in plan is indicated by an arrow.
  • the direction P in which light travels is indicated by a white arrow.
  • the edge part 11a of the 1st electrode 11 is shown with the dashed-two dotted line.
  • the region where the insulator layer 9 is disposed is indicated by hatching.
  • the edge of the insulator layer 9 closer to the second electrode 12 is indicated by a broken line.
  • the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
  • the second embodiment includes an insulator layer 9 disposed between the first electrode 11 and the third amorphous semiconductor layer 3. This point is different from the first embodiment. Other configurations may be the same as those of the first embodiment.
  • the insulator layer 9 has a function of electrically insulating the layers.
  • the insulator layer 9 suppresses contact between the first electrode 11 and the third amorphous semiconductor layer 3.
  • the insulator layer 9 straddles the edge 11 a of the first electrode 11.
  • the insulator layer 9 is disposed on the back surface 10 b of the semiconductor substrate 10 and is placed on the first electrode 11.
  • the insulator layer 9 is in contact with the semiconductor substrate 10.
  • the insulator layer 9 is in contact with the first electrode 11.
  • the insulator layer 9 covers the end portion of the first electrode 11.
  • the insulator layer 9 covers the side surface of the second amorphous semiconductor layer 2.
  • the insulator layer 9 covers the side surface of the first amorphous semiconductor layer 1.
  • the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2, and the first electrode 11 are connected to the third amorphous semiconductor layer 3 and the fourth non-crystalline semiconductor layer 3. It is electrically insulated from the crystalline semiconductor layer 4.
  • one edge of the insulator layer 9 is drawn so as to coincide with the edge of the third amorphous semiconductor layer 3 and the edge of the fourth amorphous semiconductor layer 4.
  • the edges do not necessarily coincide with each other, and the edge of the third amorphous semiconductor layer 3 and the edge of the fourth amorphous semiconductor layer 4 exist on the insulator layer 9. If you do.
  • the presence of the insulator layer 9 reduces the leakage current between the electrodes. Insulator layer 9 facilitates electrical separation between the p-side electrode and the n-side electrode, so that the leakage current between the electrodes becomes very small. Therefore, the power generation efficiency is improved, and a solar cell with good characteristics can be obtained.
  • the insulator layer 9 has a meandering shape in plan view. Since the insulator layer 9 is disposed along the shape of the edge of the comb teeth of the first electrode 11, it has a meandering shape.
  • the insulator layer 9 can be formed of an insulating material.
  • the insulating material may be an inorganic material or an organic material. Examples of the material for the insulator layer 9 include silica, silicon nitride, alumina, and polyimide.
  • the insulator layer 9 may be transparent, translucent, or opaque.
  • the thickness of the insulator layer 9 is not particularly limited, but may be in the range of 5 to 200 nm, for example. The thickness of the insulator layer 9 is, for example, about 70 nm.
  • the separation distance D may be less than 10 ⁇ m.
  • the second electrode 12 may be provided at a portion where the fourth amorphous semiconductor layer 4 is raised because the fourth amorphous semiconductor layer 4 is placed on the first electrode 11.
  • the first electrode 11 and the second electrode 12 may overlap with each other in plan view, and the separation distance D may be eliminated.
  • the separation distance D is preferably 1 ⁇ m or more and 100 ⁇ m or less.
  • FIG. 5 is a cross-sectional view showing an example of the method for manufacturing the solar cell of the first embodiment.
  • FIG. 5 is composed of FIGS. 5A to 5J.
  • the method for manufacturing a solar cell includes the following steps: Forming the first amorphous semiconductor layer 1; Forming the second amorphous semiconductor layer 2; Forming the first electrode 11; Etching the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2 and the first electrode 11 into a comb shape; Forming a third amorphous semiconductor layer 3; Forming a fourth amorphous semiconductor layer 4; Etching the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4 into a comb shape; Forming the second electrode 12;
  • the semiconductor substrate 10 is prepared.
  • An example of the semiconductor substrate 10 is an n-type single crystal silicon substrate.
  • the semiconductor substrate 10 is cleaned, transported into a vacuum chamber, and heated. As a result, moisture adhering to the surface of the substrate is removed.
  • an n-type semiconductor substrate is used will be described. However, if a p-type semiconductor substrate is used, the n-type and p-type of each material may be interchanged.
  • SiH 4 (silane) gas is introduced into the vacuum chamber, and the first amorphous semiconductor layer 1 is formed on the back surface 10b (surface opposite to the light receiving surface 10a) of the semiconductor substrate 10 by PECVD.
  • This is a step of forming the first amorphous semiconductor layer 1.
  • the first amorphous semiconductor layer 1 can be formed of i-type amorphous silicon.
  • the first amorphous semiconductor layer 1 does not contain impurities.
  • the first amorphous semiconductor layer 1 is intrinsic.
  • SiH 4 gas, H 2 (hydrogen) gas and B 2 H 6 (diborane) gas are introduced into the vacuum chamber, and the second amorphous semiconductor layer 1 is formed on the first amorphous semiconductor layer 1 by PECVD.
  • An amorphous semiconductor layer 2 is formed. This is a step of forming the second amorphous semiconductor layer 2.
  • the second amorphous semiconductor layer 2 can be formed of p-type amorphous silicon.
  • the second amorphous semiconductor layer 2 contains impurities. Impurities are doped.
  • the first electrode 11 is formed by sputtering, MOCVD (metal organic chemical vapor deposition), or printing. This is a step of forming the first electrode 11.
  • the first electrode 11 can be formed of, for example, ITO or ZnO.
  • FIG. 5A shows a state after the first electrode 11 is formed.
  • the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2 and the first electrode 11 are not patterned on the semiconductor substrate 10, It is provided in layers.
  • an etching resist material is applied in a comb shape on the first electrode 11, and the etching resist material is solidified.
  • an etching resist material a photoresist, pigment ink, polyimide, or the like may be used as long as it is a material that can be printed with high accuracy, has etching resistance, is easily peeled off after etching, and has little contamination.
  • the etching resist material can be applied by a printing method. Examples of the printing method include an inkjet printing method and a screen printing method. An etching resist layer 21 is formed from the etching resist material. Then, as shown in FIG.
  • the semiconductor substrate 10 on which the etching resist layer 21 is formed is immersed in an etching solution, and the first electrode 11, the second amorphous semiconductor layer 2, and the first amorphous semiconductor layer 10 are immersed.
  • the portion of the quality semiconductor layer 1 that is not covered with the etching resist layer 21 is removed.
  • This etching is wet etching.
  • As the etching solution for example, a mixed solution of an NH 4 F (ammonium fluoride) aqueous solution and an H 2 O 2 (hydrogen peroxide) aqueous solution is used. Etching may be performed by dry etching.
  • dry etching examples include reactive ion etching using SF 6 (sulfur hexafluoride), NF 3 (nitrogen trifluoride), CF 4 (carbon tetrafluoride), and the like.
  • the etching resist layer 21 is removed with a resist removing material.
  • the resist removing material for example, acetone is used. Accordingly, the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2, and the first electrode 11 are patterned into a comb shape. A series of these steps is a step of etching the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2, and the first electrode 11 into a comb shape.
  • the third amorphous-based semiconductor layer 3 Form.
  • the third amorphous semiconductor layer 3 can be formed of i-type amorphous silicon.
  • the third amorphous semiconductor layer 3 does not contain impurities.
  • the third amorphous semiconductor layer 3 is intrinsic.
  • the third amorphous semiconductor layer 3 is laminated so as to include a portion between the comb teeth from which the first electrode 11 is separated.
  • the fourth amorphous semiconductor layer 4 is formed by PECVD. This is a step of forming the fourth amorphous semiconductor layer 4.
  • the fourth amorphous semiconductor layer 4 can be formed of n-type amorphous silicon.
  • the fourth amorphous semiconductor layer 4 contains impurities. Impurities are doped.
  • the fourth amorphous semiconductor layer 4 is laminated so as to include a portion between the comb teeth from which the first electrode 11 is separated.
  • FIG. 5E shows a state after the fourth amorphous semiconductor layer 4 is formed.
  • the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4 are provided in layers on the back side of the semiconductor substrate 10 without being patterned. It has been.
  • an etching resist material is applied in a comb shape on the fourth amorphous semiconductor layer 4 to solidify the etching resist material.
  • an etching resist material a photoresist, pigment ink, polyimide, or the like may be used as long as it is a material that can be printed with high accuracy, has etching resistance, is easily peeled off after etching, and has little contamination.
  • the etching resist material can be applied by a printing method. Examples of the printing method include an inkjet printing method and a screen printing method. An etching resist layer 22 is formed from the etching resist material. Then, as shown in FIG.
  • the semiconductor substrate 10 on which the etching resist layer 22 is formed is immersed in an etching solution, and the fourth amorphous semiconductor layer 4 and the third amorphous semiconductor layer 3 are formed. Then, the portion not covered with the etching resist layer 22 is removed.
  • This etching is wet etching.
  • the etching solution for example, a mixed solution of an HF (hydrofluoric acid) aqueous solution and an H 2 O 2 (hydrogen peroxide) aqueous solution is used. Etching may be performed by dry etching.
  • dry etching examples include reactive ion etching using SF 6 (sulfur hexafluoride), NF 3 (nitrogen trifluoride), CF 4 (carbon tetrafluoride), and the like. Etching is performed so as not to etch the first electrode 11 and the layer closer to the semiconductor substrate 10 than the first electrode 11. As a result, the first electrode 11 is exposed. Thereafter, as shown in FIG. 5H, the etching resist layer 22 is removed by a resist removing material. As the resist removing material, for example, acetone is used. As a result, the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4 are patterned into a comb shape. A series of these steps is a step of etching the third amorphous semiconductor layer 3 and the fourth amorphous semiconductor layer 4 into a comb shape.
  • the second electrode 12 is formed in a pattern on the fourth amorphous semiconductor layer 4. This is a step of forming the second electrode 12.
  • the second electrode 12 is formed in a comb-shaped pattern.
  • the second electrode 12 can be formed by applying an ink containing an electrode material by a printing method and performing a heat treatment. Examples of the printing method include an inkjet printing method and a screen printing method.
  • the second electrode 12 is formed apart from the first electrode 11.
  • the second electrode 12 can be formed on the flat portion 4 a of the fourth amorphous semiconductor layer 4.
  • the distance D between the second electrode 12 and the first electrode 11 is preferably 10 ⁇ m or more in order to suppress a short circuit between the electrodes and a leakage current.
  • the separation distance D is preferably 100 ⁇ m or less in order to reduce the direct resistance of majority carriers to electrons.
  • the first collector electrode 5 and the second collector electrode 6 are formed in a comb shape.
  • the first collector electrode 5 is formed on the first electrode 11.
  • the second collector electrode 6 is formed on the second electrode 12.
  • the first collector electrode 5 and the second collector electrode 6 are formed in a comb-shaped pattern that meshes with each other.
  • the first collector electrode 5 and the second collector electrode 6 can be formed by applying a metal material by a printing method. Examples of the printing method include an inkjet printing method and a screen printing method.
  • the first collector electrode 5 and the second collector electrode 6 are made of, for example, Ag (silver).
  • the first collector electrode 5 and the second collector electrode 6 are preferably formed simultaneously. Thereby, the manufacturing process is simplified.
  • FIG. 5I shows the state after the collector electrode is formed.
  • the second electrode 12, the first collector electrode 5, and the second collector electrode 6 may be formed by patterning other than the printing method. For example, they can be patterned and formed by a sputtering film forming method using a mask. Alternatively, for example, after a layer is formed on one surface, an etching resist material may be formed in a patterned meandering shape, and may be patterned in a comb shape by wet etching.
  • the second electrode 12 is made of the material of the second collector electrode 6 described above. May be formed. In that case, the second electrode 12 can be formed on the fourth amorphous semiconductor layer 4 when the first collector electrode 5 is formed. At this time, the second collector electrode 6 may be omitted.
  • This structure may be a structure in which the second electrode 12 also has the second collector electrode 6.
  • the light receiving surface 10a (main surface) of the semiconductor substrate 10 is cleaned, the semiconductor substrate 10 is placed in a vacuum chamber, SiH 4 gas is introduced into the vacuum chamber, and the light receiving surface is formed by PECVD.
  • An amorphous semiconductor layer 7 is formed on 10a.
  • the amorphous semiconductor layer 7 can be formed of i-type amorphous silicon.
  • the antireflection layer 8 is formed on the amorphous semiconductor layer 7 by sputtering, for example.
  • the amorphous semiconductor layer 7 and the antireflection layer 8 are appropriately formed before the formation of the first amorphous semiconductor layer 1 or after the formation of the second electrode 12 and before the formation of the collector electrode. May be formed.
  • the patterning of the amorphous semiconductor layer is performed by etching. Therefore, impurity contamination from the mask is prevented as in the case of patterning the amorphous semiconductor layer using a mask when forming the amorphous semiconductor layer. Thereby, deterioration of the solar cell characteristics is prevented.
  • the n-type structure and the p-type structure can be arranged with high accuracy so as not to have an excessive gap while maintaining electrical isolation in a comb shape that is engaged with each other.
  • the manufacturing process is simplified and the yield is improved, so that the manufacturing cost can be reduced compared to the photolithography method, for example.
  • FIG. 6 is a cross-sectional view showing an example of a method for manufacturing the solar cell of the second embodiment.
  • FIG. 6 is configured from FIGS. 6A to 6D. The figure common to FIG. 5 and the figure understandable from FIG. 5 are omitted.
  • the method for manufacturing a solar cell according to the second embodiment includes a step of forming the insulator layer 9. Other than that may be the same as the manufacturing method of the solar cell of the first embodiment.
  • the step of forming the insulator layer 9 is performed after the step of etching the first amorphous semiconductor layer 1, the second amorphous semiconductor layer 2, and the first electrode 11.
  • FIG. 6A corresponds to FIG. 5D.
  • the insulator layer 9 is formed at the end portion of the first electrode 11 as shown in FIG. 6B.
  • the insulator layer 9 is formed so as to straddle the boundary between the first electrode 11 and the portion of the semiconductor substrate 10 exposed by etching.
  • the insulator layer 9 has a meandering shape along the comb-teeth edge 11 a of the first electrode 11.
  • the insulator layer 9 can be formed by a printing method.
  • the insulator layer 9 By forming the insulator layer 9 by a printing method, unlike a normal sputtering method or PECVD method, the physical impact can be reduced and formed at a low temperature, so that an amorphous semiconductor layer (amorphous silicon layer) is formed. Damage and modification are suppressed, and the solar cell efficiency is improved.
  • the insulator layer 9 is formed by applying the material of the insulator layer 9 in a pattern by a printing method and heating. The heating is preferably performed at a temperature of 200 ° C. or lower. Firing is performed by heating.
  • the printing method include an inkjet printing method and a screen printing method. Further, a patterning method other than the printing method may be employed.
  • the insulator layer 9 can be formed by patterning by a sputtering film forming method using a mask.
  • the insulating layer 9 may be patterned by wet etching after an etching resist material is formed in a patterned meandering shape after a layer is formed on one surface.
  • the solar cell shown in FIG. 3 is obtained.
  • the semiconductor substrate 10 was an n-type single crystal silicon substrate.
  • the amorphous semiconductor layers (on the first to fourth and main surfaces) were all amorphous silicon layers.
  • the first amorphous semiconductor layer 1 and the third amorphous semiconductor layer 3 (i-type amorphous silicon layer) have a thickness of 5 nm and an electron concentration of 1 ⁇ 10 15 cm ⁇ 3 . .
  • the second amorphous semiconductor layer 2 (p-type amorphous silicon layer) had a thickness of 5 nm, a comb tooth width of 1.5 mm, and a carrier concentration of 5 ⁇ 10 18 cm ⁇ 3 .
  • the fourth amorphous semiconductor layer 4 (n-type amorphous silicon layer) had a thickness of 5 nm and a carrier concentration of 8 ⁇ 10 18 cm ⁇ 3 .
  • the amorphous semiconductor layer 7 (i-type amorphous silicon layer) on the light receiving surface had a thickness of 5 nm and an electron concentration of 1 ⁇ 10 15 cm ⁇ 3 .
  • the width of the portion where the second amorphous semiconductor layer 2 and the fourth amorphous semiconductor layer 4 overlap in a plan view is 20 ⁇ m. This width is equal to the width at which the first electrode 11 and the third amorphous semiconductor layer 3 are in contact.
  • the width of the second electrode 12 was 200 ⁇ m.
  • the mobility of electrons in the n-type amorphous silicon layer was 5 cm 2 / Vs.
  • the hole mobility of the p-type amorphous silicon layer was duplicate of 0.3 cm 2 / Vs and 0.0001 cm 2 / Vs. The reason for the two types is that the mobility of holes cannot be accurately determined.
  • the semiconductor substrate 10 n-type single crystal silicon substrate
  • FIG. 7 shows the distance between the first electrode 11 and the second electrode 12 (electrode separation distance D) and the sun in the hole mobility ( ⁇ p) in two types of p-type amorphous silicon layers. It is a graph which shows the relationship with the relative conversion efficiency of a battery. The graph is normalized with respect to the maximum value.
  • the electrode separation distance is 10 ⁇ m, the conversion efficiency is maximum, and the hole mobility ( ⁇ p) is 0.
  • the electrode separation distance is 20 ⁇ m, and the conversion efficiency is maximum. If the electrode separation distance is smaller than these maximum values, the conversion efficiency is considered to decrease because the leak current between the electrodes increases. Further, if the distance between the electrodes becomes too small, there is a possibility of short circuit. Taking into account variations in the processing accuracy of the electrodes, the electrode separation distance is preferably 10 ⁇ m or more. In the graph, the conversion efficiency gradually decreases as the electrode separation distance increases.
  • the electrode separation distance is preferably 100 ⁇ m or less.
  • Such a tendency is considered to be the same when the width, thickness, carrier concentration and the like of the amorphous silicon layer are changed. That is, when the distance between the electrodes is 10 ⁇ m or more and 100 ⁇ m or less, a solar cell with good characteristics with a small leakage current between the electrodes can be obtained.
  • Example 2 About the solar cell of 2nd Embodiment, the influence which insertion of the insulator layer 9 has on the characteristic of a solar cell was investigated by simulation of the computer. The calculation parameters and method were the same as in Example 1. The surface recombination velocity at the interface between the semiconductor substrate 10 and the insulator layer 9 was 10 cm / s.
  • the leakage current between the electrodes is reduced by inserting the insulator layer 9, the open-circuit voltage and the fill factor are improved, and the conversion efficiency is increased by about 5% compared to the case without the insulator layer 9. It has been shown. Further, when the width of the insulator layer 9 in contact with the semiconductor substrate 10 was changed from 10 ⁇ m to 100 ⁇ m, the conversion efficiency was reduced within 5%. Thus, the arrangement of the insulator layer 9 makes it possible to obtain a solar cell with good characteristics with a small leakage current between the electrodes.
  • the dimension of the insulator layer 9 is within the patterning accuracy that can be handled by the printing method. That is, these dimensions are within the processing accuracy that can be realized by a simple patterning method such as a printing method, and the manufacturing cost and the manufacturing time can be reduced.
  • Japanese Patent Publication No. 2013-168605 discloses a solar cell.
  • the p-type electrode is formed only on a part of the p-type amorphous silicon layer. Therefore, holes that are minority carriers in the semiconductor substrate cannot be efficiently extracted to the outside.
  • Japanese Patent Publication No. 2013-131586 discloses a solar cell.
  • the p-type electrode can be formed on the entire surface of the p-type amorphous semiconductor layer (amorphous silicon layer), holes that are minority carriers in the semiconductor substrate are efficiently used. It can be taken out well and efficiency is improved.
  • Japanese Patent Publication No. 2005-101151 discloses a solar cell.
  • a structure in which a p-type electrode is formed on one surface of a p-type amorphous silicon layer is disclosed as a second embodiment.
  • this solar cell does not have a comb shape in which the p-type silicon layer and the n-type silicon layer are engaged with each other, the p-type electrode is covered with the silicon layer, and the n-type electrode Is formed in a deformed portion of the silicon layer.
  • a leak current is likely to occur.
  • the solar cell of this indication can make it difficult to generate the leak current between electrodes compared with the structure of this literature.
  • Patent Cooperation Treaty International Publication No. WO 2010/113750 discloses solar cells. This solar cell has an insulator layer. However, even in this solar cell, the p-type electrode is formed only on a part of the p-type amorphous silicon layer. Therefore, holes that are minority carriers in the semiconductor substrate cannot be efficiently extracted to the outside. The same applies to Japanese Patent Publication No. 2009-200267.
  • US Patent US8525018 discloses a solar cell.
  • This solar cell has an insulator layer and a p-type electrode formed on one surface of a p-type amorphous silicon layer.
  • the insulator layer is also disposed between the p-type amorphous silicon layer and the semiconductor substrate, holes that are minority carriers cannot be taken out at this portion.
  • the insulator layer can have a structure that is not disposed between the p-type amorphous semiconductor layer (amorphous silicon layer) and the semiconductor substrate. Are efficiently extracted to the outside, and the efficiency is improved.

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  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne une cellule solaire. La cellule solaire comporte : un substrat semi-conducteur (10) ; une première couche de semi-conducteur amorphe intrinsèque (1) ; une deuxième couche de semi-conducteur amorphe (2) contenant une impureté ; une première électrode (11) qui est disposée sur la totalité d'une surface sur la deuxième couche de semi-conducteur amorphe (2) ; une troisième couche de semi-conducteur amorphe intrinsèque (3) ; une quatrième couche de semi-conducteur amorphe (4) contenant une impureté ; et une seconde électrode (12) qui est disposée sur la quatrième couche de semi-conducteur amorphe (4). La première couche de semi-conducteur amorphe (1) présente une forme de peigne. La troisième couche de semi-conducteur amorphe (3) présente une forme de peigne qui s'engage dans la première couche de semi-conducteur amorphe (1). Une partie de la troisième couche de semi-conducteur amorphe (3) chevauche la première électrode (11) dans une vue plane.
PCT/JP2014/003159 2014-06-13 2014-06-13 Cellule solaire et son procédé de fabrication Ceased WO2015189878A1 (fr)

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WO2018168180A1 (fr) * 2017-03-17 2018-09-20 株式会社カネカ Cellule solaire et son procédé de fabrication
JP2019079916A (ja) * 2017-10-24 2019-05-23 株式会社カネカ バックコンタクト型太陽電池モジュール
WO2021124991A1 (fr) * 2019-12-19 2021-06-24 株式会社カネカ Procédé de fabrication de cellule solaire
WO2024098920A1 (fr) * 2022-11-07 2024-05-16 隆基绿能科技股份有限公司 Cellule solaire à contact arrière, son procédé de fabrication et module photovoltaïque
AU2024205235A1 (en) * 2023-08-02 2025-02-20 Trina Solar Co., Ltd Back contact cell and solar cell module

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WO2018168180A1 (fr) * 2017-03-17 2018-09-20 株式会社カネカ Cellule solaire et son procédé de fabrication
JP2019079916A (ja) * 2017-10-24 2019-05-23 株式会社カネカ バックコンタクト型太陽電池モジュール
WO2021124991A1 (fr) * 2019-12-19 2021-06-24 株式会社カネカ Procédé de fabrication de cellule solaire
JPWO2021124991A1 (fr) * 2019-12-19 2021-06-24
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CN114830357B (zh) * 2019-12-19 2024-03-15 株式会社钟化 太阳能电池的制造方法
WO2024098920A1 (fr) * 2022-11-07 2024-05-16 隆基绿能科技股份有限公司 Cellule solaire à contact arrière, son procédé de fabrication et module photovoltaïque
AU2024205235A1 (en) * 2023-08-02 2025-02-20 Trina Solar Co., Ltd Back contact cell and solar cell module
AU2024205235B2 (en) * 2023-08-02 2025-04-10 Trina Solar Co., Ltd Back contact cell and solar cell module

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