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WO2015165226A1 - 显示基板的制造方法和显示基板 - Google Patents

显示基板的制造方法和显示基板 Download PDF

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Publication number
WO2015165226A1
WO2015165226A1 PCT/CN2014/089553 CN2014089553W WO2015165226A1 WO 2015165226 A1 WO2015165226 A1 WO 2015165226A1 CN 2014089553 W CN2014089553 W CN 2014089553W WO 2015165226 A1 WO2015165226 A1 WO 2015165226A1
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Prior art keywords
doped region
lightly doped
region
active layer
display substrate
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English (en)
French (fr)
Inventor
张家祥
姜晓辉
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method of manufacturing a display substrate and a display substrate.
  • LTPS Low temperature poly-silicon
  • PPI Pixels per inch
  • a lightly doped drain may be disposed on both sides of the gate between the source and drain patterns, and the function of the LDD is equivalent to a large resistance in series, thereby reducing leakage.
  • the current is formed, and the length of the LDD determines the magnitude of the leakage current.
  • FIG. 1a is a schematic view of manufacturing a display substrate in the prior art.
  • a first buffer layer 2, a second buffer layer 3, and an active source are sequentially formed on the substrate substrate 1.
  • a layer pattern and a first insulating layer 5 over the active layer pattern then forming a gate metal layer on the first insulating layer 5, performing photoresist coating, exposure, development, and etching on the gate metal layer to form The gate 6 and the remaining photoresist 14 over the gate 6. Since there is a lateral indentation amount when etching the gate metal layer, the width of the remaining photoresist 14 after the etching process is larger than the width of the gate electrode 6. Subsequently, the active layer pattern is heavily doped by the first insulating layer 5 with the gate electrode 6 and the remaining photoresist 14 located above the gate electrode 6 as a mask to form the heavily doped region 43 and the active layer region. 45.
  • FIG. 1b is another schematic diagram of manufacturing a display substrate in the prior art.
  • an ashing process is performed on the remaining photoresist 14, and a portion of the remaining photoresist 14 is removed to form a portion of the remaining photoresist.
  • the remaining photoresist 14 that is ashed may include a gate
  • the active layer region 45 is lightly doped through the first insulating layer 5 to form a lightly doped drain region 44, and the remaining active layer is not doped.
  • the area is a polysilicon region 42. Then, a portion of the remaining photoresist 15 is removed by a lift-off process, and a source-drain pattern and a pixel electrode are sequentially formed over the gate electrode 6, which are not specifically shown here.
  • the remaining photoresist 14 on both sides of the gate 6 corresponds to the lightly doped drain region 44, so the remaining photoresist 14 on both sides of the gate 6 needs to be removed by an ashing process.
  • the lightly doped drain region 44 can be formed by light doping treatment, that is, in the process of ashing the remaining photoresist 14, it is necessary to control the residual light in the ashing process according to the length of the lightly doped drain region 44.
  • the amount of gelatin 14 removed determines the length of the lightly doped drain region 44.
  • Embodiments of the present invention provide a method of manufacturing a display substrate and a display substrate for accurately controlling the length of the lightly doped region to improve the uniformity of the length of the lightly doped region and to improve the doping efficiency.
  • Embodiments of the present invention provide a method of manufacturing a display substrate, including the steps of: forming an active layer pattern over a substrate; forming a gate over the active layer pattern; and patterning the active layer Performing light doping to form a lightly doped region under both sides of the gate, the active layer pattern directly under the gate being doped is a polysilicon region; formed in the lightly doped region Re-doping the lightly doped region from the first via above the polysilicon region to form a heavily doped region, the lightly doped region between the heavily doped region and the polysilicon region a lightly doped drain region; a source drain pattern formed over the heavily doped region, the source drain pattern being coupled to the heavily doped region through the first via.
  • the step of lightly doping the active layer pattern to form the lightly doped region and the polysilicon region may include: lightly doping the active layer pattern to form the lightly doped region with the gate as a mask.
  • the step of lightly doping the active layer pattern to form the lightly doped region and the polysilicon region may include: lightly doping the active layer pattern with a mixed gas to form the lightly doped region, the mixed gas mixed gas is PH 3 and H 2, PH 3, and H 2 ratio of 5% to 15%, the pressure of the mixed gas is 30mTorr to 60mTorr.
  • the step of heavily doping the lightly doped region to form a heavily doped region through a first via formed above the polysilicon region of the lightly doped region may include: forming a The lightly doped region is heavily doped to form the heavily doped region by a first via above the lightly doped region, the mixed gas is a mixed gas of PH 3 and H 2 , and the ratio of PH 3 to H 2
  • the pressure of the mixed gas is from 5% to 15%, and the pressure of the mixed gas is from 90 mTorr to 150 mTorr.
  • the manufacturing method further includes forming a first insulating layer over the active layer pattern. Further, after lightly doping the active layer pattern to form a lightly doped region and a polysilicon region, the manufacturing method further includes: forming a second insulating layer over the gate; and at the first The first via hole is formed in the insulating layer and the second insulating layer.
  • the manufacturing method further includes: forming a passivation layer over the source drain pattern; forming a second via hole in the passivation layer; and forming a pixel electrode over the passivation layer, the pixel An electrode is connected to the source drain pattern through the second via.
  • the manufacturing method further includes: forming a first buffer layer on the base substrate; and forming a second buffer layer on the first buffer layer.
  • the step of forming an active layer pattern over the base substrate may include: forming an amorphous silicon layer over the base substrate; performing laser annealing treatment on the amorphous silicon layer to form a polysilicon layer; and forming the polysilicon layer A patterning process is performed to form the active layer pattern.
  • Another embodiment of the present invention provides a display substrate fabricated by the above method for manufacturing a display substrate.
  • the active layer pattern is lightly doped to form a lightly doped region, so that the active layer pattern is formed into a lightly doped region and a polysilicon region, and
  • the lightly doped region is heavily doped through the first via, so that the doped ions are in direct contact with the lightly doped region, thereby increasing the doping speed and thereby increasing the doping efficiency.
  • Fig. 1a is a schematic view showing the manufacture of a display substrate in the prior art.
  • Fig. 1b is another schematic view showing the manufacture of a display substrate in the prior art.
  • FIG. 2 is a flowchart of a method for manufacturing a display substrate according to Embodiment 1 of the present invention.
  • Fig. 3 is a detailed flow chart of the manufacturing method shown in Fig. 2.
  • 4a is a schematic view showing formation of a first buffer layer, a second buffer layer, and an active layer pattern in the manufacturing method of FIG.
  • 4b is a schematic view showing formation of a first insulating layer and a gate in the manufacturing method.
  • Fig. 4c is a schematic view showing formation of a lightly doped region and a polycrystalline silicon region in the manufacturing method.
  • Fig. 4d is a schematic view showing formation of a second insulating layer in the manufacturing method.
  • Fig. 4e is a schematic view showing formation of a residual photoresist in the manufacturing method.
  • Fig. 4f is a schematic view showing the formation of the first via hole in the manufacturing method.
  • 4g is a schematic view showing formation of a heavily doped region and a lightly doped drain region in the manufacturing method.
  • Figure 4h is a schematic view showing the peeling of the remaining photoresist in the manufacturing method.
  • 4i is a schematic view showing formation of a source drain pattern in the manufacturing method.
  • 4j is a schematic view showing formation of a passivation layer and a second via hole in the manufacturing method.
  • 4k is a schematic view showing formation of a pixel electrode in the manufacturing method.
  • FIG. 2 is a flowchart of a method for manufacturing a display substrate according to Embodiment 1 of the present invention. As shown in FIG. 2, the method includes the following steps 101 to 105.
  • step 101 an active layer pattern is formed over the base substrate.
  • step 102 a gate is formed over the active layer pattern.
  • the active layer pattern is lightly doped to form a lightly doped region under both sides of the gate, and the active layer pattern not doped under the gate is a polysilicon region (hereinafter referred to as "Polsilicon area").
  • the lightly doped region is heavily doped by a first via formed above the polysilicon region of the lightly doped region to form a heavily doped region, and the lightly doped region is located between the heavily doped region and the polysilicon region.
  • the area is a lightly doped drain area.
  • step 105 a source drain pattern is formed over the heavily doped region, and the source drain pattern is connected to the heavily doped region through the first via.
  • the active layer pattern is lightly doped to form a lightly doped region, so that the active layer pattern is formed into a lightly doped region and a polysilicon region, and is formed by The first via that is away from the polysilicon region of the lightly doped region heavily dopes the lightly doped region to form a heavily doped region such that the lightly doped region is formed as a heavily doped region and a lightly doped drain region. Therefore, by precisely controlling the length of the heavily doped region, it is possible to accurately control the length of the lightly doped region, thereby improving the uniformity of the length of the lightly doped region on the display substrate.
  • the lightly doped region is heavily doped through the first via, so that the doped ions are in direct contact with the lightly doped region, thereby increasing the doping speed and thereby increasing the doping efficiency. Further, precise control of the length of the lightly doped region can also effectively prevent the occurrence of poor mura.
  • FIG. 3 is a detailed flowchart of a method of manufacturing the display substrate shown in FIG. 2. As shown in FIG. 3, the method includes the following steps 201 to 215.
  • a first buffer layer is formed on the base substrate, and a second buffer layer is formed on the first buffer layer.
  • step 202 an amorphous silicon layer is formed over the base substrate.
  • step 203 the amorphous silicon layer is subjected to laser annealing treatment to form a polysilicon layer.
  • step 204 a patterning process is performed on the polysilicon layer to form an active layer pattern.
  • FIG. 4a is a schematic view showing formation of a first buffer layer, a second buffer layer, and an active layer pattern.
  • a first buffer layer 2, a second buffer layer 3 and an amorphous silicon layer are sequentially deposited on the base substrate 1; amorphous silicon is processed by Excimer Laser Annealer (ELA) technology.
  • ELA Excimer Laser Annealer
  • the layer is subjected to laser annealing treatment to form a polysilicon layer; the polysilicon layer is patterned to form an active layer pattern 4.
  • the material of the first buffer layer 2 is SiN
  • the material of the second buffer layer 3 is SiO 2 .
  • the first buffer layer 2 formed over the base substrate 1 can effectively prevent Na/K in the base substrate 1 from entering the active layer pattern 4, and the second buffer layer 3 formed under the active layer pattern 4 is advantageous for Lattice matching is achieved with the polysilicon in the active layer pattern 4.
  • step 205 a first insulating layer is formed over the active layer pattern.
  • step 206 a gate is formed over the first insulating layer.
  • Fig. 4b is a schematic view showing the formation of the first insulating layer and the gate.
  • a first insulating layer 5 and a gate metal layer are sequentially deposited on the active layer pattern 4, and the gate metal layer is patterned to form the gate electrode 6.
  • the material of the gate electrode 6 may include: Mo, Cu, or Al/Mo.
  • the first insulating layer 5 covers the second buffer layer 3 and the active layer pattern 4.
  • the active layer pattern is lightly doped to form a lightly doped region under both sides of the gate, and the active layer pattern not doped directly under the gate is a polysilicon region (hereinafter referred to as "Polsilicon area").
  • Figure 4c is a schematic diagram showing the formation of lightly doped regions.
  • the active layer pattern 4 is lightly doped to form the lightly doped region 41 with the gate 6 as a mask.
  • the step of lightly doping the active layer pattern 4 to form the lightly doped region 41 may specifically include: lightly doping the active layer pattern 4 with a mixed gas to form the lightly doped region 41.
  • a mixed gas of the mixed gas is PH 3 and H 2, PH 3, and H 2 ratio of 5% to 15%
  • the pressure of the mixed gas is 30mTorr to 60mTorr.
  • the length of the lightly doped region 41 is L1.
  • the purpose of controlling the flow rate of the mixed gas can be achieved by controlling the pressure of the mixed gas.
  • step 208 a second insulating layer is formed over the gate.
  • Figure 4d is a schematic view showing the formation of a second insulating layer. As shown in Figure 4d, a second insulating layer 7 is deposited over the gate 6.
  • step 209 a first via hole is formed on the first insulating layer and the second insulating layer.
  • the first via holes may be formed on the first insulating layer and the second insulating layer by a patterning process.
  • step 209 can include the following steps 2091 and 2092.
  • step 2091 a photoresist is coated on the second insulating layer, and the photoresist is exposed and developed to remove a portion of the photoresist, leaving the remaining photoresist.
  • Figure 4e is a schematic diagram showing the formation of residual photoresist. As shown in FIG. 4e, a photoresist is coated on the second insulating layer 7, and the photoresist is exposed and developed to remove a portion of the photoresist, leaving the remaining photoresist 8.
  • step 2092 the first insulating layer and the second insulating layer are etched to form a first via.
  • Figure 4f is a schematic diagram showing the formation of a first via.
  • the first insulating layer 5 and the second insulating layer 7 are etched to form a first via 9.
  • the etch can be a dry etch.
  • the first via 9 has a diameter or width L2.
  • the purpose of controlling the diameter or width of the first via hole 9 can be achieved by controlling the exposure amount of the photoresist.
  • the lightly doped region is heavily doped by a first via formed above the polysilicon region of the lightly doped region to form a heavily doped region, and the lightly doped region is located between the heavily doped region and the polysilicon region.
  • the impurity region is a lightly doped drain region.
  • Figure 4g is a schematic diagram showing the formation of heavily doped regions and lightly doped drain regions.
  • the lightly doped region 41 is heavily doped by the first via 9 to form the heavily doped region 43
  • the lightly doped region 41 between the heavily doped region 43 and the polysilicon region 42 is Lightly doped drain region 44.
  • a heavily doped region 43 is formed at a position corresponding to the first via 9 of the lightly doped region 41. Since the polysilicon region 42 is located directly under the gate 6, it can also be said that the lightly doped drain region 44 is located between the heavily doped region 43 and the gate 6.
  • the step of forming the heavily doped region by heavily doping the lightly doped region by the first via formed above the polysilicon region in the lightly doped region includes: using the mixed gas through the first formed over the lightly doped region vias of heavily doped regions lightly doped heavily doped region, the mixed gas is a mixed gas of PH 3 and H 2, PH 3, and H 2 ratio of 5% to 15%, the pressure of the mixed gas is formed 90mTorr Up to 150mTorr.
  • the purpose of controlling the flow rate of the mixed gas can be achieved by controlling the pressure of the mixed gas.
  • step 211 the remaining photoresist is removed.
  • Figure 4h is a schematic diagram showing the peeling of the remaining photoresist. As shown in Figure 4h, the remaining photoresist 8 is stripped.
  • a source drain pattern is formed over the heavily doped region, and the source drain pattern is connected to the heavily doped region through the first via.
  • Figure 4i is a schematic diagram showing the formation of a source drain pattern.
  • a source/drain metal layer is deposited, a source-drain metal layer is patterned to form a source-drain pattern 10, and a source-drain pattern 10 is filled in the first via 9 to achieve passage through the first via 9 and The doped regions 43 are connected.
  • the source drain pattern 10 may include a source or a drain.
  • the source-drain pattern 10 on the left side of the gate 6 is the source
  • the source-drain pattern 10 on the right side of the gate 6 is the drain.
  • step 213 a passivation layer is formed over the source drain pattern.
  • step 214 a second via is formed on the passivation layer.
  • FIG. 4j is a schematic view showing the formation of a passivation layer and a second via.
  • a passivation layer 11 is formed on the source drain pattern 10 by a spin process, which covers the second insulating layer 7 and the source drain pattern 10.
  • the material of the passivation layer 11 is a resin.
  • the passivation layer 11 is patterned to form a second via hole 12.
  • the second via 12 is located above the source drain pattern 10, specifically, the second via 12 is disposed above the drain.
  • step 215 a pixel electrode is formed on the passivation layer, and the pixel electrode is connected to the source drain pattern through the second via.
  • Fig. 4k is a schematic view showing the formation of a pixel electrode.
  • a pixel electrode material layer is deposited on the passivation layer 11, and a pixel electrode material layer 13 is patterned to form a pixel electrode 13, and the pixel electrode 13 is connected to the source/drain pattern 10 through the second via hole 12.
  • the pixel electrode 13 fills the second via hole 12 to achieve connection with the source drain pattern 10 through the second via hole 12.
  • the pixel electrode 13 is connected to the source/drain pattern 10 as a drain.
  • the material of the pixel electrode 13 may be a transparent conductive material such as ITO.
  • the patterning process may include: photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the display substrate is formed by the six-time patterning process (ie, the 6mask process), and the number of mask processes is not required to be increased compared with the prior art, thereby realizing the manufacturing process of the display substrate without increasing the process difficulty.
  • the active layer pattern is lightly doped to form a lightly doped region, so that the active layer pattern is formed into a lightly doped region and a polysilicon region, and is formed by
  • the lightly doped region is heavily doped to form a heavily doped region to form the heavily doped region into a heavily doped region and a lightly doped drain region. Therefore, precise control of the length of the lightly doped region is achieved by precisely controlling the length of the heavily doped region, thereby improving the uniformity of the length of the lightly doped region on the display substrate.
  • the lightly doped region is heavily doped through the first via, so that the doped ions are in direct contact with the lightly doped region, thereby increasing the doping speed and thereby increasing the doping efficiency. Further, precise control of the length of the lightly doped region can also effectively prevent the occurrence of poor mura.
  • Embodiment 2 of the present invention provides a display substrate manufactured by the method for manufacturing a display substrate provided by the above embodiments.
  • a display substrate manufactured by the method for manufacturing a display substrate provided by the above embodiments.
  • the display substrate may be an LTPS array substrate.
  • the display substrate and the opposite substrate may be subjected to a box processing to form a display device.
  • the opposite substrate may be a color film substrate.
  • the display substrate provided in this embodiment is manufactured by using the above manufacturing method of the display substrate.
  • the length of the lightly doped region is accurately controlled by precisely controlling the length of the heavily doped region, thereby improving the display. Uniformity of the length of the lightly doped regions on the substrate.
  • the lightly doped region is heavily doped through the first via, so that the doped ions are in direct contact with the lightly doped region, thereby increasing the doping speed and thereby increasing the doping efficiency. Further, precise control of the length of the lightly doped region can also effectively prevent the occurrence of poor mura.

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Abstract

提供一种显示基板的制造方法和显示基板。显示基板的制造方法包括：在衬底基板（1）的上方形成有源层图形（4）；在有源层图形（4）的上方形成栅极（6）；对有源层图形（4）进行轻掺杂形成轻掺杂区域（41）和多晶硅区域（42），轻掺杂区域（41）位于栅极（6）的两侧，多晶硅区域（42）位于栅极（6）的下方；通过形成于轻掺杂区域（41）上方的第一过孔（9）对轻掺杂区域（41）进行重掺杂形成重掺杂区域（43）和轻掺杂漏区（44），轻掺杂漏区（44）位于重掺杂区域（43）和多晶硅区域（42）之间；在重掺杂区域（43）之上形成源漏极图形，源漏极图形通过第一过孔（9）与重掺杂区域（43）连接。因此提高了显示基板上轻掺杂区域长度的均匀性以及提高了掺杂效率。

Description

显示基板的制造方法和显示基板 技术领域
本发明涉及显示技术领域，特别涉及一种显示基板的制造方法和一种显示基板。
背景技术
低温多晶硅(Low Temperature Poly-silicon，简称：LTPS)技术由于具有迁移率高等优点受到越来越多的重视。随着显示技术的发展，LTPS技术凭借其高效能和高清晰的特点，得到了越来越广泛的应用，特别是对于较高的每英寸所拥有的像素(Pixels per inch，简称：PPI)产品。采用LTPS技术制造薄膜晶体管的过程中，需要执行将非晶硅(a-Si)转换为多晶硅(p-si)的工艺。在将a-Si转换为p-Si时，产生的晶界会造成漏电流的增加。为解决上述问题，可在源漏极图形之间的栅极两侧设置轻掺杂漏区(Lightly Doped Drain，简称：LDD)，该LDD的作用等同于串联一大电阻，从而减小了漏电流的形成，并且该LDD的长度决定了漏电流的大小。
图1a为现有技术中制造显示基板的示意图，如图1a所示，在制造显示基板的过程中，首先在衬底基板1上依次形成第一缓冲层2、第二缓冲层3、有源层图形以及位于有源层图形之上的第一绝缘层5，然后在第一绝缘层5上形成栅极金属层，对栅金属层进行光刻胶涂覆、曝光、显影和刻蚀，形成栅极6和位于栅极6之上的剩余光刻胶14。由于对栅金属层进行刻蚀时存在横向缩进量，因此刻蚀工艺后，剩余光刻胶14的宽度大于栅极6的宽度。随后，以栅极6及位于栅极6上方的剩余光刻胶14为掩体，通过第一绝缘层5对有源层图形进行重掺杂处理，来形成重掺杂区域43和有源层区域45。
图1b为现有技术中制造显示基板的另一个示意图，如图1b所示，对剩余光刻胶14进行灰化(ashing)工艺，去除部分的剩余光刻胶14，形成部分剩余光刻胶15，其中，灰化掉的剩余光刻胶14可包括位于栅极 6两侧上方的剩余光刻胶14以及位于栅极6正上方的一部分剩余光刻胶14。随后，以部分剩余光刻胶15和栅极6为掩体，通过第一绝缘层5对有源层区域45进行轻掺杂形成轻掺杂漏区44，没有进行掺杂的剩余的有源层区域为多晶硅区域42。然后，通过剥离工艺去除部分剩余光刻胶15，并在栅极6的上方依次形成源漏极图形和像素电极，此处不再具体画出。
现有技术中，位于栅极6两侧上方的剩余光刻胶14对应于轻掺杂漏区44，因此需要通过灰化(ashing)工艺去除位于栅极6两侧上方的剩余光刻胶14，并通过轻掺杂处理才能形成轻掺杂漏区44，也就是说，在灰化剩余光刻胶14的过程中，需要根据轻掺杂漏区44的长度控制灰化工艺中对剩余光刻胶14的去除量。因此，灰化掉位于栅极6两侧上方的剩余光刻胶14的多少决定了轻掺杂漏区44的长度。在通过灰化工艺去除剩余光刻胶14的过程中，受到灰化工艺本身的限制，会出现位于栅极6两侧上方的剩余光刻胶14的去除量难以控制的问题，这就导致通过灰化工艺难以精确控制轻掺杂漏区44的长度，从而造成显示基板上轻掺杂漏区44的长度不均匀的问题。此外，由于重掺杂处理过程中，掺杂离子是通过第一绝缘层5到达有源层图形的多晶硅材料中，降低了掺杂速度，从而造成掺杂效率低。
发明内容
本发明实施例提供一种显示基板的制造方法和一种显示基板，用于实现精确控制轻掺杂区域的长度以提高轻掺杂区域长度的均匀性，以及提高掺杂效率。
本发明实施例提供了一种显示基板的制造方法，包括以下步骤：在衬底基板的上方形成有源层图形；在所述有源层图形的上方形成栅极；对所述有源层图形进行轻掺杂，以在所述栅极的两侧下方形成轻掺杂区域，所述栅极正下方的没有进行掺杂的有源层图形为多晶硅区域；通过形成于所述轻掺杂区域的远离所述多晶硅区域上方的第一过孔对所述轻掺杂区域进行重掺杂形成重掺杂区域，位于所述重掺杂区域和所述多晶硅区域之间的所述轻掺杂区域为轻掺杂漏区；在所述重掺杂区域之上形成源漏极图形，所述源漏极图形通过所述第一过孔与所述重掺杂区域连接。
对所述有源层图形进行轻掺杂形成轻掺杂区域和多晶硅区域的步骤可以包括：以所述栅极为掩体，对所述有源层图形进行轻掺杂形成所述轻掺杂区域。
对所述有源层图形进行轻掺杂形成轻掺杂区域和多晶硅区域的步骤可以包括：采用混合气体对所述有源层图形进行轻掺杂形成所述轻掺杂区域，所述混合气体为PH3和H2的混合气体，PH3和H2的比例为5％至15％，所述混合气体的压强为30mTorr至60mTorr。
通过形成于所述轻掺杂区域的远离所述多晶硅区域上方的第一过孔对所述轻掺杂区域进行重掺杂形成重掺杂区域的步骤可以包括：采用混合气体通过形成于所述轻掺杂区域上方的第一过孔对所述轻掺杂区域进行重掺杂形成所述重掺杂区域，所述混合气体为PH3和H2的混合气体，PH3和H2的比例为5％至15％，所述混合气体的压强为90mTorr至150mTorr。
在衬底基板的上方形成有源层图形之后，所述制造方法还包括：在所述有源层图形之上形成第一绝缘层。此外，在对所述有源层图形进行轻掺杂形成轻掺杂区域和多晶硅区域之后，所述制造方法还包括：在所述栅极之上形成第二绝缘层；以及在所述第一绝缘层和所述第二绝缘层中形成所述第一过孔。
所述轻掺杂漏区的长度L3＝L1-L2，L1为所述轻掺杂区域的长度，L2为所述重掺杂区域的长度。
所述制造方法还包括：在所述源漏极图形之上形成钝化层；在所述钝化层中形成第二过孔；以及在所述钝化层之上形成像素电极，所述像素电极通过所述第二过孔与所述源漏极图形连接。
在衬底基板的上方形成有源层图形之前，所述制造方法还包括：在所述衬底基板上形成第一缓冲层；以及在所述第一缓冲层上形成第二缓冲层。
在衬底基板的上方形成有源层图形的步骤可以包括：在衬底基板的上方形成非晶硅层；对所述非晶硅层进行激光退火处理，形成多晶硅层；以及对所述多晶硅层进行构图工艺，形成所述有源层图形。
本发明另一实施例提供了一种显示基板，所述显示基板采用上述显示基板的制造方法制成。
本发明提供的显示基板的制造方法和显示基板的技术方案中，对有源层图形进行轻掺杂形成轻掺杂区域，使得将有源层图形形成为轻掺杂区域和多晶硅区域，并通过形成于轻掺杂区域的远离多晶硅区域上方的第一过孔对轻掺杂区域进行重掺杂形成重掺杂区域，使得将轻掺杂区域形成为重掺杂区域和轻掺杂漏区。因此，通过精确控制重掺杂区域的长度实现了精确控制轻掺杂区域的长度，从而提高了显示基板上轻掺杂区域长度的均匀性。此外，通过第一过孔对轻掺杂区域进行重掺杂，使得掺杂离子与轻掺杂区域直接接触，提高了掺杂速度，从而提高了掺杂效率。
附图说明
图1a为示出现有技术中制造显示基板的示意图。
图1b为示出现有技术中制造显示基板的另一个示意图。
图2为本发明实施例一提供的一种显示基板的制造方法的流程图。
图3为图2中示出的制造方法的详细流程图。
图4a为示出图3的制造方法中形成第一缓冲层、第二缓冲层和有源层图形的示意图。
图4b为示出所述制造方法中形成第一绝缘层和栅极的示意图。
图4c为示出所述制造方法中形成轻掺杂区域和多晶硅区域的示意图。
图4d为示出所述制造方法中形成第二绝缘层的示意图。
图4e为示出所述制造方法中形成剩余光刻胶的示意图。
图4f为示出所述制造方法中形成第一过孔的示意图。
图4g为示出所述制造方法中形成重掺杂区域和轻掺杂漏区的示意图。
图4h为示出所述制造方法中剥离剩余光刻胶的示意图。
图4i为示出所述制造方法中形成源漏极图形的示意图。
图4j为示出所述制造方法中形成钝化层和第二过孔的示意图。
图4k为示出所述制造方法中形成像素电极的示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的显示基板的制造方法和显示基板进行详细描述。
图2为本发明实施例一提供的一种显示基板的制造方法的流程图，如图2所示，该方法包括以下步骤101至步骤105。
步骤101中，在衬底基板的上方形成有源层图形。
步骤102中，在有源层图形的上方形成栅极。
步骤103中，对有源层图形进行轻掺杂，以在栅极的两侧下方形成轻掺杂区域，栅极正下方的没有进行掺杂的有源层图形为多晶硅区域(以下简称为“多晶硅区域”)。
步骤104中，通过形成于轻掺杂区域的远离多晶硅区域上方的第一过孔对轻掺杂区域进行重掺杂形成重掺杂区域，位于重掺杂区域和多晶硅区域之间的轻掺杂区域为轻掺杂漏区。
步骤105中，在重掺杂区域之上形成源漏极图形，源漏极图形通过第一过孔与重掺杂区域连接。
本实施例提供的显示基板的制造方法的技术方案中，对有源层图形进行轻掺杂形成轻掺杂区域，使得将有源层图形形成为轻掺杂区域和多晶硅区域，并通过形成于轻掺杂区域的远离多晶硅区域上方的第一过孔对轻掺杂区域进行重掺杂来形成重掺杂区域，使得将轻掺杂区域形成为重掺杂区域和轻掺杂漏区。因此，通过精确控制重掺杂区域的长度，实现了精确控制轻掺杂区域的长度，从而提高了显示基板上轻掺杂区域长度的均匀性。此外，通过第一过孔对轻掺杂区域进行重掺杂，使得掺杂离子与轻掺杂区域直接接触，提高了掺杂速度，从而提高了掺杂效率。进一步地，精确控制轻掺杂区域的长度还可以有效避免mura不良的产生。
图3为图2中示出的显示基板的制造方法的详细流程图，如图3所示，该方法包括以下步骤201至步骤215。
步骤201中，在衬底基板上形成第一缓冲层，在第一缓冲层上形成第二缓冲层。
步骤202中，在衬底基板的上方形成非晶硅层。
步骤203中，对非晶硅层进行激光退火处理，形成多晶硅层。
步骤204中，对多晶硅层进行构图工艺，形成有源层图形。
图4a为示出形成第一缓冲层、第二缓冲层和有源层图形的示意图。如图4a所示，在衬底基板1上依次沉积第一缓冲层2、第二缓冲层3和非晶硅层；通过准分子激光退火(Excimer Laser Annealer，简称：ELA)技术对非晶硅层进行激光退火处理，以形成多晶硅层；对多晶硅层进行构图工艺，形成有源层图形4。例如，第一缓冲层2的材料为SiN，第二缓冲层3的材料为SiO2。在衬底基板1之上形成的第一缓冲层2可有效防止衬底基板1中的Na/K进入有源层图形4，在有源层图形4之下形成的第二缓冲层3有利于与有源层图形4中的多晶硅实现晶格匹配。
步骤205中，在有源层图形之上形成第一绝缘层。
步骤206中，在第一绝缘层之上形成栅极。
图4b为示出形成第一绝缘层和栅极的示意图。如图4b所示，在有源层图形4上依次沉积第一绝缘层5和栅金属层，对栅金属层进行构图工艺形成栅极6。例如，栅极6的材料可包括：Mo、Cu或者Al/Mo。第一绝缘层5覆盖第二缓冲层3和有源层图形4。
步骤207中，对有源层图形进行轻掺杂，以在栅极的两侧下方形成轻掺杂区域，栅极正下方的没有进行掺杂的有源层图形为多晶硅区域(以下简称为“多晶硅区域”)。
图4c为示出形成轻掺杂区域的示意图。如图4c所示，以栅极6为掩体，对有源层图形4进行轻掺杂来形成轻掺杂区域41。对有源层图形4进行轻掺杂来形成轻掺杂区域41的步骤具体可包括：采用混合气体对有源层图形4进行轻掺杂来形成轻掺杂区域41。例如，混合气体为PH3和H2的混合气体，PH3和H2的比例为5％至15％，混合气体的压强为30mTorr至60mTorr。如图4c所示，轻掺杂区域41的长度为L1。本实施例中，可通过控制混合气体的压强达到控制混合气体流量的目的。
步骤208中，在栅极之上形成第二绝缘层。
图4d为示出形成第二绝缘层的示意图。如图4d所示，在栅极6之上沉积第二绝缘层7。
步骤209中，在第一绝缘层和第二绝缘层上形成第一过孔。
例如，可通过构图工艺在第一绝缘层和第二绝缘层上形成第一过孔。具体地，步骤209可包括以下步骤2091和步骤2092。
步骤2091中，在第二绝缘层上涂覆光刻胶，并对光刻胶进行曝光和显影以去除部分光刻胶，保留剩余光刻胶。
图4e为示出形成剩余光刻胶的示意图。如图4e所示，在第二绝缘层7上涂覆光刻胶，并对光刻胶进行曝光和显影以去除部分光刻胶，保留剩余光刻胶8。
步骤2092中，对第一绝缘层和第二绝缘层进行刻蚀，形成第一过孔。
图4f为示出形成第一过孔的示意图。如图4f所示，对第一绝缘层5和第二绝缘层7进行刻蚀，形成第一过孔9。例如，该刻蚀可以为干法刻蚀。如图4f所示，第一过孔9的直径或宽度为L2。本实施例中，可通过控制光刻胶的曝光量来达到控制第一过孔9的直径或宽度的目的。
步骤210中，通过形成于轻掺杂区域的远离多晶硅区域上方的第一过孔对轻掺杂区域进行重掺杂来形成重掺杂区域，位于重掺杂区域和多晶硅区域之间的轻掺杂区域为轻掺杂漏区。
图4g为示出形成重掺杂区域和轻掺杂漏区的示意图。如图4g所示，通过第一过孔9对轻掺杂区域41进行重掺杂来形成重掺杂区域43，并且位于重掺杂区域43和多晶硅区域42之间的轻掺杂区域41为轻掺杂漏区44。在重掺杂过程中，在与轻掺杂区域41的与第一过孔9对应的位置处形成重掺杂区域43。由于多晶硅区域42位于栅极6的正下方，因此，也可以说，轻掺杂漏区44位于重掺杂区域43和栅极6之间。
通过形成于轻掺杂区域的远离多晶硅区域上方的第一过孔对轻掺杂区域进行重掺杂来形成重掺杂区域的步骤包括：采用混合气体通过形成于轻掺杂区域上方的第一过孔对轻掺杂区域进行重掺杂来形成重掺杂区域，混合气体为PH3和H2的混合气体，PH3和H2的比例为5％至15％，混合气体的压强为90mTorr至150mTorr。本实施例中，可通过控制混合气体的压强达到控制混合气体流量的目的。
轻掺杂漏区44的长度L3＝L1-L2，由于第一过孔9的直径或宽度与重掺杂区域43的长度相等，因此L2也为重掺杂区域43的长度。由于L3＝L1-L2，因此本实施例中可通过控制L2达到控制L3的目的。与现有技术中通过灰化工艺控制轻掺杂漏区的长度L3相比，本实施例可实现对轻掺杂漏区的长度L3的精确控制。
步骤211中，去除剩余光刻胶。
图4h为示出剥离剩余光刻胶的示意图。如图4h所示，剥离剩余光刻胶8。
步骤212中，在重掺杂区域之上形成源漏极图形，源漏极图形通过第一过孔与重掺杂区域连接。
图4i为示出形成源漏极图形的示意图。如图4i所示，沉积源漏极金属层，对源漏极金属层进行构图工艺形成源漏极图形10，源漏极图形10填充第一过孔9以实现通过第一过孔9与重掺杂区域43连接。具体地，源漏极图形10可包括：源极或者漏极。图4i中，位于栅极6左侧的源漏极图形10为源极，位于栅极6右侧的源漏极图形10为漏极。
步骤213中，在源漏极图形之上形成钝化层。
步骤214中，在钝化层上形成第二过孔。
图4j为示出形成钝化层和第二过孔的示意图。如图4j所示，通过旋涂(spin)工艺在源漏极图形10上形成钝化层11，该钝化层11覆盖第二绝缘层7和源漏极图形10。该钝化层11的材料为树脂。随后，对钝化层11进行构图工艺，形成第二过孔12。第二过孔12位于源漏极图形10的上方，具体地，第二过孔12设置在漏极上方。
步骤215中，在钝化层之上形成像素电极，像素电极通过第二过孔与源漏极图形连接。
图4k为示出形成像素电极的示意图。如图4k所示，在钝化层11上沉积像素电极材料层，对像素电极材料层进行构图工艺形成像素电极13，该像素电极13通过第二过孔12与源漏极图形10连接。具体地，像素电极13填充第二过孔12以实现通过第二过孔12与源漏极图形10连接。此时，像素电极13与作为漏极的源漏极图形10连接。像素电极13的材料可以为透明导电材料，例如，ITO。
本实施例中，构图工艺可包括：光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工艺。
本实施例通过六次构图工艺(即，6mask工艺)形成显示基板，与现有技术相比无需增加mask工艺次数，从而在不增加工艺难度的前提下实现了显示基板的制造过程。
本实施例提供的显示基板的制造方法的技术方案中，对有源层图形进行轻掺杂形成轻掺杂区域，使得将有源层图形形成为轻掺杂区域和多晶硅区域，并通过形成于轻掺杂区域的远离多晶硅区域上方的第一过孔对轻掺杂区域进行重掺杂形成重掺杂区域，使得将轻掺杂区域形成为重掺杂区域和轻掺杂漏区。因此通过精确控制重掺杂区域的长度实现了精确控制轻掺杂区域的长度，从而提高了显示基板上轻掺杂区域长度的均匀性。此外，通过第一过孔对轻掺杂区域进行重掺杂，使得掺杂离子与轻掺杂区域直接接触，提高了掺杂速度，从而提高了掺杂效率。进一步地，精确控制轻掺杂区域的长度还可以有效避免mura不良的产生。
本发明实施例二提供了一种显示基板，该显示基板采用上述实施例提供的显示基板的制造方法制造。具体结构可参考上述实施例中的图4k所示出的内容及相关描述，此处不再赘述。
本实施例中，显示基板可以为LTPS阵列基板。在该情况下，在制造显示装置的过程中，可将该显示基板与对端基板进行对盒处理以形成显示装置，例如，该对端基板可以为彩膜基板。
本实施例提供的显示基板采用上述显示基板的制造方法制成，在该显示基板的技术方案中，通过精确控制重掺杂区域的长度实现了精确控制轻掺杂区域的长度，从而提高了显示基板上轻掺杂区域长度的均匀性。此外，通过第一过孔对轻掺杂区域进行重掺杂，使得掺杂离子与轻掺杂区域直接接触，提高了掺杂速度，从而提高了掺杂效率。进一步地，精确控制轻掺杂区域的长度还可以有效避免mura不良的产生。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种显示基板的制造方法，包括步骤：
    在衬底基板的上方形成有源层图形；
    在所述有源层图形的上方形成栅极；
    对所述有源层图形进行轻掺杂，以在所述栅极的两侧下方形成轻掺杂区域，所述栅极正下方的没有进行掺杂的有源层图形为多晶硅区域；
    通过形成于所述轻掺杂区域的远离所述多晶硅区域上方的第一过孔对所述轻掺杂区域进行重掺杂来形成重掺杂区域，位于所述重掺杂区域和所述多晶硅区域之间的所述轻掺杂区域为轻掺杂漏区；以及
    在所述重掺杂区域之上形成源漏极图形，所述源漏极图形通过所述第一过孔与所述重掺杂区域连接。
  2. 根据权利要求1所述的显示基板的制造方法，其中，对所述有源层图形进行轻掺杂形成轻掺杂区域和多晶硅区域的步骤包括：
    以所述栅极为掩体，对所述有源层图形进行轻掺杂形成所述轻掺杂区域。
  3. 根据权利要求1或2所述的显示基板的制造方法，其中，对所述有源层图形进行轻掺杂形成轻掺杂区域的步骤包括：采用混合气体对所述有源层图形进行轻掺杂形成所述轻掺杂区域，所述混合气体为PH3和H2的混合气体，PH3和H2的比例为5％至15％，所述混合气体的压强为30mTorr至60mTorr。
  4. 根据权利要求1所述的显示基板的制造方法，其中，通过形成于所述轻掺杂区域的远离所述多晶硅区域上方的第一过孔对所述轻掺杂区域进行重掺杂来形成重掺杂区域的步骤包括：采用混合气体通过形成于所述轻掺杂区域上方的第一过孔对所述轻掺杂区域进行重掺杂形成所述重掺杂区域，所述混合气体为PH3和H2的混合气体，PH3和H2的比例为5％至15％，所述混合气体的压强为90mTorr至150mTorr。
  5. 根据权利要求1所述的显示基板的制造方法，其中，
    在衬底基板的上方形成有源层图形之后，所述制造方法还包括：在所述有源层图形之上形成第一绝缘层，并且
    在对所述有源层图形进行轻掺杂形成轻掺杂区域之后，所述制造方法还包括：在所述栅极之上形成第二绝缘层；以及在所述第一绝缘层和所述第二绝缘层中形成所述第一过孔。
  6. 根据权利要求1所述的显示基板的制造方法，其中，所述轻掺杂漏区的长度L3＝L1-L2，L1为所述轻掺杂区域的长度，L2为所述重掺杂区域的长度。
  7. 根据权利要求1所述的显示基板的制造方法，还包括步骤：
    在所述源漏极图形之上形成钝化层；
    在所述钝化层中形成第二过孔；以及
    在所述钝化层之上形成像素电极，所述像素电极通过所述第二过孔与所述源漏极图形连接。
  8. 根据权利要求1所述的显示基板的制造方法，其中，在衬底基板的上方形成有源层图形之前，所述制造方法还包括：在所述衬底基板上形成第一缓冲层；以及在所述第一缓冲层上形成第二缓冲层。
  9. 根据权利要求1所述的显示基板的制造方法，其中，在衬底基板的上方形成有源层图形的步骤包括：
    在衬底基板的上方形成非晶硅层；
    对所述非晶硅层进行激光退火处理，形成多晶硅层；以及
    对所述多晶硅层进行构图工艺，形成所述有源层图形。
  10. 一种显示基板，其采用权利要求1至9中任一项所述的显示基板的制造方法制造。
PCT/CN2014/089553 2014-04-30 2014-10-27 显示基板的制造方法和显示基板 Ceased WO2015165226A1 (zh)

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