WO2015160718A2

WO2015160718A2 - Flip light emitting diode chip and method of fabricating the same

Info

Publication number: WO2015160718A2
Application number: PCT/US2015/025604
Authority: WO
Inventors: Pao Chen; Chung Chi Chang; Chang Han
Original assignee: Starlite LED Inc
Current assignee: Starlite LED Inc
Priority date: 2014-04-14
Filing date: 2015-04-13
Publication date: 2015-10-22
Anticipated expiration: 2016-10-14
Also published as: WO2015160718A3

Abstract

A method of fabricating a light emitting diode device comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench and depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact.

Description

FLIP LIGHT EMITTING DIODE CHIP AND METHOD OF FABRICATING THE SAME

TECHNICAL FIELD

[0001] The example embodiments of the present invention generally relate to light emitting diodes device, and more particularly to flip light emitting diode chips and method of fabricating the same.

BACKGROUND

[0002] There are two fundamental ways to envisage light emitting diode chips, i.e., a lateral and a vertical die structure. FIG. 1(a) shows a lateral light emitting diode chip 100 of the prior art. FIG. 1(b) illustrates the lateral light emitting diode chip 100 assembled to a printed circuit board 160. With reference to FIG. 1(a), the lateral light emitting diode chip 100 includes a substrate 102, an n-type GaN layer 104 on the substrate 102, an active layer 106 on the n-type GaN layer 104, a p-type GaN layer 108 on the active layer 106, and contact pads 110 on the n- type GaN layer 104 and the p-type GaN layer 108 respectively. As shown in FIGs. 1(a) and 1(b), when the light emitting diode chip 100 is assembled to the printed circuit board 160, a lead frame 114 connects the contact pads 110 of the light emitting diode chip 100 to contact pads 168 of the printed circuit board 160.

[0003] FIG. 2(a) illustrates a vertical light emitting diode chip 200 of the prior art. FIG. 2(b) illustrates the vertical light emitting diode chip 200 assembled to a printed circuit board of the prior art. Similar to the lateral structure, the vertical light emitting diode chip 200 includes a substrate 202, an n-type GaN layer 204 on the substrate 202, an active layer 206 on the n-type GaN layer 204, a p-type GaN layer 208 on the active layer 206, and a contact pad 210 on the p- type GaN layer 208. As shown in FIG. 2(b), a lead frame 214 connects the contact pads (not numbered) of the light emitting diode chip 200 to contact pads 268 of a printed circuit board (not numbered).

[0004] As the light emitting diode chips (100, 200) are wiring bonded to the printed circuit boards, the heat generated in the active region may propagate through the substrate (102, 202) before being dissipated into the printed circuit board.

BRIEF SUMMARY [0005] According to one exemplary embodiment of the present invention, a method of fabricating a light emitting diode device comprises providing a substrate, growing an epitaxial structure on the substrate. The epitaxial structure includes a first layer on the substrate, an active layer on the first layer and a second layer on the active layer. The method further comprises depositing a conductive and reflective layer on the epitaxial structure, forming at least one space, forming a group of first trenches and a second trench. The at least one space extends from surface of the conductive and reflective layer to the substrate to expose part of the substrate. Each of the first and second trenches extending from surface of the conductive and reflective layer to the first layer to expose part of the first layer. The method further comprises depositing conductive material to cover a portion of surface of a conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad; and depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench and depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact, a first light emitting diode bonding pad, formed on the first contact pad covering a portion of surface of the first contact pad, a second light emitting diode bonding pad, formed on the second contact pad covering a portion of surface of the second contact pad and a third light emitting diode bonding pad formed on the first planar passivation contact surface covering a portion of surface of the first planar passivation contact.

[0006] According to one exemplary embodiment of the present invention, a light emitting diode device comprises a substrate, an epitaxial structure grown on the substrate, a conductive layer deposited on the epitaxial structure. The epitaxial structure includes a first layer having a first material, an active layer on the first layer, the active layer having a second material and a second layer on the active layer. The second layer has the first material. The first layer and the second layer include different types of doping. The first material has wider band gap than that of the second material. The light emitting diode device further comprises a first contact pad formed on the conductive layer and a second contact pad covering surfaces between adjacent first trenches. The first contact pad is spatially separated from the second contact pad by a second trench. The second contact pad electrically connects to the first layer by filling conductive material in the first trenches. The first and second trenches extend from the conductive layer to the first layer to expose part of the first layer.

[0007] According to one exemplary embodiment of the present invention, a light emitting diode device comprises a light emitting diode die and a metal core printed circuit board. The light emitting diode die comprises a first contact pad, a first light emitting diode bonding pad on the first contact pad, a second contact pad, a second light emitting diode bonding pad on the second contact pad, and a planar passivation contact surface between the first contact pad and the second contact pad, and a third light emitting diode bonding pad on the planar passivation contact surface.

[0008] The metal core printed circuit board comprises a metal core substrate, a dielectric layer on the metal core substrate, a first conductive pad, the first conductive pad formed above the dielectric layer, a first printed circuit board bonding pad on the first conductive pad surface, a second conductive pad formed above the dielectric layer, a second printed circuit board bonding pad on the second conductive pad surface, a mesa structure, extending from the metal core and positioning between the first conductive pad and the second conductive pad, and a third printed circuit board bonding pad on the mesa structure surface. The first light emitting diode bonding pad, the second light emitting diode bonding pad and the third light emitting diode bonding pad of the light emitting diode die are bonded to the first printed circuit board bonding pad, the second printed circuit board bonding pad, and the third printed circuit board bonding pad of the metal core printed circuit board respectively. The first contact pad and the second contact pad of the light emitting diode die are electrically connected to the first conductive pad and the second conductive pad of the metal core printed circuit board respectively. The planar passivation contact surface is in thermally coupled with the mesa structure.

BRIEF DESCRIPTION OF THE DRAWING(S)

[0009] Having thus described the example embodiments of the present invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0010] FIG. 1(a) illustrates a lateral light-emitting diode chip of the prior art; [0011] FIG. 1(b) illustrates a lateral light-emitting diode chip assembled to a metal core printed circuit board;

[0012] FIG. 2(a) illustrates a vertical light-emitting diode chip of the prior art;

[0013] FIG. 2(b) illustrates a vertical light-emitting diode chip assembled to a metal core printed circuit board;

[0014] FIGs. 3(a) - 3(f) are cross-sectional views to illustrate process of fabricating a flip light emitting diode chip according to one example embodiment of the present invention;

[0015] FIGs. 3(g)-3(h) are cross-sectional views to illustrate a flip light emitting diode chip having a single passivation layer assembled to a printed circuit board according to one example embodiment of the present invention;

[0016] FIG. 3(i) illustrate a cross-sectional view of a flip light emitting diode chip having light emitting diode bonding pads according to one example embodiment of the present invention;

[0017] FIGs. 3(j) and 3(k) are cross-sectional views to illustrate a flip light emitting diode chip having light emitting diode bonding pads assembled to a printed circuit board according to one example embodiment of the present invention;

[0018] FIG. 4(a) illustrates a 3-D view of trenches formed in FIG. 3(d);

[0019] FIGs. 4(b)-4(d) illustrate top views of exemplary trenches formed in FIG. 3(d).

[0020] FIGs. 5(a)-5(b) are cross- sectional views to illustrate an alternative example embodiment of FIGs. 3(f) and 3(g);

[0021] FIGs. 6(a)-6(b) are cross- sectional views to illustrate an alternative example embodiment of FIGs. 3(f) and 3(g);

[0022] FIGs. 7(a) - 7(e) are cross-sectional views to illustrate an alternative example embodiment of FIGs. 3(f)-3(h);

[0023] FIGs. 8(a) - 8(b) are cross-sectional views to illustrate an alternative example embodiment of FIGs.7(c)-7(d);

[0024] FIGs. 9(a) - 9(b) are cross-sectional views to illustrate an alternative example embodiment of FIGs.7(c)-7(d);

[0025] FIGs. 10(a) - 10(d) are cross-sectional views to illustrate process of fabricating a flip light emitting diode chipset according to one example embodiment of the present invention; [0026] FIGs. 11(a)- 11(b) illustrate cross-sectional views of assembling a light emitting diode chip to a printed circuit board according to example embodiments of the present invention;

[0027] FIG. 12(a) illustrates a cross-sectional view of a metal core printed circuit board according to one example embodiment of the present invention;

[0028] FIG. 12(b) illustrates a cross-sectional view of a light emitting diode device according to one example embodiment of the present invention;

[0029] FIG. 13(a) illustrates a cross-sectional view of a 3-pad LED die according to one example embodiment of the present invention;

[0030] FIG. 13(b) illustrates a cross-sectional view of a metal core printed circuit board according to one example embodiment of the present invention;

[0031] FIG. 13(c) illustrates a cross-sectional view of a light emitting diode device according to one example embodiment of the present invention;

[0032] FIG. 14(a) illustrates a cross-sectional view of a metal core printed circuit board according to one example embodiment of the present invention; and

[0033] FIG. 14(b) illustrates a cross-sectional view of a light emitting diode device according to one example embodiment of the present invention.

DETAILED DESCRIPTION

[0034] The present disclosure now will be described more fully with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. This disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0035] FIGs. 3(a) - 3(f) are cross-sectional views to illustrate method of fabricating a flip light emitting diode chip according to one example embodiment of the present invention. As illustrated in FIG. 3(a), the method includes growing an epitaxial structure 304 on a substrate 302. The epitaxial structure 304 may include a first layer 304a, an active layer 304b on the first layer 304a and a second layer 304c on the active layer 304b. The first layer 304a and the second layer 304c may include a first material. The active layer 304b may include a second material that has narrower band gap than that of the first material. The first layer 304a and the second layer 304c may include different types of doping. For instance, the first layer 304a may be an n- doped semiconductor layer. The second layer 304c may be a p-doped semiconductor layer. An additional layer, such as an adhesion layer, a seed layer or a buffer layer (not shown) may be deposited on the substrate 302 prior to the growth of the epitaxial structure 304 to improve the adhesion between the epitaxial structure 304 and the substrate 302.

[0036] The substrate 302 may include AI₂O₃ or any other insulating material such as SiC, ZnO, MgO, Ga₂0₃, AlGaN, GaLiO, AlLiO, or Si. In one embodiment, the active layer 304b may include at least one of indium gallium nitride (InGaN), AlGaAs, GaP, AlInGaP, or GaAsP. The first and second layers 304a and 304c may include gallium nitride (GaN), or Gallium

Arsenide (GaAs). The epitaxial structure 304 may be deposited on the substrate 302 by metal organic chemical vapor deposition (MOCVD) process or any other suitable deposition processes.

[0037] The method may further include depositing a conductive layer 310 on the epitaxial structure 304 as shown in FIG. 3(b). The conductive layer 310 may be deposited by metal film deposition methods such as physical vapor deposition (PVD). The conductive layer 310 may include at least one of conductive materials that have light reflection properties, such as Ag, Al, Rh, Ti, Ni, W, Mo, Cr, Pt and Pd. In an alternative embodiment, the conductive layer 310 may include at least one of materials that have translucent or transparent properties or insufficient reflective properties, such as ln₂0₃, Sn0₂, EVIO, ZnO, IZO, ITO, Ni, Au, Ti or Ni.

[0038] An additional layer (not shown), such as an adhesion layer, a seed layer or a buffer layer, may be deposited on the epitaxial structure 304 prior to the deposition of the conductive layer 310. The additional layer may include at least one of conductive materials, such as Ti, Ni, Sn, Cr and WTi.

[0039] A photolithograph process may then be applied to transfer a pattern on a photomask to a light-sensitive photoresistor. Reactive ion etching process may be used to selectively remove parts of the layers (304a, 304b, 304c, 310) previously deposited on the substrate 302, resulting in a space 312 that extends from surface of the conductive layer 310 to the substrate 302 to expose part of the substrate 302, as shown in FIG. 3(c). The space 312 may separate adjacent light emitting diode dies that are described in detail in FIGs. 11(a) and 11(b) and may also be used to separate a die from a wafer in later packaging process.

[0040] Referring to FIG. 3(d), another photolithograph and etching process may be applied to form a plurality of trenches (e.g., first trenches 314a, a second trench 314b) that extends from surface of the conductive layer 310 to the first layer 304a to expose part of the first layer 304. The trenches may have different sizes in accordance with their uses. For instance, the second trench 314b having larger width may be used for isolating a contact pad from layers (304b, 304c, 310) in later fabrication process. The trench(es) with smaller width, for example the first trenches 314a, may be used for forming a contact pad connecting to the first layer 304a in next step shown in FIG. 3(e). The first trenches 314a may be in various forms. In an example embodiment, the first trenches 314a may be in form of columns. A 3D view and a top view of columns of the first trenches 314a are respectively illustrated in FIGs. 4(a) and 4(b).

Alternatively, the first trenches 314a may be in form of grids as shown in FIG. 4(c) and meshes as shown in FIG. 4(d).

[0041] To form contact pads for the light emitting diode device, a layer of conductive material may be deposited on surface of the wafer. A photolithography process may

subsequently be applied to remove undesired conductive material to form a first contact pad 316a and a second contact pad 316b on the conductive layer 310. The first contact pad 316a covers a portion of the conductive layer 310 on one side of the second trench 314b. The second contact pad 316b on the other side of the second trench 314b covers surfaces of the conductive layer 310 between adjacent first trenches 314a and electrically connects to the first layer 304a by filling the conductive material in the first trenches 314a, as shown in FIG. 3(e). The electric connections formed by the trenches 314a between the second contact pad 316b and the first layer 304a may result in lower contact resistance and higher driving current, thus reducing heat generated on the first layer 304a. The conductive material of the first contact pad 316a and the second contact pad 316b may include at least one of Ti, Ni, Au, Cr, Ag, Al, Cu and W.

[0042] A passivation layer may be deposited over the wafer followed by applying a photolithography process to remove undesired passivation material from the first and second contact pads 316a and 316b and obtain a desired thickness of the passivation layer. In one embodiment, the passivation layer, such as a passivation layer 318 shown in FIG. 3(f), may be formed at the same plane level as that of the first and second contact pads 316a and 316b.

[0043] Subsequent to the deposition of the passivation layer 318, the substrate may be chemically or mechanically polished to a desired thickness. The wafer may be diced into individual light emitting diode chip, resulting in a plurality of light emitting diode chips per wafer, such as light emitting diode chip 330 as shown in FIG. 3(f). In an assembly process illustrated in FIG. 3(g), the light emitting diode chip 330 may be flipped over so that the first and second contact pads 316a and 316b face down. To attach the flip light emitting diode chip 330 onto a metal core printed circuit board 340g, conductive bonder 332, such as solder paste or conductive epoxy, are re-melted to produce an electric connection between the contact pads (316a, 316b) of the light emitting diode chip 330 and conductive pads (342a, 342b) of the metal core printed circuit board 340g using one of reflow solder process, thermal cure, ultrasonic and ultraviolet methods. On top surface the metal core printed circuit board 340g and between the two conductive pads 342a and 342b, a metal mesa structure 348 may physically contact the passivation layer 318 resulting in an acceleration of heat dissipation from the flip light emitting diode chip 330 to the metal core printed circuit board 340g in operation.

[0044] In an instance in which a metal core printed circuit board has no metal mesa structure, as a metal core printed circuit board 340h shown in FIG. 3(h), there may be a space existing between the flip light emitting diode chip 330 and the metal core printed circuit board 340h. To couple the flip light emitting diode chip 330 to the metal core printed circuit board 340h, dielectric thermal-conductive material 344 may be filled in the space that may improve thermal dissipation.

[0045] In another embodiment, the flip light emitting diode chip 330 as shown in FIG. 3(f) may further comprise LED bonding pads, such as 320a, 320b and 320c as illustrated in FIG. 3(i) to form a light emitting diode chip 330L The LED bonding pads 320a, 320b and 320c may be respectively formed on the first contact pad 316a, the second contact pad 316b, and the first planar passivation contact surface 1318. Each of the LED bonding pads 320a, 320b and 320c may cover at least a portion of surface of its underlying layer. For example, the LED bonding pad 320a may cover at least a portion of surface of the first conductive pad 316a. The LED bonding pad 320b may cover at least a portion of surface of the second conductive pad 316b. The LED bonding pad 320c may cover at least a portion of surface of the passivation layer 318. LED bonding pads 320a and 320b are formed on two sides of the bonding pad 320c and may be spatially separated from the LED bonding pad 320c. Each of the LED bonding pads 320a, 320b and 320c may comprise one or more base metals such as copper, bronze, silver, brass, tin, nickel, chromium, aluminum, platinum, titanium, tungsten, or eutectic alloy such as Au-In, Cu-Sn, Au- Sn, Au-Ge, Au-Si, Al-Ge and Al-Si. [0046] FIG. 3(j) is a cross-sectional view to illustrate structure of a light emitting diode device having the flip light emitting diode chip 330i assembled to a metal core printed circuit board (MCPCB) 340j according to one example embodiment of the present invention. The MCPCB 340j may comprise a substrate 3402 with a mesa structure 3404 projecting from surface of the substrate 3402. The MCPCB 340j may further comprise a dielectric layer 3406, covering at least a portion of the substrate 3402 without covering surface of the mesa structure 3404. A conductive layer may be formed on the dielectric layer 3406 to form a first conductive pad 3408a and a second conductive pad 3408b. PCB bonding pads 3410a, 3410b and 3410c may be formed on the first conductive pad 3408a, the second conductive pad 3408b and the mesa structure 3404, respectively. Each of the PCB bonding pads 3410a, 3410b and 3410c may cover at least a portion of surface of its underlying layer. For example, the PCB bonding pad 3410a may cover at least a portion of surface of the first conductive pad 3408a. The PCB bonding pad 3410b may cover at least a portion of surface of the second conductive pad 3408b. The PCB bonding pad 3410c may cover at least a portion of surface of the mesa structure 3404. Each of the PCB bonding pads 3410a, 3410b and 3410c may comprise one or more base metals such as copper, bronze, silver, brass, tin, nickel, chromium, aluminum, platinum, titanium, tungsten, or eutectic alloy such as Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge and Al-Si.

[0047] When the light emitting diode die 330i is assembled to the MCPCB 340j, the LED bonding pads 320a and 320b of the light emitting diode die 330i may be directly bonded to the bonding pads 3410a and 3410b of the MCPCB 340j via a boding process, such as eutectic bonding process to allow the first contact pads 316a and the second contact pad 316b of the light emitting diode die 330i to be electrically connected to the first conductive pad 3408a and the second conductive pad 3408b of the MCPCB 340j, respectively. Meanwhile, the LED bonding pad 320c of the light emitting diode die 330i may be directly bonded to the PCB bonding pad 3410c of the MCPCB 340j via a bonding process such as eutectic bonding process. As a result, the first planar passivation contact surface 318 of the light emitting diode die 330i may be thermally coupled with the mesa structure 3404 of the MCPCB 340j.

[0048] FIG. 3(k) shows a structure of a light emitting diode device according to another example embodiment of the present invention. The device may comprise the light emitting diode die 330i, the MCPCB 340j and bonding materials filled in between the light emitting diode die 330i and the MCPCB 340j. The LED bonding pads 320a and 320b of the light emitting diode die 330i may be bonded to the PCB bonding pads 3410a and 3410b of the MCPCB 340j through the bonding material 350a and 350b, respectively to allow the first contact pads 316a and the second contact pad 316b of the light emitting diode die 330i to be electrically connected to the first conductive pad 3408a and the second conductive pad 3408b of the MCPCB 340j, respectively. The bonding materials 350a and 350b may comprise electrically conductive materials such as solder, solder paste and conductive epoxy. The LED bonding pad 320c of the light emitting diode die 330i may be directly bonded to the PCB bonding pad 3410c of the MCPCB 340j via bonding material 350c to allow the first planar passivation contact surface 318 of the light emitting diode die 330i to be thermally coupled with the mesa structure 3404 of the MCPCB 340j. The bonding material 350c may comprise thermally conductive material such as solder, solder paste, thermally conductive epoxy, and thermally conductive grease/paste.

[0049] Alternatively, the coupling between the flip light emitting diode chip and the metal core printed circuit board may be made by altering thickness of the passivation layer 318 during the deposition and photolithography process.

[0050] Depending on various height of the metal mesa structure of the metal core printed circuit boards (including the embodiment that has no metal mesa structure) the passivation layer may be thicker or thinner than that illustrated in FIG. 3(f). In an example embodiment illustrated in FIGs. 5(a) and 5(b), because surface of a metal mesa structure 548 of a metal core printed circuit board 540 is lower than that of first and second contact pads 516a and 516b of a light emitting diode chip 530 a thicker passivation layer 518 may be formed to allow the metal mesa structure 548 physically contact the passivation layer 518. In another example embodiment illustrated in FIGs. 6(a) and 6(b), surface of a metal mesa structure 648 of a metal core printed circuit board 640 is higher than that of first and second contact pads 616a and 616b of a light emitting diode chip 630, a thinner passivation layer 618 is formed to allow the metal mesa structure 648 physically contact the passivation layer 618.

[0051] In another embodiment, the passivation layer 318 illustrated in FIG. 3(f) may have a lower surface than that of the contact pads 316a and 316b. A passivation layer 718 having a lower surface is illustrated in FIG. 7(a). In this embodiment, a reflective layer 720 may be deposited to cover at least a portion of a passivation layer 718 and to reflect light toward the substrate 302, as illustrated in FIG. 7(b). The reflective layer 720 may include at least one of reflective materials that have light reflection properties, such as Ag, Al, Rh, Ti, Ni, W, Mo, Cr, Pt and Pd. A second passivation layer 722 may then be deposited to cover the reflective layer 720, as shown in FIG. 7(c) and followed by applying a photolithography process to selectively remove part of passivation material from the first and second contact pads 316a and 316b and obtain a desired thickness of the second passivation layer 722. The passivation layer 722 may have different thickness depending on various embodiments.

[0052] In one embodiment as illustrated in FIG. 7(c), surface of the passivation layer 722 may be at the same plane level as that of the first and second contact pads 316a and 316b. An additional layer, such as an adhesion layer, a seed layer or a buffer layer (not shown) may be sandwiched between the passivation layer 718 and the reflective layer 720 depending on strength of the adhesion between the reflective and passivation materials. Similar to the assembly process described in FIG. 3(g), subsequent to the deposition of the passivation layer 722, the substrate may be chemically or mechanically polished to a desired thickness. The wafer may be diced into individual light emitting diode chip, resulting in a plurality of light emitting diode chips per wafer. As illustrated in FIG. 7(d), a light emitting diode chip 730 is flipped over so that contact pads 316a and 316b face down. To attach the flip light emitting diode chip 730 onto a metal core printed circuit board 740d, conductive bonder 732 are re-melted to produce an electric connection between the contact pads (316a, 316b) of the light emitting diode chip 730 and conductive pads (742a, 742b) of the metal core printed circuit board 740d using one of reflow solder process, thermal cure, ultrasonic and ultraviolet methods or any other suitable methods. On top surface the metal core printed circuit board 740d and between the two conductive pads 742a and 742b, a metal mesa structure 748 may physically contact the passivation layer 722 resulting in an acceleration of heat dissipation from the flip light emitting diode chip 730 to the metal core printed circuit board 740d in operation.

[0053] Similar to the metal core printed circuit board 340h shown in FIG. 3(h), a metal core printed circuit board 740e has no metal mesa structure on its top surface as shown in FIG. 7(e). A space may exist between the flip light emitting diode chip 730 and the metal core printed circuit board 740e. To couple the flip light emitting diode chip 730 to the metal core printed circuit board 740e dielectric thermal-conductive material 744 may be filled in the space to improve thermal dissipation. Alternatively, the coupling between a flip light emitting diode chip and a metal core printed circuit board may be made by altering thickness of any of the first passivation layer 718, the reflective layer 720 and the second passivation layer 722 during the deposition and photolithography process. Example embodiments of altering thickness of the second passivation layer 722 are illustrated by FIGs. 8(a)-8(b) and FIGs. 9(a) and 9(b).

[0054] With reference to FIGs. 8(a) and 8(b), a metal core printed circuit board 840 having a metal mesa structure 848 with a lower surface than that of the first and second contact pads 316a and 316b may be assembled to a light emitting diode chip 830 having a thicker second passivation layer 822. With reference to FIGs. 9(a) and 9(b), a metal core printed circuit board 940 having a metal mesa structure 948 with a higher surface than that of the first and second contact pads 316a and 316b may be assembled to a light emitting diode chip 930 having a thinner second passivation layer 922.

[0055] The passivation layers, such as the passivation layers 318, 518, 618 and 718 and the second passivation layers 322, 722, 822 and 922 may include passivation material such as Si0₂, Si₃N₄, A1₂0₃, A1N, TiO or Ta₂0₅.

[0056] FIGs. 10(a)-10(c) are cross-sectional views to illustrate a method of fabricating a flip light emitting diode chipset 1000 according to one example embodiment of the present invention. The light emitting diode chipset 1000 including a plurality of light emitting diode dies, such as a light emitting diode die 1030a and a light emitting diode die 1030b. Each of the light emitting diode die is not limited to have a single passivation layer. Surface of the most upper layer is not limited to be at the same plane level as that of contact pads of each light emitting diode chip. In this embodiment, in order to describe concisely and briefly, the light emitting diode dies 1030a and 1030b are fabricated using the same fabrication process described in FIGs. 3(a)-3(f). Other fabrication processes described above may be used.

[0057] Referring to FIG. 10(a), the space 312 formed in FIG. 3(c) may separate the first light emitting diode die 1030a from the second light emitting diode die 1030b. The passivation layer 318 deposited over the wafer may cover sidewall 1032 and bottom wall 1034 of the space 312. A photolithography process may be applied to remove part of the passivation layer 318 on the sidewall 1032 of the space 312 to expose part of sidewall of the second contact pad 316b of the first light emitting diode die 1030a and part of sidewall of the first contact pad 316a of the second light emitting diode die 1030b, as illustrated in FIG. 10(b). As shown in FIG. 10(c), a layer of conductive material may then be deposited to cover surface of the passivation layer 318 in the space 312 thus electrically connecting the second contact pad 316b of the first light emitting diode die 1030a to the first contact pad 316a of the second light emitting diode die 1030b. A passivation layer 1018 may be applied over the second contact pad 316b of the first light emitting diode die 1030a, surface of the conductive material in the space 312 and the first contact pad 316a of the second light emitting diode die 1030b, as shown in FIG. 10(d). Hence, adjacent light emitting diode dies are electrically connected. A light emitting diode chipset is obtained. The light emitting diode chipset may be assembled to a metal core printed circuit board (not shown) by connecting a plurality of the first and second conduct pads 316a and 316b to a plurality of first and second conductive pads (not shown) of the metal core printed circuit board, respectively.

[0058] FIGS. 11(a) and 11(b) illustrate chip on board assemblies according to example embodiments of the present invention. As illustrated in FIG. 11(a), contact pads 1116a and 1116b of a light emitting diode chip 1130 face down. To attach the flip light emitting diode chip 1130 onto a metal core printed circuit board 1140, conductive bonders (not shown) are re-melted to produce an electric connection between the contact pads (1116a, 1116b) of the light emitting diode chip 1130 and conductive pads (1142a, 1142b) of the metal core printed circuit board 1140 using one of reflow solder process, thermal cure, ultrasonic and ultraviolet methods or any other suitable methods. The flip light emitting diode chip 1130 may physically contact the metal core printed circuit board 1140 as illustrated in FIG. 11(a). Alternatively, dielectric thermal- conductive material 1144 may be filled in a space between the flip light emitting diode chip 1130 and the metal core printed circuit board 1140, as illustrated in FIG. 11(b), to improve thermal dissipation.

[0059] Some embodiments may provide for techniques that mitigate the effects of misalignments in the fabrication process. For example, the production of metal core printed circuit board (MCPCB) may suffer from alignment inaccuracy between the conductive pads and the mesa structure. Standard MCPCB production usually has 25 micron to 50 micron of accuracy tolerance during the layer lamination process, and that means the correlative positions of the conductive pads and the mesa structure can be (e.g., are usually) misaligned by the accuracy tolerance. FIG. 12(a) shows an example MCPCB 1202 including a mesa structure 1204, conductive pads 1208a and 1208b, and dielectric layer 1206. The mesa structure 1204 is not positioned at the center between the conductive pads 1208a and 1208b. Misalignment by the accuracy tolerance may result in a bigger gap or area 1218a between the mesa structure 1204 and contact pad 1208a, and a smaller gap 1218b between the conductive pad 1208b and the mesa structure 1204. In contrast, as shown in the properly aligned MCPCB 340j of FIG. 3(j), the mesa structure 3404 is positioned at the center between the conductive pads 3408a and 3408b.

[0060] While bonding an LED die onto the MCPCB 1202, the contact pads of a LED die should be aligned with the positions of the conductive pads of the MCPCB to avoid resistance increase by loss coupling, i.e., the contact pads 1216a and 1216b of the LED die 1214 in FIG. 2(b) should be fully coupled to the conductive pads 1208a and 1208b, respectively. FIG. 12(b) shows a diagram of a light emitting diode device 1200 where a LED die 1214 is bonded onto the MCPCB 1202, which exhibits a common misalignment between the conductive pads 1208a and 1208b and the mesa structure 1204. Unfortunately, such misalignment can cause short-circuit damage in the area 1218b, and insufficient thermal dissipation in the area 1218a. In the area 1218b, both contact pad 1216b and conductive pad 1208b are closer to the mesa structure 1204 due to the misalignment, and the reduced gap could induce electrical arcing or leakage from either contact pad 1216b or conductive pad 1208b to the mesa structure 1204 while the LED die 1214 is powered up. In the area 1218a, a portion of the planar passivation contact window 1220 loses direct contact with the mesa structure 1204, and that may cause a hot spot (heat accumulated area) and results in an efficiency decrease in thermal dissipation.

[0061] To address issues caused by misalignment, some embodiments may include a flip light emitting diode (LED) device including a 3-pad LED die and a 3-pad pillar MCPCB. FIG. 13(a) shows a structural diagram of the 3-pad LED die 1302 that comprises a LED epitaxial substrate 1304, two contact pads 1316a and 1316b on the epitaxial substrate, a planar passivation contact window 1318 on the LED epitaxial substrate 1304 positioned between the two contact pads 1316a and 1316b, a thermal pad 1316c on the top and covering most surface of the planar passivation contact window 1318 with spatial separation from both contact pads 1316a and 1316b. Thermal pad 1316c is defined as a thermal path to couple the heat directly from the planar passivation contact window 1318, and electrically isolated from the contact pads 1316a and 1316b.

[0062] The materials of two contact pads 13116a and 1316b and the thermal pad 1316c can be at least one of Ti, Sn, Cu, Ni, Au, Cr, Al, Ag, W, Pt, and alloy such as Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge and Al-Si. The planar passivation contact window 1318 may include at least one of Si0₂, Si₃N₄, A1₂0₃, A1N, TiO and Ta₂0₅. [0063] FIG. 13(b) shows a structural diagram of the 3-pad pillar MCPCB 1320, which comprises a metal substrate 1322, a dielectric layer 1326 on the metal substrate 1322, a mesa structure 1324 extending from the metal substrate 1322 through the dielectric layer 1326 and having the same planar level to the dielectric layer 1326, a conductive pad 1328c on the top of the mesa structure 1324 covering the entire mesa structure 1324 and a portion of the dielectric layer 1326, and two conductive pads 1328a and 1328b on the dielectric layer 1326 positioned individually on each side of the conductive pad 1328c. Each of conductive pads 1328a, 1328b, and 1328c are electrically isolated via the gaps in between. The size of the conductive pad 1328c, the gap between conductive pads 1328a and 1328c, and the gap between conductive pads 1328b and 1328c are designed to coordinate with 3-pad LED die's thermal pad 1316c, gap between contact pad 1316a and thermal pad 1316c, and the gap between contact pad 1316b and thermal pad 1316c, respectively. The dimension of the mesa structure 1324 is designed to ensure that the conductive pad 1328c can fully cover the surface of the mesa structure 1324. In some embodiments, the dimension of the measure structure 1324 may be designed to ensure that the conductive pad 1328c can fully cover the surface of the mesa structure 1324 even in the event of the largest misalignment during the manufacture.

[0064] The materials of the conductive pads 1328a, 1328b, and 1328c can be at least one of Ti, Sn, Cu, Ni, Au, Cr, Al, Ag, W, Pt, and alloy such as Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al- Ge and Al-Si. The mesa structure 1324 may be made of thermal conductive material including at least one of metal, ceramic, solder paste and solder.

[0065] FIG. 13(c) shows a structural diagram of a light emitting diode device 1300 including a 3-pad LED die 1302 bonded to the 3-pad Pillar MCPCB 1320 without any misalignment. The contact pads 1316a and 1316b of the LED die 1302 are electrically coupled to the conductive pads 1328a and 1328b of the 3-pad Pillar MCPCB 1320, respectively. The thermal pad 1316c of the 3-pad LED die 1302 is thermally coupled to the conductive pad 1328c of the 3-pad Pillar MCPCB.

[0066] The contact pads 1316a and 1316b are bonded to the conductive pads 1328a and 1328b, respectively, by means of one of conductive bonders, conductive epoxy, eutectic contact, solder, solder paste, etc. The thermal pad 1316c is bonded to the conductive pad 1328c by means of one of conductive bonders, conductive epoxy, eutectic contact, solder, solder paste, etc. [0067] In this structure, the heat generated by the LED die 1302 can be dissipated sequentially through the planar passivation contact window 1318, thermal pad 1316c, conductive pad 1328c, mesa structure 1324 and finally into the metal substrate 1322.

[0068] FIG. 14(a) shows a structure diagram of a 3-pad Pillar MCPCB 1420 with a misalignment where the conductive pads 1438a, 1438b, and 1438c are shifted toward left, and the right edge of the conductive pad 1438c is aligned with the right edge of the mesa structure 1424. The 3-pad Pillar MCPCB 1420 may include a metal substrate 1404, a dielectric layer 1406 on the metal substrate, a mesa structure 1424 extending from the metal substrate through the dielectric layer and having the same planar level to the dielectric layer, a conductive pad 1438c on the top of the mesa structure 1424 covering the entire mesa structure and partial of the dielectric layer, and two conductive pads 1438a and 1438b on the dielectric layer positioning individually on each side of the conductive pad 1438c.

[0069] FIG. 14(b) shows a structural diagram of a light emitting diode device 1400 including a misalignment in the 3-pad Pillar MPCB. The dimensions and positions of the conductive pads 1438a, 1438b, and 1438c of the Pillar MCPCB 1420 may be configured to correspond with the dimensions and positions of the two contact pads 1416a, 1416b, and the thermal pad 1416c of the 3-pad LED die 1402. The bonding positions of the contact pads 1416a, 1416b, and thermal pad 1416c of the LED die 1402 may follow the misaligned positions of the conductive pads 1438a, 1438b, and 1438c, respectively. As a result, the gap between the mesa structure 1424 and the contact pad 1416b remains the same as that in the perfectly aligned case to prevent the short circuit damage. Meanwhile, the thermal pad 1416c is fully coupled to the conductive pad 1438c, and therefore the thermal energy can be fully dissipated sequentially through the planar passivation contact window 1418, thermal pad 1416c, conductive pad 1438c, mesa structure 1424 and finally the metal substrate 1404.

[0070] Many modifications and other example embodiments set forth herein will come to mind to one skilled in the art to which these example embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the embodiments are not to be limited to the specific ones disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing descriptions and the associated drawings describe example embodiments in the context of certain example combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions other than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

THAT WHICH IS CLAIMED:

1. A method of fabricating a light emitting diode device, comprising:

providing a substrate;

providing an epitaxial structure on the substrate, a first layer on the substrate, an active layer on the first layer and a second layer on the active layer;

depositing a conductive and reflective layer on the second layer of the epitaxial structure; forming an array of first trenches, a second trench on one side of the first trenches and a space on the other side of the first trenches, each of the first trenches and the second trench extending from surface of the conductive and reflective layer into the first layer to expose part of the first layer, the space extending from surface of the conductive and reflective layer to the substrate to expose part of the substrate;

depositing conductive material to cover a portion of surface of the conductive and reflective layer to form a first contact pad, and surfaces between adjacent first trenches to form a second contact pad, wherein the second contact pad electrically connects the first layer by filling the conductive material in the first trenches, and wherein the first contact pad is spatially separated from the second contact pad by the second trench; and

depositing a first passivation layer over uncovered portion of surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench, the first passivation layer comprising a first passivation material; and

depositing bonding material to cover a portion of surface of the first contact pad, a portion of the second contact pad and a portion of the first planar passivation contact to form a first light emitting diode bonding pad on the first contact pad, a second light emitting diode bonding pad on the second contact pad, and a third light emitting diode bonding pad on the first planar passivation contact, respectively.

2. The method of claim 1, further comprising:

applying a photolithography process to transfer patterns on a photomask to the conductive and reflective layer; and

selectively removing parts of the first layer, the active layer, the second layer and the conductive and reflective layer to form the array of the first trenches, wherein the patterns include at least one of column arrays, row arrays, bar arrays, grids and meshes.

3. The method of claim 1, further comprising applying a photolithography process subsequent to the deposition of the conductive material to selectively remove parts of the conductive material to form the first and second contact pads.

4. The method of claim 1, further comprising applying a planarization process and an etching process to the first contact pad, the second contact pad and the first passivation layer to obtain a desired thickness of the first passivation layer, wherein the first planar passivation contact surface is at the same plane level as, higher or lower than that of the first and second contact pads.

5. The method of claim 1, depositing the first passivation layer further comprising depositing the first passivation material over side wall and bottom wall of the second trench, side wall and bottom wall of the space.

6. The method of claim 1 further comprising depositing a reflective layer to cover a portion of the first passivation layer, the reflective layer including reflective material having reflective properties.

7. The method of claim 6, further comprising depositing one of an adhesion layer, a seed layer and a buffer layer prior to the deposition of the reflective layer.

8. The method of claim 6 further comprising:

depositing a second passivation layer subsequent to the deposition of the reflective layer to form a second planar passivation contact surface to cover surface of the reflective layer, the second passivation layer including a second passivation material; and

applying a planarization process and an etching process to the first contact pad, the second contact pad and the second passivation layer to obtain a desired thickness of the second passivation layer, wherein the second planar passivation contact surface is at the same plane level as, higher or lower than that of the first and second contact pads.

9. The method of claim 1, further comprising depositing one of adhesion layer, seed layer or buffer layer on the substrate prior to one of steps of providing the epitaxial structure, depositing the conductive and reflective layer and depositing the conductive material to form the contact pads.

10. The method of claim 1, further comprising a coating process to deposit bonding material on the first contact pad, the second contact pad and the first planar passivation contact surface to form a first light emitting diode bonding pad, a second light emitting diode bonding pad and a third light emitting diode bonding pad, respectively.

11. The method of claim 1, further comprising:

bonding the first contact pad to a first conductive pad of a metal core printed circuit board;

bonding the second contact pad to a second conductive pad of the metal core printed circuit board; and

bonding the first planar passivation contact to a third printed circuit board bonding pad of the metal core printed circuit board, wherein the metal core printed circuit board includes:

a metal core substrate,

a dielectric layer on the metal core substrate,

the first conductive pad formed above the dielectric layer,

the second conductive pad formed above the dielectric layer,

a mesa structure, extending from the metal core and positioning between the first conductive pad and the second conductive pad, and

the third printed circuit board bonding pad on the mesa structure surface.

12. The method of claim 1, wherein a surface of the third printed circuit board bonding pad is at the same plane level as surfaces defined by the first and second conductive pads.

13. The method of claim 1, wherein the surface of the mesa structure is at the same plane level as a surface of the dielectric layer.

A light emitting diode die comprising:

a substrate; an epitaxial structure on the substrate, the epitaxial structure comprising: a first layer having a first material;

an active layer on the first layer, the active layer having a second material; and a second layer on the active layer, the second layer having the first material, the first layer and the second layer including different types of doping, the first material having wider band gap than that of the second material;

a conductive and reflective layer deposited on the epitaxial structure;

a first contact pad formed on the conductive and reflective layer covering a portion of surface of the conductive and reflective layer;

a second contact pad covering surfaces between adjacent first trenches, the first trenches extending from the conductive and reflective layer into the first layer to expose part of the first layer, wherein the second contact pad electrically connects to the first layer by filling conductive material in the first trenches;

a second trench extending from the conductive and reflective layer to the first layer to expose part of the first layer, wherein the second trench and a portion of uncovered surface of the conductive and reflective layer spatially separates the first contact pad from the second contact pad;

a space extending from surface of the conductive and reflective layer to the substrate to expose part of the substrate, the first trenches formed between the second trench and the space;

a first passivation layer formed over uncovered surface of the conductive and reflective layer to form a first planar passivation contact surface between the first contact pad and the second trench, the first passivation layer comprising a first passivation material;

a first light emitting diode bonding pad, formed on the first contact pad covering a portion of surface of the first contact pad;

a second light emitting diode bonding pad, formed on the second contact pad covering a portion of surface of the second contact pad; and

a third light emitting diode bonding pad formed on the first planar passivation contact surface covering a portion of surface of the first planar passivation contact.

15. The light emitting diode die of claim 14, wherein the first trenches are formed by applying a photolithography process to: transfer patterns on a photomask to the conductive and reflective layer; and

selectively remove parts of the epitaxial structure and the conductive and reflective layer to form the first and second trenches, wherein the patterns comprise at least one of column array, row array, bar array, grids and meshes.

16. The light emitting diode die of claim 14 further comprises one of an adhesion layer, a seed layer and a buffer layer, wherein the one of the adhesion layer, seed layer and buffer layer is sandwiched between the substrate and the epitaxial structure, or between the conductive and reflective layer and the second layer.

17. The light emitting diode die of claim 14, wherein the substrate comprises at least one of A1₂0₃, SiC, ZnO, MgO, Ga₂0₃, AlGaN, GaLiO, AlLiO and Si.

18. The light emitting diode die of claim 14, wherein the first and second layer comprises at least one of doped gallium nitride and gallium arsenide.

19. The light emitting diode die of claim 14, wherein the active layer comprises at least one of indium gallium nitride, AlGaAs, GaP, AlInGaP and GaAsP.

20. The light emitting diode die of claim 14, wherein the conductive and reflective layer comprises at least one of Ag, Al, Rh, Ti, Ni, W, Mo, Cr, Pt and Pd or one of ln₂0₃, Sn0₂, IMO, ZnO, IZO, ITO, Ni, Au, Ti and Ni.

21. The light emitting diode die of claim 14, wherein at least one of the first and second contact pads comprises at least one of Ti, Ni, Au, Cr, Al and Ag.

22. The light emitting diode die of claim 14, further comprising one of an adhesion layer, a seed layer and a buffer layer sandwiched between the epitaxial structure and the conductive and reflective layer, wherein the adhesion layer, the seed layer and the buffer layer comprises at least one of Pt, Ti, Ni, Sb, Cr and WTi.

23. The light emitting diode die of claim 14, wherein the first planar passivation contact surface of the first passivation layer is at the same plane level as, higher or lower than that of the first and second contact pads and wherein the first passivation layer comprises at least one of Si02, Si₃N₄, A1₂0₃, A1N, TiO and Ta₂0₅.

24. The light emitting diode die of claim 14, further comprising a reflective layer covering a portion of the surface of the first passivation layer, wherein the reflective layer comprises at least one of Ag, Al, Rh, Ti, Ni, W, Mo, Cr, Pt and Pd.

25. The light emitting diode die of claim 24, further comprising a second passivation layer covering the reflective layer to form a second planar passivation contact surface, wherein the second planar passivation contact surface of the second passivation layer is at the same plane level as, higher or lower than that of the first and second contact pads and wherein the second passivation layer includes at least one of Si0₂, Si₃N₄, A1₂0₃, A1N, TiO and Ta₂0₅.

26. The light emitting diode die of claim 14, wherein the light emitting diode bonding pad comprises one of base metal and eutectic alloy.

27. The light emitting diode die of claim 26, wherein the base metal comprises at least one of gold, copper, bronze, silver, brass, tin, nickel, chromium, aluminum, platinum, titanium and tungsten,

28. The light emitting diode die of claim 26, wherein the eutectic alloy comprises at least one of Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge and Al-Si.

29. A light emitting diode device, comprising:

a light emitting diode die, comprising:

a first contact pad,

a first light emitting diode bonding pad on the first contact pad,

a second contact pad,

a second light emitting diode bonding pad on the second contact pad, a planar passivation contact surface, the planar passivation contact surface formed between the first contact pad and the second contact pad, and

a third light emitting diode bonding pad on the planar passivation contact surface; and

a metal core printed circuit board, comprising:

a metal core substrate,

a dielectric layer on the metal core substrate, a first conductive pad, the first conductive pad formed above the dielectric layer, a first printed circuit board bonding pad on the first conductive pad surface, a second conductive pad formed above the dielectric layer,

a second printed circuit board bonding pad on the second conductive pad surface, a mesa structure, extending from the metal core and positioning between the first conductive pad and the second conductive pad, and

a third printed circuit board bonding pad on the mesa structure surface, wherein the first light emitting diode bonding pad, the second light emitting diode bonding pad and the third light emitting diode bonding pad of the light emitting diode die are bonded to the first printed circuit board bonding pad, the second printed circuit board bonding pad, and the third printed circuit board bonding pad of the metal core printed circuit board respectively, wherein the first contact pad and the second contact pad of the light emitting diode die are electrically connected to the first conductive pad and the second conductive pad of the metal core printed circuit board respectively, and wherein the planar passivation contact surface is thermally coupled with the mesa structure.

30. The light emitting diode device of claim 29, wherein the first, second and third light emitting diode bonding pads are bonded to the first, second and third printed circuit board bonding pads respectively by means of one of conductive bonders, conductive epoxy, eutectic contact, solder and solder paste.

31. The light emitting diode device of claim 29, wherein the mesa structure is made of thermal conductive material including at least one of metal, ceramic, solder paste and solder.

32. The light emitting diode device of claim 29, wherein the printed circuit board bonding pad comprises one of base metal and eutectic alloy.

33. The light emitting diode device of claim 29, wherein the base metal comprises at least one of gold, copper, bronze, silver, brass, tin, nickel, chromium, aluminum, platinum, titanium and tungsten,

34. The light emitting diode device of claim 33, wherein the eutectic alloy comprises at least one of Au-In, Cu-Sn, Au-Sn, Au-Ge, Au-Si, Al-Ge and Al-Si.

35. The light emitting diode device of claim 29, wherein a surface of the third printed circuit board bonding pad is at the same plane level as surfaces defined by the first and second conductive pads.

36. The light emitting diode device of claim 29, the surface of the mesa structure is at the same plane level as a surface of the dielectric layer.