WO2015141773A1 - Current driver, and driving method of current driver - Google Patents

Abstract

A power supply line configuration unit configures a writing level in a power supply line, and a select line configuration unit configures a conduction level in a select line, and thereby, a hold voltage corresponding to the writing level is held in a holding capacitor. Further, the power supply configuration unit configures a drive level in the power supply line, and in the select line, the select line configuration unit configures a non-conductive level which is between a first level at which the on-state current of the holding transistor is reached and a second level in which the off-state current of the holding transistor is reached, and thereby, on the basis of the drive level, a drive transistor passes to a current drive element a current corresponding to the hold voltage.

Description

Current driving device and driving method of current driving device

The technology of the present disclosure relates to a current driving device including a holding transistor that holds a voltage for driving the driving transistor in a holding capacitor, and a driving method of the current driving device.

An electroluminescence (EL) device includes, for example, a plurality of EL elements arranged in a matrix, and each of the plurality of EL elements is connected to different pixel circuits. Each of the plurality of pixel circuits includes, for example, a drive transistor, a storage capacitor connected between the gate and the source of the drive transistor, a storage transistor connected to both electrodes of the storage capacitor, and a selection transistor.

The drive transistor constituting the pixel circuit is connected to the power supply driver through the power supply line, and a drive current corresponding to the holding voltage of the storage capacitor flows from the power supply line to the EL element. The selection transistor constituting the pixel circuit is connected to one of the two electrodes of the holding capacitor and the data line, and the holding transistor constituting the pixel circuit is connected to the other of the two electrodes of the holding capacitor and the power line. Yes. The holding transistor and the selection transistor selected by the selection driver hold the voltage corresponding to the difference between the light emission level of the power supply line and the gradation level of the data line in the holding capacitor (for example, Patent Document 1 and , See Patent Document 2).

JP 2003-195810 A JP 2012-73498 A

By the way, a thin film transistor such as a holding transistor may have a defect in the channel, and the defect included in the channel is one factor that causes an off current to flow through the thin film transistor in an off state. Then, when an off-current flows through the holding transistor that connects the power supply line and the holding capacitor, the current value of the current flowing through the driving transistor is different from the current value based on the gradation data. As a result, control defects such as a bright spot defect in the black display of the EL element and a dark spot defect in the white display of the EL element occur.

It is an object of the technology of the present disclosure to provide a current driving device capable of suppressing the occurrence of control defects and a driving method of the current driving device.

One aspect of the current driving device in the technology of the present disclosure includes a current driving element, a power supply line, a storage capacitor, a selection line, a first gate, a first terminal connected to the current driving element, A second terminal connected to the power supply line, the first gate having a drive transistor connected to the first terminal via a storage capacitor, and a second gate connected to the selection line. And a holding transistor that changes conduction and non-conduction between the first gate and the second terminal according to a voltage level of the selection line, and a voltage level of the power supply line. A power line setting unit; and a selection line setting unit configured to set a voltage level of the selection line. The power supply line setting unit is configured to perform a writing operation and a driving operation. In the write operation, the power supply line setting unit sets a write level for the power supply line, and the selection line setting unit sets a conduction level for the selection line, thereby setting the write level. And holding the holding voltage corresponding to the above in the holding capacitor. In the driving operation, the power supply line setting unit sets a drive level for the power supply line, and the selection line setting unit includes a first level for raising an on-current of the holding transistor, and the holding By setting a non-conduction level between the second level for raising the off-state current of the transistor to the selection line, a current corresponding to the holding voltage is caused to flow to the current driving element based on the driving level. To cause the driving transistor to perform the following.

One aspect of the driving method of the current driver according to the technique of the present disclosure includes a first gate, a first terminal connected to the current driver element, and a second terminal connected to a power supply line. One gate has a driving transistor connected to the first terminal via a storage capacitor, and a second gate connected to a selection line, and conduction between the first gate and the second terminal And a non-conductive transistor that changes according to the voltage level of the selection line, a power supply line setting unit that sets the voltage level of the power supply line, and a selection line setting unit that sets the voltage level of the selection line A driving method of a current driving device, wherein the power supply line setting unit sets a write level for the power supply line, and the selection line setting unit sets a conduction level for the selection line, thereby The holding voltage corresponding to the write level is Comprising to be held in the serial holding capacity. The power supply line setting unit sets a drive level for the power supply line, and the selection line setting unit sets a first level for raising the on-current of the holding transistor and an off-current of the holding transistor. A non-conduction level between the second level to be raised is set in the selection line, whereby the driving transistor causes a current corresponding to the holding voltage to flow to the current driving element based on the driving level. Prepare.

According to one aspect of the technology of the present disclosure, since the level of the selection line in the driving operation is between the first level and the second level, it is possible to suppress an off current from flowing through the holding transistor in the driving operation. As a result, the occurrence of control defects in the current driver is suppressed.

In another aspect of the current driver according to the technique of the present disclosure, the selection line is a first selection line, the non-conduction level is a first non-conduction level, and the selection line setting unit is a first selection line. It is a line setting unit. A second selection line; a data line; and a third gate connected to the second selection line, the thin film transistor having the same channel type as the holding transistor, and the first terminal and the data line A selection transistor that changes between conduction and non-conduction in accordance with a voltage level of the second selection line; a data line setting unit configured to set a voltage level of the data line; And a second selection line setting unit configured to set the voltage level. In the write operation, the data line setting unit sets a gradation level for the data line, and the second selection line setting unit sets a conduction level for the second selection line, The holding voltage corresponding to the difference between the writing level set by the power supply line setting unit and the gradation level set by the data line setting unit is held in the holding capacitor. In the driving operation, when the first selection line setting unit sets the first non-conduction level to the first selection line, the second selection line setting unit is the first non-conduction level. It is preferable to set a second non-conduction level, which is a different non-conduction level, in the second selection line.

According to another aspect of the current driving device in the technology of the present disclosure, the voltage level of the first selection line in the driving operation and the voltage level of the second selection line in the driving operation are different from each other. The second selection line is not forced to be applied with the first non-conducting level for suppressing the flow of.

In another aspect of the current driver according to the technology of the present disclosure, the gradation level has the same polarity as the non-conduction level of the second selection line, and the absolute value of the first non-conduction level is the second non-conduction level. It may be smaller than the absolute value of the conduction level.

It is preferable that the difference between the voltage level of the second gate and the drive level is small in order to suppress the off current from flowing through the holding transistor in the drive operation. In order to suppress the off current from flowing through the selection transistor in the driving operation, it is preferable that the difference between the voltage level of the third gate and the gradation level is small. In this regard, according to another aspect of the current driver in the technology of the present disclosure, the voltage level of the first selection line and the voltage level of the second selection line are set separately, so the voltage of the second gate It is possible to reduce both the difference between the level and the drive level and the difference between the voltage level of the third gate and the gradation level.

In another aspect of the current driver according to the technology of the present disclosure, the conduction level of the first selection line is a first selection level, the conduction level of the second selection line is a second selection level, The one selection level is preferably equal to the second selection level.

According to another aspect of the current driver in the technology of the present disclosure, the first selection level set for the first selection line and the second selection level set for the second selection line are equal to each other. The circuit configuration for generating the first selection level and the second selection level can be simplified.

In another aspect of the current drive device according to the technology of the present disclosure, the current drive element is an EL element.
In another aspect of the current drive device according to the technology of the present disclosure, the current drive element is a sensor element.

According to the current driving device and the driving method of the current driving device in the technology of the present disclosure, the occurrence of control defects can be suppressed.

It is a block diagram which shows the structure of EL device in one Embodiment of EL device in the technique of this indication, Comprising: It is a figure shown in the state which planarly viewed the EL panel. It is an electric circuit diagram which shows an example of the electrical constitution which the pixel in one Embodiment has. It is a timing chart which shows an example of the operation transition of the pixel in one embodiment. FIG. 3 is a circuit diagram showing a pixel circuit according to an embodiment together with voltage levels of nodes, and is a diagram showing a state during a writing operation in black display. It is a circuit diagram which shows the pixel circuit in one Embodiment with the voltage level of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in black display. FIG. 6 is a circuit diagram showing a pixel circuit according to an embodiment together with a voltage level of each node, and is a diagram showing a state during a writing operation in white display. It is a circuit diagram which shows the pixel circuit in one Embodiment with the voltage level of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in white display. It is a characteristic view which shows the characteristic line of the drive transistor in one Embodiment, Comprising: It is a figure which shows a characteristic line when a drive transistor is diode-connected. It is a graph which shows the load line of the EL element in one Embodiment. It is a characteristic view which shows the characteristic line of the drive transistor in one Embodiment, Comprising: It is a figure which shows a characteristic line when the diode connection of a drive transistor is cancelled | released. FIG. 4 is a characteristic diagram illustrating a characteristic line of a driving transistor according to an embodiment, and illustrates a load line of an EL element together with a characteristic line of the driving transistor in association with a difference between a light emission voltage and a reference voltage. FIG. 4 is a characteristic diagram illustrating a characteristic line of a driving transistor according to an embodiment, and illustrates a load line of an EL element together with a characteristic line of the driving transistor in association with a difference between a light emission voltage and a reference voltage. It is an electric circuit diagram which shows an example of the electrical constitution which the pixel in a reference example has. It is a circuit diagram which shows the pixel circuit in a reference example with the voltage level of each node, Comprising: It is a figure which shows the state at the time of the write-in operation | movement in black display. It is a circuit diagram which shows the pixel circuit in a reference example with the voltage level of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in black display. It is a circuit diagram which shows the pixel circuit in a reference example with the voltage level of each node, Comprising: It is a figure which shows the state at the time of write-in operation | movement in white display. It is a circuit diagram which shows the pixel circuit in a reference example with the voltage level of each node, Comprising: It is a figure which shows the state at the time of the light emission operation | movement in white display. 4 is a timing chart showing an example of an operation flow in an i-th row pixel and an operation flow in an (i + 1) -th row pixel of the EL device according to the embodiment. 4 is a time chart illustrating an example of an operation flow in an upper pixel group and an operation flow in a lower pixel group included in an EL device according to an embodiment. 4 is a graph showing a relationship between a gate-source voltage and an on-current of a thin film transistor and a relationship between a gate-source voltage and an off-current in an embodiment. It is a graph which shows the relationship between the gate-drain voltage and off-state current of the selection transistor in one Embodiment. It is an electric circuit diagram which shows an example of the electrical constitution which the drive circuit in a modification has.

With reference to FIG. 1 to FIG. 21, an EL device and a driving method of the EL device according to an embodiment embodying the technique of the present disclosure will be described.
[EL device 100]
An example of the configuration of the EL device will be described with reference to FIG.

As shown in FIG. 1, the EL device 100 includes a display signal generation unit 110, a system controller 120, a first selection driver 130A, a second selection driver 130B, a data driver 140, a power supply driver 150, and an EL panel 160. Yes.

The first selection driver 130A is an example of a first selection line setting unit configured to set the voltage level of the first selection line. The second selection driver 130B is an example of a second selection line setting unit configured to set the voltage level of the second selection line. The data driver 140 is an example of a data line setting unit configured to set the voltage level of the data line. The power supply driver 150 is an example of a power supply line setting unit configured to set the voltage level of the power supply line.

The display signal generation unit 110 accepts the video signal SIG from the outside of the EL device 100, extracts the gradation voltage component included in the video signal SIG from the video signal SIG, and the gradation voltage component is a digital signal as gradation data D1. Convert to Then, the display signal generation unit 110 outputs the gradation data D1 for each row of the EL panel 160 to the data driver 140 in the order of the row numbers. The display signal generation unit 110 extracts or generates a timing signal SCLK such as a system clock for displaying an image based on the gradation data D1 on the EL panel 160, and outputs the timing signal SCLK to the system controller 120. When the video signal SIG includes a timing signal component that defines the display timing of an image, such as a composite video signal such as a television broadcast signal, for example, the display signal generation unit 110 has a function of extracting a gradation voltage component. In addition, the timing signal component is extracted and output to the system controller 120.

Based on the timing signal SCLK output from the display signal generation unit 110, the system controller 120 generates a selection control signal SCON1 for controlling the driving of the first selection driver 130A and the second selection driver 130B. The selection control signal SCON1 is output to the first selection driver 130A and the second selection driver 130B. Based on the timing signal SCLK output from the display signal generation unit 110, the system controller 120 generates a data control signal SCON2 for controlling the driving of the data driver 140, and outputs the data control signal SCON2 to the data driver 140. To do. Based on the timing signal SCLK output from the display signal generation unit 110, the system controller 120 generates a power control signal SCON3 for controlling driving of the power driver 150, and outputs the power control signal SCON3 to the power driver 150. To do.

The EL panel 160 includes a plurality of first selection lines Ls1 extending along the row direction which is one direction, a plurality of second selection lines Ls2 extending along the row direction, and a plurality of extensions extending along the row direction. A power supply line Lv and a plurality of data lines Ld extending along a column direction which is a direction orthogonal to the row direction are provided. In plan view, the pixel PIX is located in the vicinity of a portion where each of the plurality of first selection lines Ls1 and each of the plurality of second selection lines Ls2 and each of the plurality of data lines Ld intersects. The pixels PIX are located in a matrix composed of n rows × m columns (n and m are arbitrary positive integers).

Each of the plurality of first selection lines Ls1 is electrically connected to the first selection driver 130A, and the plurality of pixels PIX located in a matrix are connected to each first selection line Ls1 by one row of pixels PIX. Yes.

Each of the plurality of second selection lines Ls2 is electrically connected to the second selection driver 130B, and the plurality of pixels PIX located in a matrix are connected to each second selection line Ls2 by one pixel PIX. Yes.

Each of the plurality of data lines Ld is electrically connected to the data driver 140, and the plurality of pixels PIX located in a matrix are connected to each data line Ld by one column of pixels PIX.

The plurality of pixels PIX located in a matrix form includes an upper pixel group composed of a plurality of pixels PIX located in the upper half in the vertical direction in FIG. 1 and a plurality of pixels located in the lower half in the vertical direction in FIG. It is divided into a lower pixel group consisting of PIX. The plurality of pixels PIX constituting the upper pixel group are connected to each power line Lv by one row of pixels PIX, and the plurality of power lines Lv connected to the plurality of pixels PIX constituting the upper pixel group are connected to the power driver 150. Commonly connected to The plurality of pixels PIX constituting the lower pixel group are connected to each power line Lv by one pixel PIX, and the plurality of power lines Lv connected to the plurality of pixels PIX constituting the lower pixel group are Are also commonly connected to the power supply driver 150.

The first selection driver 130A includes a shift register. For example, based on the selection control signal SCON1 output from the system controller 120, the shift register selects a target line selected from the plurality of first selection lines Ls1 as the row number of the plurality of first selection lines Ls1. A shift signal for sequentially shifting is output. The first selection driver 130A includes an output buffer. The output buffer generates the first selection signal Vsel1 obtained by converting the voltage level of the shift signal to the selection level H, and outputs the first selection signal Vsel1 to the first selection line Ls1 of the row selected by the shift signal.

Based on the selection control signal SCON1 output from the system controller 120, the first selection driver 130A outputs the first selection signal Vsel1 set to the selection level H to each of the plurality of first selection lines Ls1 in the order of row numbers. Then, each of the plurality of pixels PIX is set to a selected state one by one. For example, the first selection driver 130A outputs the first selection signal Vsel1 set to the selection level H to the first selection line Ls1 in the specific row in the writing operation of the pixel PIX located in the specific row. Then, the first selection driver 130A executes the output of the first selection signal Vsel1 at the selection level H one row at a time in the row number order, and sets each of the plurality of pixels PIX in the selected state one row at a time in the row number order. To do.

The second selection driver 130B includes a shift register. For example, based on the selection control signal SCON1 output from the system controller 120, the shift register selects the target line selected from the plurality of second selection lines Ls2 as the row number of the plurality of second selection lines Ls2. A shift signal for sequentially shifting is output. The second selection driver 130B includes an output buffer. The output buffer generates a second selection signal Vsel2 obtained by converting the voltage level of the shift signal to the selection level H, and outputs the second selection signal Vsel2 to the second selection line Ls2 selected by the shift signal.

Based on the selection control signal SCON1 output from the system controller 120, the second selection driver 130B inputs the second selection signal Vsel2 set to the selection level H to each of the plurality of second selection lines Ls2 in the order of row numbers. Then, each of the plurality of pixels PIX is set to a selected state one by one. For example, the second selection driver 130B outputs the second selection signal Vsel2 set to the selection level H to the second selection line Ls2 in the specific row in the writing operation of the pixel PIX located in the specific row. Then, the second selection driver 130B executes the output of the second selection signal Vsel2 at the selection level H one row at a time in the row number order, and sets each of the plurality of pixels PIX in the selected state one row at a time in the row number order. To do.

For example, based on the data control signal SCON2 output from the system controller 120, the data driver 140 shifts the gradation data for each pixel PIX output from the display signal generation unit 110 by one line in the order of application numbers. It has a register. In addition, the data driver 140 includes a data latch unit that holds the data of each column included in the gradation data fetched into the shift register in one column. In addition, the data driver 140 generates a gradation level Vdata of each column, which is a voltage level corresponding to the gradation data of each column held in the data latch unit, and converts the gradation voltage of each column to the corresponding column. Output circuit for outputting to the data line Ld.

The data driver 140 sequentially holds the gradation data of each pixel PIX input from the display signal generation unit 110 line by line. Next, the data driver 140 generates a gradation level Vdata of each column that is a voltage level corresponding to the gradation data, and outputs a signal of the gradation level Vdata to the data line Ld of each column all at once.

The power supply driver 150 includes a timing generator that generates a timing signal corresponding to each of the two pixel groups based on, for example, the power supply control signal SCON3 output from the system controller 120. The power supply driver 150 converts the timing signal generated by the timing generator into a predetermined voltage level based on the power supply control signal SCON3 output from the system controller 120, and supplies it to the power supply lines Lv of the two pixel groups. An output buffer for outputting the power supply signal Vcc is provided.

Based on the power supply control signal SCON3 output from the system controller 120, the power supply driver 150 is configured to write each of the plurality of power supply lines Lv connected to the specific pixel group in the writing operation of the pixel PIX configuring the specific pixel group. Write level Vccw is set as the voltage level. For example, the power supply driver 150 sets the write level Vccw to the voltage level of the plurality of power supply lines Lv connected to the upper pixel group in the write operation of the pixels PIX constituting the upper pixel group. On the other hand, in the light emission operation of the pixel PIX constituting the specific pixel group, the power supply driver 150 has a light emission level different from the write level Vccw at each voltage level of the plurality of power supply lines Lv connected to the specific pixel group. Set Vcss. For example, the power supply driver 150 sets the light emission level Vcss to the voltage level of the plurality of power supply lines Lv connected to the upper pixel group in the light emission operation of the pixels PIX constituting the upper pixel group.

[Configuration and Operation of Pixel PIX]
An example of the configuration and operation of the pixel PIX will be described with reference to FIG. 2 and FIG.
As shown in FIG. 2, each of the plurality of pixels PIX includes an EL element OEL that is a current-driven light emitting element, and a pixel circuit DC for driving the EL element OEL. The pixel circuit DC includes a drive transistor T1, a holding transistor T2, a selection transistor T3, and a holding capacitor Cs.

The drive transistor T1 is an n-channel transistor, and the gate of the drive transistor T1, which is an example of the first gate, is electrically connected to the node N1. The source of the driving transistor T1 is electrically connected to the anode of the EL element OEL through the node N2, and the drain of the driving transistor T1 is electrically connected to the power supply line Lv through the node N3. The drive transistor T1 has a function of flowing a drive current corresponding to the voltage between the gate and the source of the drive transistor T1 to the EL element OEL based on the voltage level of the power supply line Lv.

The anode of the EL element OEL is electrically connected to the node N2 in the pixel circuit DC, and a reference level Vss such as a ground voltage is set as the cathode voltage level of the EL element OEL.

Among the two electrodes of the storage capacitor Cs, the first electrode is electrically connected to the node N1, and among the two electrodes of the storage capacitor Cs, the second electrode is electrically connected to the node N2. The storage capacitor Cs may be a parasitic capacitor formed between the gate of the driving transistor T1 and the source of the driving transistor T1, or may be a capacitive element provided separately between the node N1 and the node N2. Or a combination thereof. The holding capacitor Cs has a function of holding the voltage between the gate and the source of the driving transistor T1.

The holding transistor T2 is an n-channel transistor, and the gate of the holding transistor T2, which is an example of the second gate, is electrically connected to the first selection line Ls1 through the node N4. The drain of the holding transistor T2 is electrically connected to the power supply line Lv through the node N3, and the source of the holding transistor T2 is electrically connected to the node N1. The holding transistor T2 has a function of selecting whether or not the drive transistor T1 is diode-connected based on the voltage level of the first selection signal Vsel1 in the first selection line Ls1.

The selection transistor T3 is an n-channel transistor, and the gate of the selection transistor T3, which is an example of the third gate, is electrically connected to the second selection line Ls2. The source of the selection transistor T3 is electrically connected to the data line Ld, and the drain of the selection transistor T3 is electrically connected to the node N2. The selection transistor T3 has a function of selecting whether to electrically connect the source of the driving transistor T1 and the data line Ld based on the voltage level of the second selection signal Vsel2 in the second selection line Ls2. . The selection transistor T3 has a function of holding a voltage corresponding to the gradation level Vdata in the holding capacitor Cs in cooperation with the driving transistor T1 and the holding transistor T2.

As shown in FIG. 3, the operation of the pixel PIX includes a writing operation performed by the power supply setting unit, a holding operation, and a light emitting operation that is an example of a driving operation. The pixel PIX includes the writing operation and the holding operation. These are repeated in the order of the light emitting operation.

In the write operation in the pixel PIX, the first selection driver 130A and the second selection driver 130B set the selection level H to the voltage level Vhld of the first selection line Ls1 and the second selection line Ls2, and the holding transistor T2 and select transistor T3 transition to the on state. In the writing operation in the pixel PIX, the power supply driver 150 sets the power supply signal Vcc to the write level Vccw, and the holding transistor T2 and the selection transistor T3 apply a voltage corresponding to the gradation level Vdata to the holding capacitor Cs. Write to.

In the holding operation in the pixel PIX, the first selection driver 130A and the second selection driver 130B are not selected as an example of a non-conduction level to the voltage level Vhld of the first selection line Ls1 and the second selection line Ls2. The level L is set, and the holding transistor T2 and the selection transistor T3 transition from the on state to the off state. In the holding operation in the pixel PIX, the power driver 150 keeps the power signal Vcc at the writing level Vccw, and the holding transistor T2 and the selection transistor T3 hold the voltage at the writing operation in the holding capacitor Cs.

In the light emission operation in the pixel PIX, the first selection driver 130A and the second selection driver 130B keep the voltage level Vhld of the first selection line Ls1 and the second selection line Ls2 at the non-selection level L, and the holding transistor T2 , And the selection transistor T3 maintains the off state. In the light emission operation in the pixel PIX, the power supply driver 150 changes the power supply signal Vcc from the write level Vccw to the light emission level Vcss which is an example of the drive level, and the drive transistor T1 corresponds to the voltage held by the storage capacitor Cs. The drive current is supplied to the EL element OEL based on the difference between the light emission level Vcss and the reference level Vss.

[Gate-drain voltage Vgd in black display]
With reference to FIG. 4 and FIG. 5, an example of the voltage level of each terminal during the black display write operation and an example of the voltage level of each terminal during the black display light emission operation will be described.

As shown in FIG. 4, in the writing operation in the black display, the first selection driver 130A inputs the first selection signal Vsel1 in which 15V, which is an example of the first selection level H1, is set to the gate of the holding transistor T2. Then, the holding transistor T2 is changed to the ON state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, and the driving transistor T1 is diode-connected.

Further, in the writing operation in black display, the second selection driver 130B inputs 15V, which is an example of the second selection level H2 and equal to the first selection level H1, to the gate of the selection transistor T3 as the second selection signal Vsel2. Then, the selection transistor T3 is turned on. As a result, the source and drain of the select transistor T3 become conductive, and the source of the drive transistor T1 and the data line Ld are electrically connected.

At this time, the first selection level H1 set for the first selection line Ls1 and the second selection level H2 set for the second selection line Ls2 have the same polarity and are absolute. The values are equal to each other. Therefore, in the first selection driver 130A and the second selection driver 130B, these circuit configurations are simplified, such as sharing the power supply circuit for generating the first selection level H1 and the second selection level H2. Is possible.

On the other hand, the power supply driver 150 is an example of the write level Vccw, and sets 0V equal to the reference level Vss to the voltage level of the power supply line Lv. The data driver 140 is an example of the gradation level Vdata for black display, and sets 0 V equal to the reference level Vss. As a result, the level of the source of the driving transistor T1 is set to 0V, and the voltage level of the gate of the driving transistor T1 becomes equal to the voltage level of the drain of the driving transistor T1. Since the drain-source voltage Vds of the driving transistor T1 is 0 V, the drain-source current Ids does not flow. At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is equal to the gate-source voltage Vgs, and 0V is written to the storage capacitor Cs as the gate-source voltage Vgs. It is.

In the holding operation in the black display, the first selection driver 130A inputs the first selection signal Vsel1 set to −2V, which is an example of the first non-selection level L1, to the gate of the holding transistor T2, and sets the holding transistor T2 Transition to the off state. As a result, the gate of the drive transistor T1 and the drain of the drive transistor T1 become non-conductive, and the diode connection in the drive transistor T1 is released. The first non-selection level L1 is an example of the first non-conduction level.

In the holding operation in the black display, the second selection driver 130B is an example of the second non-selection level L2, and is a second selection signal that is set to −14V that is a voltage level lower than the first non-selection level L1. Vsel2 is input to the gate of the selection transistor T3 to cause the selection transistor T3 to transition to the off state. As a result, the source and drain of the selection transistor T3 become non-conductive, and the electrical connection between the source of the driving transistor T1 and the data line Ld is released. The second non-selection level L2 is an example of the second non-conduction level.

As shown in FIG. 5, in the light emission operation in black display, the first selection driver 130A inputs the first selection signal Vsel1 set to −2V, which is an example of the first non-selection level L1, to the gate of the holding transistor T2. Then, the holding transistor T2 is maintained in the off state. Thereby, the non-conduction between the gate of the driving transistor T1 and the drain of the driving transistor T1 is maintained, and the diode connection in the driving transistor T1 is continuously released.

On the other hand, the second selection driver 130B selects the second selection signal Vsel2 set to −14V, which is an example of the second non-selection level L2 and is a voltage level lower than the first non-selection level L1. The selection transistor T3 is maintained in the OFF state by continuing input to the gate of T3. As a result, the non-conduction between the source and drain of the selection transistor T3 is maintained, and the electrical connection between the source of the driving transistor T1 and the data line Ld continues to be released.

On the other hand, the power supply driver 150 has a polarity opposite to that of the first non-selection level L1 and the second non-selection level L2 and higher than the reference level Vss in order to drive the drive transistor T1 in the saturation region. A level of 15V is set to the power supply line Lv as an example of the light emission level Vcss. Thereby, the voltage level of the drain of the driving transistor T1 is set higher than the source of the driving transistor T1. However, since the gate-source voltage Vgs held in the holding capacitor Cs is 0 V, the drain-source current Ids does not flow between the drain and source of the driving transistor T1, and the EL element OEL does not emit light.

At this time, the voltage level of the gate of the holding transistor T2 is a negative voltage having the same polarity as the second non-selection level L2, and has an absolute value smaller than the second non-selection level L2. The first non-selection level L1 (-2V) is set. Therefore, a voltage corresponding to the difference (−17V) between the first non-selection level L1 and the light emission level Vcss (15V) is applied between the gate of the holding transistor T2 and the node N3. 2 Less than a voltage (-29V) corresponding to the difference between the non-selection level L2 (-14V) and the light emission level Vcss (15V). As a result, the voltage between the gate of the holding transistor T2 and the node N3 can be suppressed as compared with the configuration in which the gate of the holding transistor T2 and the gate of the selection transistor T3 are selected by one second selection line Ls2. Is possible.

The first non-selection level L1 (-2V) is a first level (a level at which the on-current of the holding transistor T2 rises among the voltage levels of the gate of the holding transistor T2 after the black display write operation). 0V) and the second level (−10V) that raises the off-state current of the holding transistor T2. Therefore, a leakage current due to the voltage level of the gate of the holding transistor T2 flows to the holding transistor T2, and the voltage level of the node N1 rises toward the voltage level of the node N3. Occurrence is suppressed.

Further, since the first non-selection level L1 and the second non-selection level L2 are different from each other, the application of the first non-selection level L1 for suppressing the off-current from flowing through the holding transistor T2 is applied to the second selection line Ls2. There is no force.

[Gate-drain voltage Vgd in white display]
With reference to FIG. 6 and FIG. 7, an example of the voltage level of each terminal during the white display writing operation and an example of the voltage level of each terminal during the white display light emitting operation will be described.

As shown in FIG. 6, in the writing operation in the white display, the first selection driver 130A inputs the first selection signal Vsel1 set to 15V, which is an example of the first selection level H1, to the gate of the holding transistor T2. Then, the holding transistor T2 is changed to the ON state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, and the driving transistor T1 is diode-connected.

The second selection driver 130B inputs the second selection signal Vsel2 set to 15V, which is an example of the second selection level H2, to the gate of the selection transistor T3, and causes the selection transistor T3 to transition to the on state. As a result, the source and drain of the select transistor T3 become conductive, and the source of the drive transistor T1 and the data line Ld are electrically connected.

At this time, as in the black display writing operation, the first selection level H1 set on the first selection line Ls1 and the second selection level H2 set on the second selection line Ls2 are mutually different. They have the same polarity and absolute values are equal to each other. Therefore, whether black display or white display, the first selection driver 130A and the second selection driver 130B are power supply circuits for generating the first selection level H1 and the second selection level H2 in the write operation. These circuit configurations can be simplified, such as common use.

On the other hand, the power supply driver 150 is an example of the write level Vccw, and sets 0V equal to the reference level Vss to the voltage level of the power supply line Lv. The data driver 140 applies −12V, which is the same polarity as the first non-selection level L1 and the second non-selection level L2 and lower than the reference level Vss, to the data line Ld as a gray level Vdata for white display. Set. As a result, the voltage level of the source of the driving transistor T1 is set to −10V, and the voltage level of the gate of the driving transistor T1 becomes equal to the voltage level of the drain of the driving transistor T1. Then, a voltage of 10 V is written in the storage capacitor Cs as the gate-source voltage Vgs.

At this time, the data driver 140 sets the gradation level Vdata so that the voltage level of the node N2 that is the anode of the EL element OEL is lower than the reference level Vss that is the voltage level of the cathode of the EL element OEL. It is set to -12V. Then, the data driver 140 sets a reverse bias between both electrodes of the EL element OEL, and suppresses the drain-source current Ids of the drive transistor T1 from flowing through the EL element OEL.

In the holding operation in the white display, the first selection driver 130A inputs the first selection signal Vsel1 set to −2V, which is an example of the first non-selection level L1, to the gate of the holding transistor T2, and sets the holding transistor T2 Transition to the off state. As a result, the gate of the drive transistor T1 and the drain of the drive transistor T1 become non-conductive, and the diode connection in the drive transistor T1 is released.

In the holding operation in the white display, the second selection driver 130B is an example of the second non-selection level L2, and is a second selection signal Vsel2 set to −14V, which is a level lower than the first non-selection level L1. Is input to the gate of the selection transistor T3, and the selection transistor T3 is turned off. As a result, the source and drain of the selection transistor T3 become non-conductive, and the electrical connection between the source of the driving transistor T1 and the data line Ld is released.

As shown in FIG. 7, in the light emission operation in white display, the first selection driver 130A inputs the first selection signal Vsel1 set to −2V, which is an example of the first non-selection level L1, to the gate of the holding transistor T2. Then, the holding transistor T2 is maintained in the off state. Thereby, the non-conduction between the gate of the driving transistor T1 and the drain of the driving transistor T1 is maintained, and the diode connection in the driving transistor T1 is continuously released.

On the other hand, the second selection driver 130B selects the second selection signal Vsel2 set to −14V, which is an example of the second non-selection level L2 and is a voltage level lower than the first non-selection level L1. The selection transistor T3 is maintained in the OFF state by continuing input to the gate of T3. Thereby, the non-conduction between the source and the drain of the selection transistor T3 is maintained, and the electrical connection between the source of the driving transistor T1 and the data line Ld is continuously released.

On the other hand, the power supply driver 150 has a polarity opposite to that of the first non-selection level L1 and the second non-selection level L2 and higher than the reference level Vss in order to drive the drive transistor T1 in the saturation region. The level of 15 V is set as the light emission level Vcss to the voltage level of the power supply line Lv. Thereby, the voltage level of the drain of the driving transistor T1 is set to a voltage level higher than that of the source of the driving transistor T1 based on the light emission level Vcss. Then, the drain-source current Ids corresponding to 10 V which is the gate-source voltage Vgs held in the holding capacitor Cs flows between the drain and source of the driving transistor T1, and the node N2 rises to 7 V. A drain-source current Ids flows through the EL element OEL having a positive bias, and the EL element OEL emits light.

At this time, the potential of the gate of the holding transistor T2 has the same polarity as the second non-selection level L2 (−12V), and the absolute value is a voltage level smaller than the second non-selection level L2. 1 Non-selection level L1 (-2V) is set. A voltage of −19 V corresponding to the difference between the first non-selection level L1 and the voltage level of the node N1 is applied between the gate of the holding transistor T2 and the node N1, and this voltage is the second non-selection level. The voltage is lower than the voltage (−31V) corresponding to the difference between the level L2 and the voltage level of the node N1. As a result, the voltage between the gate of the holding transistor T2 and the node N1 can be suppressed as compared with the configuration in which the gate of the holding transistor T2 and the gate of the selection transistor T3 are selected by one selection line. is there.

The first non-selection level L1 is the first level (0 V) which is the voltage level of the gate that raises the on-current of the holding transistor T2 in the holding transistor T2 after the white display writing operation, and the first non-selection level L1. This is between the second level (−10 V), which is the voltage level of the gate that raises the off-current. Therefore, a leakage current due to the gate level of the holding transistor T2 flows to the holding transistor T2, the voltage level of the node N1 decreases toward the voltage level of the node N3, and a dark spot defect occurs in the white display light emitting operation. Is suppressed.

In addition, since the first non-selection level L1 in the light emission operation and the second non-selection level L2 in the light emission operation are different from each other, it is possible to suppress an off current from flowing through the holding transistor T2 in black display or white display. Therefore, the second selection line Ls2 is not forced to apply the first non-selection level L1.

Note that, in order to suppress the off-current from flowing through the holding transistor T2 in the light emission operation, it is preferable that the difference between the voltage level of the gate of the holding transistor T2 and the light emission level Vcss is small. Further, in order to suppress the off current from flowing through the selection transistor T3 in the light emitting operation, the voltage level of the gate of the selection transistor T3 must be maintained at a negative voltage appropriate to the gradation level Vdata. In this respect, in the above-described EL device 100, the voltage level of the first selection line Ls1 and the voltage level of the second selection line Ls2 are set separately, so that the voltage level and light emission level of the gate of the holding transistor T2 are set. Only the first non-selection level L1 can be set to -2V so that the difference from Vcss becomes small. Further, since the level of the first selection line Ls1 and the level of the second selection line Ls2 are set separately, the voltage level of the gate of the selection transistor T3 is an appropriate negative voltage with respect to the gradation level Vdata (max) -12V. Thus, it is possible to set only the second non-selection level L2 to −14V.

[Write level Vccw and light emission level Vcss]
The write level Vccw and light emission level Vcss common to the drain voltage level of the drive transistor T1 and the drain voltage level of the holding transistor T2 will be described with reference to FIGS. First, the write level Vccw during the write operation will be described based on the characteristic line of the diode-connected drive transistor T1 and the load line of the EL element OEL. Next, the writing level Vccw during the holding operation and the light emission level Vcss during the light emitting operation will be described in order based on the characteristic line of the drive transistor T1 from which the diode connection is released.

[Characteristic line when diode is connected]
A characteristic line SPw, which is a solid line shown in FIG. 8, is a curve showing the relationship between the drain-source voltage Vds of the diode-connected driving transistor T1 and the drain-source current Ids of the diode-connected driving transistor T1. The relationship that the drive transistor T1 has in the initial state is shown. A characteristic line SPw2 which is a broken line shown in FIG. 8 is an example of a characteristic line when a change occurs in the characteristics of the driving transistor T1 in accordance with the driving history of the driving transistor T1. A point PMw on the characteristic line SPw indicates an operating point of the drive transistor T1.

The characteristic line SPw has a threshold voltage Vth with respect to the drain-source current Ids. When the drain-source voltage Vds exceeds the threshold voltage Vth, the drain-source current increases as the drain-source voltage Vds increases. Ids increases nonlinearly. The effective voltage Veff is a voltage component that effectively causes the drain-source current Ids to flow in the drain-source voltage Vds. As shown in the following formula (1), the drain-source voltage Vds is represented by the sum of the threshold voltage Vth and the effective voltage Veff. During the write operation, the drive transistor T1 is diode-connected, and the operation point of the drive transistor T1 is a write operation point that is a point on the characteristic line SPw.

Vds = Vth + Veff (1)
On the other hand, the threshold voltage Vth of the drive transistor T1 usually increases according to the drive history of the drive transistor T1. A characteristic line SPw2 shows an example of a characteristic line when the characteristics of the drive transistor T1 change due to the drive history of the drive transistor T1, and a threshold change amount ΔVth shows a change amount of the threshold voltage Vth due to the drive history. The characteristic line SPw2 has a shape in which the characteristic line SPw in the drive transistor T1 in the initial state is substantially translated by the threshold change amount ΔVth.

Here, when the gradation level Vdata is the same between the driving transistor T1 having the writing operation point on the characteristic line SPw and the driving transistor T1 having the writing operation point on the characteristic line SPw2, At the write operation point on the characteristic line SPw2, the drain-source current Ids is lower than that at the write operation point on the characteristic line SPw. For example, when the gradation level Vdata at the maximum gradation is the maximum gradation level Vdata (max), the maximum gradation current Ids (max) can be obtained at the writing operation point on the characteristic line SPw. At the write operation point on the characteristic line SPw2, the drain-source current Ids becomes lower than the maximum gradation current Ids (max). Therefore, when fluctuation occurs in the characteristics of the driving transistor T1, the threshold value is higher than the drain-source voltage Vds before fluctuation so that the same drain-source current Ids flows as the drain-source current Ids before fluctuation. A drain-source voltage Vds that is higher by the change amount ΔVth is set by correcting the gradation level Vdata.

[Load line of EL element OEL]
The load line SPe, which is a solid line shown in FIG. 9, is a curve showing the relationship between the drive voltage Vel applied to the EL element OEL and the drive current Iel flowing through the EL element OEL, and has the EL element OEL in the initial state. Show the relationship. A load line SPe2 that is a broken line shown in FIG. 9 is an example of a characteristic line when a change occurs in the characteristic of the EL element OEL in accordance with the driving history of the EL element OEL.

The load line SPe has a threshold voltage Vthel with respect to the drive current Iel. When the drive voltage Vel exceeds the threshold voltage Vthel, the drive current Iel increases nonlinearly as the drive voltage Vel increases.

On the other hand, the EL element OEL usually increases in resistance as the accumulated time that the EL element OEL is driven becomes longer. The load line SPe2 shows an example of a characteristic line when a change occurs in the characteristic of the EL element OEL due to a longer cumulative time during which the EL element OEL is driven. The increase rate of the drive current Iel with respect to the drive voltage Vel decreases in the load line SPe2 rather than in the load line SPe.

Here, when the voltage value of the drive voltage Vel is the same between the EL element OEL having the operating point on the load line SPe and the EL element OEL having the operating point on the load line SPe2, the load line At the operating point on SPe2, the drive current Iel is lower than the operating point on the load line SPe. Therefore, when the characteristics of the EL element OEL change, the drive voltage Vel higher than the drive voltage Vel before the change is the gradation level Vdata so that the same drive current Iel as the drive current Iel before the change is obtained. It is set by correction. The increase amount ΔVel of the drive voltage Vel is the maximum increase amount ΔVel (max) at the maximum gray level when the drive current Iel is the maximum value Iel (max).

[Write level Vccw during write operation]
In the write operation, the first selection driver 130A connects the gate and drain of the drive transistor T1 to set the drive transistor T1 in a diode connection state. Further, the power supply driver 150 sets the voltage level of the drain of the drive transistor T1 to be more positive than the voltage level of the source of the drive transistor T1 in order to flow the drain-source current Ids. That is, the power supply driver 150 sets the write level Vccw so as to satisfy the following expression (2) with respect to the gradation level Vdata. Further, the data driver 140 sets the gradation level Vdata at the source of the drive transistor T1 through the conduction of the selection transistor T3.

Thereby, a drain-source current Ids corresponding to the level difference (Vccw-Vdata) between the drain and source flows between the drain and source of the driving transistor T1. At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is equal to the gate-source voltage Vgs, and is expressed by the following equation (3). Then, such a gate-source voltage Vgs is written in the storage capacitor Cs.

Vdata <Vccw (2)
Vds = Vgs = Vccw−Vdata (3)
Note that since the source of the drive transistor T1 and the anode of the EL element OEL are both connected to the node N2, the gray level is set so that the drain-source current Ids does not flow to the EL element OEL during the write operation. Level Vdata is set. That is, the gradation level Vdata is set to be equal to or less than the sum of the reference level Vss, which is the cathode voltage of the EL element OEL, and the threshold voltage Vthel of the EL element OEL so as to satisfy the following expression (4). Further, when the reference level Vss is the ground level (0 V), the gradation level Vdata is set so as to satisfy the following expression (5).

Vdata ≦ Vss + Vthel (4)
Vdata ≦ Vthel (5)
When the above formula (3) is substituted into the above formula (5), the following formula (6) is obtained. When the above formula (1) is substituted into the following formula (6), the following formula (7) is obtained. Further, since the following formula (7) needs to hold even when Veff = 0V, the following formula (8) is obtained by substituting Veff = 0 into the following formula (7).

From the above, the write level Vccw during the write operation is set to a level lower than the reference level Vss so as to satisfy the relationship of the following equation (8).
Vccw−Vgs ≦ Vthel (6)
Vccw ≦ Vthel + Vth + Veff (7)
Vdata <Vccw ≦ Vthel + Vth (8)
[Characteristic line when diode is disconnected]
A characteristic line SPh, which is a solid line shown in FIG. 10, is a curve showing the relationship between the drain-source voltage Vds in the driving transistor T1 and the drain-source current Ids in the driving transistor T1, and the diode connection is released. The characteristic line when the gate-source voltage Vgs is constant in the driving transistor T1 is shown. A characteristic line SPw, which is a broken line in FIG. 10, is the characteristic line SPw described in FIG. 8, and is a characteristic line when the drive transistor T1 is diode-connected. A characteristic line SPo that is a one-dot chain line in FIG. 12 is a curve including an operating point obtained by subtracting the drain-source voltage Vds at each writing operation point on the characteristic line SPw by the threshold voltage Vth.

As shown in FIG. 10, the operating point PMh is an intersection of the characteristic line SPw of the diode-connected driving transistor T1 and the characteristic line SPh of the driving transistor T1 whose diode connection is released. The operating point Po is an intersection with the characteristic line SPh of the driving transistor T1 from which the diode connection is released, and the drain-source voltage Vds at the operating point Po is the pinch-off voltage Vpo. During the holding operation and the light emitting operation, the driving transistor T1 is disconnected from the diode connection. The operating point of the driving transistor T1 is a holding operating point that is a point on the characteristic line SPh, and a light emitting operating point. It is.

In the characteristic line SPh, a region where the drain-source voltage Vds is 0 V to the pinch-off voltage Vpo is a linear region, and a region where the drain-source voltage Vds is equal to or higher than the pinch-off voltage Vpo is the drain-source current Ids. It is a saturation region that is almost constant. The drain-source current Ids corresponds to the drive current of the EL element OEL.

Here, in the holding operation, the first selection driver 130A releases the diode connection in the driving transistor T1, and holds the gate-source voltage Vgs of the driving transistor T1 in the writing operation in the holding capacitor Cs. At this time, in controlling the drain-source current Ids by the gate-source voltage Vgs of the driving transistor T1 in the subsequent light emitting operation, the drain-source current Ids is constant with respect to the drain-source voltage Vds. It is required to be. Therefore, during the write operation and the hold operation, the write level Vccw is a voltage that drives the drive transistor T1 in the saturation region of the drain-source current Ids.

Next, in the light emitting operation, the first selection driver 130A continues to release the diode connection in the driving transistor T1. The power supply driver 150 changes the power supply signal Vcc, which is the voltage level of the drain of the drive transistor T1, from the write level Vccw to the light emission level Vcss in order to flow the drain-source current Ids. As a result, the driving transistor T1 is driven in the saturation region, and a drain-source current Ids corresponding to the gate-source voltage Vgs held in the holding capacitor Cs flows between the drain and source of the driving transistor T1. Then, the drain-source current Ids is supplied to the EL element OEL, so that the EL element OEL emits light with luminance corresponding to the drain-source current Ids.

As shown in FIG. 11, the characteristic line SPw and the characteristic line SPo are the characteristic lines explained in FIG. 8, and the characteristic line SPh is the characteristic line explained in FIG. The load line SPe and the load line SPe2 are the load lines described with reference to FIG. 9, and the voltage between the drain of the drive transistor T1 and the cathode of the EL element OEL, that is, the light emission level Vcss and the reference level Vss. Is a curve corresponding to the drive voltage Vel of the EL element OEL.

During the holding operation, the operating point of the driving transistor T1 is a holding operating point that is the intersection of the characteristic line SPw of the diode-connected driving transistor T1 and the characteristic line SPh of the driving transistor T1 that has been disconnected from the diode. On the other hand, the operating point of the drive transistor T1 during the light emitting operation changes from the holding operating point to the light emitting operating point PMe that is the intersection of the characteristic line SPh and the load line SPe.

At the light emission operating point PMe, a voltage corresponding to the difference between the light emission level Vcss and the reference level Vss is applied between the drain of the drive transistor T1 and the cathode of the EL element OEL. The light emission operating point PMe determines a ratio of distributing a voltage corresponding to the difference between the light emission level Vcss and the reference level Vss between the drain and source of the drive transistor T1 and between the anode and cathode of the EL element OEL. That is, the light emission operating point PMe determines the drain-source voltage Vds of the driving transistor T1 and the driving voltage Vel of the EL element OEL.

As shown in FIG. 12, the load line of the EL element OEL changes in order of the load line SPe, the load line SPe2, and the load line SPe3 as the EL element OEL is driven for a longer time. That is, the load line of the EL element OEL changes in a direction in which the increase rate of the drive current Iel decreases with respect to the drive voltage Vel corresponding to the difference between the light emission level Vcss and the reference level Vss. The light emission operation point of the drive transistor T1 also increases on the characteristic line SPh of the drive transistor T1 in order of the light emission operation point PMe, the light emission operation point PMe2, and the light emission operation point PMe3 as the driving time of the EL element OEL becomes longer. change.

Here, the light emission operation point PMe and the light emission operation point PMe2 are located in the saturation region on the characteristic line SPh, while the light emission operation point PMe3 is located in the linear region on the characteristic line SPh. If the light emitting operation point is in the saturation region, the drive current Iel of the EL element OEL is substantially equal to the drain-source current Ids of the drive transistor T1 during the write operation. On the other hand, at the light emission operation point PMe3 in the linear region, the drive current Iel of the EL element OEL becomes lower than the drain-source current Ids of the drive transistor T1 during the write operation. Therefore, since the drain-source current Ids of the drive transistor T1 and the drive current Iel are substantially equal during the write operation, the light emission operation point needs to be located in the saturation region on the characteristic line SPh.

The compensation range Vmarg is a potential difference between the operating point Po corresponding to the pinch-off voltage Vpo and the light emitting operating point PMe on the characteristic line SPh of the driving transistor T1. The compensation range Vmarg is a range in which the drain-source current Ids of the drive transistor T1 during the write operation can be maintained as the drive current Iel with respect to a change in the characteristics of the EL element OEL due to the drive history of the EL element OEL. That is, the voltage range that the light emission operating point can take on the saturation region is the compensation range Vmarg. The compensation range Vmarg decreases as the drain-source current Ids of the driving transistor T1 increases during the write operation, and increases as the difference between the light emission level Vcss and the reference level Vss increases.

From the above, the light emission level Vcss in the light emission operation is set so that the light emission operation point can be located in the saturation region on the characteristic line SPh and the compensation range Vmarg is sufficient. That is, when the maximum value of the drive voltage Vel applied to the EL element OEL is the maximum drive voltage Vel (max), the light emission level Vcss satisfies the following expression (9), and the reference level Vss is the ground level. When (= 0V), the level is set higher than the reference level Vss so as to satisfy the following expression (10).

Vccs−Vss ≧ Vpo + Vmarg + Vel (max) (9)
Vccs ≧ Vpo + Vmarg + Vel (max) (10)
[Control defects in reference examples]
In order to describe the operation of the EL device 100, the electrical configuration of the pixel in the reference example and the level of each terminal in the pixel will be described with reference to FIGS. The EL device in the reference example is different from the EL device 100 in the above embodiment in the configuration of the selection line connected to one pixel PIX, the configuration of the selection driver that drives the selection line, and the level in the selection signal. The rest of the configuration is the same as that of the EL device of the above embodiment. Therefore, in the following, differences between the EL device in the reference example and the EL device 100 in the above embodiment will be mainly described, and the same reference numerals are given to the same configurations as those in the EL device in the above embodiment, The detailed explanation is omitted. FIG. 13 is a diagram corresponding to FIG. 2 referred to in the description of the configuration of the pixel circuit in the above embodiment, and each of FIGS. 14 to 17 is from FIG. 4 referred to in the description of the operation of the pixel in the above embodiment. It is a figure corresponding to each of FIG.

[Pixel configuration of reference example]
As shown in FIG. 13, each of the plurality of pixels PIX includes an EL element OEL and a pixel circuit DC for driving the EL element OEL. The pixel circuit DC includes a drive transistor T1, a holding transistor T2, a selection transistor T3, and a holding capacitor Cs.

The holding transistor T2 is an n-channel transistor, and the gate of the holding transistor T2 is electrically connected to the selection line Ls through the node N4. The drain of the holding transistor T2 is electrically connected to the power supply line Lv through the node N3, and the source of the holding transistor T2 is electrically connected to the node N1. The holding transistor T2 has a function of selecting whether or not the drive transistor T1 is diode-connected based on the level of the selection signal of the selection line Ls.

The selection transistor T3 is an n-channel transistor, and the gate of the selection transistor T3 is electrically connected to the selection line Ls in the same manner as the gate of the holding transistor T2. The source of the selection transistor T3 is electrically connected to the data line Ld, and the drain of the selection transistor T3 is electrically connected to the node N2. The selection transistor T3 has a function of holding a voltage corresponding to the gradation level Vdata in the holding capacitor Cs in cooperation with the driving transistor T1 and the holding transistor T2.

The selection driver 130 outputs the selection signal set to the selection level H to each of the plurality of selection lines Ls in the order of the row numbers based on the selection control signal SCON1 output from the system controller 120. Each pixel PIX is set to a selected state for each row. For example, the selection driver 130 outputs a selection signal set to the selection level H to the selection line Ls in the specific row in the writing operation of the pixel PIX located in the specific row. Then, the selection driver 130 executes the output of the selection signal set to the selection level H for each row in the order of the row number, and sets each of the plurality of pixels PIX in the selected state in the order of the row number. .

[Bright spot defect in black display of reference example]
14 and 15, an example of the voltage level of each terminal during the black display write operation of the reference example, and an example of the voltage level of each terminal during the black display light emission operation of the reference example, The bright spot defect in the black display of the reference example will be described.

As shown in FIG. 14, in the black display write operation of the reference example, the selection driver 130 supplies an example of the selection level H to the gate of the holding transistor T2 and the gate of the selection transistor T3 through one selection line Ls. The selection signal set to 15V is input. Then, the selection driver 130 causes the holding transistor T2 and the selection transistor T3 to transition to the on state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, and the driving transistor T1 is diode-connected. Further, the source and the drain of the selection transistor T3 are brought into conduction, and the source of the driving transistor T1 and the data line Ld are electrically connected.

On the other hand, the power supply driver 150 sets 0 V equal to the reference level Vss as the write level Vccw to the voltage level of the power supply line Lv, and the data driver 140 is equal to the reference level Vss as an example of the black display gradation level Vdata. 0V is set to the data line Ld. As a result, the level of the source of the driving transistor T1 is set to 0V, and the voltage level of the gate of the driving transistor T1 becomes equal to the voltage level of the drain of the driving transistor T1. Since the drain-source voltage Vds of the driving transistor T1 is 0 V, the drain-source current Ids does not flow. At this time, since the drive transistor T1 is diode-connected, the drain-source voltage Vds of the drive transistor T1 is equal to the gate-source voltage Vgs, and 0V is written to the storage capacitor Cs as the gate-source voltage Vgs. It is.

In the black display holding operation of the reference example, the selection driver 130 is an example of the non-selection level L at the gate of the selection transistor T3 through one selection line Ls in order to set the selection transistor T3 to the OFF state. A selection signal set to 14V is input. Accordingly, a selection signal set to −14V, which is an example of the non-selection level L, is also input to the gate of the holding transistor T2 through one selection line Ls. As a result, both the holding transistor T2 and the selection transistor T3 transition to the off state.

As shown in FIG. 15, in the light emission operation of black display of the reference example, the selection driver 130 does not select the gate of the selection transistor T3 through one selection line Ls in order to maintain the selection transistor T3 in the OFF state. The selection signal set to -14V, which is an example of the level L, is continuously input. Accordingly, the selection signal set to −14V, which is an example of the non-selection level L, is continuously input to the gate of the holding transistor T2 through one selection line Ls. As a result, both the holding transistor T2 and the selection transistor T3 are maintained in the off state.

On the other hand, in order to drive the drive transistor T1 in the saturation region, the power driver 150 sets 15V, which is a voltage level higher than the reference level Vss, as the light emission level Vcss to the voltage level of the power line Lv. The voltage level of the data line Ld is continuously set as 0 V equal to the reference level Vss as the gradation level Vdata.

At this time, the voltage level of the drain of the driving transistor T1 is set to a higher voltage level than the source of the driving transistor T1. Here, if the gate-source voltage Vgs held in the storage capacitor Cs is maintained at 0 V, the drain-source current Ids does not flow between the drain and source of the drive transistor T1, and the EL element OEL Does not emit light. However, since the gate of the holding transistor T2 is set to the non-selection level L of −14V common to the gate of the selection transistor T3, the non-selection level L between the gate of the holding transistor T2 and the node N3 is set. A large reverse bias of −29 V corresponding to the difference between the light emission level Vcss and the light emission level Vcss is applied. Therefore, a leakage current due to the gate level of the holding transistor T2 flows to the holding transistor T2, the voltage level of the node N1 increases toward the voltage level of the node N3, and the gate-source voltage Vgs of the driving transistor T1 is 0V. Will rise from. As a result, a bright spot defect occurs in the light emission operation of black display of the reference example.

[Dark spot defect in white display of reference example]
Referring to FIG. 16 and FIG. 17, an example of the voltage level of each terminal during the white display write operation of the reference example, and an example of the voltage level of each terminal during the white display light emission operation of the reference example, The dark spot defect in the white display of the reference example will be described.

As shown in FIG. 16, in the white display writing operation of the reference example, the selection driver 130 supplies an example of the selection level H to the gate of the holding transistor T2 and the gate of the selection transistor T3 through one selection line Ls. The selection signal set to 15V is input. Then, the selection driver 130 causes the holding transistor T2 and the selection transistor T3 to transition to the on state. As a result, the gate of the driving transistor T1 and the drain of the driving transistor T1 become conductive, and the driving transistor T1 is diode-connected. Further, the source and the drain of the selection transistor T3 are brought into conduction, and the source of the driving transistor T1 and the data line Ld are electrically connected.

On the other hand, the power supply driver 150 sets 0V equal to the voltage level of the reference level Vss as the write level Vccw to the voltage level of the power supply line Lv. The data driver 140 sets -12V, which has the same polarity as the non-selection level L and is lower than the reference level Vss, to the electric voltage level of the data line Ld as the gray level Vdata for white display. As a result, the voltage level of the source of the driving transistor T1 is set to −10V, and the voltage level of the gate of the driving transistor T1 becomes equal to the voltage level of the drain of the driving transistor T1. Then, a voltage of 10 V is written in the storage capacitor Cs as the gate-source voltage Vgs.

In the white display holding operation of the reference example, the selection driver 130 is an example of the non-selection level L at the gate of the selection transistor T3 through one selection line Ls in order to set the selection transistor T3 to the OFF state. A selection signal set to 14V is input. Accordingly, a selection signal set to −14V, which is an example of the non-selection level L, is also input to the gate of the holding transistor T2 through one selection line Ls. As a result, both the holding transistor T2 and the selection transistor T3 transition to the off state.

As shown in FIG. 17, in the white display light emitting operation of the reference example, the selection driver 130 does not select the gate of the selection transistor T3 through one selection line Ls in order to maintain the selection transistor T3 in the OFF state. The selection signal set to -14V, which is an example of the level L, is continuously input. Accordingly, the selection signal set to −14V, which is an example of the non-selection level L, is continuously input to the gate of the holding transistor T2 through one selection line Ls. As a result, both the holding transistor T2 and the selection transistor T3 are maintained in the off state.

On the other hand, in order to drive the drive transistor T1 in the saturation region, the power driver 150 sets 15V, which is a voltage level higher than the reference level Vss, as the light emission level Vcss to the voltage level of the power line Lv. The voltage level of −12V, which is lower than the reference level Vss, is continuously set to the voltage level of the data line Ld as the gradation level Vdata. Thereby, the voltage level of the drain of the driving transistor T1 is set to a voltage level higher than that of the source of the driving transistor T1 based on the light emission level Vcss. Then, the drain-source current Ids corresponding to 10 V which is the gate-source voltage Vgs held in the holding capacitor Cs flows between the drain and source of the driving transistor T1, and the node N2 rises to 7 V. A drain-source current Ids flows through the EL element OEL having a positive bias, and the EL element OEL emits light.

At this time, if the gate-source voltage Vgs held in the holding capacitor Cs is maintained at 10 V, the drain-source current Ids corresponding to the gradation level Vdata is provided between the drain and source of the driving transistor T1. Continues to flow, and the EL element OEL continues to emit light. However, since the non-selection level L of −14V common to the gate of the selection transistor T3 is set to the gate of the holding transistor T2, the gate of the holding transistor T2 is between the gate of the holding transistor T2 and the node N1. A large reverse bias of −31 V corresponding to the difference between the drain voltage level (17 V) and the non-selection level L is applied. Therefore, a leakage current due to the gate level of the holding transistor T2 flows to the holding transistor T2, the voltage level of the node N1 increases toward the voltage level of the node N3, and the gate-source voltage Vgs of the driving transistor T1 is 10V. It will descend from. As a result, a dark spot defect occurs in the white display light emitting operation of the reference example.

[Operation of EL Device 100]
An example of the operation of the EL device 100 according to this embodiment will be described with reference to FIG. FIG. 18 is a timing chart illustrating an example of a driving mode in a plurality of pixels located in a specific row. In FIG. 18, for convenience of explaining the operation of the EL device 100, i rows and j columns and (i + 1) rows and j columns (i is 1) included in the same pixel group among a plurality of pixels PIX located in a matrix. A timing chart when a pixel PIX having a positive integer satisfying ≦ i ≦ n and j being a positive integer satisfying 1 ≦ j ≦ m is caused to emit light with luminance gradation based on gradation data is shown.

As shown in FIG. 18, the driving cycle Tcyc of the pixels PIX in each row includes a writing operation period Twrt in which a writing operation is performed, a holding operation period Thld in which a holding operation is performed, and a light emitting operation. It is composed of a light emission operation period Tem that is a period to be performed.

[Write operation period Twrt]
In the write operation period Twrt, the power supply driver 150 writes to a plurality of power supply lines Lv connected to all the pixels PIX with respect to the pixel group including the pixels PIX in the i rows and j columns and the (i + 1) rows and j columns. Level Vccw is set.

During the write operation period Twrt, the first selection driver 130A inputs the first selection signal Vsel1 set to the first selection level H1 to the first selection line Ls1 in the i-th row. As a result, in the pixel PIX in the i-th row, the holding transistor T2 is turned on, and the driving transistor T1 is diode-connected. The second selection driver 130B inputs the second selection signal Vsel2 set to the second selection level H2 to the second selection line Ls2 in the i-th row. As a result, in the pixel PIX in the i-th row, the selection transistor T3 is turned on. The voltage level of the drain of the drive transistor T1 and the voltage level of the gate of the drive transistor T1 are set to the write level Vccw, and the source of the drive transistor T1 is electrically connected to the data line Ld. That is, one of the electrodes of the storage capacitor Cs is set to a voltage level corresponding to the write level Vccw, and the other electrode is electrically connected to the data line Ld.

In the write operation period Twrt, the data driver 140 sets the gradation level Vdata corresponding to the i-th gradation data to the voltage level of each data line Ld. As a result, a voltage corresponding to the difference between the gradation level Vdata and the write level Vccw is written as the gate-source voltage Vgs of the drive transistor T1.

[Holding operation period Thld]
In the writing operation period Twrt, the power supply driver 150 applies the power supply lines Lv connected to all the pixels PIX to the pixel group including the pixels PIX in the i row and j column and the (i + 1) row and j column. The write level Vccw is continuously set as the voltage level.

In the holding operation period Thld, the first selection driver 130A inputs the first selection signal Vsel1 set to the first non-selection level L1 to the first selection line Ls1 in the i-th row. As a result, in the pixel PIX in the i-th row, the holding transistor T2 changes to the off state, and the driving transistor T1 is released from the diode connection. The second selection driver 130B inputs the second selection signal Vsel2 set to the second non-selection level L2 to the second selection line Ls2 in the i-th row. As a result, in the pixel PIX in the i-th row, the selection transistor T3 transitions to an off state. Then, the input of the gradation level Vdata to the source of the driving transistor T1 is canceled, and the gate-source voltage Vgs of the driving transistor T1 is held in the holding capacitor Cs.

[Light emitting operation period Tem]
In the light emission operation period Tem, the power supply driver 150 emits light through a plurality of power supply lines Lv connected to all the pixels PIX with respect to the pixel group including the pixels PIX in the i rows and j columns and the (i + 1) rows and j columns. Set the level Vcss. The first selection driver 130A continues to input the first selection signal Vsel1 set to the first non-selection level L1 to the i-th first selection line Ls1. The second selection driver 130B continues to input the second selection signal Vsel2 set to the second non-selection level L2 to the second selection line Ls2 in the i-th row. As a result, in the pixel PIX in the i-th row, it is possible to suppress an off current from flowing through the holding transistor T2 and the selection transistor T3.

At this time, the voltage level corresponding to the holding voltage written in the holding capacitor Cs is set to the anode of the EL element OEL, while the reference level Vss is continuously set to the cathode of the EL element OEL. As a result, in the pixel PIX in which the holding voltage of the holding capacitor Cs exceeds 0 V, the both electrodes of the EL element OEL are set to the forward bias, and the driving current Iel according to the gate-source voltage Vgs of the driving transistor T1, that is, A gradation current Imsb corresponding to the gradation data flows through the EL element. Such a light emission operation is continuously executed until the start of the next drive cycle Tcyc.

FIG. 19 is a time chart showing a flow in the upper pixel group and a flow in the lower pixel group of three operations including a writing operation, a holding operation, and a light emitting operation. For convenience of explaining the relationship between the operation of the upper pixel group and the operation of the lower pixel group, the upper pixel group is composed of the pixels PIX from the first row to the sixth row, and the lower pixel group is from the seventh row. An example including pixels PIX up to the 12th row is shown.

As shown in FIG. 19, the pixels PIX from the first row of pixels PIX to the sixth row execute the write operation in the order of the row numbers from the first row of pixels PIX for each write operation period Twrt. The holding operation is started in the order of the row numbers from the pixel PIX that has finished the operation. When the pixels PIX in the seventh row finish the writing operation, all the pixels PIX in the upper pixel group start the light emitting operation all at once.

Further, when the pixel PIX in the sixth row finishes the writing operation, the pixel PIX from the pixel PIX in the seventh row to the twelfth row changes the row number from the pixel PIX in the seventh row every writing operation period Twrt. The writing operation is executed in order, and the holding operation is started in the order of the row numbers from the pixel PIX that has finished the writing operation. At this time, the pixels PIX from the 8th row to the 12th row are set according to the setting of the write level Vccw from the time when the pixel PIX of the upper pixel group starts the light emission operation to the time when the write operation starts. Perform a non-light emitting operation. When the pixels PIX in the twelfth row finish the writing operation, all the pixels PIX in the lower pixel group start the light emitting operation all at once.

Further, when the pixel PIX in the twelfth row finishes the writing operation, the pixels PIX from the pixel PIX in the first row to the sixth row finish the light emitting operation all at once, and the writing is performed again every writing operation period Twrt. The storing operation is executed in the order of the row numbers, and the holding operation is started in the order of the row numbers from the pixel PIX that has finished the writing operation. At this time, the pixels PIX from the second row to the seventh row set the write level Vccw from the time when the pixel PIX in the lower pixel group starts the light emission operation to the time when the write operation starts. Executes the non-light emission operation.

[First level and second level]
With reference to FIG. 20 and FIG. 21, the relationship between the on-current and the gate-source voltage Vgs in the holding transistor T2 and the relationship between the off-current and the gate-source voltage Vgs will be described. 20 and FIG. 21 are graphs showing the relationship between the gate-source voltage Vgs in the holding transistor T2 and the drain current Id flowing between the source and drain, and the drain-source voltage Vds. Shows the relationship when is set to 15V. 20 and 21 are graphs showing an estimation of the off-state current of the holding transistor T2 in the light emission operation. The light emission level Vcss (= 15V) is shown in the relationship between the gate-source voltage Vgs and the drain current Id. ) Is a graph obtained by adding the gate-drain voltage Vgd in the holding transistor T2. 20 is an estimate obtained by the EL device 100 of the above embodiment, and FIG. 21 is an estimate obtained by the EL device of the reference example.

As shown in FIG. 20, the drain current Id flowing between the gate and the source is a value determined by the gate-source voltage Vgs, and the gate-source voltage Vgs is from 0 V to 10 V, which is an example of the first level. When increasing, the drain current Id increases rapidly as an on-current. On the other hand, when the gate-source voltage Vgs is between 0V, which is an example of the first level, and -10V, which is an example of the second level, the drain current Id does not flow, and the holding transistor T2 remains off. is doing. When the gate-source voltage Vgs decreases from −10 V, which is an example of the second level, to −30 V, the drain current Id gradually increases as an off-current as indicated by the curve LC.

Note that the off-current flowing through the n-channel thin film transistor includes a current in which holes generated due to defects included in the channel are carriers. Therefore, as indicated by an arrow ER in FIG. 20, the off-state current of the holding transistor T2 has a variation depending on the manufacturing difference of the holding transistor T2.

In the light emission operation, when the light emission level Vcss of 15V is set to the drain of the holding transistor T2 and −2V is set to the gate potential as an example of the first non-selection level L1, as shown in FIG. The voltage between the gate and the drain of the holding transistor T2 in the display is -17V. As indicated by the arrow in FIG. 20, when the drain of the holding transistor T2 is at the light emission level Vcss, if the voltage level of the gate of the holding transistor T2 is between the first level and the second level, that is, the holding transistor T2 When the gate-drain voltage Vgd is in the range of -15V to -25V, no off-current flows through the holding transistor T2. As a result, if the first non-selection level L1 is set in the EL device 100, the occurrence of bright spot defects in black display can be suppressed.

As shown in FIG. 7, the voltage between the gate and the drain of the holding transistor T2 in the white display is −19V. At this time, a terminal connected to the node N1 among the terminals of the holding transistor T2 functions as a drain set to a high voltage level (17V). Even in such a configuration, since the gate-drain voltage Vgd of the holding transistor T2 is in the range of −15V to −25V, no off-current flows through the holding transistor T2. Therefore, if the first non-selection level L1 is set in the EL device 100, the occurrence of dark spot defects in white display can be suppressed.

On the other hand, when the light emission level Vcss of 15V is set at the drain of the holding transistor T2, and -14V is set as the gate potential as an example of the non-selection level L as in the reference example, FIG. Thus, the gate-drain voltage of the holding transistor T2 in black display is −29V.

As shown by the arrow in FIG. 21, when the drain of the holding transistor T2 is at the light emission level Vcss, the voltage level of the gate of the holding transistor T2 is lower than the second level, that is, between the gate and the drain of the holding transistor T2. In a state where the voltage Vgd is lower than −25V, an off-current flows through the holding transistor T2. As a result, when the non-selection level L is set in the EL device of the reference example, a bright spot defect occurs in black display.

As shown in FIG. 17, the voltage between the gate and the drain of the holding transistor T2 in the white display of the reference example is −31V. At this time, a terminal connected to the node N1 among the terminals of the holding transistor T2 functions as a drain set to a high voltage level (17V). Even in such a configuration, since the gate-drain voltage Vgd of the holding transistor T2 is lower than −25V, an off-current flows through the holding transistor T2. As a result, when the non-selection level L is set in the EL device of the reference example, a dark spot defect occurs in white display.

According to the embodiment, the effects listed below can be obtained.
(1) Since the off-state current of the holding transistor T2 can be suppressed, the occurrence of control defects in the EL device 100 can be suppressed.

(2) The first non-selection level L1 input to the holding transistor T2 and the second non-selection level L2 input to the selection transistor T3 can be set to different levels. As a result, it is possible to set the first non-selection level L1 input to the holding transistor T2 to a level specialized for suppressing the off-current in the holding transistor T2.

(3) Since the level of the first selection line Ls1 and the level of the second selection line Ls2 are set separately, the difference between the gate level of the holding transistor T2 and the light emission level Vcss is reduced, and the selection transistor It is possible to maintain both the level of the gate of T3 at an appropriate negative voltage with respect to the gradation level Vdata.

(4) Since the first selection level H1 set on the first selection line Ls1 and the second selection level H2 set on the second selection line Ls2 are equal to each other, the first selection level H1 and the second selection level The circuit configuration for generating H2 can be simplified.

The embodiment described above can be implemented with the following modifications.
[First level and second level]
The first non-selection level L1, which is an example of a non-conduction level, raises the on-current of the holding transistor T2 when the light emission level Vcss is set to the power supply line Lv from the state of the holding transistor T2 immediately before the light emission operation. It may be between the first level and the second level that raises the off-state current of the holding transistor T2. For example, the first non-selection level L1 in black display is not limited to −2V, and may be within a range from 0V to −10V, for example. When the light emission level Vcss is 10V, −5V to − It may be in the range up to 15V.

Further, at the gate level of the holding transistor T2, the first level at which the on-current rises and the second level at which the off-current rises vary depending on various configurations of the holding transistor T2, such as the channel length and channel width of the holding transistor T2. It is.

Therefore, the non-conducting level L1 is positioned so that the first non-selection level L1 is positioned between the first level for raising the on-current of the holding transistor T2 and the second level for raising the off-current of the holding transistor T2. The first non-selection level L1, which is an example, is appropriately selected for each configuration of the holding transistor T2.

-Assuming that the first non-selection level L1 is located between the first level and the second level, the first non-selection level L1 and the second non-selection level L2 may be the same as each other The first non-selection level L1 may be lower than the second non-selection level L2. In such a configuration, in the light emitting operation, the gradation level Vdata is restricted so that the voltage level of each terminal in the selection transistor T3 and the voltage level of each terminal in the holding transistor T2 are approximately the same. It is possible to obtain the effect according to).

[Pixel circuit]
The driving transistor T1, the holding transistor T2, and the selection transistor T3 may be p-channel thin film transistors. At this time, the source of the driving transistor T1 is electrically connected to the power supply line Lv, and the drain of the driving transistor T1 is electrically connected to the node N2. The source of the holding transistor T2 is electrically connected to the source of the driving transistor T1, and the drain of the holding transistor T2 is electrically connected to the gate of the driving transistor T1. The drain of the selection transistor T3 is electrically connected to the data line Ld, and the source of the selection transistor T3 is electrically connected to the drain of the driving transistor T1.

The pixel circuit included in the pixel PIX is not limited to the 3Tr1C type described above, and the connection form between the plurality of thin film transistors may be another connection form. For example, a plurality of pixels PIX are arranged in a one-dimensional direction, and one pixel circuit may be a 2Tr1C type including a driving transistor that is two thin film transistors, a holding transistor, and one capacitor element. Good. In other words, the selection transistor T3 may be omitted in the pixel circuit. The pixel circuit included in the pixel PIX may include a driving transistor and a holding transistor, and may have four or more thin film transistors.

In short, in the light emitting operation after the writing operation, the first non-selection level L1 is positioned between the first level that raises the on-current of the holding transistor T2 and the second level that raises the off-current of the holding transistor T2. As long as the first non-selection level L1 is set, any configuration may be used.

The current drive element that receives the drive current from the drive transistor T1 is not limited to the EL element OEL, and may be, for example, a light emitting diode or various sensor elements.
The drive circuit including the drive transistor T1 is not limited to the pixel circuit DC including the holding transistor T2 and the EL element OEL, and may be a sensor circuit including the holding transistor T2 and a sensor element, for example. The current driving device to which the sensor circuit is applied is not limited to the EL device, and may be a sensor device including a plurality of sensor circuits. The sensor device may be embodied in any one of, for example, a biosensor device, a temperature sensor device, an illuminance sensor device, and a concentration sensor device. The sensor element may be embodied in any one of a biosensor element, a temperature sensor element, an illuminance sensor element, and a concentration sensor element, for example, in accordance with an object to be measured by the sensor device.

For example, as shown in FIG. 22, an electric field cell EC (electrolytic cell) is used as an example of a current driving element. The electric field cell EC is a second electrode that generates an electric field reaction between an electrolyte solution containing a substrate for advancing a desired electrochemical reaction, the first working electrode WE1 connected to the node N2, and the first working electrode WE1. A working electrode WE2 and a reference electrode RE are provided. The first working electrode WE1, the second working electrode WE2, and the reference electrode RE are all connected to the electrolyte solution. Among the first working electrode WE1 and the second working electrode WE2, when the electrochemical reaction proceeds, the negative potential side electrode functions as a cathode electrode, and when the electrochemical reaction proceeds, the positive potential side electrode is the anode electrode. Function as. The voltage level of the cathode electrode and the voltage level of the anode electrode are relatively measured based on the voltage level of the reference electrode RE.

The data driver 140 includes two switch elements SW connected to the data line Ld. The two switch elements SW are switched between a state in which the voltage level of the data line Ld in the drive circuit ECD is set to the reaction level Vreac and a state in which the data line Ld in the drive circuit ECD is set to the high impedance state.

The data driver 140 includes a measurement unit 140S that measures a voltage level. The measurement unit 140S measures the voltage level VM of the data line Ld set to the high impedance state and the voltage level VRE of the reference electrode RE, and calculates the voltage level VM of the data line Ld and the voltage level VRE of the reference electrode RE. Calculate the difference.

In the write operation, as described in the above embodiment, the first selection driver 130A and the second selection driver 130B set the selection levels H1, V2 to the voltage levels of the first selection line Ls1 and the second selection line Ls2. H2 is set, whereby the holding transistor T2 and the selection transistor T3 transition from the off state to the on state. Then, the power supply driver 150 sets the power supply signal Vcc to the write level Vccw, whereby the holding transistor T2 and the selection transistor T3 write a voltage corresponding to the reaction level Vreac to the holding capacitor Cs.

In the holding operation in the drive circuit ECD, the first selection driver 130A sets the non-selection level L1 to the voltage level of the first selection line Ls1, thereby causing the holding transistor T2 to transition from the on state to the off state. In the holding operation in the drive circuit ECD, the power supply driver 150 keeps the power supply signal Vcc at the write level Vccw, and the holding transistor T2 holds the voltage during the write operation in the holding capacitor Cs. At this time, after setting the data line Ld to the high impedance state, the data driver 140 measures the difference between the voltage level VM of the node N2 and the voltage level VRE of the reference electrode RE.

In the driving operation in the drive circuit ECD, the first selection driver 130A and the second selection driver 130B set the non-selection levels L1 and L2 to the voltage levels of the first selection line Ls1 and the second selection line Ls2, Accordingly, the holding transistor T2 and the selection transistor T3 are set to an off state. In the drive operation in the drive circuit ECD, the power supply driver 150 changes the power supply signal Vcc from the write level Vccw to a drive level that is an example of the drive level, whereby the drive transistor T1 holds the holding capacitor Cs. A driving current corresponding to the voltage is supplied to the electric field cell EC. That is, the drive transistor T1 drives the electric field cell EC at a constant current based on the difference between the drive level and the reference level Vss. According to these holding operations and driving operations, by specifying the reaction level Vreac with respect to the data line Ld and measuring the voltage level of the first working electrode WE1 when a current flows according to the specification of the reaction level Vreac, It is possible to measure the redox potential Vred of the substrate.

That is, the drive circuit only needs to have a configuration that exhibits a display function and a measurement function by being provided in the drive circuit. The sensor element included in the drive circuit only needs to have a configuration that exhibits a measurement function by selecting a thin film transistor included in the drive circuit.

[EL device]
The EL layer possessed by the EL element OEL may be composed of, for example, only a light emitting layer that serves both hole transport and electron transport, or has a laminated structure composed of a hole transporting light emitting layer and an electron transport layer. Alternatively, a stacked structure in which a charge transport layer is sandwiched between these layers may be used.

The EL element OEL whose emission is controlled by the pixel circuit DC may be, for example, an organic EL element, an inorganic EL element, a light emitting diode, or a drive type light emitting element If it is.

The EL device can be used in a display unit of various electronic devices such as a digital camera, a mobile personal computer, and a portable device.
In the EL device, the pixel arrangement direction is not limited to the two-dimensional direction, and may be a one-dimensional direction. For example, the EL device is an exposure device that is mounted on a photosensitive drum as a light emitting element array substrate in which a plurality of pixels PIX are arranged in a one-dimensional direction, and irradiates the photosensitive drum with light emitted from the light emitting element array substrate. Can also be used.

H: Selection level, L: Non-selection level, Cs: Retention capacitance, D1: Gradation data, DC: Pixel circuit, H1: First selection level, H2: Second selection level, Id: Drain current, L1: First Unselected level, L2 ... second unselected level, LC ... curve, Ld ... data line, Ls ... selected line, Lv ... power supply line, N1, N2, N3, N4 ... node, Po, PMh ... operating point, T1 ... Drive transistor, T2 ... hold transistor, T3 ... select transistor, Iel ... drive current, Ls1 ... first select line, Ls2 ... second select line, OEL ... EL element, PIX ... pixel, PMe, PMe2, PMe3 ... light emission operating point , SIG: video signal, SPe, SPe2, SPe3 ... load line, SPh, SPo, SPw ... characteristic line, Tem ... light emission operation period, Vcc ... power supply signal, Vel ... drive voltage, Vpo ... pin OFF voltage, Vth ... threshold voltage, OELL ... EL layer, SCLK ... timing signal, Tcyc ... drive cycle, Thld ... hold operation period, Twrt ... write operation period, Vccw ... write level, Vcss ... light emission level, Veff ... effective Voltage, SCON1 ... selection control signal, SCON2 ... data control signal, SCON3 ... power control signal, Vdata ... tone level, Vsel1 ... first selection signal, Vsel2 ... second selection signal, 100 ... EL device, 110 ... display signal generation Part 120, system controller 130, selection driver 130A, first selection driver 130B, second selection driver 140 data driver, 150 power driver, 160 EL panel.

Claims (7)

A current driving element;
A power line;
Holding capacity,
A selection line,
A first terminal connected to the current drive element; and a second terminal connected to the power supply line, wherein the first gate is connected to the first terminal via the storage capacitor. A driving transistor connected to
A holding transistor having a second gate connected to the selection line and changing conduction and non-conduction between the first gate and the second terminal according to a voltage level of the selection line;
A power line setting unit configured to set a voltage level of the power line;
A selection line setting unit configured to set a voltage level of the selection line;
With
The power supply line setting unit is configured to perform a writing operation and a driving operation,
In the write operation, the power supply line setting unit sets a write level for the power supply line, and the selection line setting unit sets a conduction level for the selection line, thereby setting the write level. A holding voltage corresponding to the
During the driving operation, the power line setting unit sets a driving level for the power line, and the selection line setting unit sets a first level for raising an on-current of the holding transistor, and Setting a non-conduction level between the second level at which the off-current is raised to the selection line, thereby causing a current corresponding to the holding voltage to flow to the current driving element based on the driving level. A current drive device that causes the drive transistor to perform. The selection line is a first selection line;
The non-conductive level is a first non-conductive level;
The selection line setting unit is a first selection line setting unit,
A second selection line;
Data lines,
A thin film transistor of the same channel type as the holding transistor, having a third gate connected to the second selection line, and conducting and non-conducting between the first terminal and the data line. A selection transistor that changes according to the voltage level of the selection line;
A data line setting unit configured to set a voltage level of the data line;
A second selection line setting unit configured to set a voltage level of the second selection line;
Further comprising
In the write operation, the data line setting unit sets a gradation level for the data line, and the second selection line setting unit sets a conduction level for the second selection line, Holding the holding voltage according to the difference between the writing level set by the power line setting unit and the gradation level set by the data line setting unit in the holding capacitor;
During the driving operation, when the first selection line setting unit sets the first non-conduction level to the first selection line, the second selection line setting unit is different from the first non-conduction level. The current driving device according to claim 1, wherein a second non-conduction level that is a level is set in the second selection line. The gradation level has the same polarity as the second non-conductive level;
The current driving device according to claim 2, wherein an absolute value of the first non-conduction level is smaller than an absolute value of the second non-conduction level. A conduction level of the first selection line is a first selection level;
A conduction level of the second selection line is a second selection level;
The current driving apparatus according to claim 2, wherein the first selection level is equal to the second selection level. The current drive device according to any one of claims 1 to 4, wherein the current drive element is an EL element. The current drive device according to any one of claims 1 to 4, wherein the current drive element is a sensor element. A first gate, a first terminal connected to the current driving element, and a second terminal connected to a power supply line, wherein the first gate is connected to the first terminal via a storage capacitor. A driving transistor,
A holding transistor having a second gate connected to a selection line, and changing conduction and non-conduction between the first gate and the second terminal according to a voltage level of the selection line;
A power line setting unit for setting a voltage level of the power line;
A selection line setting unit for setting a voltage level of the selection line;
A driving method of a current driving device comprising:
The power supply line setting unit sets a write level for the power supply line, and the selection line setting unit sets a conduction level for the selection line, whereby a holding voltage corresponding to the write level is set. Being held in the holding capacity;
The power supply line setting unit sets a drive level for the power supply line, and the selection line setting unit sets a first level for raising an on-current of the holding transistor and a first level for raising an off-current of the holding transistor. Setting a non-conduction level between two levels to the selection line, whereby the driving transistor causes a current corresponding to the holding voltage to flow to the current driving element based on the driving level. A driving method of a current driving device.

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