WO2015017876A1 - Potential control of modules - Google Patents

Abstract

The present invention relates to a method for controlling parallel-connected modules (M₁, M₂, M_N), each having at least two serially connected, controllable semiconductor valves (Y₁₁, Y₁₂,...Y_N1, Y_N2), preferably IGBT modules having two IGBTs each, and each having two direct current connections (1, 2) and an alternating current connection (3), wherein module currents (I₁, I₂...I_N) at the respective alternating current connection (3) form the currents through the controllable semiconductor valves (Y₁₁, Y₁₂,...Y_N1, Y_N2) of the relevant module (M₁, M₂, M_N), and the total of the module currents (I₁, I₂...I_N) of all modules (M₁, M₂, M_N) forms a load current (I_L). According to the invention, potentials (U₁, U₂,...U_N) per module (M₁, M₂, M_N) are identified at a branch point (4) of the alternating current connection (3) to the controllable semiconductor valves (Y₁₁, Y₁₂,...Y_N1, Y_N2) of the relevant module (M₁, M₂, M_N) and, by means of activation delays (Δt₁, Δt_N) of the controllable semiconductor valves (Y₁₁, Y₁₂,...Y_N1, Y_N2) the potentials (U₁, U₂,...U_N) of all modules (M₁, M₂, M_N) are controlled at the respective branch points (4) to the same value on average via the switching periods of the controllable semiconductor valves (Y₁₁, Y₁₂,...Y_N1, Y_N2).

Description

 Potential regulation of modules

FIELD OF THE INVENTION

The present invention relates to a method for controlling parallel-connected modules, each having at least two serially connected, controllable

Semiconductor valves, preferably IGBT modules, each having two IGBTs, and each having two DC terminals and an AC terminal, wherein module currents at the respective AC terminal, the currents through the controllable semiconductor valves of the module in question, and the sum of the module currents of all modules forms a load current, according to the preamble of claim 1.

The present invention further relates to a switching arrangement of parallel-connected modules, each having at least two serially connected, controllable

Semiconductor valves, preferably IGBT modules with two IGBTs (Insulated Gate Bipolar Transistors), wherein the modules common DC terminals and each of the modules has an AC terminal which is connected via a branch point with the controllable semiconductor valves of that module, and each controllable semiconductor valve a gate control device according to the preamble of claim 4.

STATE OF THE ART

In power electronics modules equipped with controllable semiconductor elements for controlling the current and / or current distribution of currents of high currents are known, usually within the modules usually two controllable semiconductor valves are connected in series. Usually, the controllable semiconductor valves are serially connected IGBTs with antiparallel freewheeling diode, whereby modules with MOSFETs (metal oxide semiconductor field effect transistor) in the

Power electronics are common. The arrangement of controllable Semiconductor valves in the form of individual modules is advantageous since sometimes several dozens of such semiconductor circuits in the power electronics are needed. The individual controllable semiconductor valves can be quickly positioned and connected by means of the modules. The modules can be prefabricated, or designed as a self-made circuit of individual, controllable semiconductor valves, wherein in both cases, a serial circuit of controllable semiconductor valves with connections for the controllable semiconductor valves is generally referred to as a module.

In this case, a module has at least two DC voltage connections and an AC connection in a conventional manner. Using the DC terminals, the modules can easily be connected in parallel along two lines that provide a DC voltage, also known as a DC bus. By controlling the switching states of the controllable

Semiconductor valves, usually by means of a command line from an external processor, can from the

DC power supply a desired current form, such as a sinusoidal AC, are modulated at the AC terminals. The modulation takes place by switching the controllable semiconductor valves with a switching frequency which corresponds to a higher frequency than that of the modulated current. For this purpose, it is possible to apply, for example, the pulse width modulation known from the prior art.

However, the possible current strengths at the AC connection of the individual modules are limited, which is why in a conventional manner a plurality of modules are connected in parallel and the AC terminals of the modules are connected to one another. A high load current is thus divided as module current of lesser strength on the individual AC terminals of the modules. Such a circuit of several modules for power distribution is usually less expensive than just run a module with high amperage compatibility. Often, several IGBTs are already inside an IGBT module parallel circuit provided to increase the maximum tolerated current of a module.

With a distribution of the load current to the individual modules, it is necessary that all possible

AC power connections are loaded with the same current, namely the load current divided by the number of modules. If the currents are not evenly distributed, some modules are sometimes over-loaded and damaged. However, the components used in the modules usually do not show the same, production-related characteristic characteristics, which makes a uniform distribution of the currents more difficult. This results in a conventional manner thus distortions of the distribution of the load current, by inaccurate switching operations of the controllable semiconductor valves or by uneven voltage drops across the semiconductor valves. A desired modulation of the load current can thus sometimes not be achieved.

In a conventional manner, the input currents at the AC terminal of the individual modules, hereinafter also referred to as module current, by means of a regulation of the currents at the respective AC terminal or on

DC voltage connection regulated to equal parts of the load current. However, such a control of currents is a technically complex measurement and control method. It is often attempted to select the controllable semiconductor valves of the modules in such a way that all controllable semiconductor valves have the same characteristics as possible. This should be ensured by selecting the semiconductors from the same manufacturing batch, which means an additional logistical effort until the modules are installed. But even such a selection does not ensure the uniform distribution of the module currents, as at different temperatures and different

Amperages the switching states and voltages on the controllable semiconductor valves can still vary. On a regulation of the currents can therefore usually not be waived. Furthermore, it is known that with high time constants of decoupling inductance and resistance of the modules, the distortions in the circuit of the controllable semiconductor valves can be kept low. High decoupling inductances and resistors, however, require larger sizes, but these are not possible in many applications and installation situations of the modules. In particular, must be for high

Decoupling inductors and resistors of the DC bus be elaborate executed.

OBJECT OF THE INVENTION

It is therefore an object of the invention to avoid these disadvantages and to provide a method for controlling generic, parallel-connected modules and a switching arrangement of generic, parallel-connected modules in such a way that the load current is evenly divided among the individual modules, wherein the controllable semiconductor valves also from different

Manufacturing batches can come from that

Entkopplungsinduktivität and the resistance of the modules are not limiting variables, the temperature of individual modules may be different and a modulation of the load current using controllable semiconductor valves optimally possible.

PRESENTATION OF THE INVENTION

These objects are achieved by the features of claim 1 and claim 4.

Claim 1 relates to a method for controlling parallel-connected modules, each having at least two serially connected, controllable semiconductor valves, preferably IGBT modules each having two IGBTs, and each having two DC terminals and one AC terminal, wherein module currents at the respective AC terminal, the currents through the controllable Semiconductor valves of the respective module form, and the sum of the module currents of all modules forms a load current. According to the invention, it is provided that potentials of each module in one Branching point of the AC power connection to the controllable semiconductor valves of the relevant module are determined and controlled by Einschaltverzögerungen the controllable semiconductor valves, the potentials of all modules in the respective branch points on average over the switching period of the controllable semiconductor valves to the same value.

In order to regulate all module currents of the individual modules to the same value, the measured value of the potentials in the branch point of the AC connection to the controllable semiconductor valves of the relevant module is thus used in the method according to the invention. The measurement of potentials is a simpler method of measurement than the measurement of currents. If the decoupling inductance and the resistance at the AC voltage connection of the modules are chosen to be the same for all modules, the same potential difference across these components results in the same input currents at the AC connections. Due to the different characteristics of the controllable

Semiconductor valves, in particular the switching characteristic, however, may vary this potential. If a controllable semiconductor valve switches earlier than the others, the input current of this module is higher than with the other modules. However, if all potentials in the respective branching point are equal, the input currents are divided equally. By regulating the potentials in the branch point, the uniform distribution of the input currents to the load current can thus be ensured. In this case, the potentials of all modules in the respective branching points are controlled to the same value on average over the switching period of the controllable semiconductor valves, so that the potential differences are controlled on average over this period to zero. In order to set the potentials at the branching point of all modules to the same value, the switch-on times become controllable

Semiconductor valves delayed so that all controllable semiconductor valves switch as possible simultaneously and the Potentials when switching with a predetermined switching frequency are the same on average.

According to a preferred embodiment of the method according to the invention it is provided that potential differences of a branch point of a semiconductor module to the

Branching points of each further semiconductor module are measured and by means of turn-on delays of the controllable semiconductor valves, the measured potential differences on average over the switching period of the controllable

Semiconductor valves are controlled to zero. The measurement of potential differences between the modules is an advantageous method of measurement. In each module, only one measuring point is tapped, and the measured value in this measuring point is compared with those of other modules. If this measured potential difference is zero, the respective input currents are in those modules in which the

Potential difference was measured, apart from a small tolerance range by the decoupling impedances, the same.

In accordance with a further preferred embodiment of the method according to the invention, it is provided that the switch-on delays are determined by comparing a time integral of several times the time integral of a controllable semiconductor valve within a predetermined maximum switch-on delay

Potential differences are determined with a predetermined maximum value. Thus, if the turn-on command of an IGBT goes, the potential difference to other modules is first compared. Exceeds the time integral of this

Potential difference a predetermined value, the power is delayed at the next power-on. In this way, the switching on of the semiconductor valves of a module is waited until all controllable semiconductor valves switch simultaneously, because then the potential difference between the branch points of the two modules compared is zero and the same input currents flow through these modules. If this method is now applied to all modules to each other, all controllable Semiconductor valves are switched simultaneously and none of the input currents is increased by switching too early or reduced by switching too late.

Claim 4 refers to a switching arrangement of parallel-connected modules, each having at least two serially connected controllable semiconductor valves, preferably IGBT modules each having two IGBTs, the modules common DC terminals and each of the modules an AC connection, via a branch point with the controllable semiconductor valves of the respective Module, and each controllable semiconductor valve has a gate control device. According to the invention, at least one control device is provided in each module, which is connected to the branching point of the relevant module and to the branching points of the respective other modules via measuring lines, wherein potential differences between the branching points of the respective modules can be determined with the measuring lines.

Thus, at least one control device is provided in each module, which is connected to the branch point of the relevant module, and determines the potential at this branching point. Since this is not a current measurement, each controller of a module can easily determine the potential of all modules, as will be explained in more detail, with the aid of only one measuring line.

In a preferred embodiment of the invention, it is provided that the control device is provided on a first gate control devices of a module, and is connected by means of a bidirectional control line to a second gate control device of the relevant module. The control device can be arranged approximately at a gate control device, the so-called gate driver, an IGBT, and thus space and the installation of an additional unit can be saved as a control device. Using bidirectional control lines, the controller can address all of the module's gate controllers. Are about two Controllable semiconductor valves in series and thus provided two gate control devices, the control device is arranged approximately directly to the first gate control device for the control thereof, while the second gate control device is controlled via the bidirectional control line.

According to a further embodiment of the invention, it is provided that the control device of one module is connected to the branch points of the respective other modules via the control devices of the respective other modules. The reading required for each module by the corresponding controller is the potential at the branch point of the module in question. In this case, however, it is only decisive what potential a module has relative to another module. If the potential difference to other modules via the respective control devices is compared from each branch point, then potential differences and, as a consequence, the switch-on delays can be determined. The control device switches the controllable semiconductor valves of the relevant module depending on the evaluation of the potential differences. The measuring lines of the individual modules must therefore only be connected to the respective control device, so that only one measuring line from each branch point of a module to the control device of the relevant module is required and the control device must be connected to those of the other modules. The measuring line can thus be designed as a rail when installing the modules, wherein the corresponding potential is tapped by each control device.

BRIEF DESCRIPTION OF THE FIGURES

The invention will be described below with reference to

Embodiments explained in more detail using the accompanying drawings. It show here the

1 shows an embodiment of parallel-connected modules, each with two controllable semiconductor valves for control via the method according to the invention, Fig. 2 shows an embodiment of the invention

Switching arrangement of parallel-connected modules, each with two controllable semiconductor valves,

3a the course of the potential in a first module and a second module over time,

Fig. 3b shows the course of a potential difference of a first

 Module to a second module over time as well

Fig. 4 shows an embodiment of a block diagram for

 Control of modules connected in parallel by means of the method according to the invention.

WAYS FOR CARRYING OUT THE INVENTION

FIG. 1 shows bridge branches with two controllable semiconductor valves Yn, Y12,... YNI _? YN2 _? namely IGBTs with antiparallel freewheeling diode, in parallel circuit. There is a positive DC connection 1, and a negative DC connection 2 is provided. These two

DC connections 1.2 form the so-called DC bus. Between the direct current terminals 1,2 respectively upper controllable semiconductor valve Y _N i, and a lower controllable semiconductor valve Y _N2 is connected in series, said serial circuit is repeated in parallel with the number of modules N. Each module Mi, M ₂ ,..., M _N has an AC terminal 3 connected in series with the emitter of a first (in FIG. 1 of the upper) controllable semiconductor valve Y _N i and the collector of one In the branch between the AC connection 3 and on the one hand the first semiconductor valve Y _N i and on the other hand, the second semiconductor valve Y _N2 is located at a second (in Fig. 1 of the lower) controllable semiconductor valve YN ₂

Branch point 4. The serial connection of the two semiconductor valves Y _N i, Y _N2 between the DC terminals 1,2 forms with the incoming AC terminal 3, a module M _N. Within a module M _N can be shown on the Position of a semiconductor valve Y _N i or Y _{N2 be} executed in parallel, a plurality of controllable semiconductor valves Y _N i, Y _N2 , in the present description in this case in each case representatively only a controllable semiconductor valve Y _N i or Y _{N2 is} shown. In the present description, the preferred embodiment of the controllable semiconductor valves is assumed to be IGBTs, but in principle any type of controllable switching element such as MOSFETs, GTOs, etc. may be provided.

The AC terminals 3 of the modules Mi, M ₂ , ..., M _N are connected to each other. Each alternating current connection 3 in this case leads to a module current I i, I ₂ , I _N - The module currents I i, I ₂ ,..., I _N together form a load current I _L , preferably in equal parts. In this case, the controllable semiconductor valves Yn, Y12, ... YN _I , YN2 are not loaded with different currents.

Furthermore, a decoupling inductance L _p and a resistance R _p , the so-called decoupling impedances, are provided at the AC terminals 3. This impedance smooths the current profile, wherein the time constant of the decoupling inductance L _p and the resistance R _{p is} a measure of the smoothing. If the same decoupling impedances are used for all modules Mi, M ₂ ,..., M _N, the same currents occur in the AC terminals 3.

2 shows an embodiment of the inventive switching arrangement of parallel-connected modules Mi, M ₂ ,..., M _N , each having two controllable semiconductor valves Y _N i, Y _N2 . In FIG. 2, three modules Mi, M ₂ , M ₃ are arranged in parallel. However, the circuit can be extended to more than three modules, usually depending on the power requirements of the load current I _Lf . Each controllable semiconductor valve Yn, Y12, ... YN _I , YN2 is provided with a gate control device 6, which is controlled via a command line 9 with a switching signal, such as from a processor. In this case, a command line 9 for the upper controllable semiconductor valves Y _N i and a command line 9 for the lower controllable semiconductor valves Y _{N2 is} provided (see Fig. 2). The processor controls the semiconductor valves Yn, Yi2, ... YN _{I f} YN ₂ with a switching frequency f _s , which is usually a multiple of the frequency of the load current I _L to be reached. By this known switching arrangement of the controllable semiconductor valves Y _N i, Y _N 2, the modulo currents I _I , I2, ..., IN modulated, such as with the aid of known from the prior art pulse width modulation.

At the gate control device 6 of a first with reference to FIG. 2 upper controllable semiconductor valve Y _N i, a control device 8 is provided. From this control device 8 leads a measuring line 5 both to the branching point 4 of the own module Mi and the control device 8 of the other modules M2, M3. The measuring line 5 can be carried out approximately as a rail, to which all control devices 8 are connected. Thus, the potential U _P in the branch point 4 of the same module Mi can be determined by the control device 8 in a simple manner, and via the connection to the control devices 8 of the other modules M2, M3 potential differences Ui2, U23, Ui3 to the branch points 4 of these modules M2, M3. These measured potential differences Ui2, U23, Ui3 serve as a measured variable in order to regulate a switch-on delay At _{N of} the controllable semiconductor valves Yu, Y12,... YN _I , YN2. The determined switch-on delays At _N for the switch-on command ON are subsequently transferred from the control device 8 to the gate control device 6 of the upper controllable semiconductor valve Y _N i with reference to FIG. 2, and via a bidirectional control line 7 to the gate control device of the lower controllable semiconductor valve Y _N 2 with reference to FIG. 2. Thus, only one controller 8 per module is necessary.

The switch-on delays At _N are shown below in FIG. 3 a, FIG. 3 a being a solid line representing the time characteristic of a potential U _N and a dotted line of a further potential U _{N +} i. The left flank in Fig. 3a represents the situation with a load current I _L less than zero, and the right flank in Fig. 3a shows the situation with a load current I _L greater than zero. Fig. 3b shows the same Time base, the measured potential differences U _N , _{N +} i between the two potentials U _N , U _{N +} i. The potential differences U _N , _{N +} i should be regulated to zero on average. This now works as follows:

The controllable semiconductor valves Yn, Y12,... Y _N I r Y _N 2 receive the commands for switching with a switching frequency f _s via the command line 9. In the following, the regulation process at the first switching-on of the upper semiconductor valves _Y.sub.N i described with reference to FIG. 2 will be described. The upper controllable semiconductor valve Yn according to FIGS. 1 and 2 switches at the left flank in FIG. 3a. The next controllable semiconductor valve Y21 switches at the dashed left flank according to FIG. 3a. This would result in a short time, namely within the illustrated input delay At _N , an increased module current Ii at the first module Mi. The resulting potential difference U12 is measured and included by the control device 8. In order to regulate the potential difference U12 to zero, the controllable semiconductor valve Yn has to switch later than the switch-on delay At _N by the width of the pulse in FIG. 3b. In this case there is no potential difference U12 and the same modulator currents Ii and I2 flow. In this way, the control device 8 regulates all switch-on delays At _{N of} the modules M _N with each other and switches via the gate control devices 6, the controllable semiconductor valves Y _N i, Y _N 2 so that on average over a switching period with a switching frequency f _s in the controllable Semiconductor valves Yu, Y12, ... Y _N I, _N 2, the potential differences U _NN are regulated to zero. Thus, the same module currents Ii, I2, I _{N result?} since at the same input impedance and the same potential U _{N the} same module currents II, I2, ... I _N flow.

A block diagram for controlling parallel-connected modules is shown in FIG. 4. By a command line 9, the switch-on command ON, which is provided with reference to FIGS. 1 and 2 for the upper controllable semiconductor valves Y _N i, and this signal is fed to a ramp function 11, wherein the ramp function 11 up to a vorzugebenden, maximum Switch-on delay At _max rises and thus pretending a waiting time. In the measuring branch, a potential difference U _NN between the potentials U _N and U _{N +} i is measured. This potential difference U _NN is supplied to an integrator 10. The result of the integrator 10 is executed up to a certain value, which is predetermined by a limiter 12. The determined value is forwarded to a difference node 15 and subtracted from the ramp function 11. By appropriate comparison with the aid of a comparator 13, a logical one is sent to the AND gate 14, whereupon the controllable semiconductor valve Y _N i switches. Thus, if a potential difference U _{NN is} measurable, then with the switching on of the respective controllable semiconductor valve Y _N i at the next switch-on command by the command line 9 with the switch-on delay At _N waits so that the potential difference U _NN on average over a switching period with the switching frequency f _s is zero.

It is immediately apparent from this that a method for controlling modules M ₁ , M 2,..., M _N connected in parallel and a corresponding switching arrangement of generic modules M ₁ , M 2,..., M _N are provided, in which the Module currents II, I 2, ... I _{N of} the individual modules Mi, M2, ..., M _N contribute in equal parts to the load current I _L , even if about the controllable semiconductor valves Yn, Y12, ... Y _N I _A Y _N 2 have different properties or the temperature of individual modules Mi, M2, ..., M _{N is} different. The modulation of the load current I _L by means of the controllable semiconductor valves Yn, Y12,... Y _f Y _N 2 is optimized in this way.

Reference sign list

1 positive DC connection

 2 negative DC connection

 3 AC connection

 4 branch point

 5 measuring line

 6 gate controller

 7 bidirectional control line

 8 control device

 9 command line

 10 integrator

 11 ramp function

 12 limiters

 13 comparator

 14 AND gate

 15 difference nodes

At _{N one-} second delay

 Atmax maximum switch-on delay fs switching frequency

 II load flow

 IN module current

 LP decoupling inductance

M _N module

 N number of modules

R _P resistance

U _N potential

 UNN potential difference

 YNI's first controllable semiconductor valve

Y _N2 second controllable semiconductor valve

Claims

Claims: 1. Method for controlling parallel-connected modules (Mi, M ₂ , M _N ), each with at least two serially connected, controllable semiconductor valves (Y11, Y12, ... Y i _f Y _N 2), preferably IGBT modules each having two IGBTs, and each having two DC terminals (1,2) and one AC terminal (3), wherein module currents (II, I2 ... I _N ) at the respective AC connection (3) the currents through the controllable semiconductor valves (Y11, Y12, ... Y _N i, Y _N 2) of the relevant module (Mi, M ₂ , M _N ) form, and the sum of the module currents (Ii, I2, ... I _N ) of all modules (Mi , M ₂ , M _N ) forms a load current (I _L ), characterized in that potentials (Ui, U ₂ , ... U _N ) each of a module (Mi, M ₂ , ... M _N ) at a branch point (4) of the AC connection (3) to the controllable Semiconductor valves (Yu, Y12, ... Y _N I, _N 2) of the relevant module (Mi, M ₂ , M _N ) are determined and by means of Switch-on delays (Ati, At _N ) of the controllable Semiconductor valves (Yu, Y12, ... Y _N I _/ - Y _N 2) the potentials (Ui, U ₂ , ... U _N ) of all modules (Mi, M ₂ , M _N ) in the respective branch points (4) on average over the switching period of the controllable semiconductor valves (Yn, Y12, ... YNI _/ -YN2 ) are regulated to the same value. 2. Method for controlling parallel-connected modules (Mi, M ₂ , M _N ) of controllable semiconductor valves (Yu, Y12, ... Y _N I _/ ■ Y _N 2) according to claim 1, characterized in that potential differences (U12, U21 , ... U _NN ) one Branching point (4) of a module (Mi, M ₂ , ... M _N ) to the branch points (4) of each further module (Mi, M ₂ , ... M _N ) are measured and by means of turn-on delays (Ati, At _N ) the controllable semiconductor valves (Yu, Y12,... Y _N I, _N 2) the average of the measured potential differences (U12, U21, ... U _N N) over the switching period of the controllable semiconductor valves (Yu, Y12, ... Y _N I, _N 2) to zero. 3. Method for controlling parallel-connected modules (Mi, M ₂ , M _N ) of controllable semiconductor valves (Y11, Y12, ... YNI _/ - YN2) according to claim 2, characterized in that the switch-on delays (Ati, At _N ) by comparing one, from a switch-ON (ON) to the controllable semiconductor valves (Yn, Y12, .. .Y _f YN2) within a predetermined maximum switch-on delay (At _max ), several times determined time integral of the measured potential differences (U ₁₂ , U ₂₁ , U _NN ) are determined with a predetermined maximum value. 4. Switching arrangement of parallel-connected modules (Mi, M ₂ , M _N ), each with at least two serially connected, controllable semiconductor valves (Y11, Y12, ... YNI _/ - YN2), preferably IGBT modules with two IGBTs each, where the modules (Mi, M ₂ , M _N ) have common DC connections (1,2) and each of the modules (Mi, M ₂ , M _N ) an AC connection (3), the via a branch point (4) with the controllable Semiconductor valves (Yu, Y12, ... YNI, N2) of the relevant module (Mi, M ₂ , M _N ), and each controllable semiconductor valve (Yu, Y12, ... YNI _/ - YN2) has a gate Control device (6), characterized in that in each module (Mi, M ₂ , ..., M _N ) at least one control device (8) is provided, with the branching point (4) of the bed meeting module (Mi, M ₂ , ..., M _N ) and with the branch points (4) of the respective other modules (Mi, M ₂ , M _N ) via measuring lines (5) is connected to the measuring lines (5) potential differences ( U ₁₂ , U ₂₁ , U _NN ) between the Branching points (4) of the respective modules (Mi, M ₂ , M _N ) can be determined. 5. Switching arrangement of parallel-connected modules (Mi, M ₂ , M _N ) according to claim 4, characterized in that the control device (8) on a first gate control means (6) of a module (Mi, M ₂ , M _N ) is provided and by means of a bidirectional control line ( 7) with a second gate control device (6) of the respective module (Mi, M ₂ , M _N ) is connected. 6. Switching arrangement of parallel-connected modules (Mi, M ₂ , M _N ) according to claim 4 or 5, characterized in that the control device (8) of a module (Mi, M ₂ , M _N ) with the branch points (4) of the respective other modules (Mi, M ₂ , M _N ) via the control devices (8) of the respective other modules (Mi, M ₂ , M _N ) is connected.