WO2015094198A1

WO2015094198A1 - Low power electrostatic discharge robust linear driver

Info

Publication number: WO2015094198A1
Application number: PCT/US2013/075875
Authority: WO
Inventors: Ker Yon Lau; Christopher P. Mozak
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2013-12-17
Filing date: 2013-12-17
Publication date: 2015-06-25
Anticipated expiration: 2016-06-17
Also published as: CN104734689A; CN104734689B

Abstract

Described is an apparatus which comprises: a p-type pull-up driver coupled to a pad; an n-type device operable as a first diode, the n-type device for coupling in parallel to the p-type pull-up driver; an n-type pull-down driver coupled to the pad; and a p-type device operable as a second diode, the p-type device for coupling in parallel to the n-type pull-down driver.

Description

Low POWER ELECTROSTATIC DISCHARGE ROBUST LINEAR DRIVER

BACKGROUND

[0001] Traditional input-output (I/O) drivers use high resistive CPRs (cost precision resistor or poly resistor) to achieve driver linearity. Consequently, large PMOS and NMOS transistors and parallel CPRs are used to achieve low driver output impedance (e.g., 50Ω driver impedance). Large PMOS and NMOS devices suffer from gate leakages that degrade power performance. One way to reduce the driver size is to use low resistive resistors. However, using low resistive resistors degrades driver linearity which negatively impacts signal integrity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a driver with large resistors and driving transistors.

[0004] Fig. 2 illustrates a high level architecture of a low power electrostatic discharge

(ESD) robust driver, according to one embodiment of the disclosure.

[0005] Fig. 3 illustrates a circuit of a low power ESD robust driver, according to one embodiment of the disclosure.

[0006] Figs. 4-5 illustrate pre-drivers for the low power ESD robust driver, according to one embodiment of the disclosure.

[0007] Fig. 6 illustrates a plot showing IV (current- voltage) curves and linear resistance of the low power ESD robust driver, according to one embodiment of the disclosure.

[0008] Fig. 7 illustrates a circuit of a low power ESD robust driver with compensation, according to one embodiment of the disclosure.

[0009] Fig. 8 illustrates a circuit of a low power ESD robust driver with cascoding, according to one embodiment of the disclosure.

[0010] Fig. 9 is a smart device or a computer system or an SoC (system-on-chip) with low power ESD robust driver, according to one embodiment of the disclosure.

DETAILED DESCRIPTION

[0011] Fig. 1 illustrates a driver 100 with large resistors and driving transistors. Driver

100 includes p-type pull-up driver having p-type transistors MP1 and MP2, n-type pull-down driver having n-type transistors MNl and MN2, CPRs, and electrostatic discharge (ESD) diodes Dl and D2 coupled to a pad. Here, CPRs are very large (e.g., 2kHs) and provide the necessary impedance linearity. Pull-up and pull-down driver transistors are made large (i.e., bigger W/L) to accommodate the large CPRs. The combination of pull-up and pull-down drivers, and the CPRs result in a large area. Large pull-up and pull-down drivers result in large power dissipation from dynamic switching and static gate leakage.

[0012] Some process nodes provide low resistive ballast resistors that can reduce the overall area used up by the CPRs. However, low resistive ballast resistors may degrade linearity of driver 100. Degraded impedance linearity translates to signal integrity issues (e.g., overshoot, undershoot, ring-back, degraded voltage and timing margins, etc.).

[0013] The embodiments provide driver linearity without the use of high resistive driver resistors. The embodiments provide driver linearization design which is ESD robust and operable to be compensated for high speed precision applications. The embodiments use a driver design which is about an order magnitude smaller in size than the driver of Fig. 1 while providing the necessary linearity for high quality signal integrity.

[0014] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0015] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0016] Throughout the specification, and in the claims, the term "connected" means a direct electrical connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" means at least one current signal, voltage signal or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0017] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slow down) of a signal frequency relative to another parameter, for example, power supply level. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value.

[0018] Unless otherwise specified the use of the ordinal adjectives "first," "second," and

"third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0019] For purposes of the embodiments, the transistors are metal oxide semiconductor

(MOS) transistors, which include drain, source, gate, and bulk terminals. The transistors also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors or other devices implementing transistor functionality like carbon nano tubes or spintronic devices. Source and drain terminals may be identical terminals and are interchangeably used herein. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "MN" indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0020] Fig. 2 illustrates a high level architecture 200 of a low power ESD robust driver, according to one embodiment of the disclosure. Architecture 200 comprises p-type pull-up driver 201, n-type pull-down driver 202, n-type linearizer 203, and p-type linearizer 204. In one embodiment, n-type linearizer 203 includes an n-type device operable as a pull-up diode. In one embodiment, p-type linearizer 204 includes a p-type device operable as a pull-down diode. Here the term "linearizer" refers to apparatus to assist with making impedance linear for an operating condition of a driver. In one embodiment, architecture 200 further comprises ESD diode Dl 205 and ESD diode D2 206 coupled to the pad.

[0021] In one embodiment, architecture 200 comprises P pre-driver 207 to drive pdata to p-type pull-up driver 201; and N pre-driver 208 to drive ndata to n-type pull-down driver 202. In one embodiment, P pre-driver 207 is modified to generate control signal for n-type linearizer 203 to cause it to operate as a diode. In one embodiment, N pre-driver 208 is modified to generate control signal for p-type linearizer 204 to cause it to operate as a diode. [0022] While the embodiments are discussed with reference to n-type and p-type linearizers together in one I/O driver, in one embodiment, either n-type or p-type linearizer may be used to achieve the desired linearization for the I/O driver.

[0023] In one embodiment, architecture 200 comprises first compensation unit 209 to compensate pull-up driver for process, temperature, and voltage (PVT) variations. In one embodiment, first compensation unit 209 is also used to adjust strength of compensation enabled devices in n-type linearizer 203. In one embodiment, a first compensation unit 209 may be used to adjust strength of compensation enabled devices in p-type linearizer 204.

[0024] In one embodiment, architecture 200 comprises a second compensation unit 210 to compensate pull-down driver 202 for PVT variations. In one embodiment, second compensation unit 210 is also used to adjust strength of compensation enabled devices in n-type linearizer 203. In one embodiment, second compensation unit 210 is used to adjust strength of compensation enabled devices in p-type linearizer 204. The strength of compensation enabled devices is adjusted by turning ON/OFF transistors coupled in parallel to achieve the desired impedance linearization. For example, the strength of compensation enabled devices is adjusted to achieve 50Hs of impedance at the pad.

[0025] In one embodiment, architecture 200 includes dedicated compensation units to adjust strength of compensation enabled devices in n-type linearizer 203 and p-type linearizer 204, respectively. For example, in one embodiment, architecture 200 comprises a third compensation unit 211 to adjust strength of compensation enabled devices in n-type linearizer 203. In one embodiment, architecture 200 comprises a fourth compensation unit 212 to adjust strength of compensation enabled devices in p-type linearizer 204.

[0026] Fig. 3 illustrates a circuit 300 of a low power ESD robust driver, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0027] In one embodiment, p-type pull-up driver 201 comprises p-type MP1 and p-type

MP2 devices coupled in series with low resistive resistor R2. In this embodiment, gate terminal of MP2 is controlled by "ppre" which his generated by P pre-driver 207. In one embodiment, the drain terminal of MP2 is coupled to one end of resistor R2 while the other end of resistor R2 is coupled to the pad. In one embodiment, MP1 is used to compensate p-type pull-up driver 201 for PVT variations to maintain pull-up output impedance at the pad. In this embodiment, gate terminal(s) of MP1 are controlled by pstr<x> which is an output of first compensation unit 209, where 'x' is an integer greater than one. Here, pstr<x> adjusts strength of MP1 by turning ON/OFF transistors in parallel. [0028] In one embodiment, n-type pull-down driver 202 comprises n-type MN1 and n- type MN2 devices coupled in series with the low resistive resistor R2. In this embodiment, gate terminal of MN2 is controlled by "npre" which is generated by N pre-driver 208. In one embodiment, the drain terminal of MN2 is coupled to one end of resistor R2 which is also coupled to the drain terminal of MP2. In one embodiment, MN1 is used to compensate n-type pull-down driver 202 for PVT variations to maintain pull-down output impedance at the pad. In this embodiment, gate terminal(s) of MN1 are controlled by nstr<x> which is an output of second compensation unit 210, where 'x' is an integer greater than one. Here, nstr<x> adjusts strength of MN1 by turning on/off transistors in parallel.

[0029] In one embodiment, n-type linearizer 203 comprises n-type MNL which is operable to function as a diode. In one embodiment, n-type linearizer 203 is coupled in series with a low resistive resistor Rl which is coupled at one end to the source terminal of MNL and coupled to the pad at the other end. In one embodiment, drain terminal of MNL is coupled to power supply Vcc. In one embodiment, MNL is operable to function as a diode by ppre_b signal from P pre-driver 207, where ppre_b is an inverse of ppre.

[0030] For example, when ppre_b is a logical high, MNL operates as a diode. In this embodiment, gate terminal of MNL is decoupled from pad via resistor Rl, and so MNL is protected from ESD. Here, signal names and node names are interchangeably used. For example, ppre is used to refer to either ppre signal or ppre node depending on context of the sentence.

[0031] In one embodiment, p-type linearizer 204 comprises p-type MPL which is operable to function as a diode. In one embodiment, p-type linearizer 204 is coupled in series with the low resistive resistor Rl which is coupled at one end to the source terminal of MPL and coupled to the pad and source terminal of MNL at the other end. In one embodiment, bulk terminal of MPL is coupled to power supply Vcc. In one embodiment, drain terminal of MPL is coupled to ground supply Vss. In one embodiment, MPL is operable to function as a diode by npre_b signal from N pre-driver 208, where npre_b signal is an inverse of npre signal. For example, when npre_b signal is a logical low, MPL operates as a diode. In this embodiment, gate terminal of MPL is decoupled from pad via resistor Rl, and so MPL is protected from ESD.

[0032] The embodiments result in substantially linear relationship between ipad (current through pad) and voltage on pad i.e., the embodiments result in linear output impedance at the pad. One reason for such linear output impedance is the combination of non- linear currents inl and in2 relative to the pad voltage. In one embodiment, the non- linear currents of inl and in2 are generated by diode enabled MNL and MPL devices. [0033] In the embodiments, diode enabled MNL is used for pull-up linearization instead of pull-down linearization. One reason for using diode enabled MNL for pull-up linearization is to provide more robust ESD protection to MNL by avoiding coupling of gate terminal of MNL to the pad. In the embodiments, diode enabled MPL is used for pull-down linearization instead of pull-up linearization. One reason for using diode enabled MPL for pull-down linearization is to provide more robust ESD protection to MPL by avoiding coupling of gate terminal of MPL to the pad. Resistor Rl further provides ESD protection to MNL and MPL devices.

[0034] Figs. 4-5 illustrate pre-drivers 400 and 500 respectively for the low power ESD robust driver, according to one embodiment of the disclosure. It is pointed out that those elements of Figs. 4-5 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0035] In one embodiment, P pre-driver 400 (e.g., 207) comprises an inverter inv2, p- type Mppl and n-type Mnpl. In one embodiment, Mppl and Mnpl are coupled in series. In one embodiment, resistor Rp is coupled in series with Mppl and Mnpl. In one embodiment, gate terminals of Mppl and Mnpl are coupled to output of inverter inv2, which inverts incoming pdata. In one embodiment, source terminal of Mppl is coupled to Vcc and drain terminal of Mppl provides ppre for MP2. In one embodiment, drain terminal of Mppl is coupled to resistor Rp at one end while the other end of resistor Rp is coupled to drain terminal of Mnpl. In one embodiment, source terminal of Mnpl is coupled to ground. In one embodiment, output of inverter inv2 provides ppre_b signal for MNL.

[0036] In one embodiment, ppre_b signal turns ON MNL first to absorb reflection and then ppre signal slowly turns ON MP2. Here, the reflection which is absorbed is caused by mismatch in impedances of the source follower and the saturation resistor, where the source follower output impedance is 1/gm while the saturation transistor output impedance is r₀. Here, MNL is the source follower. In one embodiment, MP1 and MP2 have IV (current- voltage) curves that saturate at high Vds (pull-up).

[0037] In one embodiment, N pre-driver 500 (e.g., 208) comprises an inverter invl, p- type Mpp2, and n-type Mnp2. In one embodiment, Mpp2 and Mnp2 are coupled in series. In one embodiment, resistor Rn is coupled in series with Mpp2 and Mnp2. In one embodiment, gate terminals of Mpp2 and Mnp2 are coupled to output of inverter invl, which inverts incoming ndata signal. In one embodiment, source terminal of Mpp2 is coupled to resistor Rn at one end, while the other end of resistor Rn is coupled to Vcc. In one embodiment, drain terminal of Mpp2 provides npre signal for MN2. In one embodiment, source terminal of Mnp2 is coupled to ground. In one embodiment, output of inverter invl provides npre_b signal for MPL. [0038] In one embodiment, npre_b signal turns ON MPL first to absorb reflection and then npre signal slowly turns ON driver pull-down MN2. Here, the reflection which is absorbed is caused by mismatch in impedances of the source follower and the saturation resistor, where the source follower output impedance is 1/gm while the saturation transistor output impedance is r₀. Here, MPL is the source follower. In one embodiment, MN1 and MN2 have IV curves that saturate at high Vds (pull-down).

[0039] Fig. 6 illustrates a plot 600 showing IV curves and linear resistance of the low power ESD robust driver, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0040] Here, x-axis is voltage and y-axis is current. Plot 600 shows three waveforms— inl, in2, and 701, where 701 is the pad current relative to pad voltage. The embodiments use the combination of waveforms inl and in2 to form substantially linear waveform 701. Here, inl is current through resistor R2 while in2 is current through resistor Rl relative to pad voltages. Substantially linear waveform 701 indicates a substantially linear output impedance of circuit 300 and other embodiments of I/O driver.

[0041] Fig. 7 illustrates a circuit 700 of a low power ESD robust driver with

compensation, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 7, differences between Fig. 3 and Fig. 7 are discussed.

[0042] In one embodiment, n-type linearizer 203 includes compensation enable device(s). In one embodiment, compensation enable device(s) are coupled in series with MNL device. In one embodiment, compensation enable device(s) are p-type MPcL devices. In another embodiment, compensation enable device(s) are n-type devices (not shown). In one embodiment, MPcL is controllable by nstrb<x> signal, where 'x' is an integer greater than one. In one embodiment, MPcL includes a plurality of transistors coupled in parallel. In one embodiment, nstrb<x> is generated by first compensation unit 209. In one embodiment, nstrb<x> is generated by a dedicated third compensation unit 211.

[0043] In one embodiment, nstrb<x> signal adjusts strength of MPcL to compensate for

PVT variations to maintain output impedance linearity across PVT. In one embodiment, nstrb<x> signal is an inverse of nstr<x> signal which is used to compensate MN1 of pull-down driver 202. While the embodiment is discussed with reference to a p-type compensation enabled device, in one embodiment, the compensation enable device in n-type linearizer 203 is an n-type device(s).

[0044] In one embodiment, p-type linearizer 204 includes compensation enable device(s). In one embodiment, compensation enable device(s) are coupled in series with MPL device. In one embodiment, compensation enable device(s) are n-type MNcL devices. In another embodiment, compensation enable device(s) are p-type devices (not shown). In one embodiment, MNcL is controllable by pstrb<x> signal, where 'x' is an integer greater than one. In one embodiment, MNcL includes a plurality of transistors in parallel. In one embodiment, pstrb<x> signal is generated by second compensation unit 210. In one embodiment, pstrb<x> signal is generated by a dedicated fourth compensation unit 212.

[0045] In one embodiment, pstrb<x> signal adjusts strength of MNcL to compensate for

PVT variations to maintain output impedance linearity across PVT. In one embodiment, pstrb<x> signal is an inverse of pstr<x> signal which is used to compensate MP1 of pull-up driver 201. While the embodiment is discussed with reference to an n-type compensation enabled device, in one embodiment, the compensation enable device(s) in p-type linearizer 204 comprise p-type device(s).

[0046] In one embodiment, p-type pull-up driver 201 and n-type pull-down driver 202 are organized as multiple parallel instances, for example, each of the seven instances being 16x, 8x, 4x, 2x, lx, lx, and lx, where 'x' indicates number of transistors (MP1, MP2, MN2, MN1) in parallel. In one embodiment, n-type linearizer 203 and p-type linearizer 204 are organized as multiple parallel instances e.g., each of the three instances being 8y, 4y, and 2y, where 'y' indicates number of transistors (MNL, MPL) in parallel.

[0047] In one embodiment, during a negative ESD event, source PN junction of MNL is forward biased. In such an embodiment, voltage is developed across resistor Rl which pushes up voltage on the source terminal of MNL to protect the gate oxide of MNL. In one

embodiment, the same PN junction forward bias happens to MN2. In such an embodiment, resistor R2 pushes up voltage to drain terminal of MN2 to protect the gate oxide on MP2 and MN2.

[0048] In one embodiment, during a positive ESD event, source PN junction of MPL is forward biased. In such an embodiment, voltage drops across resistor Rl which protects the gate oxides of MNL and MPL. In this embodiment, PN junction forward bias happens to MP2 drain junction too. In one embodiment, resistor R2 drops voltage on drain terminal of MP2 to protect gate oxide of MP2.

[0049] Fig. 8 illustrates a circuit 800 of a low power ESD robust driver with cascoding, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 8, differences between Fig. 7 and Fig. 8 are discussed.

[0050] In one embodiment, n-type linearizer 203 includes a cascode device which is either a p-type or n-type device. In one embodiment, the cascode device is p-type MPbL device coupled in series to MNL. In one embodiment, gate terminal of MPbL is controlled by a bias voltage pbias. In one embodiment, pbias is 1.8V when Vcc is 3.3V. In other embodiments, other values for Vcc and pbias may be used. In one embodiment, source terminal of MPbL is coupled to Vcc and drain terminal of MPbL is coupled to MNL. In one embodiment, source terminal of MPbL is coupled to drain terminal of MPcL (i.e., compensation enable device).

[0051] In one embodiment, p-type pull-up driver 201 also includes a cascode device which is either a p-type or n-type device coupled in series to MP2. In one embodiment, the cascode device of p-type pull-up driver 201 is p-type MP3. In one embodiment, gate terminal of MP3 is controlled by a bias voltage pbias. In one embodiment, pbias is 1.8V when Vcc is 3.3V. In other embodiments, other values for Vcc and pbias may be used. In one embodiment, source terminal of MP3 is coupled to drain terminal of MP2 and drain terminal of MP3 is coupled to resistor R2.

[0052] In one embodiment, p-type linearizer 204 includes a cascode device which is either a p-type or n-type device. In one embodiment, the cascode device is an n-type MNbL device coupled in series to MPL. In one embodiment, gate terminal of MNbL is controlled by a bias voltage nbias. In one embodiment, nbias is 1.8V when Vcc is 3.3V. In other embodiments, other values for Vcc and nbias may be used. In one embodiment, source terminal of MNbL is coupled to Vss and drain terminal of MNbL is coupled to MPL. In one embodiment, source terminal of MNbL is coupled to drain terminal of MNcL (i.e., compensation enable device).

[0053] In one embodiment, n-type pull-down driver 202 also includes a cascode device which is either a p-type or n-type device coupled in series to MN2. In one embodiment, the cascode device of n-type pull-down driver 202 is n-type MN3. In one embodiment, gate terminal of MN3 is controlled by a bias voltage nbias. In one embodiment, nbias is 1.8V when Vcc is 3.3V. In other embodiments, other values for Vcc and nbias may be used. In one embodiment, source terminal of MN3 is coupled to drain terminal of MN2 and drain terminal of MN3 is coupled to resistor R2. One technical effect of the cascode device is improved linearity of the output impedance.

[0054] Fig. 9 is a smart device or a computer system or an SoC (system-on-chip) 1600 with low power ESD robust driver, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0055] Fig. 9 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In one embodiment, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart- phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0056] In one embodiment, computing device 1600 includes a first processor 1610 with low power ESD robust driver described with reference to embodiments discussed. Other blocks of the computing device 1600 may also include low power ESD robust driver described with reference to embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant or a wearable device.

[0057] In one embodiment, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. Processor 1690 may be optional.

While the embodiment shows two processors, a single or more than two processors may be used. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0058] In one embodiment, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[0059] Display subsystem 1630 represents hardware (e.g., display devices) and software

(e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0060] I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0061] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[0062] In one embodiment, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0063] In one embodiment, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600. [0064] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0065] Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0066] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[0067] Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems. [0068] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0069] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0070] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0071] While the disclosure has been described in conjunction with specific

embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures e.g., Dynamic RAM (DRAM) may use the embodiments discussed. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0072] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0073] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0074] For example, an apparatus is provided which comprises: a p-type pull-up driver coupled to a pad; an n-type device operable as a first diode, the n-type device for coupling in parallel to the p-type pull-up driver; an n-type pull-down driver coupled to the pad; and a p-type device operable as a second diode, the p-type device for coupling in parallel to the n-type pulldown driver.

[0075] In one embodiment, the apparatus further comprises: a first resistor coupled at one end to the pad and coupled to the n-type device and the p-type device at the other end. In one embodiment, the apparatus further comprises: a second resistor coupled at one end to the pad and coupled to the n-type pull-down driver and the p-type pull-up driver at the other end. In one embodiment, the apparatus further comprises a first compensation enable device coupled in series to the n-type device.

[0076] In one embodiment, the apparatus further comprises a first cascode device coupled in series to the n-type device. In one embodiment, the apparatus further comprises a first compensation unit to compensate the p-type pull-up driver. In one embodiment, the apparatus further comprises a second compensation unit different from the first compensation unit, the second compensation unit to compensate the pull-down driver. In one embodiment, the second compensation unit to adjust strength of the first compensation enable device. In one embodiment, the first compensation unit to adjust strength of the first compensation enable device.

[0077] In one embodiment, the apparatus further comprises a second compensation enable device coupled in series to the p-type device. In one embodiment, the apparatus further comprises a second cascode device coupled in series to the p-type device. In one embodiment, the apparatus further comprises a third compensation unit to adjust strength of the first compensation enable device. In one embodiment, the apparatus further comprises a fourth compensation unit different from the third compensation unit, the fourth compensation unit to adjust strength of the second compensation enable device.

[0078] In another example, an apparatus is provided which comprises: a p-type pull-up driver coupled to a pad; an n-type device operable as a diode; and a resistor coupled at one end to the pad and coupled to the n-type device at another end, wherein the n-type device is coupled in series to the resistor, and wherein the n-type device and the resistor are coupled together in parallel to the p-type pull-up driver. In one embodiment, the apparatus further comprises a compensation enable device coupled in series to the n-type device. In one embodiment, the apparatus further comprises a cascode device coupled in series to the n-type device.

[0079] In another example, an apparatus is provided which comprises: an n-type pulldown driver coupled to a pad; a p-type device operable as a diode; and a resistor coupled at one end to the pad and coupled to the n-type pull-down driver at another end, wherein the p-type device and the resistor are coupled together in parallel to the n-type pull-down driver. In one embodiment, the apparatus further comprises a compensation enable device coupled in series to the p-type device. In one embodiment, the apparatus further comprises a cascode device coupled in series to the p-type device.

[0080] In another example, a system is provided which comprises: a memory unit; a processor coupled to the memory unit, the processor having a transmitter according to the apparatus described above. In one embodiment, the system further comprises a wireless interface for allowing the processor to communicate with another drive. In one embodiment, the system further comprises a display unit. In one the display unit is a touch screen.

[0081] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS We claim:

1. An apparatus comprising:

a p-type pull-up driver coupled to a pad;

an n-type device operable as a first diode, the n-type device for coupling in parallel to the p-type pull-up driver;

an n-type pull-down driver coupled to the pad; and

a p-type device operable as a second diode, the p-type device for coupling in parallel to the n-type pull-down driver.

2. The apparatus of claim 1 further comprises:

a first resistor coupled at one end to the pad and coupled to the n-type device and the p-type device at the other end.

3. The apparatus of claim 1 further comprises:

a second resistor coupled at one end to the pad and coupled to the n-type pulldown driver and the p-type pull-up driver at the other end.

4. The apparatus of claim 1 further comprises a first compensation enable device coupled in series to the n-type device.

5. The apparatus of claim 4 further comprises a first cascode device coupled in series to the n-type device.

6. The apparatus of claim 4 further comprises a first compensation unit to compensate the p- type pull-up driver.

7. The apparatus of claim 6 further comprises a second compensation unit different from the first compensation unit, the second compensation unit to compensate the pull-down driver.

8. The apparatus of claim 7, wherein the second compensation unit to adjust strength of the first compensation enable device.

9. The apparatus of claim 6, wherein the first compensation unit to adjust strength of the first compensation enable device.

10. The apparatus of claim 4 further comprises a second compensation enable device coupled in series to the p-type device.

11. The apparatus of claim 10 further comprises a second cascode device coupled in series to the p-type device.

12. The apparatus of claim 10 further comprises a third compensation unit to adjust strength of the first compensation enable device.

13. The apparatus of claim 12 further comprises a fourth compensation unit different from the third compensation unit, the fourth compensation unit to adjust strength of the second compensation enable device.

14. An apparatus comprising:

a p-type pull-up driver coupled to a pad;

an n-type device operable as a diode; and

a resistor coupled at one end to the pad and coupled to the n-type device at another end, wherein the n-type device is coupled in series to the resistor, and wherein the n-type device and the resistor are coupled together in parallel to the p-type pull-up driver.

15. The apparatus of claim 14 further comprises a compensation enable device coupled in series to the n-type device.

16. The apparatus of claim 15 further comprises a cascode device coupled in series to the n- type device.

17. An apparatus comprising:

an n-type pull-down driver coupled to a pad;

a p-type device operable as a diode; and a resistor coupled at one end to the pad and coupled to the n-type pull-down driver at another end, wherein the p-type device and the resistor are coupled together in parallel to the n-type pull-down driver.

18. The apparatus of claim 17 further comprises a compensation enable device coupled in series to the p-type device.

19. The apparatus of claim 17 further comprises a cascode device coupled in series to the p- type device.

20. A system comprises:

a memory unit;

a processor coupled to the memory unit, the processor having a transmitter according to any one of apparatus claims 1 to 13; and

a wireless interface for allowing the processor to communicate with another drive.

21. A system comprises:

a memory unit;

a processor coupled to the memory unit, the processor having a transmitter according to any one of apparatus claims 14 to 16; and

22. A system comprises:

a memory unit;

a processor coupled to the memory unit, the processor having a transmitter according to any one of apparatus claims 17 to 19; and