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WO2015079582A1 - Procédé de jonction de substrat - Google Patents

Procédé de jonction de substrat Download PDF

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Publication number
WO2015079582A1
WO2015079582A1 PCT/JP2013/082267 JP2013082267W WO2015079582A1 WO 2015079582 A1 WO2015079582 A1 WO 2015079582A1 JP 2013082267 W JP2013082267 W JP 2013082267W WO 2015079582 A1 WO2015079582 A1 WO 2015079582A1
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WIPO (PCT)
Prior art keywords
metal
powder
bonding
substrates
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2013/082267
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English (en)
Japanese (ja)
Inventor
今泉延弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2013/082267 priority Critical patent/WO2015079582A1/fr
Priority to JP2015550525A priority patent/JP6269682B2/ja
Priority to TW103126218A priority patent/TWI605740B/zh
Publication of WO2015079582A1 publication Critical patent/WO2015079582A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Definitions

  • the present invention relates to a method for bonding substrates, for example, a method for bonding substrates for bonding metal layers formed on a substrate.
  • the method for bonding the substrates is aimed at improving the bonding strength between the metal layers.
  • the bonding strength between the metal layers can be improved.
  • FIG. 1A is a cross-sectional view of a semiconductor device according to Comparative Example 1
  • FIGS. 1B and 1C are enlarged perspective views of a metal layer and a molten metal.
  • 2A and 2B are cross-sectional views of the semiconductor device according to Comparative Example 2.
  • FIG. 3A and 3B are cross-sectional views of the semiconductor device according to Comparative Example 1.
  • FIG. 4A to 4C are enlarged views of the metal layer.
  • FIG. 5A to FIG. 5D are cross-sectional views illustrating the substrate bonding method according to the first embodiment.
  • FIG. 6A and FIG. 6B are cross-sectional views (part 1) illustrating the bonding method of the substrates according to the second embodiment.
  • FIG. 7A to 7C are cross-sectional views (part 2) illustrating the bonding method of the substrates according to the second embodiment.
  • FIG. 8A to FIG. 8D are cross-sectional views illustrating a method for bonding substrates according to the third embodiment.
  • FIG. 9A and FIG. 9B are cross-sectional views of the powder of Example 3.
  • FIG. 10A to FIG. 10C are cross-sectional views illustrating the substrate bonding method according to the fourth embodiment.
  • FIG. 11A and FIG. 11B are cross-sectional views of the powder of Example 4.
  • FIG. 12A to FIG. 12C are cross-sectional views illustrating the substrate bonding method according to the fifth embodiment.
  • FIG. 13A and FIG. 13B are cross-sectional views of the powder of Example 5.
  • FIG. 14C are cross-sectional views illustrating the substrate bonding method according to the sixth embodiment.
  • FIG. 15A to FIG. 15C are cross-sectional views (part 1) showing the bonding method of the substrates according to the seventh embodiment.
  • FIG. 16A to FIG. 16C are cross-sectional views (part 2) illustrating the bonding method of the substrates according to the seventh embodiment.
  • FIG. 17A and FIG. 17B are cross-sectional views (part 3) illustrating the bonding method of the substrates according to the seventh embodiment.
  • FIG. 18A to FIG. 18C are cross-sectional views (part 4) illustrating the bonding method of the substrates according to the seventh embodiment.
  • FIG. 1A is a cross-sectional view of a semiconductor device according to Comparative Example 1.
  • FIG. FIG. 1B and FIG. 1C are enlarged perspective views of the metal layer and the molten metal.
  • a metal layer 12 is formed on a substrate 10.
  • An electrode 24 is formed on the substrate 20 (lower in the drawing), and a metal layer 22 is formed on the electrode 24.
  • the metal layers 12 and 22 are joined using a molten metal 40 such as solder.
  • FIG. 1B shows an example of the metal layer 22.
  • the metal layer 22 is a metal terminal mainly including Cu (copper), for example.
  • a molten metal 40 is formed on the metal layer 22.
  • the width W1 of the metal layer 22 (diameter when the metal layer 22 is a cylinder) is, for example, 35 ⁇ m, the height H1 of the metal layer 22 is, for example, 30 ⁇ m, and the height H2 of the molten metal 40 is, for example, 13 ⁇ m.
  • a barrier layer 23 is formed between the metal layer 22 and the molten metal 40.
  • the barrier layer 23 mainly contains, for example, Ni (nickel).
  • the height H3 of the barrier layer 23 is 5 ⁇ m, for example. The barrier layer 23 suppresses the reaction between the metal layer 22 and the molten metal 40.
  • the ratio of the height H1 to the width W1 of the metal layer 22 increases, for example, 1 or more.
  • the reason for increasing this ratio is to cope with the warpage of the substrates 10 and 20 caused by the difference in the thermal expansion coefficients of the substrates 10 and 20, for example.
  • FIG. 2A and 2B are cross-sectional views of a semiconductor device according to Comparative Example 2.
  • FIG. 2A is a view before joining the substrates
  • FIG. 2B is an enlarged view of the metal layer after joining.
  • the molten metal 40 is formed on the metal layer 22 (lower in the drawing) by, for example, electrolytic plating.
  • the surface of the molten metal 40 formed by the electrolytic plating method has large irregularities.
  • the molten metal 40 and the metal layer 12 are made to contact, and the metal layers 12 and 22 are joined by heating. At this time, a region where the molten metal 40 is not in contact is formed at the interface with the metal layer 22. For this reason, a void 42 is generated in the molten metal 40.
  • the void 42 is likely to occur.
  • FIG. 3A and 3B are cross-sectional views of the semiconductor device according to Comparative Example 1.
  • FIG. 3A is a view before bonding of the substrates
  • FIG. 3B is an enlarged view of the metal layer after bonding.
  • the molten metal 40 is heated to a temperature equal to or higher than the melting point before the bases 10 and 20 are joined. Thereby, the molten metal 40 becomes dome shape (namely, hemispherical).
  • FIG. 3B after joining the metal layers 12 and 22, generation of voids in the molten metal 40 is suppressed.
  • 4 (a) to 4 (c) are enlarged views of the metal layer.
  • a semiconductor element may be mounted on a circuit board such as a silicon interposer.
  • semiconductor devices may be highly integrated by three-dimensionally stacking semiconductor elements.
  • the wiring can be formed by using a manufacturing process used in the wiring formation process of the semiconductor element. For this reason, a wiring density of 50 times or more can be realized as compared with the resin circuit board. Therefore, the diameters of the metal layers 12 and 22 are 1/8 of the diameter of the resin circuit board.
  • the height H2 of the molten metal 40 is decreased. This is because the diameter of the dome is substantially the same as the width of the metal layer 22, and therefore the upper limit of the volume of the spherical molten metal 40 that can be formed on the metal layer 22 is determined.
  • the molten metal 40 is heated to form a dome shape, the molten metal 40 and the metal layer 22 react to form an alloy layer 44.
  • the height H4 of the alloy layer 44 is determined by the amount of heat during heating regardless of the width of the metal layer 22. Therefore, the height H4 of the alloy layer 44 is substantially constant.
  • the width W1 of the metal layer 22 decreases, the ratio of the alloy layer 44 increases. Since the melting point of the alloy layer 44 is higher than that of the molten metal 40, the metal layers 12 and 22 cannot be bonded satisfactorily.
  • FIG. 5A to FIG. 5D are cross-sectional views illustrating the substrate bonding method according to the first embodiment.
  • the electrode 14 is formed on the upper surface of the substrate 10.
  • a metal layer 12 is formed on the electrode 14.
  • An electrode 24 is formed on the lower surface of the substrate 20.
  • a metal layer 22 is formed under the electrode 24.
  • the bases 10 and 20 are, for example, a semiconductor substrate such as a silicon substrate or an insulating substrate such as a resin substrate.
  • the electrodes 14 and 24 mainly contain a metal such as Cu or Al (aluminum).
  • the metal layers 12 and 22 mainly contain Cu or the like, for example.
  • a plurality of powders 32 are fixed to the lower surface of the metal layer 22.
  • the powder 32 is particulate and includes a metal 35 (first metal) such as Cu, for example.
  • the particle size of the powder 32 is, for example, 1 ⁇ m to several ⁇ m.
  • the plurality of powders 32 may be a single layer of powder 32, but may be two or more layers of powder 32.
  • the powder 32 is formed using, for example, an atomizing method.
  • the powder 32 is fixed to the surface of the metal layer 22 using, for example, ultrasonic waves.
  • the metal layers 12 and 22 are opposed to and brought into contact with each other through the plurality of powders 32 so that the powder 32 contacts the upper surface of the metal layer 22.
  • the surfaces of the plurality of powders 33 are replaced with molten metal 36 (second metal).
  • the entire metal 35 in the powder 32 is replaced with a molten metal 36 to obtain a powder 33.
  • a replacement plating method using electroless plating is used.
  • the displacement plating method is a method of replacing a metal having a low standard electrode potential with a metal having a high standard electrode potential.
  • the metal 35 includes Sn
  • the molten metal 36 may be a metal including at least one of Cu, In, Ni, Fe, Mn, Zr, Ti, Al, Cr, and Zn.
  • the powder 33 is heated to a melting point of the molten metal 36 or higher and below the melting point of the metal layer 34, whereby the molten metal 36 is melted to become the metal layer 34.
  • the metal layers 12 and 22 are joined by the metal layer 34.
  • Example 1 As shown in FIG. 5B, the metal layers 12 and 22 formed on the plurality of substrates 10 and 20 are opposed to each other through the porous body including the plurality of powders 32.
  • the metal 35 on the surface of the plurality of powders 32 is replaced with molten metal 36.
  • the metal layers 12 and 22 are joined together by heating the molten metal 36.
  • the alloy layer 44 is not formed as shown in FIGS. Therefore, the bonding strength between the metal layers 12 and 22 can be improved.
  • the porous body including the plurality of powders 32 has a large surface area per unit volume, the metal 35 can be easily replaced with the molten metal 36.
  • the porous body can be easily fixed to the surface of the metal layer 12 or 22 by using the plurality of powders 32 as the porous body.
  • Example 2 is an example in which substrates are laminated.
  • FIG. 6A to FIG. 7C are cross-sectional views illustrating a method for bonding substrates according to the second embodiment.
  • the bases 10a and 20a, the metal layers 12a and 22a, the electrodes 14a and 24a, and the powder 32a are the same as the bases 10 and 20 and the metal layers 12 and 22 shown in FIG. Same as electrodes 14 and 24 and powder 32.
  • An electrode 14b is formed on the upper surface of the base body 20a, and a metal layer 12b is formed on the electrode 14b.
  • the electrode 14b and the electrode 24a are electrically connected through a through electrode formed in the base body 20a.
  • the electrode 14b and the electrode 24a may be electrically connected to a circuit formed in the base body 20a.
  • the base body 20b is laminated on the base body 20a.
  • Each metal layer 12b is opposed to each metal layer 22b with a plurality of powders 32b interposed therebetween.
  • the base body 20c is laminated on the base body 20b.
  • Each metal layer 12c is opposed to each metal layer 22c via a plurality of powders 32c.
  • the surfaces of the plurality of powders 32a to 32c are replaced with molten metal.
  • powders 33a to 33c containing molten metal are formed.
  • the powders 33a to 33b are heated to the melting point or higher to melt the powders 33a to 33c and form the metal layers 34a to 34c.
  • the metal layers 12a and 22a are joined by the metal layer 34a.
  • the metal layers 12b and 22b are joined by the metal layer 34b, and the metal layers 12c and 22c are joined by the metal layer 34c.
  • the metal layer bonded at the initial stage of the lamination undergoes many heating processes for bonding.
  • the metal layer 34a goes through three heating steps.
  • the joining metal changes in quality, becomes brittle, and is liable to crack.
  • the quality of the bonding varies depending on the metal layers 34a to 34c.
  • Example 2 as shown in FIG. 7A, the metal layers 12a and 22a, 12b and 22b, and 12c and 22c are fixed by the powders 32a to 32c.
  • the bases 20a to 20c are laminated before the metal layers 12a and 22a are heated, the bases 20a to 20c are fixed to each other. Therefore, after laminating the bases 20a to 20c, the metal layers 12a and 22a, 12b and 22b, and 12c and 22c are bonded together by heating the plurality of powders 33a to 33c as shown in FIG. 7B. Can be joined. Thereby, the dispersion
  • the base 10 may be a circuit board such as a silicon interposer or a resin substrate, and the bases 20a to 20c may be semiconductor chips, for example.
  • the number of stacked base bodies 20a to 20c can be set to 2, 4, or 8, for example.
  • the film thickness is, for example, 20 ⁇ m to 100 ⁇ m.
  • Example 3 is an example in which a part of the surface of the powder 32 is replaced with molten metal.
  • FIG. 8A to FIG. 8D are cross-sectional views illustrating a method for bonding substrates according to the third embodiment.
  • FIG. 9A and FIG. 9B are cross-sectional views of the powder of Example 3.
  • a protective film 28 is formed on the base 20 (lower surface).
  • the protective film 28 is a protective film of the base 20 and is an insulator containing a resin such as polyimide or epoxy.
  • Other steps are the same as those in FIG. 5B of the first embodiment, and a description thereof will be omitted.
  • the powder 32 is entirely a metal 35.
  • the metal 35 is, for example, Cu.
  • the powder 33 is formed by replacing the metal 35 on the surface of the powder 32 with a molten metal 36.
  • the surface of the powder 33 is a molten metal 36, and the metal 35 remains inside the powder 33.
  • the diameter of the metal 35 remaining inside is about 1 ⁇ 2 to 1 ⁇ 4 of the diameter of the powder 33.
  • Sn can remain in the powder 33 by performing substitutional electroless Sn plating at 60 ° C. for 15 minutes.
  • the molten metal 36 is melted by heating the plurality of powders 33.
  • the metal 35 is Cu
  • the molten metal 36 is Sn
  • the metal layers 12 and 22 are Cu
  • the powder 33 is heated at 300 ° C. for 3 seconds. Thereby, the metal layer 34 including the remaining metal 35 is formed.
  • the molten metal 36 and the metal 35 are heated and alloyed.
  • the metal 35 is Cu
  • the molten metal 36 is Sn
  • the metal layers 12 and 22 are Cu
  • the peak top temperature is 240 ° C. or higher using a reflow furnace
  • the temperature above the melting point of the molten metal 36 is 30 seconds or longer.
  • the molten metal 36 and the metal 35 react to form an alloy layer 45 of Cu and Sn. Since the alloy layer 45 is harder than the metal layer 34, the bonding strength can be made higher than that of the first embodiment.
  • Example 3 it is not necessary to replace the metal 35 on the surface of the plurality of powders 32 with the molten metal 36 and replace the metal 35 inside the powder 32 with the molten metal 36. Whether or not the metal 35 inside the powder 32 is replaced with the molten metal 36 can be controlled by, for example, the time of replacement plating.
  • the alloy layer 45 is formed by alloying the inside of the powder 33 that is not replaced with the molten metal 36 and the molten metal 36. Since the molten metal 36 is soft, it is easily deformed. By forming the alloy layer 45, the metal layers 12 and 22 can be firmly joined. The alloy layer 45 may not be formed. Further, the protective film 28 may or may not be provided.
  • Example 4 is an example in which the inside of the powder 32 is a refractory metal and the metal on the surface of the powder is replaced with a molten metal.
  • FIG. 10A to FIG. 10C are cross-sectional views illustrating the substrate bonding method according to the fourth embodiment.
  • FIG. 11A and FIG. 11B are cross-sectional views of the powder of Example 4.
  • a resin film 19 is formed on the substrate 10.
  • a resin film 29 is formed on the base 20 (lower surface).
  • the resin films 19 and 29 are insulators including a thermosetting resin such as epoxy.
  • a metal 35 is formed around a refractory metal 37 via a barrier layer 38.
  • Other steps are the same as those in FIG. 5B of the first embodiment, and a description thereof will be omitted.
  • the periphery of the refractory metal 37 is surrounded by a barrier layer 38, and the barrier layer 38 is surrounded by a metal 35.
  • the refractory metal 37 is, for example, Pd (palladium) having a diameter of 1 ⁇ m, and is formed using an atomizing method.
  • a barrier layer 38 is formed on the surface of the refractory metal 37 using, for example, an electroless plating method or a barrel plating method.
  • the barrier layer 38 is, for example, a Ni film having a thickness of 0.5 ⁇ m.
  • a metal 35 is formed on the surface of the barrier layer 38 using, for example, an electroless plating method or a barrel plating method.
  • the metal 35 is, for example, Cu having a thickness of 1 ⁇ m.
  • the powder 33 is formed by replacing the metal 35 with the molten metal 36. Since the barrier layer 38 is not replaced, the replacement plating stops without controlling the time. For example, when the metal 35 is Cu and the molten metal 36 is Sn, substitutional electroless Sn plating is performed at 60 ° C. for 15 minutes. Referring to FIG. 10C, the molten metal 36 of the powder 33 is melted to form the metal layer 34 including the refractory metal 37 and the barrier layer 38. For example, when the molten metal 36 is Sn, the powder 33 is heated at 300 ° C. for 3 seconds. Using a reflow furnace, the peak top temperature is set to 240 ° C. or higher, and heating is performed for 30 seconds or more. As a result, the thermosetting resin films 19 and 29 are cured in contact with each other.
  • the plurality of powders 32 mainly include a refractory metal 37 and a metal 35 formed on the surface of the refractory metal 37.
  • the refractory metal 37 reinforces the metal layer 34, the alloying as in the third embodiment may not be performed.
  • Example 5 is an example in which the inside of the powder 32 is an insulator, and the metal on the surface of the powder is replaced with molten metal.
  • FIG. 12A to FIG. 12C are cross-sectional views illustrating the substrate bonding method according to the fifth embodiment.
  • FIG. 13A and FIG. 13B are cross-sectional views of the powder of Example 5. Referring to FIG. 12A, in the powder 32, a metal 35 is formed around an insulator 39 through a barrier layer 38. Other steps are the same as those in FIG.
  • the insulator 39 is surrounded by a barrier layer 38, and the barrier layer 38 is surrounded by a metal 35.
  • the insulator 39 is, for example, a resin such as polyimide having a diameter of 1 ⁇ m, and is formed by using an atomizing method. The other processes are the same as those in FIG.
  • the powder 33 is formed by replacing the metal 35 with the molten metal 36.
  • Other steps are the same as those in FIG. 10B and FIG. 11B of the fourth embodiment, and the description thereof is omitted.
  • the metal layer 34 including the insulator 39 and the barrier layer 38 is formed by melting the molten metal 36 of the powder 33.
  • the other steps are the same as those in FIG.
  • the powder 32 includes the insulator 39 and the metal 35 formed on the surface of the insulator 39. Thereby, since the insulator 39 reinforces the metal layer 34, it is not necessary to perform alloying as in the third embodiment.
  • the resin films 19 and 29 may be used to seal between the substrates 10 and 20. Thereby, it is not necessary to use an underfill material.
  • the powder 32 in the porous body can be formed into particles (for example, spherical) mainly containing metal. Thereby, since the surface area of the powder 32 is increased, the metal 35 can be easily replaced with the molten metal 36.
  • Example 6 is an example in which the powder is fibrous.
  • FIG. 14A to FIG. 14C are cross-sectional views illustrating the substrate bonding method according to the sixth embodiment. Referring to FIG. 14 (a), the powder 32d is fibrous. Other steps are the same as those in FIG. 5B of the first embodiment, and a description thereof will be omitted.
  • fibrous powder 33d is formed by replacing fibrous powder 32d with molten metal.
  • the other steps are the same as those in FIG.
  • the metal layer 34 is formed by melting the powder 33d.
  • the other processes are the same as those in FIG.
  • the porous body may include a plurality of fibrous powders.
  • the powders of Examples 1 to 5 may be fibrous.
  • Example 7 is an example in which the substrate bonding method according to Example 3 is applied to a method for manufacturing a semiconductor device.
  • FIG. 15A to FIG. 18C are cross-sectional views illustrating the substrate bonding method according to the seventh embodiment.
  • the electronic circuit 50 is formed on the base 20.
  • the substrate 20 is a silicon substrate and is in a wafer state including a plurality of chips.
  • An insulating film 52 is formed on the substrate 20.
  • the electronic circuit 50 includes a transistor formed on the base 20 and a wiring formed in the insulating film 52.
  • the insulating film 52 is a silicon oxide film, for example, and includes an interlayer insulating film of multilayer wiring.
  • the electrode 24 is formed on the insulating film 52.
  • the electrode 24 contains Cu and is electrically connected to the electronic circuit 50.
  • the chip size is, for example, 8.5 mm ⁇ 8.5 mm.
  • the interval between the electrodes 24 is, for example, 50 ⁇ m, and 400 electrodes 24 are formed in
  • a protective film 28 containing polyimide and having a film thickness of, for example, 5 ⁇ m is formed on the insulating film 52.
  • an opening is formed in the protective film 28 on the electrode 24.
  • a metal layer 22 containing Cu and having a height of, for example, 15 ⁇ m is formed on the electrode 24.
  • the metal layer 22 is a bump (projection terminal) for connection.
  • a powder 56 mainly containing Cu is arranged on a substrate 54.
  • the powder 56 is formed using an atomizing method.
  • the average particle diameter of the powder 56 is, for example, 3 ⁇ m.
  • the surface of the metal layer 22 and the surface of the substrate 54 are brought into contact with each other.
  • the powder 56 is fixed to the surface of the metal layer 22 by applying ultrasonic waves.
  • the ultrasonic output is 100 kHz and the amplitude is 2 ⁇ m.
  • the base body 20 is peeled from the substrate 54.
  • a powder 32 mainly containing Cu is fixed on the metal layer 22.
  • a circuit board is prepared as the base 10.
  • the substrate 10 mainly contains BT (Bismaleimide-Triazine) resin and has a film thickness of, for example, 0.35 mm.
  • An electrode 14 is formed on the base 10.
  • the electrode 14 mainly includes Cu and is disposed so as to correspond to the electrode 24.
  • a metal layer 12 mainly containing Cu and having a height of, for example, 15 ⁇ m is formed.
  • the metal layer 12 is a bump.
  • An electrode 58 is formed on the back surface of the substrate 10.
  • the electrode 58 and the electrode 14 are electrically connected via a wiring formed in the base 10.
  • the base 20 is placed on the base 10 and aligned.
  • the metal layers 12 and 22 are brought into contact with each other through the powder 32.
  • the metal layers 12 and 22 are mechanically connected through the powder 32 using ultrasonic waves.
  • the surface of powder 32 is replaced with Sn using a substitutional electroless tin plating solution (for example, 580MJ manufactured by Ishihara Yakuhin) to form powder 33.
  • the plating process is performed at 60 ° C. for 15 minutes.
  • Cu of about 1 ⁇ m on the surface of the powder 32 is replaced with Sn, and Cu remains in the center of the powder 32.
  • the powder 33 is heated. As an example, heat is applied for 3 seconds from the substrate 20 side so that the temperature of the powder 33 becomes 300 ° C. Thereby, Sn in the powder 33 is melted. Further, using a reflow furnace, heating is performed so that the peak top temperature is 240 ° C. and the time above the melting point of Sn is 30 seconds or more. Thereby, Sn and Cu in the powder 33 are alloyed, and the alloy layer 45 is formed.
  • a substitutional electroless tin plating solution for example, 580MJ manufactured by Ishihara Yakuhin
  • an underfill material 60 is injected between the substrates 10 and 20.
  • the underfill material 60 mainly includes a thermosetting epoxy resin.
  • the underfill material 60 is cured by heating at 150 ° C. for 2 hours using a thermostatic bath.
  • solder balls 62 are formed on the electrodes 58.
  • the solder ball 62 mainly contains Sn—Ag (tin silver).
  • Example 7 the example in which the plurality of powders 32 are fixed to the surface of the metal layer 22 has been described.
  • the plurality of powders 32 may be fixed to at least one surface of the metal layers 12 and 22.
  • the substrate bonding method according to the third embodiment is used, the substrate bonding method according to the first to sixth embodiments may be used.
  • bumps have been described as examples of the metal layers 12 and 22, but one may be a bump and the other may be a pad.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Powder Metallurgy (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé de jonction de substrat comprenant ce qui suit : une étape destinée à former des couches métalliques (12, 22) sur une pluralité de substrats (10, 20), respectivement, pour se faire mutuellement face, un corps poreux (32) comprenant un premier métal (35) intercalé entre eux ; une étape destiné à remplacer le premier métal qui se trouve sur la surface du corps poreux par un second métal (36) ; et une étape destiné à joindre les couches métalliques par le chauffage du second métal.
PCT/JP2013/082267 2013-11-29 2013-11-29 Procédé de jonction de substrat Ceased WO2015079582A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3533083A4 (fr) * 2016-10-27 2020-07-01 Invensas Corporation Structures et procédés de liaison à basse température
WO2024219418A1 (fr) * 2023-04-17 2024-10-24 三菱マテリアル株式会社 CORPS ASSEMBLÉ DE PILIER DE Cu ET PROCÉDÉ DE FABRICATION DE CORPS ASSEMBLÉ DE PILIER DE Cu

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Publication number Priority date Publication date Assignee Title
JPH0536306A (ja) * 1991-07-26 1993-02-12 Sekisui Fine Chem Kk 導電性微粒子、電極接続構造体及びその製造方法
JP2008172215A (ja) * 2005-03-29 2008-07-24 Matsushita Electric Ind Co Ltd フリップチップ実装体及びその実装装置並びにバンプ形成装置
WO2013069798A1 (fr) * 2011-11-11 2013-05-16 住友ベークライト株式会社 Procédé de fabrication pour dispositif semi-conducteur

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CN101483144B (zh) * 2002-12-27 2013-08-28 富士通株式会社 半导体器件及其制法、基板处理装置和半导体制造装置

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH0536306A (ja) * 1991-07-26 1993-02-12 Sekisui Fine Chem Kk 導電性微粒子、電極接続構造体及びその製造方法
JP2008172215A (ja) * 2005-03-29 2008-07-24 Matsushita Electric Ind Co Ltd フリップチップ実装体及びその実装装置並びにバンプ形成装置
WO2013069798A1 (fr) * 2011-11-11 2013-05-16 住友ベークライト株式会社 Procédé de fabrication pour dispositif semi-conducteur

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3533083A4 (fr) * 2016-10-27 2020-07-01 Invensas Corporation Structures et procédés de liaison à basse température
EP4435152A3 (fr) * 2016-10-27 2024-12-18 Adeia Semiconductor Technologies LLC Structures et procédés de liaison à basse température
WO2024219418A1 (fr) * 2023-04-17 2024-10-24 三菱マテリアル株式会社 CORPS ASSEMBLÉ DE PILIER DE Cu ET PROCÉDÉ DE FABRICATION DE CORPS ASSEMBLÉ DE PILIER DE Cu

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