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WO2015050350A1 - Method for preparing transition substrate, transition substrate prepared thereby, and method for preparing semiconductor device by using same - Google Patents

Method for preparing transition substrate, transition substrate prepared thereby, and method for preparing semiconductor device by using same Download PDF

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Publication number
WO2015050350A1
WO2015050350A1 PCT/KR2014/009152 KR2014009152W WO2015050350A1 WO 2015050350 A1 WO2015050350 A1 WO 2015050350A1 KR 2014009152 W KR2014009152 W KR 2014009152W WO 2015050350 A1 WO2015050350 A1 WO 2015050350A1
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Prior art keywords
substrate
crystalline
thick film
pattern
transition substrate
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French (fr)
Korean (ko)
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정진욱
서중원
김경준
어성우
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Corning Precision Materials Co Ltd
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Corning Precision Materials Co Ltd
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/04—After-treatment of single crystals or homogeneous polycrystalline material with defined structure using electric or magnetic fields or particle radiation
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates to a method for manufacturing a transition substrate, a transition substrate manufactured by the same, and a method for manufacturing a semiconductor device using the same, more particularly, a method for manufacturing a transition substrate using a layer transfer process, a transition substrate manufactured by the same, and using the same It relates to a semiconductor device manufacturing method.
  • nitride semiconductors such as aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN), which are used as materials for advanced devices such as light emitting diodes (LEDs) and laser diodes (LDs).
  • AlN aluminum nitride
  • GaN gallium nitride
  • InN indium nitride
  • LEDs light emitting diodes
  • LDs laser diodes
  • Gallium Nitride is a direct transition semiconductor material with a very high bandgap energy of 3.39 eV. It is a blue LD for the next generation of DVD light sources, a white LED to replace the lighting market, high temperature and It is the next generation optoelectronic material used as a core material in high power electronic device field.
  • hydride substrates such as sapphire, SiC, Si, diamond, GaAs, etc.
  • HVPE hydride vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • MBE metal organic chemical vapor deposition
  • MOCVD method metal organic chemical vapor deposition
  • It is grown by methods such as (Molecular Beam Epitaxy) method, Ammonothermal method, Na Flux method.
  • the MOCVD method can obtain a high quality gallium nitride film, but has a disadvantage in that the growth rate is too slow to be suitable for use in producing tens or hundreds of micrometers gallium nitride films. Accordingly, the HVPE method that can rapidly grow a relatively thick gallium nitride film of several tens to hundreds of micrometers on a substrate using ammonia, hydrogen, and various chloride gases is most commonly used.
  • gallium nitride thin film when a gallium nitride thin film is directly grown on a dissimilar substrate, gallium nitride grown on the dissimilar substrate due to lattice mismatch and thermal expansion coefficient mismatch between the dissimilar substrate and the gallium nitride thin film The problem of high defect density of the thin film occurs.
  • a gallium nitride substrate is manufactured through the following process.
  • a gallium nitride thick film is grown on a dissimilar substrate to reduce the defect density of the gallium nitride thick film grown on the dissimilar substrate, and then a laser is irradiated to the interface between the dissimilar substrate and the gallium nitride thick film.
  • the gallium nitride thick film is manufactured through a laser lift-off process of separating the gallium nitride thick film from the film.
  • a gallium nitride substrate is manufactured through a layer transfer process as shown in FIG. 1. That is, a gallium nitride thick film is implanted with an ion implanter to form an ion implantation layer.
  • the gallium nitride thick film on which the ion implantation layer is formed is pressurized onto a dissimilar substrate to be bonded, and then heat is applied.
  • a gallium nitride substrate having a gallium nitride thin film formed on a heterogeneous substrate separated therefrom is manufactured.
  • an object of the present invention is to provide a method for manufacturing a transition substrate having a good bonding quality and a large available area, a transition substrate manufactured by the same, and a semiconductor device using the same It is to provide a manufacturing method.
  • the present invention is a crystalline thick film preparation step of preparing a crystalline thick film; A pattern forming step of forming an uneven pattern on one surface of the crystalline thick film; An ion implantation step of forming an ion implantation layer on the convex portion of the pattern by implanting ions into one surface of the crystalline thick film; Bonding the one surface of the crystalline thick film to one surface of the dissimilar substrate; And a separation step of separating the crystalline thick film based on the ion implantation layer formed in the convex portion of the pattern.
  • the recess width of the pattern may be 10 to 100 ⁇ m.
  • the pattern may be a grid pattern.
  • the crystalline thick film may be made of GaN, and the hetero substrate may be made of any one of Si, Sapphire, Diamond, and SiC.
  • the ion implanted in the ion implantation step may include at least one of hydrogen, helium, nitrogen, oxygen, and argon.
  • the present invention is heterogeneous substrate; And a crystalline thin film formed on the hetero substrate, wherein the crystalline thin films are formed to expose the hetero substrate in a predetermined pattern.
  • the crystalline thin film is made of GaN
  • the hetero substrate may be made of any one of Si, Sapphire, Diamond and SiC.
  • the present invention provides a transition substrate preparation step of preparing a transition substrate prepared by the above-described method for manufacturing a transition substrate; An element forming step of forming an element on the crystalline thin films of the transition substrate; And a cutting step of cutting the transition substrate on which the device is formed along the crystalline thin films.
  • the semiconductor device manufacturing method may further include a planarization step of flattening the surface by filling a dielectric between grooves between the crystalline thin films of the transition substrate after the transition substrate preparation step and before the device formation step.
  • the dielectric may be made of any one of SiO 2 or SiN.
  • the present invention it is possible to improve the warpage of the crystalline thick film by ion implantation, thereby improving the bonding quality and bonding rate of the dissimilar substrate and the crystalline bulk, thereby improving the quality of the crystalline thin film finally transferred onto the dissimilar substrate.
  • cracks generated in some crystalline thin films may not propagate to other crystalline thin films, thereby improving the usable area of the transition substrate.
  • FIG. 1 is a schematic conceptual diagram of a method of manufacturing a gallium nitride substrate through a conventional layer transfer process.
  • FIG. 2 is a photograph showing that cracks generated in a gallium nitride substrate manufactured by a conventional method propagate throughout the gallium nitride substrate.
  • Figure 3 is a schematic conceptual diagram of a method for manufacturing a transition substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic conceptual view of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic conceptual diagram of a method of manufacturing a transition substrate according to an embodiment of the present invention.
  • the method for manufacturing a transition substrate according to an embodiment of the present invention is a crystalline thick film preparation step (Fig. 3 (a)), a pattern forming step (Fig. 3 (b)), the ion implantation step ( 3 (c)), the bonding step (FIG. 3 (D)), and may comprise a separation step (FIG. 3 (e)).
  • a crystalline thick film 1 is prepared (FIG. 3A).
  • the crystalline thick film 1 may be prepared by thickly growing a crystalline semiconductor material on a substrate using various growth methods such as HVPE method and MOCVD method, and then separating the substrate and the crystalline thick film.
  • the crystalline thick film 1 is preferably made of GaN, but is not necessarily limited thereto, and may be made of various compound semiconductor materials such as AlN and InN.
  • a substrate used for growing the crystalline thick film 1 may be a homogeneous substrate or a hetero substrate made of Si, Sapphire, SiC, Diamond, or the like. And, the separation of the crystalline thick film and the substrate used for growth can be achieved through the technique of laser lift-off.
  • the convex portion of the pattern may be used as a die in which a semiconductor element is formed later, and the recess may be used as a street for removing each element formed on a substrate for packaging of the semiconductor element.
  • the recess width of the pattern will be 10-100 ⁇ m.
  • the recessed part depth of the pattern may be 1 to 100 ⁇ m.
  • the pattern may be a lattice pattern, but is not limited thereto and may have various forms.
  • the pattern of the unevenness may be formed by various methods such as dry etching.
  • ions are implanted into one surface of the crystalline thick film 1 to form an ion implantation layer 2 in the convex portion of the pattern (FIG. 3C).
  • the ion implantation layer 2 is formed at a predetermined depth from the surface of the convex portion by implanting ions into one surface of the crystalline thick film 1 on which the uneven pattern to be bonded to the dissimilar substrate 3 is formed.
  • the ion implantation layer 2 may be formed at a depth of about 0.4 to 0.6 ⁇ m from the surface of the convex portion.
  • Implantation of ions may be performed through an ion implanter, and the implanted ions may include at least one of hydrogen, helium, nitrogen, oxygen, and argon.
  • the ion implantation layer is formed at a predetermined depth from the surface of the recess, but this portion is a portion to be removed later in the device manufacturing process, and the ion implantation layer formed at a predetermined depth from the surface of the recess is continuously formed at both ends of the crystalline thick film. Since it is not possible to separate the crystalline thick film by the separation step described below, it does not affect the practice of the present invention.
  • one surface of the crystalline thick film 1 is bonded to one surface of the hetero substrate 3 (FIG. 3 (d)).
  • the bonding of one surface of the crystalline thick film 1 and the heterogeneous substrate 3 may be performed by applying heat and pressure or applying heat or pressure to the crystalline thick film 1 and the heterogeneous substrate 3.
  • the heterogeneous substrate 3 may be made of any one of Si, Sapphire, Diamond, and SiC, but is not necessarily limited thereto, and may be made of various materials such as glass, GaAs, Ge, AlN, poly-AlN, or ZnO.
  • the surface of the convex portion of the pattern before the bonding step may be activated by plasma treatment, and then one surface of the crystalline thick film 1 may be bonded to one surface of the dissimilar substrate 3.
  • Separation step may be made through a heat treatment method. That is, when the crystalline thick film 1 bonded to the dissimilar substrate 3 is heat-treated, the ion implantation layer 2 formed in the crystalline thick film 1 turns into a gas layer and expands, whereby the crystalline thick film 1 is ion implanted. Separated on the basis of layer (2). At this time, the heat treatment temperature may be adjusted to 200 ⁇ 800 °C according to the characteristics of the implanted ions.
  • Separation step (e) of FIG. 3 may be performed in air or nitrogen (N 2 ) atmosphere.
  • the warpage of the crystalline thick film by ion implantation can be improved to improve the bonding quality and the bonding rate. That is, in the case of the present invention, the ion implantation layer formed on the crystalline thick film is dispersed and distributed by the uneven pattern, thereby reducing the warpage of the crystalline thick film due to ion implantation, and thus the bonding quality and bonding of the dissimilar substrate and the crystalline bulk. The rate is improved.
  • FIG. 4 is a schematic conceptual diagram of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
  • the semiconductor device manufacturing method is a transition substrate preparation step (Fig. 4 (a)), a device forming step (Fig. 4 (b)), and a cutting step ( It may be made including (c)) of FIG.
  • the substrate 3 is formed on the dissimilar substrate 3 and the dissimilar substrate 3 through the process described in the method for manufacturing the transition substrate, and the dissimilar substrate 3 is formed in a predetermined pattern.
  • a transition substrate including the crystalline thin films 4 formed to be exposed is prepared.
  • the element 6 is formed on the crystalline thin films 4 of the transition substrate (FIG. 4B).
  • the epitaxial growth process and the fab process according to the semiconductor device to be manufactured are performed.
  • the semiconductor device to be manufactured such as LED, LD, SBD, HEMT, etc.
  • the semiconductor device can be manufactured by cutting the transition substrate on which the device is formed to separate into individual devices ((c) of FIG. 4). That is, individual semiconductor devices can be manufactured by cutting the transition substrate on which the elements 6 are formed along the crystalline thin films 4 through a die-sawing process.
  • the semiconductor device manufacturing method after the transition substrate preparation step (Fig. 4 (a)) to produce a high-quality semiconductor device by planarizing the surface to form the device, the device formation step (Fig. Before (b) of FIG. 4, a planarization step may be further included to fill the grooves between the crystalline thin films 4 of the transition substrate to planarize the surface (FIG. 4A ′).
  • the dielectric 5 may be made of one of SiO 2 or SiN.

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Abstract

The present invention relates to a method for preparing a transition substrate, a transition substrate prepared thereby, and a method for preparing a semiconductor device by using the same, and more specifically, to a method for preparing a transition substrate by using a layer transfer process, a transition substrate prepared thereby, and a method for preparing a semiconductor device by using the same. To this end, the present invention provides a method for preparing a transition substrate, comprising: a crystalline thick film preparation step for preparing a crystalline thick film; a pattern formation step for forming a pattern of a protrusion shape on one side of the crystalline thick film; an ion injection step for forming an ion injection layer on an convex part of the pattern by injecting ions on one side of the crystalline thick film; a bonding step for bonding one side of the crystalline thick film to one side of a heterogeneous substrate; and a separation step for separating the crystalline thick film on the basis of the ion injection layer formed on the convex part of the pattern.

Description

전이 기판 제조방법, 이에 의해 제조된 전이 기판, 및 이를 이용한 반도체 소자 제조방법A method of manufacturing a transition substrate, a transition substrate manufactured thereby, and a method of manufacturing a semiconductor device using the same

본 발명은 전이 기판 제조방법, 이에 의해 제조된 전이 기판, 및 이를 이용한 반도체 소자 제조방법에 관한 것으로서, 더욱 상세하게는 레이어 트랜스퍼 공정을 이용한 전이 기판 제조방법, 이에 의해 제조된 전이 기판, 및 이를 이용한 반도체 소자 제조방법 에 관한 것이다.The present invention relates to a method for manufacturing a transition substrate, a transition substrate manufactured by the same, and a method for manufacturing a semiconductor device using the same, more particularly, a method for manufacturing a transition substrate using a layer transfer process, a transition substrate manufactured by the same, and using the same It relates to a semiconductor device manufacturing method.

최근 들어, 발광다이오드(LED), 레이저 다이오드(LD: Laser Diode) 등과 같은 첨단 소자의 재료로 사용되는 질화 알루미늄(AlN), 질화갈륨(GaN), 질화 인듐(InN)과 같은 질화물 반도체에 관한 활발한 연구가 진행되고 있다.In recent years, there has been an active interest in nitride semiconductors such as aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN), which are used as materials for advanced devices such as light emitting diodes (LEDs) and laser diodes (LDs). Research is ongoing.

특히, 질화갈륨(GaN: Gallium Nitride)은 3.39eV의 매우 큰 밴드갭 에너지(bandgap energy)를 갖는 직접 천이형 반도체 물질로서, 차세대 DVD광원으로 쓰이는 청색 LD, 조명용 시장 대체를 위한 백색 LED, 고온·고출력 전자소자 분야 등에서 핵심소재로 사용되는 차세대 광전자 재료이다.In particular, Gallium Nitride (GaN) is a direct transition semiconductor material with a very high bandgap energy of 3.39 eV. It is a blue LD for the next generation of DVD light sources, a white LED to replace the lighting market, high temperature and It is the next generation optoelectronic material used as a core material in high power electronic device field.

이와 같은 질화물 반도체는 실용적인 동종의 기판이 없기 때문에 사파이어(sapphire), SiC, Si, Diamond, GaAs 등과 같은 결정질 이종기판에 HVPE(Hydride Vapor Phase Epitaxy)법, MOCVD(Metal Organic Chemical Vapor Deposition)법, MBE(Molecular Beam Epitaxy)법, Ammonothermal법, Na Flux법 등의 방법에 의해 성장되게 된다. MOCVD법은 고품질의 질화갈륨 막을 얻을 수 있으나, 성장 속도가 너무 느려 수십 또는 수백 ㎛의 질화갈륨 막 제조에 사용하기에는 부적당하다는 단점이 있다. 이에, 암모니아, 수소, 및 각종 염화물 가스를 이용하여 기판 상에 수십 ~ 수백 마이크로미터의 비교적 두꺼운 질화갈륨 막을 빠르게 성장시킬 수 있는 HVPE법이 가장 많이 사용되고 있다.Since nitride semiconductors do not have practical homogeneous substrates, hydride substrates such as sapphire, SiC, Si, diamond, GaAs, etc., are used in the hydride vapor phase epitaxy (HVPE) method, metal organic chemical vapor deposition (MOCVD) method, and MBE. It is grown by methods such as (Molecular Beam Epitaxy) method, Ammonothermal method, Na Flux method. The MOCVD method can obtain a high quality gallium nitride film, but has a disadvantage in that the growth rate is too slow to be suitable for use in producing tens or hundreds of micrometers gallium nitride films. Accordingly, the HVPE method that can rapidly grow a relatively thick gallium nitride film of several tens to hundreds of micrometers on a substrate using ammonia, hydrogen, and various chloride gases is most commonly used.

한편, 이종기판 상에 질화갈륨 박막을 직접 성장시켜 제조하는 경우, 이종기판과 질화갈륨 박막 간의 격자불일치(lattice mismatch)와 열팽창계수 불일치(thermal expansion coefficient mismatch)로 인해 이종기판 상에 성장된 질화갈륨 박막의 결함밀도가 높은 문제가 발생한다.Meanwhile, when a gallium nitride thin film is directly grown on a dissimilar substrate, gallium nitride grown on the dissimilar substrate due to lattice mismatch and thermal expansion coefficient mismatch between the dissimilar substrate and the gallium nitride thin film The problem of high defect density of the thin film occurs.

이에 이와 같은 문제를 해결하고자 종래에는 하기와 같은 공정을 통해 질화갈륨 기판을 제조하고 있다.In order to solve this problem, conventionally, a gallium nitride substrate is manufactured through the following process.

이를 좀더 구체적으로 설명해보면, 우선 이종기판 상에 질화갈륨 후막을 성장시켜 이종기판 상에 성장된 질화갈륨 후막의 결함밀도를 감소시킨 후, 레이저를 이종기판과 질화갈륨 후막의 계면에 조사하여 이종기판으로부터 질화갈륨 후막을 분리하는 레이저 리프트-오프(laser lift-off) 공정을 통해 질화갈륨 후막을 제조한다. 이후, 도 1에 도시된 바와 같은 레이어 트랜스퍼(layer transfer) 공정을 통해 질화갈륨 기판을 제조한다. 즉, 질화갈륨 후막에 이온 주입기를 통해 이온을 주입하여 이온 주입층을 형성하고, 이온 주입층이 형성된 질화갈륨 후막을 이종기판 상에 가압하여 접합시킨 후 열을 가하면, 질화갈륨 후막이 이온 주입층을 기준으로 분리되어 이종기판 상에 질화갈륨 박막이 형성된 질화갈륨 기판이 제조된다.In more detail, first, a gallium nitride thick film is grown on a dissimilar substrate to reduce the defect density of the gallium nitride thick film grown on the dissimilar substrate, and then a laser is irradiated to the interface between the dissimilar substrate and the gallium nitride thick film. The gallium nitride thick film is manufactured through a laser lift-off process of separating the gallium nitride thick film from the film. Thereafter, a gallium nitride substrate is manufactured through a layer transfer process as shown in FIG. 1. That is, a gallium nitride thick film is implanted with an ion implanter to form an ion implantation layer. The gallium nitride thick film on which the ion implantation layer is formed is pressurized onto a dissimilar substrate to be bonded, and then heat is applied. A gallium nitride substrate having a gallium nitride thin film formed on a heterogeneous substrate separated therefrom is manufactured.

그러나, 이와 같은 종래 방법에 의하여 질화갈륨 기판을 제조하는 경우, 질화갈륨 후막에의 이온 주입 시 질화갈륨 후막의 휨이 급격히 증가하게 되어 이종기판과의 접합과 박막 분리 공정의 진행이 어렵고, 접합율이 낮아지는 문제가 발생한다. 또한, 도 2에 도시된 바와 같이 이종기판과 접합된 질화갈륨 박막의 일 부분에 발생한 크랙(crack)이 질화갈륨 박막 전체로 전파(propagation)되거나, 질화갈륨 후막이 파손되어 더 이상 반복적으로 레이어 트래스퍼 공정을 진행할 수 없게 된다는 문제가 발생할 수 있다.However, when manufacturing a gallium nitride substrate by such a conventional method, the warpage of the gallium nitride thick film rapidly increases during ion implantation into the gallium nitride thick film, it is difficult to proceed with the bonding process and thin film separation process with the hetero substrate, This lowering problem occurs. In addition, as shown in FIG. 2, cracks generated in a part of the gallium nitride thin film bonded to the dissimilar substrate are propagated through the entire gallium nitride thin film, or the gallium nitride thick film is broken, and thus the layer trace is no longer repeatedly repeated. The problem may arise that the spur process cannot proceed.

(선행기술문헌) (Prior art document)

대한민국 공개특허 제10-2013-0059677호(2013.06.07)Republic of Korea Patent Publication No. 10-2013-0059677 (2013.06.07)

본 발명은 상술한 바와 같은 종래기술의 문제점을 해결하기 위해 안출된 것으로서, 본 발명의 목적은 접합 품질이 우수하고 가용면적이 넓은 전이 기판 제조방법, 이에 의해 제조된 전이 기판, 및 이를 이용한 반도체 소자 제조방법을 제공하는 것이다.The present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to provide a method for manufacturing a transition substrate having a good bonding quality and a large available area, a transition substrate manufactured by the same, and a semiconductor device using the same It is to provide a manufacturing method.

이를 위해, 본 발명은 결정질 후막을 준비하는 결정질 후막 준비단계; 상기 결정질 후막의 일면에 요철 형상의 패턴을 형성하는 패턴 형성단계; 상기 결정질 후막의 일면에 이온을 주입하여 상기 패턴의 철부에 이온 주입층을 형성하는 이온 주입단계; 상기 결정질 후막의 일면을 이종기판의 일면에 접합하는 접합단계; 및 상기 결정질 후막을 상기 패턴의 철부에 형성된 이온 주입층을 기준으로 분리하는 분리단계를 포함하는 것을 특징으로 하는 전이 기판 제조방법을 제공한다.To this end, the present invention is a crystalline thick film preparation step of preparing a crystalline thick film; A pattern forming step of forming an uneven pattern on one surface of the crystalline thick film; An ion implantation step of forming an ion implantation layer on the convex portion of the pattern by implanting ions into one surface of the crystalline thick film; Bonding the one surface of the crystalline thick film to one surface of the dissimilar substrate; And a separation step of separating the crystalline thick film based on the ion implantation layer formed in the convex portion of the pattern.

바람직하게, 상기 패턴의 요부 폭은 10 ~ 100㎛일 수 있다.Preferably, the recess width of the pattern may be 10 to 100㎛.

또한, 상기 패턴은 격자 패턴일 수 있다.In addition, the pattern may be a grid pattern.

그리고, 상기 결정질 후막은 GaN으로 이루어지고, 상기 이종기판은 Si, Sapphire, Diamond 및 SiC 중 어느 하나로 이루어질 수 있다.The crystalline thick film may be made of GaN, and the hetero substrate may be made of any one of Si, Sapphire, Diamond, and SiC.

또한, 상기 이온 주입단계에서 주입되는 이온은 수소, 헬륨, 질소, 산소, 및 아르곤 중 적어도 어느 하나를 포함할 수 있다.In addition, the ion implanted in the ion implantation step may include at least one of hydrogen, helium, nitrogen, oxygen, and argon.

또한, 본 발명은 이종기판; 및 상기 이종기판 상에 형성되되, 상기 이종기판이 소정 패턴으로 노출되도록 형성된 결정질 박막들을 포함하는 것을 특징으로 하는 전이 기판을 제공한다.In addition, the present invention is heterogeneous substrate; And a crystalline thin film formed on the hetero substrate, wherein the crystalline thin films are formed to expose the hetero substrate in a predetermined pattern.

상기 결정질 박막은 GaN으로 이루어지고, 상기 이종기판은 Si, Sapphire, Diamond 및 SiC 중 어느 하나로 이루어질 수 있다.The crystalline thin film is made of GaN, the hetero substrate may be made of any one of Si, Sapphire, Diamond and SiC.

또한, 본 발명은 상술한 전이 기판 제조방법에 의해 제조된 전이 기판을 준비하는 전이 기판 준비단계; 상기 전이 기판의 결정질 박막들 상에 소자를 형성하는 소자 형성단계; 및 상기 소자가 형성된 전이 기판을 상기 결정질 박막들을 따라 절단하는 절단단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법을 제공한다.In addition, the present invention provides a transition substrate preparation step of preparing a transition substrate prepared by the above-described method for manufacturing a transition substrate; An element forming step of forming an element on the crystalline thin films of the transition substrate; And a cutting step of cutting the transition substrate on which the device is formed along the crystalline thin films.

또한, 상기 반도체 소자 제조방법은 상기 전이 기판 준비단계 후, 소자 형성단계 전, 상기 전이 기판의 결정질 박막들 사이의 홈에 유전체를 충진하여 표면을 평탄화하는 평탄화 단계를 더 포함할 수 있다.In addition, the semiconductor device manufacturing method may further include a planarization step of flattening the surface by filling a dielectric between grooves between the crystalline thin films of the transition substrate after the transition substrate preparation step and before the device formation step.

여기서, 상기 유전체는 SiO2 또는 SiN 중 어느 하나로 이루어질 수 있다.Here, the dielectric may be made of any one of SiO 2 or SiN.

본 발명에 따르면, 이온 주입에 의한 결정질 후막의 휨을 개선하여 이종기판과 결정질 벌크의 접합 품질 및 접합률이 향상시켜 종국적으로 이종기판 상으로 전이된 결정질 박막의 품질을 향상시킬 수 있다.According to the present invention, it is possible to improve the warpage of the crystalline thick film by ion implantation, thereby improving the bonding quality and bonding rate of the dissimilar substrate and the crystalline bulk, thereby improving the quality of the crystalline thin film finally transferred onto the dissimilar substrate.

또한, 일부 결정질 박막에 발생한 크랙이 다른 결정질 박막으로 전파되지 못하게 되어 전이 기판의 가용면적을 향상시킬 수 있다.In addition, cracks generated in some crystalline thin films may not propagate to other crystalline thin films, thereby improving the usable area of the transition substrate.

도 1은 종래 레이어 트랜스퍼 공정을 통한 질화갈륨 기판 제조방법의 개략적인 개념도.1 is a schematic conceptual diagram of a method of manufacturing a gallium nitride substrate through a conventional layer transfer process.

도 2는 종래 방법에 의해 제조된 질화갈륨 기판에 발생한 크랙이 질화갈륨 기판 전체로 전파된 것을 촬영한 사진.FIG. 2 is a photograph showing that cracks generated in a gallium nitride substrate manufactured by a conventional method propagate throughout the gallium nitride substrate. FIG.

도 3은 본 발명의 일 실시예에 따른 전이 기판 제조방법의 개략적인 개념도.Figure 3 is a schematic conceptual diagram of a method for manufacturing a transition substrate according to an embodiment of the present invention.

도 4는 본 발명의 일 실시예에 따른 반도체 소자 제조방법의 개략적인 개념도.4 is a schematic conceptual view of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

이하에서는 첨부된 도면들을 참조하여 본 발명의 실시 예에 따른 전이 기판 제조방법, 이에 의해 제조된 전이 기판, 및 이를 이용한 반도체 소자 제조방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a transition substrate, a transition substrate manufactured by the same, and a method of manufacturing a semiconductor device using the same will be described in detail with reference to the accompanying drawings.

아울러, 본 발명을 설명함에 있어서, 관련된 공지 기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단된 경우 그 상세한 설명은 생략한다.In addition, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.


도 3은 본 발명의 일 실시예에 따른 전이 기판 제조방법의 개략적인 개념도이다.3 is a schematic conceptual diagram of a method of manufacturing a transition substrate according to an embodiment of the present invention.

도 3에 도시된 바와 같이, 본 발명의 일 실시예에 따른 전이 기판 제조방법은 결정질 후막 준비단계(도 3의 (a)), 패턴 형성단계(도 3의 (b)), 이온 주입단계(도 3의 (c)), 접합단계(도 3의 (d)), 및 분리단계(도 3의 (e))를 포함하여 이루어질 수 있다.As shown in Figure 3, the method for manufacturing a transition substrate according to an embodiment of the present invention is a crystalline thick film preparation step (Fig. 3 (a)), a pattern forming step (Fig. 3 (b)), the ion implantation step ( 3 (c)), the bonding step (FIG. 3 (D)), and may comprise a separation step (FIG. 3 (e)).

본 발명의 일 실시예에 따라 전이 기판을 제조하기 위해, 우선 결정질 후막(1)을 준비한다(도 3의 (a)). In order to manufacture a transition substrate according to an embodiment of the present invention, first, a crystalline thick film 1 is prepared (FIG. 3A).

결정질 후막(1)은 HVPE법, MOCVD법 등의 다양한 성장법을 이용하여 기판 상에 결정질 반도체 물질을 두껍게 성장시킨 후, 기판과 결정질 후막을 분리함으로써 준비될 수 있다. 여기서, 결정질 후막(1)은 GaN으로 이루어지는 것이 바람직할 것이나, 반드시 이에 국한될 것은 아니며, AlN, InN 등 다양한 화합물 반도체 물질로 이루어질 수 있다. 또한, 결정질 후막(1) 성장에 사용되는 기판은 동종기판 또는 Si, Sapphire, SiC, Diamond 등으로 이루어진 이종기판이 사용될 수 있다. 그리고, 성장에 사용된 기판과 결정질 후막의 분리는 레이저 리프트-오프의 기술을 통해 이루어질 수 있다.The crystalline thick film 1 may be prepared by thickly growing a crystalline semiconductor material on a substrate using various growth methods such as HVPE method and MOCVD method, and then separating the substrate and the crystalline thick film. Here, the crystalline thick film 1 is preferably made of GaN, but is not necessarily limited thereto, and may be made of various compound semiconductor materials such as AlN and InN. In addition, a substrate used for growing the crystalline thick film 1 may be a homogeneous substrate or a hetero substrate made of Si, Sapphire, SiC, Diamond, or the like. And, the separation of the crystalline thick film and the substrate used for growth can be achieved through the technique of laser lift-off.

이후, 결정질 후막(1)의 일면에 요철 형상의 패턴을 형성한다(도 3의 (b)).Thereafter, an uneven pattern is formed on one surface of the crystalline thick film 1 (FIG. 3B).

패턴의 철부는 추후 반도체 소자가 형성되는 부분(die)으로 사용되고, 요부는 반도체 소자의 패키징(packaging)을 위해 기판에 형성된 각각의 소자를 떼어내기 위한 스트리트 부분(street)으로 사용될 수 있다.The convex portion of the pattern may be used as a die in which a semiconductor element is formed later, and the recess may be used as a street for removing each element formed on a substrate for packaging of the semiconductor element.

바람직하게, 패턴의 요부 폭은 10 ~ 100㎛일 것이다. 또한, 패턴의 요부 깊이는 1 ~ 100㎛일 수 있다.Preferably, the recess width of the pattern will be 10-100 μm. In addition, the recessed part depth of the pattern may be 1 to 100 μm.

그리고, 패턴은 격자 패턴일 수 있으나, 반드시 이에 국한될 것은 아니며 다양한 형태를 가질 수 있다.The pattern may be a lattice pattern, but is not limited thereto and may have various forms.

요철 형성의 패턴은 건식 식각(dry etching) 등 다양한 방법에 의해 이루어질 수 있다.The pattern of the unevenness may be formed by various methods such as dry etching.

다음으로, 결정질 후막(1)의 일면에 이온을 주입하여 패턴의 철부에 이온 주입층(2)을 형성한다(도 3의 (c)).Next, ions are implanted into one surface of the crystalline thick film 1 to form an ion implantation layer 2 in the convex portion of the pattern (FIG. 3C).

즉, 이종기판(3)과 접합될 요철 형상의 패턴이 형성된 결정질 후막(1)의 일면에 이온을 주입하여 철부의 표면으로부터 소정 깊이에 이온 주입층(2)을 형성한다. 이때, 이온 주입층(2)은 철부의 표면으로부터 약 0.4 ~ 0.6㎛ 깊이에 형성될 수 있다. That is, the ion implantation layer 2 is formed at a predetermined depth from the surface of the convex portion by implanting ions into one surface of the crystalline thick film 1 on which the uneven pattern to be bonded to the dissimilar substrate 3 is formed. In this case, the ion implantation layer 2 may be formed at a depth of about 0.4 to 0.6 μm from the surface of the convex portion.

이온의 주입은 이온 주입기를 통해 이루어질 수 있으며, 주입되는 이온은 수소, 헬륨, 질소, 산소, 및 아르곤 중 적어도 어느 하나를 포함할 수 있다.Implantation of ions may be performed through an ion implanter, and the implanted ions may include at least one of hydrogen, helium, nitrogen, oxygen, and argon.

한편, 이온 주입층은 요부의 표면으로부터 일정 깊이에도 형성되나 이 부분은 추후 소자 제조 공정에서 제거될 부분이고, 또한 요부의 표면으로부터 일정 깊이에 형성된 이온 주입층은 결정질 후막의 양측단으로 연속적으로 형성되지 않아 후술한 분리단계에 의해 결정질 후막을 분리시키지도 못하므로, 본 발명의 실시에 영향을 미치지 않는다.On the other hand, the ion implantation layer is formed at a predetermined depth from the surface of the recess, but this portion is a portion to be removed later in the device manufacturing process, and the ion implantation layer formed at a predetermined depth from the surface of the recess is continuously formed at both ends of the crystalline thick film. Since it is not possible to separate the crystalline thick film by the separation step described below, it does not affect the practice of the present invention.

다음으로, 결정질 후막(1)의 일면을 이종기판(3)의 일면에 접합한다(도 3의 (d)).Next, one surface of the crystalline thick film 1 is bonded to one surface of the hetero substrate 3 (FIG. 3 (d)).

결정질 후막(1)의 일면과 이종기판(3)의 접합은 결정질 후막(1)과 이종기판(3)에 열과 압력을 가하거나 열 또는 압력을 가함으로써 이루어질 수 있다.The bonding of one surface of the crystalline thick film 1 and the heterogeneous substrate 3 may be performed by applying heat and pressure or applying heat or pressure to the crystalline thick film 1 and the heterogeneous substrate 3.

이종기판(3)은 Si, Sapphire, Diamond 및 SiC 중 어느 하나로 이루어질 수 있으나, 반드시 이에 국한될 것은 아니며, Glass, GaAs, Ge, AlN, poly-AlN 또는 ZnO 등과 같은 다양한 물질로 이루어질 수 있다.The heterogeneous substrate 3 may be made of any one of Si, Sapphire, Diamond, and SiC, but is not necessarily limited thereto, and may be made of various materials such as glass, GaAs, Ge, AlN, poly-AlN, or ZnO.

한편, 접합률 내지 접합 품질을 향상시키기 위해 접합단계 전 패턴의 철부 표면을 플라즈마 처리하여 활성화시킨 후 결정질 후막(1)의 일면과 이종기판(3)의 일면을 접합할 수 있다.Meanwhile, in order to improve the bonding rate or the bonding quality, the surface of the convex portion of the pattern before the bonding step may be activated by plasma treatment, and then one surface of the crystalline thick film 1 may be bonded to one surface of the dissimilar substrate 3.

마지막으로, 결정질 후막(1)을 패턴의 철부에 형성된 이온 주입층을 기준으로 분리함으로써, 이종기판(3) 상에 결정질 박막(4)들이 전이된 전이 기판을 제조할 수 있다(도 3의 (e)). 즉, 이종기판 및 이종기판 상에 형성되되 이종기판이 소정 패턴으로 노출되도록 형성된 결정질 박막(1)들을 포함하는 전이기판을 제조할 수 있다.Finally, by separating the crystalline thick film 1 on the basis of the ion implantation layer formed in the convex portion of the pattern, it is possible to manufacture a transition substrate in which the crystalline thin films 4 are transferred on the hetero substrate 3 (FIG. e)). That is, it is possible to manufacture a transition substrate including the crystalline thin films 1 formed on the hetero substrate and the hetero substrate, the hetero substrate being exposed in a predetermined pattern.

분리단계(도 3의 (e))는 열처리 방법을 통해 이루어질 수 있다. 즉, 이종기판(3)과 접합된 결정질 후막(1)을 열처리하면, 결정질 후막(1)에 형성된 이온 주입층(2)이 가스층으로 변하며 팽창하게 되고, 이에 의해 결정질 후막(1)이 이온 주입층(2)을 기준으로 분리된다. 이때, 열처리 온도는 주입되는 이온의 특성에 따라 200~800℃로 조절될 수 있다.Separation step (Fig. 3 (e)) may be made through a heat treatment method. That is, when the crystalline thick film 1 bonded to the dissimilar substrate 3 is heat-treated, the ion implantation layer 2 formed in the crystalline thick film 1 turns into a gas layer and expands, whereby the crystalline thick film 1 is ion implanted. Separated on the basis of layer (2). At this time, the heat treatment temperature may be adjusted to 200 ~ 800 ℃ according to the characteristics of the implanted ions.

분리단계(도 3의 (e))는 공기 또는 질소(N2) 분위기에서 이루어질 수 있다.Separation step (e) of FIG. 3 may be performed in air or nitrogen (N 2 ) atmosphere.

이종 기판 상에 결정질 박막들이 전이된 전이 기판을 상술한 바와 같이 제조함으로써, 이온 주입에 의한 결정질 후막의 휨을 개선하여 접합 품질 및 접합률을 향상시킬 수 있다. 즉, 본 발명의 경우 요철 형상의 패턴에 의해 결정질 후막에 형성되는 이온 주입층은 분산되어 분포하게 되고 이에 의해 이온 주입에 의한 결정질 후막의 휨이 완화되게 되어 이종기판과 결정질 벌크의 접합 품질 및 접합률이 향상되게 된다. By manufacturing the transition substrate in which the crystalline thin films are transferred on the heterogeneous substrate as described above, the warpage of the crystalline thick film by ion implantation can be improved to improve the bonding quality and the bonding rate. That is, in the case of the present invention, the ion implantation layer formed on the crystalline thick film is dispersed and distributed by the uneven pattern, thereby reducing the warpage of the crystalline thick film due to ion implantation, and thus the bonding quality and bonding of the dissimilar substrate and the crystalline bulk. The rate is improved.

또한, 이종기판에 접합된 일부 결정질 박막에 크랙이 발생하더라도 크랙이 결정질 박막들 전체로 전파되는 것을 방지할 수 있다. 즉, 이종기판에 접합된 결정질 박막들은 각각 독립적으로 존재하게 되므로 일부 결정질 박막에 발생한 크랙이 다른 결정질 박막으로 전파되지 못하게 되고, 이에 의해 전이 기판의 가용면적을 크게 향상시킬 수 있다.In addition, even if cracks occur in some crystalline thin films bonded to the dissimilar substrate, cracks may be prevented from propagating through the crystalline thin films. That is, since the crystalline thin films bonded to the dissimilar substrate are each independently present, cracks generated in some crystalline thin films do not propagate to other crystalline thin films, thereby greatly improving the usable area of the transition substrate.


도 4는 본 발명의 일 실시예에 따른 반도체 소자 제조방법의 개략적인 개념도이다.4 is a schematic conceptual diagram of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 4에 도시된 바와 같이, 본 발명의 일 실시예에 따른 반도체 소자 제조방법은 전이 기판 준비단계(도 4의 (a)), 소자 형성단계(도 4의 (b)), 및 절단단계(도 4의 (c))를 포함하여 이루어질 수 있다.As shown in Figure 4, the semiconductor device manufacturing method according to an embodiment of the present invention is a transition substrate preparation step (Fig. 4 (a)), a device forming step (Fig. 4 (b)), and a cutting step ( It may be made including (c)) of FIG.

전이 기판 준비단계(도 4의 (a))에서는 상술한 전이 기판 제조방법에서 설명한 바와 같은 공정을 거쳐 이종기판(3) 및 이종기판(3) 상에 형성되되 이종기판(3)이 소정 패턴으로 노출되도록 형성된 결정질 박막(4)들을 포함하여 이루어진 전이 기판을 준비한다.In the transition substrate preparation step (FIG. 4A), the substrate 3 is formed on the dissimilar substrate 3 and the dissimilar substrate 3 through the process described in the method for manufacturing the transition substrate, and the dissimilar substrate 3 is formed in a predetermined pattern. A transition substrate including the crystalline thin films 4 formed to be exposed is prepared.

이후 전이 기판의 결정질 박막(4)들 상에 소자(6)를 형성한다(도 4의 (b)).Then, the element 6 is formed on the crystalline thin films 4 of the transition substrate (FIG. 4B).

소자 형성단계(도 4의 (b))는 LED, LD, SBD, HEMT 등과 같은 제조하고자 하는 반도체 소자에 따른 에피(epi) 성장 공정과 팹(fab) 공정을 전이 기판의 결정질 박막(4)들 상에 진행함으로써 이루어진다.In the device forming step (FIG. 4B), the epitaxial growth process and the fab process according to the semiconductor device to be manufactured, such as LED, LD, SBD, HEMT, etc., are performed. By proceeding to the phase.

마지막으로, 소자가 형성된 전이 기판을 개개의 소자들로 분리하기 위해 절단(도 4의 (c))함으로써 반도체 소자를 제조할 수 있다. 즉, 다이-소잉(die-sawing) 공정을 통해 소자(6)가 형성된 전이 기판을 결정질 박막(4)들을 따라 절단함으로써 개개의 반도체 소자를 제조할 수 있다.Finally, the semiconductor device can be manufactured by cutting the transition substrate on which the device is formed to separate into individual devices ((c) of FIG. 4). That is, individual semiconductor devices can be manufactured by cutting the transition substrate on which the elements 6 are formed along the crystalline thin films 4 through a die-sawing process.

한편, 본 발명의 일 실시예에 따른 반도체 소자 제조방법은 소자를 형성할 표면을 평탄화시켜 고품질의 반도체 소자를 제조하기 위해 전이 기판 준비단계(도 4의 (a)) 후, 소자 형성단계(도 4의 (b)) 전, 전이 기판의 결정질 박막(4)들 사이의 홈에 유전체(5)를 충진하여 표면을 평탄화하는 평탄화 단계를 더 포함할 수 있다(도 4의 (a')).On the other hand, the semiconductor device manufacturing method according to an embodiment of the present invention after the transition substrate preparation step (Fig. 4 (a)) to produce a high-quality semiconductor device by planarizing the surface to form the device, the device formation step (Fig. Before (b) of FIG. 4, a planarization step may be further included to fill the grooves between the crystalline thin films 4 of the transition substrate to planarize the surface (FIG. 4A ′).

여기서, 유전체(5)는 SiO2 또는 SiN 중 어는 하나로 이루어질 수 있다.Here, the dielectric 5 may be made of one of SiO 2 or SiN.


이상과 같이 본 발명은 비록 한정된 실시 예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시 예에 한정되는 것은 아니며, 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다.As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

그러므로 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니 되며, 후술하는 특허청구범위뿐만 아니라 특허청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

Claims (10)

결정질 후막을 준비하는 결정질 후막 준비단계;
상기 결정질 후막의 일면에 요철 형상의 패턴을 형성하는 패턴 형성단계;
상기 결정질 후막의 일면에 이온을 주입하여 상기 패턴의 철부에 이온 주입층을 형성하는 이온 주입단계;
상기 결정질 후막의 일면을 이종기판의 일면에 접합하는 접합단계; 및
상기 결정질 후막을 상기 패턴의 철부에 형성된 이온 주입층을 기준으로 분리하는 분리단계를 포함하는 것을 특징으로 하는 전이 기판 제조방법.A crystalline thick film preparation step of preparing a crystalline thick film;
A pattern forming step of forming an uneven pattern on one surface of the crystalline thick film;
An ion implantation step of forming an ion implantation layer on the convex portion of the pattern by implanting ions into one surface of the crystalline thick film;
Bonding the one surface of the crystalline thick film to one surface of the dissimilar substrate; And
And a separation step of separating the crystalline thick film based on the ion implantation layer formed in the convex portion of the pattern. 제1항에 있어서,
상기 패턴의 요부 폭은 10 ~ 100㎛인 것을 특징으로 하는 전이 기판 제조방법.The method of claim 1,
Transition substrate manufacturing method, characterized in that the recess width of the pattern is 10 ~ 100㎛. 제1항에 있어서,
상기 패턴은 격자 패턴인 것을 특징으로 하는 전이 기판 제조방법.The method of claim 1,
The pattern is a transition substrate manufacturing method, characterized in that the lattice pattern. 제1항에 있어서,
상기 결정질 후막은 GaN으로 이루어지고, 상기 이종기판은 Si, 사파이어, 다이아몬드 및 SiC 중 어느 하나로 이루어지는 것을 특징으로 하는 전이 기판 제조방법.The method of claim 1,
The crystalline thick film is made of GaN, the hetero substrate is a transition substrate manufacturing method, characterized in that made of any one of Si, sapphire, diamond and SiC. 제1항에 있어서,
상기 이온 주입단계에서 주입되는 이온은 수소, 헬륨, 질소, 산소, 및 아르곤 중 적어도 어느 하나를 포함하는 것을 특징으로 하는 전이 기판 제조방법.The method of claim 1,
The ion implanted in the ion implantation step is a transition substrate manufacturing method characterized in that it comprises at least one of hydrogen, helium, nitrogen, oxygen, and argon. 이종기판; 및
상기 이종기판 상에 형성되되, 상기 이종기판이 소정 패턴으로 노출되도록 형성된 결정질 박막들을 포함하는 것을 특징으로 하는 전이 기판.Heterogeneous substrate; And
And a crystalline thin film formed on the hetero substrate, wherein the crystalline thin films are formed to expose the hetero substrate in a predetermined pattern. 제6항에 있어서,
상기 결정질 박막은 GaN으로 이루어지고, 상기 이종기판은 Si, 사파이어, 다이아몬드 및 SiC 중 어느 하나로 이루어지는 것을 특징으로 하는 전이 기판.The method of claim 6,
The crystalline thin film is made of GaN, the hetero substrate is a transition substrate, characterized in that made of any one of Si, sapphire, diamond and SiC. 제1항 내지 제5항 중 어느 한 항의 방법에 의해 제조된 전이 기판을 준비하는 전이 기판 준비단계;
상기 전이 기판의 결정질 박막들 상에 소자를 형성하는 소자 형성단계; 및
상기 소자가 형성된 전이 기판을 상기 결정질 박막들을 따라 절단하는 절단단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법.A transition substrate preparation step of preparing a transition substrate prepared by the method of any one of claims 1 to 5;
An element forming step of forming an element on the crystalline thin films of the transition substrate; And
And cutting the transition substrate on which the device is formed along the crystalline thin films. 제8항에 있어서,
상기 전이 기판 준비단계 후, 소자 형성단계 전, 상기 전이 기판의 결정질 박막들 사이의 홈에 유전체를 충진하여 표면을 평탄화하는 평탄화 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 8,
And a planarization step of flattening a surface by filling a dielectric between grooves between crystalline thin films of the transition substrate after the transition substrate preparation step and before the device formation step. 제9항에 있어서,
상기 유전체는 SiO2 또는 SiN 중 어는 하나로 이루어지는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 9,
The dielectric is a semiconductor device manufacturing method, characterized in that consisting of one of SiO 2 or SiN.
PCT/KR2014/009152 2013-10-01 2014-09-30 Method for preparing transition substrate, transition substrate prepared thereby, and method for preparing semiconductor device by using same Ceased WO2015050350A1 (en)

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