WO2014126182A1 - Reset circuit for memory-cell array that stores access history - Google Patents

Abstract

[Problem] To reset, in a short amount of time, a memory-cell array for analyzing an access history. [Solution] The following are provided: a memory-cell array (110) that stores an access history for a memory-cell array that stores user data; and a reset circuit (120, 150, 160, 170) that, in response to a reset signal (RESET), erases the access history stored in the aforementioned memory-cell array (110). Said memory-cell array (110) contains a plurality of word lines (RWL), a plurality of bit lines (RBL), and a plurality of memory cells at the intersections thereof. A row decoder (120) activates a plurality of word lines (RWL), and in the resulting state, a write circuit (150) supplies an initialization value to the bit lines (RBL). This makes it possible to reset an access history in a short amount of time.

Description

[Name of invention determined by ISA based on Rule 37.2] Memory cell array reset circuit for storing access history

The present invention relates to a semiconductor device, and more particularly to a semiconductor device that needs to hold information by a refresh operation.

DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device, stores information by the electric charge accumulated in the cell capacitor. Therefore, information is lost unless it is periodically refreshed. For this reason, a refresh command for instructing a refresh operation is periodically issued from the control device that controls the DRAM (see Patent Document 1). The refresh command is issued from the control device at a frequency at which all word lines are always refreshed once during one refresh cycle (for example, 64 msec).

JP 2011-258259 A

However, depending on the access history to the memory cell, the information retention characteristic of the predetermined memory cell may be deteriorated. When the information holding time of a predetermined memory cell is reduced to less than one refresh cycle, even if a refresh command is issued with a frequency that all word lines are refreshed once during one refresh cycle, a part of the information is stored. There was a risk of being lost.

As a method of analyzing the access history, a method of using a counter circuit assigned to each word line and updating the count value of the counter circuit every time an access is performed can be considered. As another method, a dedicated memory cell array for holding the access history is prepared separately, the corresponding count value is read from the dedicated memory cell array every time access is performed, and the count value is counted up and then written back. A method is also conceivable. Although the operation of the latter method is slightly more complicated than the former method, it is considered that the latter method is highly practical because the access history can be analyzed with a smaller circuit scale. However, when the latter method is adopted, it is necessary to write initial values to all the memory cells included in the dedicated memory cell array at the time of resetting after power-on, and there is a problem that the time required for this becomes long. .

The semiconductor device according to the present invention includes a plurality of first word lines, a plurality of first bit lines intersecting with the plurality of first word lines, the plurality of first word lines, and the plurality of firsts. A first memory cell array including a plurality of first memory cells arranged at intersections of the plurality of bit lines, a second memory cell array for storing access histories for the plurality of first word lines, and a reset signal And a reset circuit for erasing the access history stored in the second memory cell array, wherein the second memory cell array corresponds to one or more of the plurality of first word lines, respectively. A plurality of second word lines, a plurality of second bit lines intersecting with the plurality of second word lines, the plurality of second word lines, and the plurality of second bits. Place at intersection with line A plurality of second memory cells, and the reset circuit supplies an initial value to the plurality of second bit lines in a state where the plurality of second word lines are activated, The access history is reset.

According to the present invention, since the reset circuit for resetting the access history is provided, the access history can be reset in a short time.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. 3 is an enlarged circuit diagram showing a part of a memory cell array 11. FIG. FIG. 3 is a cross-sectional view of two memory cells MC sharing a bit line, and a word line WL includes a trench gate type cell transistor Tr embedded in a semiconductor substrate 4. 2 is a schematic plan view for explaining the structure of the memory cell array 11 in more detail. FIG. 3 is a circuit diagram of a refresh control circuit 40. FIG. 3 is a block diagram of an access count unit 100. FIG. 2 is a circuit diagram of a memory cell array 110. FIG. 2 is a circuit diagram of an SRAM cell SC included in a memory cell array 110. FIG. 3 is a block diagram showing a configuration of a row decoder 120. FIG. 3 is a circuit diagram of a command control circuit 160. FIG. It is a timing diagram for explaining the operation of the command control circuit 160 when an active command ACT is issued from the outside. It is a timing diagram for explaining the operation of the command control circuit 160 when a refresh command REF is issued from the outside. 2 is a block diagram illustrating a configuration of a power supply control circuit 170, where (a) is a first circuit example and (b) is a second circuit example. FIG. 3 is a block diagram of an address generation unit 200. FIG. 7 is a timing chart for explaining operations of an additional refresh counter 280 and a selection signal generation circuit 270. FIG. 3 is a circuit diagram of a selection signal generation circuit 270. FIG. 4 is a timing chart for explaining the operation of the semiconductor device 10. FIG. FIG. 10 is a circuit diagram of an SRAM cell SC according to a first modification. It is a block diagram which shows the structure of the power supply control circuits 170 and 290 by a modification, (a) is a 3rd circuit example, (b) is a 4th circuit example. FIG. 12 is a circuit diagram of an SRAM cell SC according to a second modification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

The semiconductor device 10 according to the present embodiment is a DDR3 (Double Data Rate 3) type DRAM integrated on a single semiconductor chip, and is mounted on the external substrate 2. The external substrate 2 is a memory module substrate or a mother board, and is provided with an external resistor Re. The external resistor Re is connected to the calibration terminal ZQ of the semiconductor device 10, and its impedance is used as the reference impedance of the calibration circuit 38. In the present embodiment, the ground potential VSS is supplied to the external resistor Re.

As shown in FIG. 1, the semiconductor device 10 has a memory cell array 11. The memory cell array 11 includes p + 1 word lines WL (WL0 to WLp) and a plurality of bit lines BL, and has a configuration in which memory cells MC are arranged at intersections thereof. Selection of the word line WL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13.

Also, the semiconductor device 10 is provided with a command address terminal 21, a reset terminal 22, a clock terminal 23, a data terminal 24, power supply terminals 25 and 26, and a calibration terminal ZQ as external terminals.

The command address terminal 21 is a terminal to which an address signal ADD and a command signal COM are input from the outside. The address signal ADD input to the command address terminal 21 is supplied to the address latch circuit 32 via the command address input circuit 31 and latched. The address signal IADD latched by the address latch circuit 32 is supplied to the row decoder 12, the column decoder 13, or the mode register 14. The mode register 14 is a circuit in which a parameter indicating the operation mode of the semiconductor device 10 is set.

The command signal COM input to the command address terminal 21 is supplied to the command decode circuit 33 via the command address input circuit 31. The command decode circuit 33 is a circuit that generates various internal commands by decoding the command signal COM. The internal commands include an active signal IACT, a column signal ICOL, a refresh signal IREF, a mode register set signal MRS, a calibration signal ZQC, and the like.

The active signal IACT is a signal that is activated when the command signal COM indicates row access (active command). When the active signal IACT is activated, the address signal IADD latched in the address latch circuit 32 is supplied to the row decoder 12. As a result, the word line WL designated by the address signal IADD is selected. Although not particularly limited, in the present embodiment, the address signal IADD used for row access has a 14-bit configuration including A0 to A13. This means that the memory cell array 11 includes 16k (= 2 ¹⁴ ) word lines WL.

The column signal ICOL is a signal that is activated when the command signal COM indicates column access (read command or write command). When the internal column signal ICOL is activated, the address signal IADD latched in the address latch circuit 32 is supplied to the column decoder 13. As a result, the bit line BL designated by the address signal IADD is selected.

Therefore, when an active command and a read command are input and a row address and a column address are input in synchronization therewith, read data is read from the memory cell MC specified by the row address and the column address. The read data DQ is output to the outside from the data terminal 24 via the read / write amplifier 15 and the input / output circuit 16.

On the other hand, when an active command and a write command are input, and a row address and a column address are input in synchronization therewith, and then write data DQ is input to the data terminal 24, the write data DQ is input to the input / output circuit 16 and the read The data is supplied to the memory cell array 11 via the write amplifier 15 and written to the memory cell MC specified by the row address and the column address.

The refresh signal IREF is a signal that is activated when the command signal COM indicates a refresh command. The refresh signal IREF is supplied to the refresh control circuit 40. The refresh control circuit 40 is a circuit that activates a predetermined word line WL included in the memory cell array 11 by controlling the row decoder 12, thereby executing a refresh operation. In addition to the refresh signal IREF, the refresh control circuit 40 is supplied with an active signal IACT, an address signal IADD, and a reset signal RESET input via the reset terminal 22. Details of the refresh control circuit 40 will be described later.

The mode register set signal MRS is a signal that is activated when the command signal COM indicates a mode register set command. Therefore, if a mode register set command is input and a mode signal is input from the command address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.

Here, returning to the description of the external terminals provided in the semiconductor device 10, the external clock signals CK and / CK are input to the clock terminal 23. The external clock signal CK and the external clock signal / CK are complementary signals, and both are supplied to the clock input circuit 34. The external clock signals CK and / CK input to the clock input circuit 34 are supplied to the internal clock generation circuit 35, thereby generating the internal clock signal ICLK. The internal clock signal ICLK is supplied to the timing generator 36, whereby various internal clock signals are generated. Various internal clock signals generated by the timing generator 36 are supplied to circuit blocks such as the address latch circuit 32 and the command decode circuit 33, and define the operation timing of these circuit blocks.

The power supply terminal 25 is a terminal to which power supply potentials VDD and VSS are supplied. The power supply potentials VDD and VSS supplied to the power supply terminal 25 are supplied to the internal power supply generation circuit 37. The internal power supply generation circuit 37 generates various internal potentials VPP, VOD, VARY, VPERI and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is a potential mainly used in the row decoder 12, the internal potentials VOD and VARY are potentials used in the sense amplifier in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. Potential. On the other hand, the reference potential ZQVREF is a reference potential used in the calibration circuit 38.

The power supply terminal 26 is a terminal to which power supply potentials VDDQ and VSSQ are supplied. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal 26 are supplied to the input / output circuit 16. The power supply potentials VDDQ and VSSQ are the same as the power supply potentials VDD and VSS supplied to the power supply terminal 25, respectively, but the input / output circuit 16 does not propagate power supply noise generated by the input / output circuit 16 to other circuit blocks. Uses dedicated power supply potentials VDDQ and VSSQ.

The calibration terminal ZQ is connected to the calibration circuit 38. When the calibration circuit 38 is activated by the calibration signal ZQC, the calibration circuit 38 performs a calibration operation with reference to the impedance of the external resistor Re and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the input / output circuit 16, whereby the impedance of an output buffer (not shown) included in the input / output circuit 16 is designated.

FIG. 2 is a circuit diagram showing a part of the memory cell array 11 in an enlarged manner.

As shown in FIG. 2, a plurality of word lines WL extending in the Y direction and a plurality of bit lines BL extending in the X direction are provided inside the memory cell array 11, and memory cells are arranged at the intersections. MC is arranged. The memory cell MC is a so-called DRAM cell, and has a configuration in which a cell transistor Tr composed of an N-channel MOS transistor and a cell capacitor C are connected in series. The gate electrode of the cell transistor Tr is connected to the corresponding word line WL, one of the source / drain is connected to the corresponding bit line BL, and the other of the source / drain is connected to the cell capacitor C.

The memory cell MC stores information by the electric charge accumulated in the cell capacitor C. Specifically, when the cell capacitor C is charged to the internal potential VARY, that is, when charged to a high level, one logic level (for example, logic value = 1) is stored, and the cell capacitor C When charged to the ground potential VSS, that is, when charged to a low level, the other logic level (for example, logic value = 0) is stored. Since the electric charge accumulated in the cell capacitor C is gradually lost due to the leakage current, it is necessary to perform a refresh operation every time a certain time elapses.

The refresh operation is basically the same as the row access in response to the active signal IACT. That is, the word line WL to be refreshed is driven to an active level, thereby turning on the cell transistor Tr connected to the word line WL. The activation level of the word line WL is, for example, the internal potential VPP, which is higher than the internal potential VPERI used in most peripheral circuits. Accordingly, since the cell capacitor C is connected to the corresponding bit line BL, the potential of the bit line BL varies according to the charge accumulated in the cell capacitor C. Then, by activating the sense amplifier SA to amplify the potential difference generated between the paired bit lines BL and then returning the word line WL to the inactive level, the charge level of the cell capacitor C is regenerated. . The inactive level of the word line WL is, for example, a negative potential VKK lower than the ground potential VSS.

The cycle for performing the refresh operation is called a refresh cycle, and is defined as 64 msec by the standard, for example. Therefore, if the information holding time of each memory cell MC is designed to be longer than the refresh cycle, the information can be continuously held by a periodic refresh operation. Actually, the information holding time of each memory cell MC has a sufficient margin with respect to the refresh cycle. Therefore, when the refresh operation is performed in a slightly longer cycle than the refresh cycle defined by the standard. Even so, it is possible to correctly hold the information of the memory cell MC.

However, in recent years, a disturb phenomenon in which the information holding time of the memory cell MC is reduced due to the access history has been a problem. The disturb phenomenon is a phenomenon in which when a certain word line WL is repeatedly accessed, the information retention characteristics of the memory cells MC connected to the other word lines WL adjacent thereto are deteriorated. For example, when the word line WLm shown in FIG. 2 is repeatedly accessed, the information retention characteristics of the memory cells MC connected to the word lines WLm−1 and WLm + 1 adjacent thereto are deteriorated. There are various theories about the cause, but it is considered to be caused by, for example, a parasitic capacitance Cp generated between adjacent word lines.

That is, when a predetermined word line WLm is repeatedly accessed, the potential repeatedly changes from the negative potential VKK to the high potential VPP. Therefore, the adjacent word lines WLm−1 and WLm + 1 are fixed to the negative potential VKK. Regardless, the potential increases slightly due to the coupling by the parasitic capacitance Cp. As a result, the off-leak current of the cell transistor Tr connected to the word lines WLm−1 and WLm + 1 increases, and the charge level of the cell capacitor C is lost faster than usual.

Also, there are other ideas as follows. FIG. 3 is a cross-sectional view of two memory cells MC sharing a bit line, and includes a trench gate type cell transistor Tr in which a word line WL is embedded in a semiconductor substrate 4. The word lines WLm and WLm + 1 shown in FIG. 3 are embedded in the same active region partitioned by the element isolation region 6, and when this is activated, a channel is formed between the corresponding source / drain SD. One of the source / drain SD is connected to the bit line node, and the other is connected to the capacitor node. In such a cross section, when the word line WLm is accessed and then the cell transistor Tr is turned off (that is, the channel is cut), floating electrons as carriers are generated near the channel. When access to the word line WLm is repeated, the stray electrons accumulate, the accumulated stray electrons move to the capacitor node on the word line WLm + 1 side, induce a PN junction leak, and the charge level of the cell capacitor C is lost. Make it.

In any case, if the information holding time of the memory cell MC is reduced by such a mechanism, there is a risk that the information holding time falls below the refresh cycle defined by the standard. If the information holding time falls below the refresh cycle, some data will be lost even if the refresh operation is executed correctly.

The semiconductor device 10 according to the present embodiment is characterized in that an additional refresh operation is performed based on the access history in consideration of the disturb phenomenon described above.

FIG. 4 is a schematic plan view for explaining the structure of the memory cell array 11 in more detail.

As shown in FIG. 4, in the present embodiment, word lines WL (for example, word lines WLn (0) and WLn (1)) corresponding to two cell transistors Tr sharing the bit line contact BLC are close to each other. The interval is W1. The bit line contact BLC is a contact conductor for connecting one of the source / drain of the cell transistor Tr and the bit line BL. The other of the source / drain is connected to a cell capacitor C (not shown) via a cell contact CC.

On the other hand, the interval between adjacent word lines WL (for example, word lines WLn (1) and WLn + 1 (0)) corresponding to the cell transistors Tr not sharing the bit line contact BLC is an interval W2 wider than the interval W1. . The reason for this layout is that, as shown in FIG. 4, active regions ARa whose longitudinal direction is the A direction and active regions ARb whose longitudinal direction is the B direction are alternately formed in the X direction. It is.

When the memory cell array 11 has such a layout, even if a certain word line WLn (0) is repeatedly accessed, a parasitic capacitance is applied to the adjacent word line WLn (1) at the interval W1. Since Cp1 is large, a disturb phenomenon occurs. However, since the parasitic capacitance Cp2 is small for the adjacent word line WLn-1 (1) at the interval W2, the disturb phenomenon hardly occurs. Therefore, in the case of such a layout, it is necessary to perform an additional refresh operation for the word line WLn (1) in which the disturb phenomenon occurs, but the other word line WLn−1. There is no need to perform an additional refresh operation for (1).

Also, adjacent word lines WLn (0) and WLn (1) at the interval W1 differ only in the least significant bit (A0) of the assigned row address, and the values of the other bits (A1 to A13) match. ing. In consideration of such characteristics, in the present embodiment, the circuit configuration of the refresh control circuit 40 is simplified. Hereinafter, the configuration and operation of the refresh control circuit 40 provided in the semiconductor device 10 will be described in detail.

FIG. 5 is a circuit diagram of the refresh control circuit 40.

As shown in FIG. 5, the refresh control circuit 40 includes a refresh counter 41, an access count unit 100, an address generation unit 200, and a selection circuit 42.

The refresh counter 41 is a circuit that generates a row address (refresh address) RADDa to be refreshed in response to a refresh signal IREF. The refresh address RADDa that is the count value is updated (incremented or decremented) in response to the refresh signal IREF. For this reason, if a refresh command is input from the outside a plurality of times (for example, 8k times) so that the count value of the refresh counter 41 makes one round during one refresh cycle, all word lines WL are refreshed during one refresh cycle. be able to. However, when the selection signal SEL is activated, the count value is not updated even if the refresh signal IREF is input. When the reset signal RESET is input, the count value of the refresh counter 41 is reset to the initial value.

The access count unit 100 is a circuit that analyzes a history of row access to the memory cell array 11. The address signal IADD supplied to the access count unit 100 is only 13 bits including bits A1 to A13 among the bits A0 to A13. That is, the least significant bit A0 is degenerated.

FIG. 6 is a block diagram of the access count unit 100.

As shown in FIG. 6, the access count unit 100 includes a memory cell array 110 and a row decoder 120. Although not particularly limited, the memory cell array 110 has a configuration in which a plurality of SRAM (Static Random Access Memory) cells SC are arranged in a matrix as shown in FIG. Specifically, it has (p + 1) / 2 word lines RWL0 to RWL (p-1) / 2 and T + 1 bit lines RBL0 to RBLT, and SRAM cells are respectively arranged at the intersections thereof. have. Here, the value of p + 1 is the number of word lines WL0 to WLp included in the memory cell array 11 shown in FIG. That is, the number of word lines RWL included in the memory cell array 110 is half of the number of word lines WL included in the memory cell array 11. This is because the least significant bit A0 is degenerated in the analysis of the access history.

FIG. 8 is a circuit diagram of the SRAM cell SC included in the memory cell array 110.

As shown in FIG. 8, the SRAM cell SC has a configuration in which two inverters INV1 and INV2 are connected in a circulating manner. The input node of the inverter INV2 (the output node of the inverter INV1) is connected to the other bit line RBL (B) via the transistor TrB. The gate electrodes of the transistors TrT and TrB are connected to the corresponding word line RWL. With this configuration, when a certain word line RWL is activated, complementary data is output to the corresponding bit lines RBL (T) and RBL (B).

Further, the inverters INV1 and INV2 have a high-order power supply node and a low-order power supply node, and operate by a voltage applied between them. The internal potential VPERI is supplied to the higher power supply node of the inverter INV1, while the internal potential VPERIZ is supplied to the higher power supply node of the inverter INV2. The ground potential VSS is supplied to the lower power supply nodes of the inverters INV1 and INV2. The internal potential VPERIZ will be described later.

The bit lines RBL0 to RBLT are connected to the read circuits 130 ₀ to 130 _T constituting the read circuit 130, respectively. The bit lines RBL0 to RBLT are complementary wirings each composed of two signal lines. In FIG. 6 and FIG. 7, each bit line RBL0 to RBLT is shown by one solid line. The read circuit 130 is a circuit that writes data (count value) read via the bit lines RBL0 to RBLT to the register circuits 140 ₀ to 140 _T included in the counter circuit 140. The register circuits 140 ₀ to 140 _T are connected in cascade, thereby constituting a binary counter. Further, the highest-order register circuit 140 _{T + 1} is added to the counter circuit 140, and the value is output as the detection signal MAX. Therefore, when the value of the register circuits 140 ₀ to 140 _T is the maximum value (all 1), the detection signal MAX, which is the stored value of the register circuit 140 _{T + 1} , is inverted from 0 to 1. Thus, the register circuit 140 _{T + 1} functions as a detection circuit that detects that the count value has reached a predetermined value.

Data (count values) output from the register circuits 140 ₀ to 140 _T are respectively supplied to the corresponding bit lines RBL 0 to RBLT by the corresponding write circuits 150 ₀ to 150 _{T, and} are written back to the memory cells.

The operations of the row decoder 120, the read circuit 130, the counter circuit 140, and the write circuit 150 are controlled by the command control circuit 160. The command control circuit 160 receives the active signal IACT, the refresh signal IREF, and the reset signal RESET, and generates an active signal RACT, a count up signal RCNT, a reset signal RRST, a read signal RREAD, and a write signal RWRT based on them. Here, the active signal RACT is a signal that activates the row decoder 120, the count-up signal RCNT is a signal that counts up the count value of the counter circuit 140, and the reset signal RRST resets the count value of the counter circuit 140. Signal. The read signal RREAD is a signal that activates the read circuit 130, and the write signal RWRT is a signal that activates the write circuit 150.

FIG. 9 is a block diagram showing the configuration of the row decoder 120.

As shown in FIG. 9, the row decoder 120 decodes the row address IADD or the refresh address RADD in response to the active signal RACT, and the corresponding word line RWL0 based on the decoding result by the address decoder 121. A plurality of word drivers 122 for driving each of RWL (p−1) / 2 are provided. With this configuration, when the row address IADD or the refresh address RADD is input in synchronization with the active signal RACT, one of the corresponding word lines RWL0 to RWL (p−1) / 2 is activated.

Further, the reset signal RESET is also supplied to the word driver 122. When this is activated, all the word lines RWL0 to RWL (p−1) / 2 are activated regardless of the output signal from the address decoding unit 121. In the example shown in FIG. 9, the delay circuit 123 is inserted on the wiring through which the reset signal RESET is transmitted, so that the half word lines RWL0 to RWL {(p + 1) / 4} -1 are simultaneously activated. And the timing at which the remaining half word lines RWL (p + 1) / 4 to RWL (p−1) / 2 are simultaneously activated. This is because the peak of the current consumption by the word driver 122 is dispersed by reducing the number of word lines activated simultaneously, and the peak of the current consumption by the write circuit 150 is reduced by reducing the number of simultaneously selected SRAM cells. Is to disperse.

However, in the present invention, it is not essential to distribute the activation timing of the word driver 122 during the reset operation. Further, when the activation timing of the word driver 122 is distributed, the word driver 122 is not limited to two divisions as described above, and may be three or more divisions.

FIG. 10 is a circuit diagram of the command control circuit 160.

As shown in FIG. 10, the command control circuit 160 includes a latch circuit SR1 set by an active signal IACT and a latch circuit SR2 set by a refresh signal IREF. The output signal OUT1 of the latch circuit SR1 is output as a read signal RREAD via the delay element DLY2 and the pulse generation circuit PLS1. The output signal OUT2 of the latch circuit SR2 is output as the reset signal RRST through the pulse generation circuit PLS2.

Further, the output signals OUT1 and OUT2 are supplied to the NAND gate circuit G1, and the output signal is output as the active signal RACT via the delay element DLY1. The active signal RACT is output as the count up signal RCNT through the delay element DLY3.

Further, the command control circuit 160 includes a latch circuit SR3 that is set by the output signal of the NOR gate circuit G2 that receives the read signal RREAD and the reset signal RRST. The latch circuit SR3 is reset by the output signal of the NAND gate circuit G1. The output signal of the latch circuit SR3 is output as the write signal RWRT via the delay element DLY4 and the AND gate circuit G3. The write signal RWRT is fed back to the latch circuits SR1 and SR2 via the delay element DLY5 and the OR gate circuit G4 to reset them. The latch circuits SR1 to SR3 are also reset by a reset signal RESET.

FIG. 11 is a timing chart for explaining the operation of the command control circuit 160 when an active command ACT is issued from the outside.

When an active command ACT is issued from the outside, the active signal IACT is activated and the latch circuit SR1 is set. As a result, the output signal OUT1 changes to the low level, and the active signal RACT and the read signal RREAD are activated in this order. The timing from when the output signal OUT1 changes to the low level until the active signal RACT and the read signal RREAD are activated is defined by the delay amounts of the delay elements DLY1 and DLY2, respectively. Further, when the active signal RACT is activated, the count-up signal RCNT is activated through a delay by the delay element DLY3.

On the other hand, since the latch circuit SR3 is set when the read signal RREAD is activated, the write signal RWRT is activated through the delay by the delay element DLY4. Thereafter, the end signal END is activated through a delay by the delay element DLY5, the latch circuits SR1 and SR3 are reset, and the initial state is restored. Thus, when the active command ACT is issued from the outside, the active signal RACT, the read signal RREAD, the count up signal RCNT, and the write signal RWRT are activated in this order.

First, when the active signal RACT is activated, the row decoder 120 shown in FIGS. 6 and 9 selects the word line RWL indicated by the row address IADD (A1 to A13). As a result, data (count value) corresponding to the selected word line RWL is read to the bit line RBL. As described above, in the row address IADD input to the access count unit 100, the least significant bit A0 is degenerated. Therefore, the word line RWL selected in response to the active signal RACT is to two adjacent word lines WL (for example, the word line WLn (0) and the word line WLn (1)) at the interval W1 shown in FIG. Assigned in common.

Next, when the read signal RREAD is activated, the data (count value) read to the bit line RBL is amplified by the read circuit 130 and loaded into the counter circuit 140. In the example shown in FIG. 11, the read count value is k, and this value is loaded into the counter circuit 140.

Subsequently, when the count-up signal RCNT is activated, the count value loaded in the counter circuit 140 is incremented. That is, the count value changes from k to k + 1. When the write signal RWRT is activated, the updated count value (k + 1) is written back to the memory cell array 110 via the write circuit 150.

By the above operation, the count value corresponding to the input row address IADD (A1 to A13) is incremented. Since this operation is executed every time an active command ACT is issued from the outside, the number of row accesses can be counted with two adjacent word lines WL as a unit at the interval W1. However, since the least significant bit A0 of the row address IADD is degenerated, it is not distinguished which of the two adjacent word lines WL is accessed at the interval W1.

As a result of repeating such an operation, when the value of the highest register circuit 140 _{T + 1} included in the counter circuit 140 is inverted from 0 to 1, that is, when the count value reaches a predetermined value, the detection signal MAX is activated to a high level. Turn into. The detection signal MAX is supplied to the address generator 200 shown in FIG.

FIG. 12 is a timing chart for explaining the operation of the command control circuit 160 when a refresh command REF is issued from the outside.

When a refresh command REF is issued from the outside, the refresh signal IREF is activated, and the latch circuit SR2 shown in FIG. 10 is set. As a result, the output signal OUT2 changes to a low level, and the reset signal RRST and the active signal RACT are activated in this order. The timing from when the output signal OUT2 changes to the low level to when the active signal RACT is activated is defined by the delay amount of the delay element DLY1.

When the reset signal RRST is activated, the latch circuit SR3 is set, so that the write signal RWRT is activated after being delayed by the delay element DLY4. Thereafter, the end signal END is activated through a delay by the delay element DLY5, the latch circuits SR2 and SR3 are reset, and the initial state is restored. Thus, when the refresh command REF is issued from the outside, the reset signal RRST, the active signal RACT, and the write signal RWRT are activated in this order. In this example, the count-up signal RCNT is also activated, but the operation due to this is ignored by the reset signal RRST. A circuit configuration that prohibits activation of the count-up signal RCNT in response to the refresh command REF is also possible.

Further, when the reset signal RRST is activated, the register circuits 140 ₀ to 140 _{T + 1} constituting the counter circuit 140 are reset, and thereby the count value of the counter circuit 140 is reset to an initial value (for example, 0). In this example, the count-up signal RCNT is then activated, but the count signal of the counter circuit 140 is maintained at the initial value because the active state of the reset signal RRST is maintained. Next, the active signal RACT is activated, and the word line RWL corresponding to the refresh address RADD (A1 to A13) is selected.

Then, when the write signal RWRT is activated, the initialized count value (for example, 0) is written into the memory cell array 110 via the write circuit 150. As a result, the count value corresponding to the word line RWL is initialized to 0, for example.

By the above operation, the count value corresponding to the refresh address RADD (A1 to A13) is initialized. Again, since the least significant bit A0 of the refresh address RADD is degenerated, the corresponding count value is reset regardless of the refresh operation for any two adjacent word lines WL at the interval W1.

The above is the circuit configuration and operation of the command control circuit 160. By such control by the command control circuit 160, the corresponding count value is counted up regardless of which of the two adjacent word lines WL is accessed at the interval W1, and when this reaches a predetermined value, the detection signal MAX is activated. On the other hand, even if any of the two adjacent word lines WL is refreshed at the interval W1, the corresponding count value is reset.

Further, when a reset signal RESET is issued from the outside, all the SRAM cells included in the memory cell array 110 are reset, and thereby all count values are initialized to 0, for example. Such an operation is performed by selecting all the word lines RWL0 to RWL (p−1) / 2 by the row decoder 120 and giving initial values to the bit lines RBL0 to RBLT in this state. The reset signal RESET is also supplied to the power supply control circuit 170 shown in FIG. The power supply control circuit 170 is a circuit that generates the internal potential VPERIZ (or the ground potential VSSZ) described above, and plays a role of assisting the initialization operation of the memory cell array 110. In the present invention, a circuit portion that initializes data in the memory cell array 110 (210) based on the reset signal RESET may be collectively referred to as a “reset circuit”.

FIG. 13 is a block diagram showing the configuration of the power supply control circuit 170, where (a) is a first circuit example and (b) is a second circuit example.

As shown in FIG. 13A, the power supply control circuit 170 according to the first circuit example includes a selection circuit 171 that uses either the internal potential VPERI or the high impedance HiZ as the internal potential VPERIZ. The selection operation by the selection circuit 171 is controlled by the output signal RP of the SR latch circuit 172. Specifically, if the output signal RP is high level, the high impedance HiZ is selected, and if the output signal RP is low level, the internal potential VPERI is selected.

The SR latch circuit 172 is set by the reset signal RESET, and is reset by the reset signal RESET delayed by the delay circuit 173. For this reason, when the reset signal RESET is activated, the internal potential VPERIZ becomes high impedance HiZ for a predetermined period determined by the delay amount of the delay circuit 173, and then becomes the same potential as the internal potential VPERI.

The power supply control circuit 170 according to the second circuit example is the same as that shown in FIG. 13B except that the ground potential VSS is used instead of the high impedance HiZ, as shown in FIG. This is the same as the circuit example shown in FIG. Therefore, when the reset signal RESET is activated, the internal potential VPERIZ becomes the same potential as the ground potential VSS for a predetermined period determined by the delay amount of the delay circuit 173, and then becomes the same potential as the internal potential VPERI.

As described above, the internal potential VPERIZ is supplied to the higher power supply node of the inverter INV2 constituting the SRAM cell SC. For this reason, when the reset signal RESET is activated, the inverter INV2 is substantially deactivated, and the ability to drive to the high level becomes almost zero. This is because the potential difference between the high power supply node and the low power supply node becomes indefinite when the first circuit example is used, and the high power supply node and the low power supply node use the second circuit example. This is because the potential difference becomes zero. Thus, if a low level signal is supplied to the bit line RBL (T) and a high level signal is supplied to the bit line RBL (B), the initial value is immediately overwritten on the SRAM cell SC. . This is because the output of the inverter INV1 is fixed at a high level by the inactivation of the inverter INV2, and the output of the inverter INV2 is fixed at an indefinite or low level. As a result, the load on the write circuit 150 that drives the bit lines RBL (T) and RBL (B) is greatly reduced, so that the current consumption during the reset operation is reduced and the reset operation can be performed in a very short time. Can be done.

FIG. 14 is a block diagram of the address generation unit 200.

As shown in FIG. 14, the address generator 200 includes a memory cell array 210, a row decoder 220, an address write circuit 230, and an address read circuit 240. Although not particularly limited, the memory cell array 210 has a configuration in which a plurality of SRAM (Static Random Access Memory) cells are arranged in a matrix like the memory cell array 110 described above. Specifically, it has a configuration in which r + 1 word lines RRWL0 to RRWLr and 13 bit lines RRBL1 to RRBL13 are arranged, and SRAM cells are respectively arranged at intersections thereof. The configuration of the SRAM cell included in the memory cell array 210 is also the same as that of the SRAM cell SC shown in FIG.

The selection of the word lines RRWL0 to RRWLr is performed in response to the refresh signal IREF based on the row address RA output from the write counter 250 or the read counter 260. The row address RA output from the write counter 250 is referred to when the row address IADD (A1 to A13) is written to the memory cell array 210 using the address write circuit 230. The row address RA output from the read counter 260 is referred to when the refresh address RADDb (A1 to A13) is read from the memory cell array 210 using the address read circuit 240. As will be described later, the row address IADD (A1 to A13) written in the memory cell array 210 indicates the word line WLn (0) or WLn (1) whose access count has reached a predetermined value.

The address write circuit 230 includes write circuits 230 ₁ to 230 ₁₃ corresponding to the respective bits of the row address IADD (A1 to A13). The row address IADD (A1 to A13) is applied to the row address RA output from the write counter 250. Play the role of writing.

On the other hand, the address read circuit 240 includes read circuits 240 ₁ to 240 ₁₃ corresponding to the respective bits of the refresh address RADDb (A1 to A13), and the refresh address RADDb (A1 to A13) from the row address RA output from the read counter 260. ). Further, the address read circuit 240 includes a LSB output circuit 240 _0, the least significant bit A0 of the refresh address RADDb, the output signal of the LSB output circuit 240 ₀ is used. Bit A0 is the output signal of the LSB output circuit 240 _0, the clock signal CLKA output from the selection signal generating circuit 270, inverted on the basis of CLKB.

The selection signal generation circuit 270 is a circuit that generates the selection signal SEL and the clock signals CLKA and CLKB described above based on the selection signal PSEL and the refresh signal IREF. The selection signal SEL is supplied to the selection circuit 42 shown in FIG. 5 and used to select the refresh address RADDa or RADDb, and is also supplied to the refresh counter 41 to perform an update operation of the refresh counter 41 in response to the refresh signal IREF. Used to allow or prohibit.

The selection signal PSEL is generated by the additional refresh counter 280. The additional refresh counter 280 is a circuit that counts up by 2 counts in response to the detection signal MAX and counts down by 1 count in response to the refresh signal IREF. If the count value is 1 or more, the additional refresh counter 280 activates the selection signal PSEL. Make it.

FIG. 15 is a timing chart for explaining operations of the additional refresh counter 280 and the selection signal generation circuit 270.

In the example shown in FIG. 15, the active signal IACT is activated at times t31 and t32, and the refresh signal IREF is activated at times t41, t42, t43, t44, and t45. Further, in response to the activation of the active signal IACT at times t31 and t32, the detection signal MAX is activated. This is because the number of accesses to a certain word line WL exceeds a predetermined value due to the row access in response to the active signal IACT at time t31, and another word line WL is also caused by the row access in response to the active signal IACT at time t32. This means that the number of accesses exceeds the predetermined value.

In this case, the count value of the additional refresh counter 280 is counted up from “0” to “2” in response to the first activation of the detection signal MAX, and is added in response to the second activation of the detection signal MAX. The count value of the refresh counter 280 is counted up from “2” to “4”. Further, in response to the count value of the additional refresh counter 280 becoming “1” or more, the selection signal PSEL is activated to a high level.

Thereafter, in response to activation of the refresh signal IREF at times t41, t42, t43, and t44, the count value of the additional refresh counter 280 is counted down to “3”, “2”, “1”, “0”, The selection signal PSEL returns to the low level. At time t45, the refresh signal IREF is activated, but at this time, the count value of the additional refresh counter 280 has already reached the minimum value (0), so that value does not change.

FIG. 16 is a circuit diagram of the selection signal generation circuit 270.

As shown in FIG. 16, the selection signal generation circuit 270 includes a latch circuit 271 that latches the selection signal PSEL in response to the refresh signal IREF, and the output signal is used as the selection signal PSEL. Therefore, after the selection signal PSEL is activated to a high level, the selection signal SEL changes to a high level in response to the next refresh signal IREF (refresh signal IREF at time t41 shown in FIG. 15). In addition, after the selection signal PSEL is deactivated to the low level, it returns to the low level in response to the next refresh signal IREF (refresh signal IREF at time t45 shown in FIG. 15).

Further, the selection signal SEL and the refresh signal IREF are supplied to the gate circuit G5 shown in FIG. 272 and 273 are selected alternately. Since the selected latch circuits 272 and 273 invert their output signals, the clock signals CLKA and CLKB are alternately activated in response to the refresh signal IREF. This means that if the selection signal SEL is activated to a high level, whenever the refresh signal IREF is activated, the bit A0 is an output signal of the LSB output circuit 240 ₀ is meant to reverse.

As shown in FIG. 14, a reset signal RESET is supplied to a predetermined circuit block constituting the address generation unit 200, and when this is activated, the circuit block is reset to an initial state. For example, all the data held in the memory cell array 210 is reset in response to the reset signal RESET. Such an operation can be performed by outputting an initial value from the address write circuit 230 to the memory cell array 210 in a state where all the word lines RRWL0 to RRWLr are selected by the row decoder 220.

The reset signal RESET is also supplied to the power supply control circuit 290 shown in FIG. The power supply control circuit 290 has the same circuit configuration as the power supply control circuit 170 shown in FIG. 13, and assists the initialization operation of the memory cell array 210 by generating the internal potential VPERIZ (or the ground potential VSSZ). Fulfill. That is, when the reset signal RESET is activated, the internal potential VPERIZ becomes the high impedance HiZ or the ground potential VSS for a predetermined period, and then becomes the same potential as the internal potential VPERI. As a result, the load on the write circuit 230 is greatly reduced, so that the current consumption during the reset operation is reduced and the reset operation can be performed in a very short time.

Next, the operation of the semiconductor device 10 will be described.

FIG. 17 is a timing chart for explaining the operation of the semiconductor device 10.

In the example shown in FIG. 17, an active command ACT is issued from the outside at time t50, and a refresh command REF is issued from outside at times t61, t62, t63, and t64. Although not shown, before the time t50, a number of row accesses are performed by issuing the active command ACT, and the count value corresponding to the row address Addn of the access count unit 100 is counted up to a predetermined value -1. Has been up. As described above, since the least significant bit A0 is degenerated in the row address IADD input to the access count unit 100, the row address Addn is connected to the word line WLn (0) to which the row address Addn (0) is assigned. This is common to both of the word lines WLn (1) to which the row address Addn (1) is assigned. Further, before the time t50, the count value of the additional refresh counter 280 is zero.

In this state, when the row address Addn is input together with the active command ACT at time t50, the detection signal MAX that is the value of the register circuit 140T _{+ 1} shown in FIG. 6 is activated. When the detection signal MAX is activated, the count value of the additional refresh counter 280 shown in FIG. 14 changes from 0 to 2, and the selection signal PSEL becomes high level. Further, since the address write circuit 230 is activated in response to the activation of the detection signal MAX, the row address IADD (Addn) input together with the active command ACT is written into the memory cell array 210. For example, the write counter 250 designates the word line RRWL0 as a write destination of the row address IADD (Addn).

However, at this time, the selection signal SEL is still at the low level, and therefore the selection circuit 42 selects the refresh address RADDa that is the output of the refresh counter 41. In the example shown in FIG. 17, the value of the refresh address RADDa at this time is Addm (0), and therefore the value of the refresh address RADD output from the selection circuit 42 is also Addm (0). Here, Addm (0) means that the value of the upper bits A1 to A13 is m and the value of the least significant bit A0 is 0.

Next, when a refresh command REF is issued from the outside at time t61, the command decode circuit 33 shown in FIG. 1 activates the refresh signal IREF. As described above, since the value of the refresh address RADD at this time is Addm (0), the row decoder 12 accesses the word line WLm indicated by the row address Addm (0). As a result, the information in the memory cells MC connected to the word line WLm (0) is refreshed.

In response to activation of the refresh signal IREF, the count value of the refresh counter 41 is updated to Addm (1), and the word line RRWL0 is designated by the read counter 260. Here, Addm (1) means that the value of the upper bits A1 to A13 is m and the value of the least significant bit A0 is 1. As a result, the address read circuit 240 outputs the refresh address RADDb (Addn) stored in the row address corresponding to the word line RRWL0. At this point, since the clock signal CLKA is activated, the value of the LSB output circuit 240 ₀ is 0, the value of the refresh address RADDb therefore is Addn (0). Here, Addn (0) means that the value of the upper bits A1 to A13 is n and the value of the least significant bit A0 is 0.

Furthermore, since the selection signal SEL changes to a high level in response to the activation of the refresh signal IREF, the selection circuit 42 selects the refresh address RADDb that is the output of the address register 61. Therefore, the value of the refresh address RADD output from the selection circuit 42 is Addn (0). Further, the count value of the additional refresh counter 280 is decremented from 2 to 1.

Further, the count value corresponding to Addm, which is the value of the refresh address RADD, is initialized by the operation described with reference to FIG. The count value corresponding to Addm is a common count value for the word line WLm (0) and the word line WLm (1). Since these word lines differ only in the least significant bit A0 of the row address, the word line WLm ( It is considered that the time from the refresh of 0) to the refresh of the word line WLm (1) is very short. Considering this point, regardless of which of the word lines WLm (0) and WLm (1) is actually refreshed, if one of them is refreshed, the count value corresponding to both is reset.

When the refresh command REF is issued again at time t62, the row decoder 12 accesses the word line WLn (0) indicated by Addn (0) that is the value of the refresh address RADD. That is, the refresh operation is executed in an interrupt manner on the row address Addn (0) output from the address read circuit 240, not on the row address Addm (1) indicated by the refresh counter 41. As a result, the information in the memory cells MC connected to the word line WLn (0) is refreshed. Furthermore, the count value corresponding to Addn which is the value of the refresh address RADD is initialized by the operation described with reference to FIG.

Since the selection signal SEL is at the high level at this time, even if the refresh signal IREF is activated, the count value of the refresh counter 41 is not updated and is maintained as Addm (1). Further, the count value of the additional refresh counter 280 is decremented from 1 to 0. As a result, the selection signal PSEL changes to a low level.

Further, in response to the refresh signal IREF, the selection signal generation circuit 270 activates the clock signal CLKB. Thus, the value of the LSB output circuit 240 ₀ is 1, the value of the refresh address RADDb changes to Addn (1). Here, Addn (1) means that the value of the upper bits A1 to A13 is n and the value of the least significant bit A0 is 1.

When the refresh command REF is further issued at time t63, the row decoder 12 accesses the word line WLn (1) indicated by the row address Addn (1). That is, the refresh operation is executed in an interrupt manner for the row address Addn (1) output from the address read circuit 240, and the information in the memory cell MC is refreshed.

Since the selection signal SEL is at the high level also at this time, the count value of the refresh counter 41 is not updated even when the refresh signal IREF is activated, and is maintained as Addm (1). Further, in response to the activation of the refresh signal IREF, the selection signal SEL changes to a low level. Thus, since the selection circuit 42 selects the refresh address RADDa output from the refresh counter 41, the value of the refresh address RADD output from the selection circuit 42 becomes Addm (1).

When the refresh command REF is issued at time t64, the row decoder 12 accesses the word line WLm (1) indicated by the row address Addm (1). That is, as usual, the refresh operation is performed on the row address indicated by the refresh counter 41. In response to activation of the refresh signal IREF, the count value of the refresh counter 41 is updated to Addm + 1 (0). Furthermore, the count value corresponding to Addm + 1, which is the value of the refresh address RADD, is initialized by the operation described with reference to FIG.

Thus, when the total number of row accesses to the word line WLn (0) and the word line WLn (1) indicated by the row address Addn reaches a predetermined value, the word lines WLn (0) and WLn (1) Thus, an additional refresh operation is performed, and the charge amount of the memory cell MC reduced by the disturb is reproduced. Thereby, it is possible to correctly hold the information stored in each memory cell MC regardless of the access history.

In addition, when an additional refresh operation is performed, the update of the count value of the refresh counter 41 is stopped, so that the normal refresh operation can be correctly executed. However, when the update of the count value of the refresh counter 41 is stopped, the number of times of issuing the refresh command REF necessary for the count value of the refresh counter 41 to go around increases. This means that the refresh cycle is slightly longer than the design value, but as described above, the information retention time of each memory cell MC actually has a sufficient margin for the refresh cycle. Therefore, even when the refresh operation is performed in a cycle slightly longer than the refresh cycle determined by the standard, the information in the memory cell MC is correctly held.

In this embodiment, since the least significant bit A0 of the row address IADD is degenerated, it is adjacent at the interval W1 regardless of which of the word lines WLn (0) and WLn (1) is disturbed. An additional refresh operation is performed on both of these word lines WLn (0) and WLn (1). Therefore, the capacity of the memory cell array 110 included in the access count unit 100 can be reduced by half.

In addition, since the memory cell arrays 110 and 210 are used to count the number of accesses and to hold a row address to be additionally refreshed, compared with the case where a flip-flop circuit or the like is used, It is also possible to reduce the occupied area.

Furthermore, when the reset signal RESET is activated, one inverter INV2 constituting the SRAM cell SC is deactivated, so that the current consumption required for initializing the data in the memory cell arrays 110 and 210 is reduced. In addition, the time required for initialization can be shortened.

FIG. 18 is a circuit diagram of the SRAM cell SC according to the first modification.

In the SRAM cell SC shown in FIG. 18, the ground potential VSSZ is supplied to the lower power supply node of the inverter INV1, while the ground potential VSS is supplied to the lower power supply node of the inverter INV2. The internal potential VPERI is supplied to the higher power supply nodes of the inverters INV1 and INV2.

When the SRAM cell SC having such a configuration is used, the power supply control circuits 170 and 290 shown in FIG. 19 may be used. FIG. 19A shows a third circuit example, and FIG. 19B shows a fourth circuit example.

As shown in FIG. 19A, the power supply control circuits 170 and 290 according to the third circuit example include a selection circuit 174 that uses either the ground potential VSS or the high impedance HiZ as the ground potential VSSZ. The selection operation by the selection circuit 174 is controlled by the output signal RP of the SR latch circuit 175. Specifically, if the output signal RP is high level, the high impedance HiZ is selected, and if the output signal RP is low level, the ground potential VSS is selected. With this configuration, when the reset signal RESET is activated, the ground potential VSSZ becomes the high impedance HiZ for a predetermined period determined by the delay amount of the delay circuit 176, and then becomes the same potential as the ground potential VSS.

The power supply control circuits 170 and 290 according to the fourth circuit example are shown in FIG. 19A except that the internal potential VPERI is used instead of the high impedance HiZ as shown in FIG. 19B. This is the same as the third circuit example. Therefore, when the reset signal RESET is activated, the ground potential VSSZ becomes the same potential as the internal potential VPERI for a predetermined period determined by the delay amount of the delay circuit 176, and then becomes the same potential as the ground potential VSS.

In this modification, the ground potential VSSZ is supplied to the lower power supply node of the inverter INV1 constituting the SRAM cell SC. For this reason, when the reset signal RESET is activated, the inverter INV1 is substantially deactivated, and the ability to drive to the low level becomes almost zero. Thus, if a low level signal is supplied to the bit line RBL (T) and a high level signal is supplied to the bit line RBL (B), the initial value is immediately overwritten on the SRAM cell SC. . This is because the output of the inverter INV2 is fixed at a low level by the inactivation of the inverter INV1, and the output of the inverter INV1 is fixed at an indefinite or high level. Thereby, it becomes possible to obtain the same effect as the above-described embodiment.

FIG. 20 is a circuit diagram of an SRAM cell SC according to the second modification.

In the SRAM cell SC shown in FIG. 20, the internal potential VPERIZ is supplied to the higher power supply node of the inverter INV2 while the internal potential VPERIZ is supplied to the higher power supply node of the inverter INV2. The ground potential VSSZ is supplied to the lower power supply node of the inverter INV1, while the ground potential VSS is supplied to the lower power supply node of the inverter INV2.

In the second modification, when the reset signal RESET is activated, the inverter INV1 is substantially deactivated, the ability to drive to the low level becomes substantially zero, and the inverter INV2 is substantially deactivated, The ability to drive to a high level is almost zero. As a result, the output of the inverter INV1 is fixed at a high level, and the output of the inverter INV2 is fixed at a low level, so that the same effect as that of the above-described embodiment can be obtained more reliably.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2 External substrate 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 15 Read / write amplifier 16 Input / output circuit 21 Command address terminal 22 Reset terminal 23 Clock terminal 24 Data terminal 25, 26 Power supply terminal 31 Command address input circuit 32 Address latch circuit 33 Command decode circuit 34 Clock input circuit 35 Internal clock generation circuit 36 Timing generator 37 Internal power supply generation circuit 38 Calibration circuit 40 Refresh control circuit 41 Refresh counter 42 Selection circuit 100 Access count unit 110 Memory cell array 120 Row decoder 121 Address decoding unit 122 word driver 123 delay circuits 130 and 130 ₀ 130 _T read circuit 140 Counter circuit ₁₄₀ 0 ~ _{140 T + 1} register circuits 150,150 ₀ ~ 150 _T write circuit 160 commands the control circuit 170,290 power supply control circuit 171 and 174 select circuit 172 and 175 SR latch circuits 173,176 delay circuit 200 Address generator 210 Memory cell array 220 Row decoder 230, 230 ₁ to 230 ₁₃ Address write circuit 240, 240 ₁ to 240 ₁₃ Address read circuit 240 ₀ LSB output circuit 250 Write counter 260 Read counter 270 Select signal generator circuit 271 to 273 Latch circuit 280 Additional refresh counter ACT Active command ARa, ARb Active area BL Bit line BLC Bit line contact C Cell capacitor CC Cell capacitor DLY1 to DLY5 Delay elements G, G1 to G5 Logic gate circuit IACT Active signal IADD Address signal INV1, INV2 Inverter IREF Refresh signal MAX Detection signal MC Memory cell PLS1, PLS2 Pulse generation circuit PSEL, SEL selection signal RACT Active signal RADD, RADDa , RADDb Refresh address RBL0 to RBLT Bit line RCNT Count up signal REF Refresh command RESET Reset signal RRBL1 to RRBL13 Bit line RREAD Read signal RRST Reset signal RRWL0 to RRWLr Word line RWL0 to RWL Word line RWRT Write signal SC SRAM cell SR1 to SR3 latch Circuit Tr Cell transistors WL0 to WLp Word line

Claims (10)

At the intersections of the plurality of first word lines, the plurality of first bit lines intersecting the plurality of first word lines, and the plurality of first word lines and the plurality of first bit lines. A first memory cell array including a plurality of arranged first memory cells;
A second memory cell array for storing an access history for the plurality of first word lines;
A reset circuit for erasing the access history stored in the second memory cell array in response to a reset signal;
The second memory cell array includes a plurality of second word lines provided corresponding to one or more of the plurality of first word lines, and a plurality intersecting the plurality of second word lines. A plurality of second memory cells disposed at intersections of the plurality of second word lines and the plurality of second bit lines,
The reset circuit resets the access history by supplying an initial value to the plurality of second bit lines in a state where the plurality of second word lines are activated. . 2. The semiconductor device according to claim 1, wherein the plurality of second memory cells are SRAM cells in which a first inverter and a second inverter are circularly connected. 3. The semiconductor device according to claim 2, wherein the reset circuit deactivates at least one of the first and second inverters in response to the reset signal. The first inverter is operated by a voltage applied between the first and second power supply nodes,
The second inverter is operated by a voltage applied between the third and fourth power supply nodes,
4. The semiconductor device according to claim 3, wherein the reset circuit sets any one of the first to fourth power supply nodes in a high impedance state in response to the reset signal. The first inverter is operated by a first voltage applied between the first and second power supply nodes,
The second inverter is operated by a second voltage applied between the third and fourth power supply nodes,
4. The semiconductor device according to claim 3, wherein the reset circuit lowers at least one of the first and second voltages in response to the reset signal as compared with a normal operation. 6. The semiconductor device according to claim 5, wherein the reset circuit sets at least one of the first and second voltages to zero in response to the reset signal. 2. The memory cell array according to claim 1, further comprising: a third memory cell array that stores an address related to a word line whose number of accesses indicated by the access history exceeds a predetermined value among the plurality of first word lines. The semiconductor device described. The third memory cell array includes a plurality of third word lines, a plurality of third bit lines intersecting with the plurality of third word lines, the plurality of third word lines, and the plurality of third lines. A plurality of third memory cells arranged at intersections with the three bit lines,
The reset circuit supplies the initial value to the plurality of third bit lines in a state where the plurality of third word lines are activated, thereby obtaining the address stored in the third memory cell array. 8. The semiconductor device according to claim 7, wherein the semiconductor device is erased. 8. The semiconductor device according to claim 7, further comprising an address generation unit that accesses any one of the plurality of first word lines indicated by the address stored in the third memory cell array. 10. The semiconductor device according to claim 9, wherein the address generation unit accesses one of the plurality of first word lines indicated by the address in response to a refresh command.

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