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WO2014192437A1 - Silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device Download PDF

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Publication number
WO2014192437A1
WO2014192437A1 PCT/JP2014/060379 JP2014060379W WO2014192437A1 WO 2014192437 A1 WO2014192437 A1 WO 2014192437A1 JP 2014060379 W JP2014060379 W JP 2014060379W WO 2014192437 A1 WO2014192437 A1 WO 2014192437A1
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region
silicon carbide
guard ring
main surface
semiconductor device
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French (fr)
Japanese (ja)
Inventor
増田　健良
和田　圭司
透 日吉
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/0485—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts

Definitions

  • the present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device having a termination region.
  • silicon carbide has been increasingly adopted as a material for semiconductor devices in order to enable the use of high-voltage, low-loss and high-temperature environments in semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is being Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-101039
  • a guard ring layer having a high concentration of impurities is formed inside the RESURF layer, and a guard ring layer having an impurity concentration similar to that of the RESURF layer is formed outside the RESURF layer.
  • a formed high voltage silicon carbide semiconductor device is described. Accordingly, it is said that the breakdown voltage can be prevented from deteriorating even if there is a variation in impurity concentration or a variation in dimensions due to mask displacement.
  • the present invention has been made in view of the above problems, and an object thereof is to provide a silicon carbide semiconductor device capable of reducing variations in breakdown voltage.
  • the silicon carbide semiconductor device includes a silicon carbide layer and an insulating layer.
  • the silicon carbide layer has a first main surface and a second main surface opposite to the first main surface, and surrounds the element region in plan view and an element region provided with a semiconductor element portion And a termination region.
  • the insulating layer is in contact with the first main surface of the silicon carbide layer.
  • the termination region includes a guard ring region having a first conductivity type, and a second conductivity type region located between the first main surface and the guard ring region and having a conductivity type different from the guard ring region. .
  • 1 is a schematic cross-sectional view schematically showing a structure of a silicon carbide semiconductor device according to one embodiment of the present invention.
  • 1 is a schematic plan view schematically showing structures of a guard ring region and a JTE (Junction Termination Extension) region of a silicon carbide semiconductor device according to a first embodiment of the present invention. It is a figure which shows the relationship between the impurity region in a guard ring region, and the position of a Y direction. It is a figure for demonstrating the position of the Y direction in FIG. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention.
  • the guard ring region is formed by introducing an acceptor impurity such as aluminum into the main surface of the silicon carbide layer by ion implantation. It is formed.
  • ion implantation is usually performed by multistage implantation in which the ion implantation depth is changed.
  • the dose amount of the guard ring region varies due to, for example, variations in ion implantation depth.
  • the main surface of the silicon carbide layer is thermally oxidized, the position of the interface between the thermal oxide film (insulating layer) and the silicon carbide layer along the direction perpendicular to the main surface varies due to variations in the amount of thermal oxidation, for example. Therefore, the dose amount in the guard ring region fluctuated, and the breakdown voltage of the silicon carbide semiconductor device varied.
  • the inventors have provided a guard ring region separated from the main surface of the silicon carbide layer, and provided a region of a conductivity type different from the guard ring region between the guard ring region and the silicon carbide layer.
  • the variation in the dose amount of the guard ring region can be reduced.
  • the guard ring region away from the main surface of the silicon carbide layer, even when the ion implantation depth varies somewhat, it is possible to suppress variation in the total dose of the guard ring region.
  • the main surface of the silicon carbide layer is thermally oxidized to form a thermal oxide film, a part of the main surface is oxidized to become a thermal oxide film made of silicon dioxide.
  • the guard ring region When the guard ring region is provided apart from the main surface, it can be suppressed that a part of the guard ring region is oxidized to become a thermal oxide film made of silicon dioxide. Therefore, fluctuations in the total dose amount in the guard ring region can be suppressed. As a result, for example, even when the position of the interface between the thermal oxide film (insulating layer) and the silicon carbide layer along the direction perpendicular to the main surface varies due to the difference in thermal oxidation amount, the dose amount of the guard ring region is reduced. Fluctuation can be suppressed. In other words, by increasing the robustness of the breakdown voltage against the fluctuation of the interface position, it is possible to reduce the variation in breakdown voltage of the silicon carbide semiconductor device.
  • the p-type silicon carbide thermal oxide film tends to be thinner than the adjacent n-type silicon carbide thermal oxide film. Therefore, thermal oxidation is more effective when p-type silicon carbide is formed inside and only n-type silicon carbide is exposed on the main surface than when p-type and n-type silicon carbide are exposed on the main surface. The difference in film thickness is reduced. Thereby, the electric field distribution on the main surface is made uniform, so that the effect of suppressing breakdown due to electric field concentration is great when a high voltage of 600 V or higher (more preferably 1200 V or higher) is applied. This is the same when the p-type and the n-type are inverted.
  • the silicon carbide semiconductor device includes a silicon carbide layer 10 and an insulating layer 15.
  • Silicon carbide layer 10 has a first main surface 10a, a second main surface 10b opposite to first main surface 10a, and an element region IR provided with semiconductor element portion 7 and a plane.
  • the terminal region OR that surrounds the element region in view.
  • Insulating layer 15 is in contact with first main surface 10a of silicon carbide layer 10.
  • Termination region OR is guard ring region 3 having the first conductivity type, and second conductivity having a conductivity type that is located between first main surface 10a and guard ring region 3 and that is different from guard ring region 3. And a mold region 12c.
  • termination region OR is positioned between guard ring region 3 having the first conductivity type, first main surface 10a and guard ring region 3, and guard region OR.
  • Ring region 3 includes a second conductivity type region 12c having a different conductivity type.
  • the dose amount of second conductivity type region 12 c is smaller than the dose amount of guard ring region 3.
  • the dose amount of the second conductivity type region 12c is a donor dose amount
  • the dose amount of the guard ring region 3 is an acceptor dose amount.
  • the second conductivity type region 12c has a p-type conductivity type
  • the dose amount of the second conductivity type region 12c is the dose amount of the acceptor
  • the dose amount of the guard ring region 3 is the dose amount of the donor.
  • the second conductivity type region 12c can be sufficiently depleted. Therefore, it is possible to prevent the high electric field from being concentrated on the semiconductor element portion and the semiconductor element portion from being destroyed.
  • the distance from the peak position of the impurity concentration of guard ring region 3 along the normal direction of first main surface 10a to first main surface 10a. Is 0.1 ⁇ m or more and 1.0 ⁇ m or less. If the distance is 0.1 ⁇ m or more, since the distance is larger than the thickness of the insulating layer 15, a part of the guard ring region 3 is oxidized and becomes the insulating layer 15 due to variations in the thickness of the insulating layer 15. Can be suppressed. Therefore, fluctuations in the dose amount of the guard ring region 3 can be suppressed. If the distance is 1.0 ⁇ m or less, the guard ring region 3 can be efficiently formed by ion implantation.
  • the dose amount of guard ring region 3 is preferably 1 ⁇ 10 13 cm ⁇ 2 or more. Thereby, the breakdown voltage of the silicon carbide semiconductor device can be improved.
  • the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. Thereby, the dispersion
  • the first conductivity type is a p-type and the second conductivity type region is an n-type region.
  • MOSFET 1 as a silicon carbide semiconductor device according to an embodiment of the present invention.
  • MOSFET 1 includes a silicon carbide layer 10, an insulating layer 15, a gate electrode 27, a source electrode 16, a drain electrode 20, an interlayer insulating film 71, and a pad electrode. 65 and the back surface protective electrode 50 are mainly included.
  • silicon carbide layer 10 of MOSFET 1 includes an element region IR (active region) and a termination region OR (invalid region) provided outside element region IR.
  • Termination region OR includes a guard ring region 3 and a JTE region 2 as electric field relaxation regions.
  • a MOSFET part as the semiconductor element part 7 is provided in the element region IR.
  • the semiconductor element portion 7 includes a drift region 12a having an n type (second conductivity type).
  • Silicon carbide layer 10 is made of, for example, polytype 4H hexagonal silicon carbide, and has a first main surface 10a and a second main surface 10b opposite to first main surface 10a.
  • the termination region OR surrounds the element region IR in a plan view (a visual field viewed from the normal direction of the first main surface 10a).
  • the JTE region 2 is disposed so as to surround the element region IR in plan view.
  • the guard ring region 3 is disposed outside the JTE region 2 in plan view and is disposed so as to surround the JTE region 2.
  • the guard ring region 3 is provided apart from the JTE region 2.
  • the guard ring region 3 may have a plurality of guard ring portions 3a to 3i. Each of the plurality of guard ring portions 3a to 3i has an annular shape and is disposed with a gap therebetween.
  • the width W1 of the JTE region 2 is, for example, 15 ⁇ m, and the widths W2 to W10 of the nine guard ring portions 3a to 3i are, for example, 5 ⁇ m.
  • An interval d1 between the JTE region 2 and the guard ring region 3 is, for example, about 3 ⁇ m to about 5 ⁇ m, and an interval d2 between the adjacent guard ring portions 3a to 3i is, for example, about 3 ⁇ m to about 5 ⁇ m.
  • Termination region OR may have an n-type field stop region (not shown) on the outer peripheral side of guard ring region 3.
  • Each of JTE region 2 and guard ring region 3 has a p-type (first conductivity type).
  • the impurity concentration contained in each of JTE region 2 and guard ring region 3 is lower than the impurity concentration of body region 13.
  • Each dose amount of JTE region 2 and guard ring region 3 is, for example, 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the width W1 of the JTE region 2 is, for example, about 15 ⁇ m to 55 ⁇ m, and the dimension of the JTE region 2 along the normal direction of the first main surface 10a is, for example, about 0.5 ⁇ m to 0.8 ⁇ m.
  • the guard ring region 3 may be grounded.
  • guard ring region 3 is provided apart from first main surface 10 a of silicon carbide layer 10.
  • An n-type region 12c having an n-type is arranged between first main surface 10a and guard ring region 3.
  • An n-type region 12c is arranged on the first main surface 10a side of the guard ring region 3, and an n-type region 12a is arranged on the second main surface 10b side.
  • the guard ring region 3 is provided between the n-type region 12c and the n-type region 12a along the normal direction of the first main surface 10a, and in a direction parallel to the first main surface 10a.
  • the impurity concentration of each of n-type region 12c and n-type region 12a is, for example, about 7.5 ⁇ 10 15 cm ⁇ 3 .
  • each of the plurality of guard ring portions 3a to 3i is provided apart from the first main surface 10a, and between the first main surface 10a and each of the guard ring portions 3a to 3i.
  • N-type region 12c is arranged.
  • the dose amount of the n-type region 12c is smaller than the dose amount of the guard ring region 3.
  • the guard ring region 3 has a plurality of guard ring portions 3a to 3i, the dose amount of the n-type region 12c facing each of the guard ring portions 3a to 3i of the guard ring region 3 is equal to that of the guard ring portions 3a to 3i. Less than each dose.
  • the dose amount of guard ring region 3 is determined so that n type region 12c sandwiched between guard ring region 3 and first main surface 10a can be depleted.
  • the dose amount of the guard ring region 3 is, for example, about 1 ⁇ 10 13 cm ⁇ 2 .
  • the dose amount of n-type region 12c is, for example, about 1 ⁇ 10 11 cm ⁇ 2 or more and 1 ⁇ 10 12 cm ⁇ 2 or less.
  • the Y direction is a normal direction of first main surface 10 a of silicon carbide layer 10.
  • the first main surface 10a is defined as position 0, and the direction from the first main surface 10a to the second main surface 10b is positive.
  • the impurity concentration in FIG. 3 indicates an acceptor concentration when the guard ring region 3 has a p-type, and indicates a donor concentration when the guard ring region 3 has an n-type.
  • the dose amount corresponds to the amount obtained by integrating the impurity concentration at the position in the Y direction (that is, the area of the region indicated by the oblique lines in FIG. 3).
  • the dose amount of the guard ring region 3 is 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the dose amount of each of the plurality of guard ring portions 3a to 3i is 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15.
  • the fixed charges at the interface include ions that are present from the beginning and those in which holes or electrons are trapped at the interface state.
  • the fixed charge is generated by, for example, nitrogen or hydrogen introduced into the insulating layer 15.
  • the interface state density is, for example, about 1 ⁇ 10 11 cm ⁇ 2 .
  • the implantation dose amount in the guard ring region 3 is 100 times or more the interface state density.
  • the fixed charge density is, for example, about 1 ⁇ 10 12 cm ⁇ 2 .
  • the fixed charge density can be measured by, for example, a high-frequency CV (Capacitance-Voltage) method.
  • the concentration of impurities contained in the guard ring region increases as the distance from the first main surface 10a increases, and the impurity concentration peaks between position P1 and position P2.
  • the impurity concentration decreases.
  • the distance from the first main surface 10a to the position P1 where the impurity concentration becomes the first peak is, for example, 0.1 ⁇ m
  • the distance from the first main surface 10a to the position P2 where the impurity concentration becomes the last peak is, for example, 1.0 ⁇ m.
  • the distance from the position in the Y direction showing the peak of the impurity concentration to the first main surface 10a is preferably about 0.1 ⁇ m or more and 1.0 ⁇ m or less.
  • semiconductor element portion 7 in element region IR of silicon carbide layer 10 mainly includes n + substrate 11, drift region 12 a, body region 13, source region 14, and p + region 18. Have.
  • N + substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide and has a conductivity type of n type.
  • N + substrate 11 contains an impurity (donor) such as N (nitrogen) at a high concentration.
  • the concentration of impurities such as nitrogen contained in the n + substrate 11 is, for example, about 1.0 ⁇ 10 18 cm ⁇ 3 .
  • Drift region 12a is an epitaxial layer made of, for example, polytype 4H hexagonal silicon carbide and having n-type.
  • the impurity contained in drift region 12a is, for example, nitrogen.
  • the impurity concentration in drift region 12 a is lower than the impurity concentration in n + substrate 11.
  • the concentration of impurities such as nitrogen contained in drift region 12a is, for example, about 7.5 ⁇ 10 15 cm ⁇ 3 .
  • the thickness T of the drift region 12a is not less than about 10 ⁇ m and not more than about 35 ⁇ m.
  • the body region 13 is a region having a p-type different from the n-type.
  • Impurities (acceptors) contained in body region 13 are, for example, Al (aluminum), B (boron), and the like.
  • the concentration of impurities such as aluminum contained in the surface of body region 13 is about 1 ⁇ 10 16 cm ⁇ 3 or more and about 5 ⁇ 10 17 cm ⁇ 3 or less.
  • the impurity concentration in the deep part of the body region 13 is about 1 ⁇ 10 18 cm ⁇ 3 .
  • the thickness of body region 13 is not less than about 0.5 ⁇ m and not more than about 1.0 ⁇ m, for example.
  • the body region 13 and the JTE region 2 are in contact with each other at the boundary line 2a between the element region IR and the termination region OR.
  • the source region 14 is an n-type region. Source region 14 is separated by body region 13 and from drift region 12a.
  • the source region 14 includes the first main surface 10 a and is formed inside the body region 13 so as to be surrounded by the body region 13.
  • Source region 14 contains, for example, an impurity such as P (phosphorus) at a concentration of about 1 ⁇ 10 20 cm ⁇ 3 .
  • the concentration of the impurity contained in the source region 14 is higher than the concentration of the impurity contained in the drift region 12a.
  • the p + region 18 is a region having a p-type. P + region 18 is formed in contact with body region 13 and source region 14.
  • the p + region 18 contains impurities such as aluminum and boron at a concentration of about 1 ⁇ 10 20 cm ⁇ 3 , for example.
  • the concentration of impurities contained in p + region 18 is higher than the concentration of impurities contained in body region 13.
  • insulating layer 15 is exposed at gate insulating film portion 15 a provided at a position facing channel region CH formed in body region 13, end portion 10 c of silicon carbide layer 10, and JTE And an insulating film portion 15b in contact with the region 2.
  • Gate insulating film portion 15 a is formed in contact with body region 13, source region 14, and drift region 12 a so as to extend from the upper surface of one source region 14 to the upper surface of the other source region 14. .
  • Insulating layer 15 is made of, for example, silicon dioxide.
  • the thickness of the insulating layer 15 (the dimension of the insulating layer 15 along the normal direction of the first main surface 10a) is, for example, about 50 nm.
  • Gate electrode 27 faces drift region 12a, source region, and body region 13 so as to extend from one source region 14 to the other source region 14, and is in contact with gate insulating film portion 15a. Has been placed.
  • the gate electrode 27 is made of a conductor such as polysilicon doped with impurities, aluminum, or the like.
  • Source electrode 16 is in contact with gate insulating film portion 15 a, source region 14, and p + region 18.
  • the source electrode 16 is preferably made of a material having nickel and silicon.
  • the source electrode 16 may be made of a material having titanium, aluminum, and silicon.
  • source electrode 16 is in ohmic contact with source region 14 and p + region 18.
  • Drain electrode 20 is formed in contact with second main surface 10b of silicon carbide layer 10.
  • the drain electrode 20 may have a configuration similar to that of the source electrode 16, for example, or may be made of another material capable of ohmic contact with the n + substrate 11 such as nickel. Thereby, the drain electrode 20 is electrically connected to the n + substrate 11.
  • the pad electrode 65 is formed so as to be in contact with the source electrode 16 and cover the interlayer insulating film 71.
  • the pad electrode 65 is made of aluminum, for example.
  • protective film 70 is formed in contact with pad electrode 65 and insulating film portion 15b.
  • drain electrode 20 is arranged in contact with second main surface 10b of silicon carbide layer 10.
  • a back surface protective electrode 50 made of, for example, titanium, nickel, silver or an alloy thereof is disposed in contact with the drain electrode 20.
  • MOSFET 1 In a state where a voltage equal to or lower than the threshold value is applied to the gate electrode 27, that is, in an off state, the body region 13 located immediately below the gate insulating film portion 15a and the drift region 12a are reverse-biased and become non-conductive.
  • a positive voltage is applied to the gate electrode 27, an inversion layer is formed in the channel region CH in the vicinity of the body region 13 in contact with the gate insulating film portion 15a.
  • the source region 14 and the drift region 12 a are electrically connected, and a current flows between the source electrode 16 and the drain electrode 20.
  • silicon carbide layer 10 is prepared by a substrate preparation process. Specifically, n-type region 12 is formed by epitaxial growth on one main surface of n + substrate 11 made of hexagonal silicon carbide having polytype 4H. Epitaxial growth can be carried out, for example, using a mixed gas of SiH 4 (silane) and C 3 H 8 (propane) as a raw material gas. At this time, for example, N (nitrogen) is introduced as an impurity. As a result, an n-type region 12 containing impurities having a lower concentration than the impurities contained in the n + substrate 11 is formed. Thus, silicon carbide layer 10 including n + substrate 11 and n-type region 12 and having first main surface 10a and second main surface 10b is formed.
  • an oxide film made of silicon dioxide is formed on first main surface 10a of silicon carbide layer 10 by, for example, CVD. Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of the desired body region 13 is formed. Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching) to form an oxide film having an opening pattern on the n-type region 12. A mask layer is formed.
  • RIE reactive Ion Etching
  • an ion implantation process is performed.
  • ions are implanted into first main surface 10 a of silicon carbide layer 10, so that body region 13, source region 14, and element region IR are formed in silicon carbide layer 10.
  • P + region 18 is formed, and JTE region 2 and guard ring region 3 as an electric field relaxation region are formed in termination region OR of silicon carbide layer 10.
  • the guard ring region 3 has a plurality of guard ring portions 3a to 3i, and each of the plurality of guard ring portions 3a to 3i is formed so as to be separated from the first main surface 10a.
  • the body region 13 is formed by removing the resist film and ion-implanting impurities such as Al into the n-type region 12 using the mask layer as a mask. Further, an n-type impurity such as P (phosphorus) is introduced into the n-type region 12 by ion implantation, whereby the source region 14 is formed. Next, impurities such as Al and B are introduced into the n-type region 12 by ion implantation, whereby the p + region 18 is formed. Ion implantation may be performed by heating silicon carbide layer 10 to 300 ° C. to 500 ° C.
  • the JTE region 2 and the guard ring region 3 are formed.
  • the guard ring region 3 may be formed deeper than the JTE region 2.
  • JTE region 2 is formed in contact with body region 13.
  • the implantation dose amount of the guard ring region 3 is 1 ⁇ 10 13 cm ⁇ 2 or more.
  • the guard ring region 3 has a distance from the peak position of the impurity concentration of the guard ring region 3 along the normal direction of the first main surface 10a to the first main surface 10a of 0.1 ⁇ m or more. It is formed to be 0 ⁇ m or less.
  • an activation annealing step is performed.
  • a heat treatment for activating the impurities introduced by the ion implantation is performed. Specifically, silicon carbide layer 10 subjected to ion implantation is heated to, for example, about 1700 ° C. in an Ar (argon) atmosphere and held for about 30 minutes.
  • Ar argon
  • first main surface 10a of silicon carbide layer 10 in which the ion implantation region is formed is thermally oxidized.
  • Thermal oxidation can be carried out, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes.
  • insulating layer 15 made of silicon dioxide is formed in contact with first main surface 10a of silicon carbide layer 10.
  • Silicon carbide layer 10 on which insulating layer 15 is formed may be heated from 1100 ° C. to 1300 ° C. in an atmosphere containing nitrogen, NO, or N 2 O.
  • gate electrode 27 made of, for example, polysilicon or aluminum as a conductor extends from one source region 14 to the other source region 14 and is insulated. It is formed in contact with the layer 15.
  • the polysilicon may contain phosphorus at a high concentration exceeding 1 ⁇ 10 20 cm ⁇ 3 .
  • an interlayer insulating film 71 made of, for example, silicon dioxide is formed so as to cover gate electrode 27.
  • source electrode 16 made of a material containing, for example, nickel and silicon is formed in contact with source region 14 and p + region 18.
  • the source electrode 16 may be a material containing titanium, aluminum, and silicon.
  • silicon carbide layer 10 on which source electrode 16 is formed is heated to about 1000 ° C., source electrode 16 is silicided, and source electrode 16 in ohmic contact with source region 14 and p + region 18 of silicon carbide layer 10 is formed. It is formed.
  • drain electrode 20 is formed in ohmic contact with second main surface 10b of silicon carbide layer 10.
  • the material forming the drain electrode 20 may be a material containing nickel and silicon, or may be a material containing titanium, aluminum and silicon.
  • a pad electrode 65 made of, for example, aluminum is formed in contact with the source electrode 16.
  • the back surface protective electrode 50 containing, for example, titanium, nickel, and silver is formed. As described above, MOSFET 1 shown in FIGS. 1 and 8 is completed.
  • the MOSFET is described as an example of the silicon carbide semiconductor device.
  • the silicon carbide semiconductor device may be a diode such as a Schottky barrier diode, or an IGBT (Insulated Gate Bipolar). (Transistor) or the like.
  • the MOSFET may be a planar type MOSFET or a trench type MOSFET.
  • the silicon carbide semiconductor device may be a vertical semiconductor device.
  • the first conductivity type is p-type and the second conductivity type is n-type.
  • the first conductivity type is n-type and the second conductivity type is p-type. It may be a mold.
  • termination region OR is located between guard ring region 3 having the first conductivity type, first main surface 10a and guard ring region 3, and guard ring region. 3 includes an n-type region 12c having a different conductivity type. Thereby, the dispersion
  • the dose amount of n-type region 12 c is smaller than the dose amount of guard ring region 3.
  • the second conductivity type region 12c can be sufficiently depleted. Therefore, it is possible to suppress the high electric field from being concentrated on the semiconductor element portion and the semiconductor element portion from being destroyed.
  • the distance from the peak position of the impurity concentration of guard ring region 3 along the normal direction of first main surface 10a to first main surface 10a is 0.1 ⁇ m. It is 1.0 ⁇ m or less. If the distance is 0.1 ⁇ m or more, since the distance is larger than the thickness of the insulating layer 15, a part of the guard ring region 3 is oxidized and becomes the insulating layer 15 due to variations in the thickness of the insulating layer 15. Can be suppressed. Therefore, fluctuations in the dose amount of the guard ring region 3 can be suppressed. If the distance is 1.0 ⁇ m or less, the guard ring region 3 can be efficiently formed by ion implantation.
  • the dose amount of guard ring region 3 is 1 ⁇ 10 13 cm ⁇ 2 or more. Therefore, the breakdown voltage of MOSFET 1 can be improved.
  • the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. Thereby, the dispersion
  • the first conductivity type is p-type
  • the second conductivity type region is an n-type region.
  • SYMBOLS 1 MOSFET silicon carbide semiconductor device

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Abstract

A silicon carbide semiconductor device (1) is provided with a silicon carbide layer (10) and an insulating layer (15). The silicon carbide layer (10) has a first main surface (10a) and a second main surface (10b) on the opposite side of the first main surface (10a), and is composed of an element region (IR) provided with a semiconductor element section (7), and a termination region (OR) that surrounds the element region (IR) in a plan view. The insulating layer (15) is in contact with the first main surface (10a) of the silicon carbide layer (10). The termination region (OR) includes a guard ring region (3) having a first conductivity type, and a second conductivity type region (12c) that is positioned between the first main surface (10a) and the guard ring region (3), and has a different conductivity type than that of the guard ring region (3). Thus, a silicon carbide semiconductor device (1) capable of reducing variations in a breakdown voltage can be provided.

Description

炭化珪素半導体装置Silicon carbide semiconductor device

　本発明は、炭化珪素半導体装置に関するものであり、より特定的には、終端領域を有する炭化珪素半導体装置に関するものである。 The present invention relates to a silicon carbide semiconductor device, and more particularly to a silicon carbide semiconductor device having a termination region.

　近年、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）などの半導体装置の高耐圧化、低損失化、高温環境下での使用などを可能とするため、半導体装置を構成する材料として炭化珪素の採用が進められつつある。炭化珪素は、従来から半導体装置を構成する材料として広く使用されている珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体である。そのため、半導体装置を構成する材料として炭化珪素を採用することにより、半導体装置の高耐圧化、オン抵抗の低減などを達成することができる。また、炭化珪素を材料として採用した半導体装置は、珪素を材料として採用した半導体装置に比べて、高温環境下で使用された場合の特性の低下が小さいという利点も有している。 In recent years, silicon carbide has been increasingly adopted as a material for semiconductor devices in order to enable the use of high-voltage, low-loss and high-temperature environments in semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). It is being Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

　たとえば特開２００３－１０１０３９号公報（特許文献１）には、リサーフ層の内側に高濃度不純物のガードリング層が形成され、リサーフ層の外側にリサーフ層と同程度の不純物濃度のガードリング層が形成された高耐圧炭化珪素半導体装置が記載されている。これにより、不純物濃度のばらつきやマスクずれなどによる寸法のばらつきがあっても、耐圧の劣化を防ぐことができるとされている。 For example, in Japanese Patent Application Laid-Open No. 2003-101039 (Patent Document 1), a guard ring layer having a high concentration of impurities is formed inside the RESURF layer, and a guard ring layer having an impurity concentration similar to that of the RESURF layer is formed outside the RESURF layer. A formed high voltage silicon carbide semiconductor device is described. Accordingly, it is said that the breakdown voltage can be prevented from deteriorating even if there is a variation in impurity concentration or a variation in dimensions due to mask displacement.

特開２００３－１０１０３９号公報JP 2003-101039 A

　しかしながら、特開２００３－１０１０３９号公報に記載の炭化珪素半導体装置は、耐圧のばらつきが十分に低いとはいえなかった。 However, the silicon carbide semiconductor device described in Japanese Patent Laid-Open No. 2003-101039 cannot be said to have a sufficiently low variation in breakdown voltage.

　本発明は、上記課題に鑑みてなされたものであり、その目的は、耐圧のばらつきを低減可能な炭化珪素半導体装置を提供することである。 The present invention has been made in view of the above problems, and an object thereof is to provide a silicon carbide semiconductor device capable of reducing variations in breakdown voltage.

　本発明に係る炭化珪素半導体装置は、炭化珪素層と、絶縁層とを備えている。炭化珪素層は、第１の主面と、第１の主面と反対側の第２の主面とを有し、かつ半導体素子部が設けられた素子領域と、平面視において素子領域を取り囲む終端領域とにより構成されている。絶縁層は、炭化珪素層の第１の主面に接する。終端領域は、第１導電型を有するガードリング領域と、第１の主面とガードリング領域との間に位置し、かつガードリング領域とは異なる導電型を有する第２導電型領域とを含む。 The silicon carbide semiconductor device according to the present invention includes a silicon carbide layer and an insulating layer. The silicon carbide layer has a first main surface and a second main surface opposite to the first main surface, and surrounds the element region in plan view and an element region provided with a semiconductor element portion And a termination region. The insulating layer is in contact with the first main surface of the silicon carbide layer. The termination region includes a guard ring region having a first conductivity type, and a second conductivity type region located between the first main surface and the guard ring region and having a conductivity type different from the guard ring region. .

　本発明によれば、耐圧のばらつきを低減可能な炭化珪素半導体装置を提供することができる。 According to the present invention, it is possible to provide a silicon carbide semiconductor device capable of reducing variations in breakdown voltage.

本発明の一実施の形態１に係る炭化珪素半導体装置の構造を概略的に示す断面模式図である。1 is a schematic cross-sectional view schematically showing a structure of a silicon carbide semiconductor device according to one embodiment of the present invention. 本発明の一実施の形態１に係る炭化珪素半導体装置のガードリング領域およびＪＴＥ（Ｊｕｎｃｔｉｏｎ　Ｔｅｒｍｉｎａｔｉｏｎ　Ｅｘｔｅｎｓｉｏｎ）領域の構造を概略的に示す平面模式図である。1 is a schematic plan view schematically showing structures of a guard ring region and a JTE (Junction Termination Extension) region of a silicon carbide semiconductor device according to a first embodiment of the present invention. ガードリング領域における不純物領域とＹ方向の位置との関係を示す図である。It is a figure which shows the relationship between the impurity region in a guard ring region, and the position of a Y direction. 図３におけるＹ方向の位置を説明するための図である。It is a figure for demonstrating the position of the Y direction in FIG. 本発明の一実施の形態に係る炭化珪素半導体装置の製造方法の第１の工程を概略的に示す断面模式図である。It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る炭化珪素半導体装置の製造方法の第２の工程を概略的に示す断面模式図である。It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る炭化珪素半導体装置の製造方法の第３の工程を概略的に示す断面模式図である。It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る炭化珪素半導体装置の半導体素子部の構造を概略的に示す断面模式図である。It is a cross-sectional schematic diagram which shows schematically the structure of the semiconductor element part of the silicon carbide semiconductor device which concerns on one embodiment of this invention.

　以下、図面に基づいて本発明の実施の形態を説明する。なお、以下の図面において同一または相当する部分には同一の参照番号を付し、その説明は繰返さない。また、本明細書中の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示している。また、負の指数については、結晶学上、”－”（バー）を数字の上に付けることになっているが、本明細書中では、数字の前に負の符号を付けている。また角度の記載には、全方位角を３６０度とする系を用いている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is added on the number in crystallography, but in the present specification, a negative sign is attached before the number. The angle is described using a system in which the omnidirectional angle is 360 degrees.

　はじめに、本発明の実施の形態の概要について説明する。
　発明者らは、炭化珪素半導体装置の耐圧がばらつく原因について鋭意研究の結果、以下の知見を得て本発明を見出した。ガードリング領域が炭化珪素層の主面に接する構造を有する炭化珪素半導体装置の場合、たとえばアルミニウムなどのアクセプタ不純物が炭化珪素層の主面に対してイオン注入によって導入されることによりガードリング領域が形成される。またイオン注入は、通常、イオン注入深さを変化させた多段注入により行われる。ガードリング領域を一方の主面近くに形成する場合、たとえばイオン注入深さの変動によりガードリング領域のドーズ量が変動する。また炭化珪素層の主面を熱酸化する場合、たとえば熱酸化量のばらつきにより、主面と垂直な方向に沿った熱酸化膜（絶縁層）と炭化珪素層との界面の位置が変動する。そのため、ガードリング領域におけるドーズ量が変動し、炭化珪素半導体装置の耐圧がばらついていた。 First, an outline of an embodiment of the present invention will be described.
As a result of intensive studies on the cause of variations in the breakdown voltage of silicon carbide semiconductor devices, the inventors have obtained the following knowledge and found the present invention. In the case of a silicon carbide semiconductor device having a structure in which the guard ring region is in contact with the main surface of the silicon carbide layer, the guard ring region is formed by introducing an acceptor impurity such as aluminum into the main surface of the silicon carbide layer by ion implantation. It is formed. In addition, ion implantation is usually performed by multistage implantation in which the ion implantation depth is changed. When the guard ring region is formed near one main surface, the dose amount of the guard ring region varies due to, for example, variations in ion implantation depth. When the main surface of the silicon carbide layer is thermally oxidized, the position of the interface between the thermal oxide film (insulating layer) and the silicon carbide layer along the direction perpendicular to the main surface varies due to variations in the amount of thermal oxidation, for example. Therefore, the dose amount in the guard ring region fluctuated, and the breakdown voltage of the silicon carbide semiconductor device varied.

　発明者らは、鋭意研究の結果、ガードリング領域を炭化珪素層の主面から離間して設け、ガードリング領域と炭化珪素層との間に、ガードリング領域とは異なる導電型の領域を設けることにより、ガードリング領域のドーズ量の変動を低減することができることを見出した。ガードリング領域を炭化珪素層の主面から離間して設けることにより、イオン注入深さが多少変動した場合においても、ガードリング領域のトータルのドーズ量が変動することを抑制することができる。また炭化珪素層の主面が熱酸化されて熱酸化膜が形成される場合、主面の一部が酸化されて二酸化珪素からなる熱酸化膜となる。ガードリング領域が主面から離間して設けられている場合、ガードリング領域の一部が酸化されて二酸化珪素からなる熱酸化膜となることを抑制することができる。それゆえ、ガードリング領域におけるトータルのドーズ量が変動することを抑制することができる。結果として、たとえば熱酸化量の違いにより、主面と垂直な方向に沿った熱酸化膜（絶縁層）と炭化珪素層との界面の位置が変動する場合においても、ガードリング領域のドーズ量が変動することを抑制することができる。つまり、界面の位置の変動に対する耐圧の堅牢性を高めることにより、炭化珪素半導体装置の耐圧のばらつきを低減することができる。 As a result of intensive studies, the inventors have provided a guard ring region separated from the main surface of the silicon carbide layer, and provided a region of a conductivity type different from the guard ring region between the guard ring region and the silicon carbide layer. Thus, it has been found that the variation in the dose amount of the guard ring region can be reduced. By providing the guard ring region away from the main surface of the silicon carbide layer, even when the ion implantation depth varies somewhat, it is possible to suppress variation in the total dose of the guard ring region. When the main surface of the silicon carbide layer is thermally oxidized to form a thermal oxide film, a part of the main surface is oxidized to become a thermal oxide film made of silicon dioxide. When the guard ring region is provided apart from the main surface, it can be suppressed that a part of the guard ring region is oxidized to become a thermal oxide film made of silicon dioxide. Therefore, fluctuations in the total dose amount in the guard ring region can be suppressed. As a result, for example, even when the position of the interface between the thermal oxide film (insulating layer) and the silicon carbide layer along the direction perpendicular to the main surface varies due to the difference in thermal oxidation amount, the dose amount of the guard ring region is reduced. Fluctuation can be suppressed. In other words, by increasing the robustness of the breakdown voltage against the fluctuation of the interface position, it is possible to reduce the variation in breakdown voltage of the silicon carbide semiconductor device.

　さらにガードリングにｐ型を用いる場合、ｐ型の炭化珪素の熱酸化膜は、隣接するｎ型の炭化珪素の熱酸化膜に比べて薄くなる傾向がある。したがって、主面にｐ型とｎ型の炭化珪素が露出する場合より、ｐ型の炭化珪素が内部に形成され主面にｎ型の炭化珪素のみが露出している場合の方が、熱酸化膜厚の差が小さくなる。これにより、主面の電界分布が均一化されるので、６００Ｖ以上（より好ましくは１２００Ｖ以上）の高電圧印加時において、電界集中による破壊を抑制する効果は大きい。これはｐ型とｎ型とが反転した場合も同じである。 Further, when p-type is used for the guard ring, the p-type silicon carbide thermal oxide film tends to be thinner than the adjacent n-type silicon carbide thermal oxide film. Therefore, thermal oxidation is more effective when p-type silicon carbide is formed inside and only n-type silicon carbide is exposed on the main surface than when p-type and n-type silicon carbide are exposed on the main surface. The difference in film thickness is reduced. Thereby, the electric field distribution on the main surface is made uniform, so that the effect of suppressing breakdown due to electric field concentration is great when a high voltage of 600 V or higher (more preferably 1200 V or higher) is applied. This is the same when the p-type and the n-type are inverted.

　（１）実施の形態に係る炭化珪素半導体装置は、炭化珪素層１０と、絶縁層１５とを備えている。炭化珪素層１０は、第１の主面１０ａと、第１の主面１０ａと反対側の第２の主面１０ｂとを有し、かつ半導体素子部７が設けられた素子領域ＩＲと、平面視において素子領域を取り囲む終端領域ＯＲとにより構成されている。絶縁層１５は、炭化珪素層１０の第１の主面１０ａに接する。終端領域ＯＲは、第１導電型を有するガードリング領域３と、第１の主面１０ａとガードリング領域３との間に位置し、かつガードリング領域３とは異なる導電型を有する第２導電型領域１２ｃとを含む。 (1) The silicon carbide semiconductor device according to the embodiment includes a silicon carbide layer 10 and an insulating layer 15. Silicon carbide layer 10 has a first main surface 10a, a second main surface 10b opposite to first main surface 10a, and an element region IR provided with semiconductor element portion 7 and a plane. The terminal region OR that surrounds the element region in view. Insulating layer 15 is in contact with first main surface 10a of silicon carbide layer 10. Termination region OR is guard ring region 3 having the first conductivity type, and second conductivity having a conductivity type that is located between first main surface 10a and guard ring region 3 and that is different from guard ring region 3. And a mold region 12c.

　実施の形態に係る炭化珪素半導体装置によれば、終端領域ＯＲは、第１導電型を有するガードリング領域３と、第１の主面１０ａとガードリング領域３との間に位置し、かつガードリング領域３とは異なる導電型を有する第２導電型領域１２ｃとを含む。これにより、炭化珪素半導体装置の耐圧のばらつきを低減することができる。 According to the silicon carbide semiconductor device according to the embodiment, termination region OR is positioned between guard ring region 3 having the first conductivity type, first main surface 10a and guard ring region 3, and guard region OR. Ring region 3 includes a second conductivity type region 12c having a different conductivity type. Thereby, the dispersion | variation in the proof pressure of a silicon carbide semiconductor device can be reduced.

　（２）上記実施の形態に係る炭化珪素半導体装置において好ましくは、第２導電型領域１２ｃのドーズ量は、ガードリング領域３のドーズ量よりも少ない。第２導電型領域１２ｃがｎ型の導電型を有する場合、第２導電型領域１２ｃのドーズ量はドナーのドーズ量であり、ガードリング領域３のドーズ量はアクセプタのドーズ量である。一方、第２導電型領域１２ｃがｐ型の導電型を有する場合、第２導電型領域１２ｃのドーズ量はアクセプタのドーズ量であり、ガードリング領域３のドーズ量はドナーのドーズ量である。これにより、第２導電型領域１２ｃを十分に空乏化することができる。それゆえ、高電界が半導体素子部に集中して、半導体素子部が破壊されることを抑制することができる。 (2) Preferably, in the silicon carbide semiconductor device according to the above-described embodiment, the dose amount of second conductivity type region 12 c is smaller than the dose amount of guard ring region 3. When the second conductivity type region 12c has an n-type conductivity type, the dose amount of the second conductivity type region 12c is a donor dose amount, and the dose amount of the guard ring region 3 is an acceptor dose amount. On the other hand, when the second conductivity type region 12c has a p-type conductivity type, the dose amount of the second conductivity type region 12c is the dose amount of the acceptor, and the dose amount of the guard ring region 3 is the dose amount of the donor. Thereby, the second conductivity type region 12c can be sufficiently depleted. Therefore, it is possible to prevent the high electric field from being concentrated on the semiconductor element portion and the semiconductor element portion from being destroyed.

　（３）上記実施の形態に係る炭化珪素半導体装置において好ましくは、第１の主面１０ａの法線方向に沿ったガードリング領域３の不純物濃度のピーク位置から第１の主面１０ａまでの距離は、０．１μｍ以上１．０μｍ以下である。当該距離が０．１μｍ以上であれば、当該距離が絶縁層１５の厚みよりも大きいため、絶縁層１５の厚みのばらつきによって、ガードリング領域３の一部が酸化されて絶縁層１５となることを抑制することができる。それゆえ、ガードリング領域３のドーズ量が変動することを抑制することができる。また当該距離が１．０μｍ以下であれば、ガードリング領域３をイオン注入によって効率的に形成することができる。 (3) Preferably in the silicon carbide semiconductor device according to the above embodiment, the distance from the peak position of the impurity concentration of guard ring region 3 along the normal direction of first main surface 10a to first main surface 10a. Is 0.1 μm or more and 1.0 μm or less. If the distance is 0.1 μm or more, since the distance is larger than the thickness of the insulating layer 15, a part of the guard ring region 3 is oxidized and becomes the insulating layer 15 due to variations in the thickness of the insulating layer 15. Can be suppressed. Therefore, fluctuations in the dose amount of the guard ring region 3 can be suppressed. If the distance is 1.0 μm or less, the guard ring region 3 can be efficiently formed by ion implantation.

　（４）上記実施の形態に係る炭化珪素半導体装置において好ましくは、ガードリング領域３のドーズ量は、１×１０13ｃｍ-2以上である。これにより、炭化珪素半導体装置の耐圧を向上することができる。 (4) In the silicon carbide semiconductor device according to the above embodiment, the dose amount of guard ring region 3 is preferably 1 × 10 13 cm −2 or more. Thereby, the breakdown voltage of the silicon carbide semiconductor device can be improved.

　（５）上記実施の形態に係る炭化珪素半導体装置において好ましくは、ガードリング領域３のドーズ量は、炭化珪素層１０と絶縁層１５との界面における固定電荷密度よりも多い。これにより、炭化珪素半導体装置の耐圧のばらつきを抑制することができる。 (5) Preferably in the silicon carbide semiconductor device according to the above embodiment, the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. Thereby, the dispersion | variation in the proof pressure of a silicon carbide semiconductor device can be suppressed.

　（６）上記実施の形態に係る炭化珪素半導体装置において好ましくは、第１導電型はｐ型であり、かつ第２導電型領域はｎ型領域である。これにより、炭化珪素半導体装置の製造しやすさを向上することができる。 (6) Preferably, in the silicon carbide semiconductor device according to the above embodiment, the first conductivity type is a p-type and the second conductivity type region is an n-type region. Thereby, the ease of manufacture of the silicon carbide semiconductor device can be improved.

　次に、本発明の実施の形態についてより詳細に説明する。
　まず本発明の一実施の形態に係る炭化珪素半導体装置としてのＭＯＳＦＥＴ１の構成について説明する。 Next, embodiments of the present invention will be described in more detail.
First, the configuration of MOSFET 1 as a silicon carbide semiconductor device according to an embodiment of the present invention will be described.

　図１、図２および図８を参照して、ＭＯＳＦＥＴ１は、炭化珪素層１０と、絶縁層１５と、ゲート電極２７と、ソース電極１６と、ドレイン電極２０と、層間絶縁膜７１と、パッド電極６５と、裏面保護電極５０とを主に有する。 1, 2 and 8, MOSFET 1 includes a silicon carbide layer 10, an insulating layer 15, a gate electrode 27, a source electrode 16, a drain electrode 20, an interlayer insulating film 71, and a pad electrode. 65 and the back surface protective electrode 50 are mainly included.

　図１を参照して、ＭＯＳＦＥＴ１の炭化珪素層１０は、素子領域ＩＲ（活性領域）と、素子領域ＩＲの外側に設けられた終端領域ＯＲ（無効領域）とにより構成されている。終端領域ＯＲは、電界緩和領域としてのガードリング領域３およびＪＴＥ領域２とを含む。素子領域ＩＲには半導体素子部７としてのＭＯＳＦＥＴ部が設けられている。半導体素子部７は、ｎ型（第２導電型）を有するドリフト領域１２ａを含む。炭化珪素層１０は、たとえばポリタイプ４Ｈの六方晶炭化珪素からなり、第１の主面１０ａと、第１の主面１０ａと反対の第２の主面１０ｂとを有している。 Referring to FIG. 1, silicon carbide layer 10 of MOSFET 1 includes an element region IR (active region) and a termination region OR (invalid region) provided outside element region IR. Termination region OR includes a guard ring region 3 and a JTE region 2 as electric field relaxation regions. In the element region IR, a MOSFET part as the semiconductor element part 7 is provided. The semiconductor element portion 7 includes a drift region 12a having an n type (second conductivity type). Silicon carbide layer 10 is made of, for example, polytype 4H hexagonal silicon carbide, and has a first main surface 10a and a second main surface 10b opposite to first main surface 10a.

　図２を参照して、平面視（第１の主面１０ａの法線方向から見た視野）において、終端領域ＯＲは素子領域ＩＲを取り囲む。図２に示すように、平面視において素子領域ＩＲを取り囲むようにＪＴＥ領域２が配置されている。ガードリング領域３は、平面視においてＪＴＥ領域２よりも外側に配置され、かつＪＴＥ領域２を取り囲むように配置されている。ガードリング領域３は、ＪＴＥ領域２と離間して設けられている。ガードリング領域３は、複数のガードリング部３ａ～３ｉを有していてもよい。複数のガードリング部３ａ～３ｉの各々は、環形状を有し、互いに隙間を隔てて配置されている。ＪＴＥ領域２の幅Ｗ１はたとえば１５μｍであり、９本のガードリング部３ａ～３ｉの各々の幅Ｗ２～Ｗ１０はたとえば５μｍである。ＪＴＥ領域２とガードリング領域３との間隔ｄ１はたとえば３μｍ程度以上５μｍ程度以下であり、隣り合うガードリング部３ａ～３ｉの間隔ｄ２はたとえば３μｍ程度以上５μｍ程度以下である。また終端領域ＯＲは、ガードリング領域３の外周側に、ｎ型を有するフィールドストップ領域（図示せず）を有していてもよい。 Referring to FIG. 2, the termination region OR surrounds the element region IR in a plan view (a visual field viewed from the normal direction of the first main surface 10a). As shown in FIG. 2, the JTE region 2 is disposed so as to surround the element region IR in plan view. The guard ring region 3 is disposed outside the JTE region 2 in plan view and is disposed so as to surround the JTE region 2. The guard ring region 3 is provided apart from the JTE region 2. The guard ring region 3 may have a plurality of guard ring portions 3a to 3i. Each of the plurality of guard ring portions 3a to 3i has an annular shape and is disposed with a gap therebetween. The width W1 of the JTE region 2 is, for example, 15 μm, and the widths W2 to W10 of the nine guard ring portions 3a to 3i are, for example, 5 μm. An interval d1 between the JTE region 2 and the guard ring region 3 is, for example, about 3 μm to about 5 μm, and an interval d2 between the adjacent guard ring portions 3a to 3i is, for example, about 3 μm to about 5 μm. Termination region OR may have an n-type field stop region (not shown) on the outer peripheral side of guard ring region 3.

　ＪＴＥ領域２およびガードリング領域３の各々は、ｐ型（第１導電型）を有する。ＪＴＥ領域２およびガードリング領域３の各々に含まれる不純物の濃度は、ボディ領域１３の不純物濃度よりも低い。ＪＴＥ領域２およびガードリング領域３の各々のドーズ量は、たとえば１×１０13ｃｍ-2以上である。ＪＴＥ領域２の幅Ｗ１は、たとえば１５μｍ以上５５μｍ程度以下であり、第１の主面１０ａの法線方向に沿ったＪＴＥ領域２の寸法は、たとえば０．５μｍ以上０．８μｍ程度以下である。ガードリング領域３は接地されていてもよい。 Each of JTE region 2 and guard ring region 3 has a p-type (first conductivity type). The impurity concentration contained in each of JTE region 2 and guard ring region 3 is lower than the impurity concentration of body region 13. Each dose amount of JTE region 2 and guard ring region 3 is, for example, 1 × 10 13 cm −2 or more. The width W1 of the JTE region 2 is, for example, about 15 μm to 55 μm, and the dimension of the JTE region 2 along the normal direction of the first main surface 10a is, for example, about 0.5 μm to 0.8 μm. The guard ring region 3 may be grounded.

　図１に示すように、ガードリング領域３は、炭化珪素層１０の第１の主面１０ａから離間して設けられている。第１の主面１０ａとガードリング領域３との間には、ｎ型を有するｎ型領域１２ｃが配置されている。ガードリング領域３の第１の主面１０ａ側にはｎ型領域１２ｃが配置されており、第２の主面１０ｂ側にはｎ型領域１２ａが配置されている。ガードリング領域３は、第１の主面１０ａの法線方向に沿ってｎ型領域１２ｃとｎ型領域１２ａとに挟まれて設けられており、かつ第１の主面１０ａと平行な方向に沿ってｎ型領域１２ａに挟まれて設けられている。ｎ型領域１２ｃおよびｎ型領域１２ａの各々の不純物濃度は、たとえば７．５×１０15ｃｍ-3程度である。 As shown in FIG. 1, guard ring region 3 is provided apart from first main surface 10 a of silicon carbide layer 10. An n-type region 12c having an n-type is arranged between first main surface 10a and guard ring region 3. An n-type region 12c is arranged on the first main surface 10a side of the guard ring region 3, and an n-type region 12a is arranged on the second main surface 10b side. The guard ring region 3 is provided between the n-type region 12c and the n-type region 12a along the normal direction of the first main surface 10a, and in a direction parallel to the first main surface 10a. Along the n-type region 12a. The impurity concentration of each of n-type region 12c and n-type region 12a is, for example, about 7.5 × 10 15 cm −3 .

　好ましくは、複数のガードリング部３ａ～３ｉの各々は、第１の主面１０ａから離間して設けられており、第１の主面１０ａとガードリング部３ａ～３ｉの各々との間には、ｎ型領域１２ｃが配置されている。ガードリング領域３が１つの場合、ｎ型領域１２ｃのドーズ量は、ガードリング領域３のドーズ量よりも少ない。ガードリング領域３が複数のガードリング部３ａ～３ｉを有する場合、ガードリング領域３が有するガードリング部３ａ～３ｉの各々と対向するｎ型領域１２ｃのドーズ量は、ガードリング部３ａ～３ｉの各々のドーズ量よりも少ない。好ましくは、ガードリング領域３と第１の主面１０ａとに挟まれるｎ型領域１２ｃが空乏化可能なように、ガードリング領域３のドーズ量が決定される。ガードリング領域３のドーズ量は、たとえば１×１０13ｃｍ-2程度である。ｎ型領域１２ｃのドーズ量は、たとえば１×１０11ｃｍ-2以上１×１０12ｃｍ-2以下程度である。 Preferably, each of the plurality of guard ring portions 3a to 3i is provided apart from the first main surface 10a, and between the first main surface 10a and each of the guard ring portions 3a to 3i. N-type region 12c is arranged. When there is one guard ring region 3, the dose amount of the n-type region 12c is smaller than the dose amount of the guard ring region 3. When the guard ring region 3 has a plurality of guard ring portions 3a to 3i, the dose amount of the n-type region 12c facing each of the guard ring portions 3a to 3i of the guard ring region 3 is equal to that of the guard ring portions 3a to 3i. Less than each dose. Preferably, the dose amount of guard ring region 3 is determined so that n type region 12c sandwiched between guard ring region 3 and first main surface 10a can be depleted. The dose amount of the guard ring region 3 is, for example, about 1 × 10 13 cm −2 . The dose amount of n-type region 12c is, for example, about 1 × 10 11 cm −2 or more and 1 × 10 12 cm −2 or less.

　図３および図４を参照して、不純物濃度とＹ方向の位置との関係について説明する。図４に示すように、Ｙ方向は、炭化珪素層１０の第１の主面１０ａの法線方向である。第１の主面１０ａを位置０とし、第１の主面１０ａから第２の主面１０ｂに向かう方向を正としている。図３における不純物濃度とは、ガードリング領域３がｐ型を有する場合はアクセプタ濃度を示し、ガードリング領域３がｎ型を有する場合はドナー濃度を示す。ドーズ量は、不純物濃度をＹ方向の位置で積分した量（つまり図３において斜線で示す領域の面積）に対応する。好ましくは、ガードリング領域３のドーズ量は、１×１０13ｃｍ-2以上である。ガードリング領域３が複数のガードリング部３ａ～３ｉを有する場合、複数のガードリング部３ａ～３ｉの各々のドーズ量は、１×１０13ｃｍ-2以上である。 The relationship between the impurity concentration and the position in the Y direction will be described with reference to FIGS. As shown in FIG. 4, the Y direction is a normal direction of first main surface 10 a of silicon carbide layer 10. The first main surface 10a is defined as position 0, and the direction from the first main surface 10a to the second main surface 10b is positive. The impurity concentration in FIG. 3 indicates an acceptor concentration when the guard ring region 3 has a p-type, and indicates a donor concentration when the guard ring region 3 has an n-type. The dose amount corresponds to the amount obtained by integrating the impurity concentration at the position in the Y direction (that is, the area of the region indicated by the oblique lines in FIG. 3). Preferably, the dose amount of the guard ring region 3 is 1 × 10 13 cm −2 or more. When the guard ring region 3 has a plurality of guard ring portions 3a to 3i, the dose amount of each of the plurality of guard ring portions 3a to 3i is 1 × 10 13 cm −2 or more.

　好ましくは、ガードリング領域３のドーズ量は、炭化珪素層１０と絶縁層１５との界面における固定電荷密度よりも多い。当該界面における固定電荷には、最初から存在しているイオンと、界面準位に正孔または電子がトラップされたものとがある。固定電荷は、たとえば絶縁層１５に導入された窒素または水素などにより生じる。界面準位密度は、たとえば１×１０11ｃｍ-2程度である。好ましくは、ガードリング領域３の注入ドーズ量は、界面準位密度の１００倍以上である。固定電荷密度は、たとえば１×１０12ｃｍ-2程度である。固定電荷密度は、たとえば高周波Ｃ-Ｖ(Ｃａｐａｃｉｔａｎｃｅ－Ｖｏｌｔａｇｅ)法によって測定可能である。 Preferably, the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. The fixed charges at the interface include ions that are present from the beginning and those in which holes or electrons are trapped at the interface state. The fixed charge is generated by, for example, nitrogen or hydrogen introduced into the insulating layer 15. The interface state density is, for example, about 1 × 10 11 cm −2 . Preferably, the implantation dose amount in the guard ring region 3 is 100 times or more the interface state density. The fixed charge density is, for example, about 1 × 10 12 cm −2 . The fixed charge density can be measured by, for example, a high-frequency CV (Capacitance-Voltage) method.

　図３に示すように、第１の主面１０ａから離れるにつれてガードリング領域が含む不純物の濃度が高くなり、位置Ｐ１から位置Ｐ２の間において不純物の濃度のピークとなる。Ｙ方向の位置が位置Ｐ２より第２の主面１０ｂ側に移動すると、不純物の濃度は低くなる。第１の主面１０ａから不純物濃度が最初のピークとなる位置Ｐ１までの距離はたとえば０．１μｍであり、第１の主面１０ａから不純物濃度が最後のピークとなる位置Ｐ２までの距離はたとえば１．０μｍである。不純物濃度のピークを示すＹ方向の位置から、第１の主面１０ａまでの距離は、好ましくは０．１μｍ以上１．０μｍ以下程度である。 As shown in FIG. 3, the concentration of impurities contained in the guard ring region increases as the distance from the first main surface 10a increases, and the impurity concentration peaks between position P1 and position P2. When the position in the Y direction moves from the position P2 toward the second main surface 10b, the impurity concentration decreases. The distance from the first main surface 10a to the position P1 where the impurity concentration becomes the first peak is, for example, 0.1 μm, and the distance from the first main surface 10a to the position P2 where the impurity concentration becomes the last peak is, for example, 1.0 μm. The distance from the position in the Y direction showing the peak of the impurity concentration to the first main surface 10a is preferably about 0.1 μm or more and 1.0 μm or less.

　図８を参照して、炭化珪素層１０の素子領域ＩＲの半導体素子部７は、ｎ+基板１１と、ドリフト領域１２ａと、ボディ領域１３と、ソース領域１４と、ｐ+領域１８とを主に有する。 Referring to FIG. 8, semiconductor element portion 7 in element region IR of silicon carbide layer 10 mainly includes n + substrate 11, drift region 12 a, body region 13, source region 14, and p + region 18. Have.

　ｎ+基板１１は、たとえばポリタイプ４Ｈの六方晶炭化珪素からなり導電型がｎ型の基板である。ｎ+基板１１は、たとえばＮ（窒素）などの不純物（ドナー）を高濃度で含んでいる。ｎ+基板１１に含まれる窒素などの不純物濃度はたとえば１．０×１０18ｃｍ-3程度である。 N + substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide and has a conductivity type of n type. N + substrate 11 contains an impurity (donor) such as N (nitrogen) at a high concentration. The concentration of impurities such as nitrogen contained in the n + substrate 11 is, for example, about 1.0 × 10 18 cm −3 .

　ドリフト領域１２ａは、たとえばポリタイプ４Ｈの六方晶炭化珪素からなり、ｎ型を有するエピタキシャル層である。ドリフト領域１２ａに含まれる不純物は、たとえば窒素である。ドリフト領域１２ａにおける不純物濃度は、ｎ+基板１１における不純物濃度よりも低い。ドリフト領域１２ａに含まれる窒素などの不純物濃度はたとえば７．５×１０15ｃｍ-3程度である。好ましくは、ドリフト領域１２ａの厚みＴは１０μｍ程度以上３５μｍ程度以下である。 Drift region 12a is an epitaxial layer made of, for example, polytype 4H hexagonal silicon carbide and having n-type. The impurity contained in drift region 12a is, for example, nitrogen. The impurity concentration in drift region 12 a is lower than the impurity concentration in n + substrate 11. The concentration of impurities such as nitrogen contained in drift region 12a is, for example, about 7.5 × 10 15 cm −3 . Preferably, the thickness T of the drift region 12a is not less than about 10 μm and not more than about 35 μm.

　ボディ領域１３は、ｎ型とは異なるｐ型を有する領域である。ボディ領域１３に含まれる不純物（アクセプタ）は、たとえばＡｌ（アルミニウム）、Ｂ（ホウ素）などである。好ましくは、ボディ領域１３の表面（つまり第１の主面１０ａ）に含まれるアルミニウムなどの不純物濃度は１×１０16ｃｍ-3程度以上５×１０17ｃｍ-3程度以下である。またボディ領域１３の深部における不純物濃度は１×１０18ｃｍ-3程度である。ボディ領域１３の厚みは、たとえば０．５μｍ程度以上１．０μｍ程度以下である。ボディ領域１３とＪＴＥ領域２とは素子領域ＩＲおよび終端領域ＯＲの境界線２ａにおいて接している。 The body region 13 is a region having a p-type different from the n-type. Impurities (acceptors) contained in body region 13 are, for example, Al (aluminum), B (boron), and the like. Preferably, the concentration of impurities such as aluminum contained in the surface of body region 13 (that is, first main surface 10a) is about 1 × 10 16 cm −3 or more and about 5 × 10 17 cm −3 or less. The impurity concentration in the deep part of the body region 13 is about 1 × 10 18 cm −3 . The thickness of body region 13 is not less than about 0.5 μm and not more than about 1.0 μm, for example. The body region 13 and the JTE region 2 are in contact with each other at the boundary line 2a between the element region IR and the termination region OR.

　ソース領域１４はｎ型を有する領域である。ソース領域１４は、ボディ領域１３によっておよびドリフト領域１２ａと隔てられている。またソース領域１４は、第１の主面１０ａを含み、かつボディ領域１３に取り囲まれるように、ボディ領域１３の内部に形成されている。ソース領域１４は、たとえばＰ（リン）などの不純物を、たとえば１×１０20ｃｍ-3程度の濃度で含んでいる。ソース領域１４に含まれる不純物の濃度は、ドリフト領域１２ａに含まれる不純物の濃度よりも高い。 The source region 14 is an n-type region. Source region 14 is separated by body region 13 and from drift region 12a. The source region 14 includes the first main surface 10 a and is formed inside the body region 13 so as to be surrounded by the body region 13. Source region 14 contains, for example, an impurity such as P (phosphorus) at a concentration of about 1 × 10 20 cm −3 . The concentration of the impurity contained in the source region 14 is higher than the concentration of the impurity contained in the drift region 12a.

　ｐ+領域１８はｐ型を有する領域である。ｐ+領域１８は、ボディ領域１３およびソース領域１４と接して形成されている。ｐ+領域１８は、たとえばアルミニウムやホウ素などの不純物を、たとえば１×１０20ｃｍ-3程度の濃度で含んでいる。ｐ+領域１８に含まれる不純物の濃度は、ボディ領域１３に含まれる不純物の濃度よりも高い。 The p + region 18 is a region having a p-type. P + region 18 is formed in contact with body region 13 and source region 14. The p + region 18 contains impurities such as aluminum and boron at a concentration of about 1 × 10 20 cm −3 , for example. The concentration of impurities contained in p + region 18 is higher than the concentration of impurities contained in body region 13.

　図１を参照し、絶縁層１５は、ボディ領域１３に形成されるチャネル領域ＣＨと対向する位置に設けられたゲート絶縁膜部１５ａと、炭化珪素層１０の端部１０ｃに露出し、かつＪＴＥ領域２に接する絶縁膜部１５ｂとを含む。ゲート絶縁膜部１５ａは、一方のソース領域１４の上部表面から他方のソース領域１４の上部表面にまで延在するように、ボディ領域１３、ソース領域１４およびドリフト領域１２ａに接して形成されている。絶縁層１５はたとえば二酸化珪素からなっている。絶縁層１５の厚み（第１の主面１０ａの法線方向に沿った絶縁層１５の寸法）は、たとえば５０ｎｍ程度である。 Referring to FIG. 1, insulating layer 15 is exposed at gate insulating film portion 15 a provided at a position facing channel region CH formed in body region 13, end portion 10 c of silicon carbide layer 10, and JTE And an insulating film portion 15b in contact with the region 2. Gate insulating film portion 15 a is formed in contact with body region 13, source region 14, and drift region 12 a so as to extend from the upper surface of one source region 14 to the upper surface of the other source region 14. . Insulating layer 15 is made of, for example, silicon dioxide. The thickness of the insulating layer 15 (the dimension of the insulating layer 15 along the normal direction of the first main surface 10a) is, for example, about 50 nm.

　ゲート電極２７は、一方のソース領域１４上から他方のソース領域１４上にまで延在するように、ドリフト領域１２ａ、ソース領域およびボディ領域１３と対向し、かつゲート絶縁膜部１５ａに接触して配置されている。ゲート電極２７は、たとえば不純物の添加されたポリシリコン、アルミニウムなどの導電体からなっている。 Gate electrode 27 faces drift region 12a, source region, and body region 13 so as to extend from one source region 14 to the other source region 14, and is in contact with gate insulating film portion 15a. Has been placed. The gate electrode 27 is made of a conductor such as polysilicon doped with impurities, aluminum, or the like.

　ソース電極１６は、ゲート絶縁膜部１５ａ、ソース領域１４およびｐ+領域１８と接している。好ましくは、ソース電極１６は、好ましくは、ニッケルおよびシリコンを有する材料からなる。ソース電極１６は、チタン、アルミニウムおよびシリコンを有する材料からなっていてもよい。好ましくは、ソース電極１６はソース領域１４およびｐ+領域１８とオーミック接合している。 Source electrode 16 is in contact with gate insulating film portion 15 a, source region 14, and p + region 18. Preferably, the source electrode 16 is preferably made of a material having nickel and silicon. The source electrode 16 may be made of a material having titanium, aluminum, and silicon. Preferably, source electrode 16 is in ohmic contact with source region 14 and p + region 18.

　ドレイン電極２０は、炭化珪素層１０の第２の主面１０ｂに接触して形成されている。このドレイン電極２０は、たとえば上記ソース電極１６と同様の構成を有していてもよいし、ニッケルなど、ｎ+基板１１とオーミック接合可能な他の材料からなっていてもよい。これにより、ドレイン電極２０はｎ+基板１１と電気的に接続されている。 Drain electrode 20 is formed in contact with second main surface 10b of silicon carbide layer 10. The drain electrode 20 may have a configuration similar to that of the source electrode 16, for example, or may be made of another material capable of ohmic contact with the n + substrate 11 such as nickel. Thereby, the drain electrode 20 is electrically connected to the n + substrate 11.

　パッド電極６５は、ソース電極１６に接し、かつ層間絶縁膜７１を覆うように形成されている。パッド電極６５はたとえばアルミニウムからなる。図１を参照して、パッド電極６５および絶縁膜部１５ｂに接して保護膜７０が形成されている。また、炭化珪素層１０の第２の主面１０ｂと接してドレイン電極２０が配置されている。さらに、ドレイン電極２０に接してたとえばチタン、ニッケル、銀やそれらの合金からなる裏面保護電極５０が配置されている。 The pad electrode 65 is formed so as to be in contact with the source electrode 16 and cover the interlayer insulating film 71. The pad electrode 65 is made of aluminum, for example. Referring to FIG. 1, protective film 70 is formed in contact with pad electrode 65 and insulating film portion 15b. Further, drain electrode 20 is arranged in contact with second main surface 10b of silicon carbide layer 10. Further, a back surface protective electrode 50 made of, for example, titanium, nickel, silver or an alloy thereof is disposed in contact with the drain electrode 20.

　次にＭＯＳＦＥＴ１の動作について説明する。ゲート電極２７に閾値以下の電圧を与えた状態、すなわちオフ状態では、ゲート絶縁膜部１５ａの直下に位置するボディ領域１３とドリフト領域１２ａとの間が逆バイアスとなり、非導通状態となる。一方、ゲート電極２７に正の電圧を印加していくと、ボディ領域１３のゲート絶縁膜部１５ａと接触する付近であるチャネル領域ＣＨにおいて、反転層が形成される。その結果、ソース領域１４とドリフト領域１２ａとが電気的に接続され、ソース電極１６とドレイン電極２０との間に電流が流れる。 Next, the operation of MOSFET 1 will be described. In a state where a voltage equal to or lower than the threshold value is applied to the gate electrode 27, that is, in an off state, the body region 13 located immediately below the gate insulating film portion 15a and the drift region 12a are reverse-biased and become non-conductive. On the other hand, when a positive voltage is applied to the gate electrode 27, an inversion layer is formed in the channel region CH in the vicinity of the body region 13 in contact with the gate insulating film portion 15a. As a result, the source region 14 and the drift region 12 a are electrically connected, and a current flows between the source electrode 16 and the drain electrode 20.

　次に、本実施の形態に係るＭＯＳＦＥＴ１の製造方法について説明する。
　図５を参照して、まず基板準備工程によって炭化珪素層１０が準備される。具体的には、ポリタイプ４Ｈを有する六方晶炭化珪素からなるｎ+基板１１の一方の主面上にエピタキシャル成長によりｎ型領域１２が形成される。エピタキシャル成長は、たとえば原料ガスとしてＳｉＨ4（シラン）とＣ3Ｈ8（プロパン）との混合ガスを採用して実施することができる。このとき、不純物として、たとえばＮ（窒素）が導入される。これにより、ｎ+基板１１に含まれる不純物よりも低い濃度の不純物を含むｎ型領域１２が形成される。以上により、ｎ+基板１１およびｎ型領域１２を含み、第１の主面１０ａおよび第２の主面１０ｂを有する炭化珪素層１０が形成される。 Next, a method for manufacturing MOSFET 1 according to the present embodiment will be described.
Referring to FIG. 5, first, silicon carbide layer 10 is prepared by a substrate preparation process. Specifically, n-type region 12 is formed by epitaxial growth on one main surface of n + substrate 11 made of hexagonal silicon carbide having polytype 4H. Epitaxial growth can be carried out, for example, using a mixed gas of SiH 4 (silane) and C 3 H 8 (propane) as a raw material gas. At this time, for example, N (nitrogen) is introduced as an impurity. As a result, an n-type region 12 containing impurities having a lower concentration than the impurities contained in the n + substrate 11 is formed. Thus, silicon carbide layer 10 including n + substrate 11 and n-type region 12 and having first main surface 10a and second main surface 10b is formed.

　次に、たとえばＣＶＤにより、炭化珪素層１０の第１の主面１０ａ上に二酸化珪素からなる酸化膜が形成される。そして、酸化膜の上にレジストが塗布された後、露光および現像が行なわれ、所望のボディ領域１３の形状に応じた領域に開口を有するレジスト膜が形成される。そして、当該レジスト膜をマスクとして用いて、たとえばＲＩＥ（Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ；反応性イオンエッチング）により酸化膜が部分的に除去されることによって、ｎ型領域１２上に開口パターンを有する酸化膜からなるマスク層が形成される。 Next, an oxide film made of silicon dioxide is formed on first main surface 10a of silicon carbide layer 10 by, for example, CVD. Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of the desired body region 13 is formed. Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching) to form an oxide film having an opening pattern on the n-type region 12. A mask layer is formed.

　次に、イオン注入工程が実施される。図６を参照して、イオン注入工程では、炭化珪素層１０の第１の主面１０ａ対してイオンが注入されることにより、炭化珪素層１０の素子領域ＩＲにボディ領域１３、ソース領域１４およびｐ+領域１８が形成され、炭化珪素層１０の終端領域ＯＲに電界緩和領域としてのＪＴＥ領域２およびガードリング領域３が形成される。ガードリング領域３は、複数のガードリング部３ａ～３ｉを有し、複数のガードリング部３ａ～３ｉの各々は、第１の主面１０ａから離間するように形成される。 Next, an ion implantation process is performed. Referring to FIG. 6, in the ion implantation step, ions are implanted into first main surface 10 a of silicon carbide layer 10, so that body region 13, source region 14, and element region IR are formed in silicon carbide layer 10. P + region 18 is formed, and JTE region 2 and guard ring region 3 as an electric field relaxation region are formed in termination region OR of silicon carbide layer 10. The guard ring region 3 has a plurality of guard ring portions 3a to 3i, and each of the plurality of guard ring portions 3a to 3i is formed so as to be separated from the first main surface 10a.

　具体的には、上記レジスト膜を除去した上で、当該マスク層をマスクとして用いて、Ａｌなどの不純物をｎ型領域１２に対してイオン注入することにより、ボディ領域１３が形成される。また、Ｐ（リン）などのｎ型不純物がｎ型領域１２にイオン注入により導入されることによりソース領域１４が形成される。次に、Ａｌ、Ｂなどの不純物がｎ型領域１２にイオン注入により導入されることによりｐ+領域１８が形成される。３００℃から５００℃に炭化珪素層１０を加熱してイオン注入が行われてもよい。 Specifically, the body region 13 is formed by removing the resist film and ion-implanting impurities such as Al into the n-type region 12 using the mask layer as a mask. Further, an n-type impurity such as P (phosphorus) is introduced into the n-type region 12 by ion implantation, whereby the source region 14 is formed. Next, impurities such as Al and B are introduced into the n-type region 12 by ion implantation, whereby the p + region 18 is formed. Ion implantation may be performed by heating silicon carbide layer 10 to 300 ° C. to 500 ° C.

　またＡｌなどの不純物をｎ型領域１２に対してイオン注入することにより、ＪＴＥ領域２およびガードリング領域３が形成される。ガードリング領域３は、ＪＴＥ領域２よりも深くに形成されてもよい。ＪＴＥ領域２はボディ領域１３と接するように形成される。好ましくは、ガードリング領域３の注入ドーズ量は、１×１０13ｃｍ-2以上である。また好ましくは、ガードリング領域３は、第１の主面１０ａの法線方向に沿ったガードリング領域３の不純物濃度のピーク位置から第１の主面１０ａまでの距離が０．１μｍ以上１．０μｍ以下となるように形成される。 Further, by implanting impurities such as Al into the n-type region 12, the JTE region 2 and the guard ring region 3 are formed. The guard ring region 3 may be formed deeper than the JTE region 2. JTE region 2 is formed in contact with body region 13. Preferably, the implantation dose amount of the guard ring region 3 is 1 × 10 13 cm −2 or more. Preferably, the guard ring region 3 has a distance from the peak position of the impurity concentration of the guard ring region 3 along the normal direction of the first main surface 10a to the first main surface 10a of 0.1 μm or more. It is formed to be 0 μm or less.

　次に、活性化アニール工程が実施される。上記イオン注入によって導入された不純物を活性化させる熱処理が実施される。具体的には、イオン注入が実施された炭化珪素層１０が、たとえばＡｒ（アルゴン）雰囲気中において１７００℃程度に加熱され、３０分間程度保持される。 Next, an activation annealing step is performed. A heat treatment for activating the impurities introduced by the ion implantation is performed. Specifically, silicon carbide layer 10 subjected to ion implantation is heated to, for example, about 1700 ° C. in an Ar (argon) atmosphere and held for about 30 minutes.

　次に、熱酸化膜形成工程が実施される。具体的には、図７を参照して、イオン注入領域が形成された炭化珪素層１０の第１の主面１０ａが熱酸化される。熱酸化は、たとえば酸素雰囲気中で１３００℃程度に加熱し、４０分間程度保持することにより実施することができる。これにより、炭化珪素層１０の第１の主面１０ａに接して二酸化珪素からなる絶縁層１５が形成される。窒素、ＮＯまたはＮ2Ｏを含む雰囲気中において、絶縁層１５が形成された炭化珪素層１０が、１１００℃から１３００℃に加熱されてもよい。 Next, a thermal oxide film forming step is performed. Specifically, referring to FIG. 7, first main surface 10a of silicon carbide layer 10 in which the ion implantation region is formed is thermally oxidized. Thermal oxidation can be carried out, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes. Thereby, insulating layer 15 made of silicon dioxide is formed in contact with first main surface 10a of silicon carbide layer 10. Silicon carbide layer 10 on which insulating layer 15 is formed may be heated from 1100 ° C. to 1300 ° C. in an atmosphere containing nitrogen, NO, or N 2 O.

　次に、ゲート電極形成工程が実施される。具体的には、図８を参照して、たとえば導電体であるポリシリコン、アルミニウムなどからなるゲート電極２７が、一方のソース領域１４上から他方のソース領域１４上にまで延在するとともに、絶縁層１５に接触するように形成される。ゲート電極２７の材料としてポリシリコンを採用する場合、当該ポリシリコンは、リンが１×１０20ｃｍ-3を超える高い濃度で含まれていてもよい。その後、ゲート電極２７を覆うように、たとえば二酸化珪素からなる層間絶縁膜７１が形成される。 Next, a gate electrode formation step is performed. Specifically, referring to FIG. 8, gate electrode 27 made of, for example, polysilicon or aluminum as a conductor extends from one source region 14 to the other source region 14 and is insulated. It is formed in contact with the layer 15. When polysilicon is employed as the material of the gate electrode 27, the polysilicon may contain phosphorus at a high concentration exceeding 1 × 10 20 cm −3 . Thereafter, an interlayer insulating film 71 made of, for example, silicon dioxide is formed so as to cover gate electrode 27.

　次に、電極形成工程が実施される。具体的には、図８を参照して、たとえばニッケルおよびシリコンを含む材料からなるソース電極１６がソース領域１４およびｐ+領域１８に接して形成される。ソース電極１６は、チタン、アルミニウムおよびシリコンを含む材料であってもよい。ソース電極１６が形成された炭化珪素層１０が１０００℃程度に加熱されることにより、ソース電極１６がシリサイド化し、炭化珪素層１０のソース領域１４およびｐ+領域１８とオーミック接合するソース電極１６が形成される。同様に、炭化珪素層１０の第２の主面１０ｂにオーミック接合するドレイン電極２０が形成される。ドレイン電極２０を形成する材料は、ニッケルおよびシリコンを含む材料であってもよいし、チタン、アルミニウムおよびシリコンを含む材料であってもよい。ソース電極１６と接し、たとえばアルミニウムからなるパッド電極６５が形成される。また、たとえばチタン、ニッケルおよび銀を含む裏面保護電極５０が形成される。以上の様に、図１および図８に示すＭＯＳＦＥＴ１が完成する。 Next, an electrode forming step is performed. Specifically, referring to FIG. 8, source electrode 16 made of a material containing, for example, nickel and silicon is formed in contact with source region 14 and p + region 18. The source electrode 16 may be a material containing titanium, aluminum, and silicon. When silicon carbide layer 10 on which source electrode 16 is formed is heated to about 1000 ° C., source electrode 16 is silicided, and source electrode 16 in ohmic contact with source region 14 and p + region 18 of silicon carbide layer 10 is formed. It is formed. Similarly, drain electrode 20 is formed in ohmic contact with second main surface 10b of silicon carbide layer 10. The material forming the drain electrode 20 may be a material containing nickel and silicon, or may be a material containing titanium, aluminum and silicon. A pad electrode 65 made of, for example, aluminum is formed in contact with the source electrode 16. Moreover, the back surface protective electrode 50 containing, for example, titanium, nickel, and silver is formed. As described above, MOSFET 1 shown in FIGS. 1 and 8 is completed.

　なお、上記実施の形態では、炭化珪素半導体装置の一例としてＭＯＳＦＥＴを例に挙げて説明したが、炭化珪素半導体装置は、ショットキーバリアダイオードなどのダイオードであってもよいし、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）などであってもよい。またＭＯＳＦＥＴは、プレナー型ＭＯＳＦＥＴであってもよいし、トレンチ型ＭＯＳＦＥＴであってもよい。さらに炭化珪素半導体装置は、縦型半導体装置であってもよい。 In the above embodiment, the MOSFET is described as an example of the silicon carbide semiconductor device. However, the silicon carbide semiconductor device may be a diode such as a Schottky barrier diode, or an IGBT (Insulated Gate Bipolar). (Transistor) or the like. The MOSFET may be a planar type MOSFET or a trench type MOSFET. Further, the silicon carbide semiconductor device may be a vertical semiconductor device.

　また、上記実施の形態では、第１導電型がｐ型であり、かつ第２導電型がｎ型であるとして説明したが、第１導電型がｎ型であり、かつ第２導電型がｐ型であってもよい。 In the above embodiment, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type is n-type and the second conductivity type is p-type. It may be a mold.

　次に、本実施の形態に係るＭＯＳＦＥＴ１の作用効果について説明する。
　本実施の形態に係るＭＯＳＦＥＴ１によれば、終端領域ＯＲは、第１導電型を有するガードリング領域３と、第１の主面１０ａとガードリング領域３との間に位置し、かつガードリング領域３とは異なる導電型を有するｎ型領域１２ｃとを含む。これにより、ＭＯＳＦＥＴ１の耐圧のばらつきを低減することができる。 Next, the function and effect of MOSFET 1 according to the present embodiment will be described.
According to MOSFET 1 according to the present embodiment, termination region OR is located between guard ring region 3 having the first conductivity type, first main surface 10a and guard ring region 3, and guard ring region. 3 includes an n-type region 12c having a different conductivity type. Thereby, the dispersion | variation in the proof pressure of MOSFET1 can be reduced.

　また本実施の形態に係るＭＯＳＦＥＴ１によれば、ｎ型領域１２ｃのドーズ量は、ガードリング領域３のドーズ量よりも少ない。これにより、第２導電型領域１２ｃを十分に空乏化することができる。それゆえ、高電界が半導体素子部に集中し、半導体素子部が破壊されることを抑制することができる。 Further, according to MOSFET 1 according to the present embodiment, the dose amount of n-type region 12 c is smaller than the dose amount of guard ring region 3. Thereby, the second conductivity type region 12c can be sufficiently depleted. Therefore, it is possible to suppress the high electric field from being concentrated on the semiconductor element portion and the semiconductor element portion from being destroyed.

　さらに本実施の形態に係るＭＯＳＦＥＴ１によれば、第１の主面１０ａの法線方向に沿ったガードリング領域３の不純物濃度のピーク位置から第１の主面１０ａまでの距離は、０．１μｍ以上１．０μｍ以下である。当該距離が０．１μｍ以上であれば、当該距離が絶縁層１５の厚みよりも大きいため、絶縁層１５の厚みのばらつきによって、ガードリング領域３の一部が酸化されて絶縁層１５となることを抑制することができる。それゆえ、ガードリング領域３のドーズ量が変動することを抑制することができる。また当該距離が１．０μｍ以下であれば、ガードリング領域３をイオン注入によって効率的に形成することができる。 Furthermore, according to MOSFET 1 according to the present embodiment, the distance from the peak position of the impurity concentration of guard ring region 3 along the normal direction of first main surface 10a to first main surface 10a is 0.1 μm. It is 1.0 μm or less. If the distance is 0.1 μm or more, since the distance is larger than the thickness of the insulating layer 15, a part of the guard ring region 3 is oxidized and becomes the insulating layer 15 due to variations in the thickness of the insulating layer 15. Can be suppressed. Therefore, fluctuations in the dose amount of the guard ring region 3 can be suppressed. If the distance is 1.0 μm or less, the guard ring region 3 can be efficiently formed by ion implantation.

　さらに本実施の形態に係るＭＯＳＦＥＴ１によれば、ガードリング領域３のドーズ量は、１×１０13ｃｍ-2以上である。これにより、ＭＯＳＦＥＴ１の耐圧を向上することができる。 Furthermore, according to MOSFET 1 according to the present embodiment, the dose amount of guard ring region 3 is 1 × 10 13 cm −2 or more. Thereby, the breakdown voltage of MOSFET 1 can be improved.

　さらに本実施の形態に係るＭＯＳＦＥＴ１によれば、ガードリング領域３のドーズ量は、炭化珪素層１０と絶縁層１５との界面における固定電荷密度よりも多い。これにより、ＭＯＳＦＥＴ１の耐圧のばらつきを抑制することができる。 Furthermore, according to MOSFET 1 according to the present embodiment, the dose amount of guard ring region 3 is larger than the fixed charge density at the interface between silicon carbide layer 10 and insulating layer 15. Thereby, the dispersion | variation in the proof pressure of MOSFET1 can be suppressed.

　さらに本実施の形態に係るＭＯＳＦＥＴ１によれば、第１導電型はｐ型であり、かつ第２導電型領域はｎ型領域である。これにより、ＭＯＳＦＥＴの製造しやすさを向上することができる。 Furthermore, according to MOSFET 1 according to the present embodiment, the first conductivity type is p-type, and the second conductivity type region is an n-type region. Thereby, the ease of manufacture of MOSFET can be improved.

　今回開示された実施の形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiment disclosed this time is illustrative in all respects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

　１　ＭＯＳＦＥＴ（炭化珪素半導体装置）、２　ＪＴＥ領域、２ａ　境界線、３　ガードリング領域、３ａ～３ｉ　ガードリング部、７　半導体素子部、１０　炭化珪素層、１０ａ　第１の主面、１０ｂ　第２の主面、１０ｃ　端部、１１　基板、１２　ｎ型領域、１２ａ　ドリフト領域（ｎ型領域）、１２ｃ　ｎ型領域（第２導電型領域）、１３　ボディ領域、１４　ソース領域、１５　絶縁層、１５ａ　ゲート絶縁膜部、１５ｂ　絶縁膜部、１６　ソース電極、１８　ｐ+領域、２０　ドレイン電極、２７　ゲート電極、５０　裏面保護電極、６５　パッド電極、７０　保護膜、７１　層間絶縁膜、ＩＲ　素子領域、ＯＲ　終端領域、Ｔ　厚み、Ｗ１，Ｗ２～Ｗ１０　幅、ｄ１，ｄ２　間隔。 DESCRIPTION OF SYMBOLS 1 MOSFET (silicon carbide semiconductor device), 2 JTE area | region, 2a boundary line, 3 guard ring area | region, 3a-3i guard ring part, 7 semiconductor element part, 10 silicon carbide layer, 10a 1st main surface, 10b 2nd Main surface, 10c edge, 11 substrate, 12 n-type region, 12a drift region (n-type region), 12cn region (second conductivity type region), 13 body region, 14 source region, 15 insulating layer, 15a gate Insulating film part, 15b Insulating film part, 16 source electrode, 18 p + region, 20 drain electrode, 27 gate electrode, 50 back surface protective electrode, 65 pad electrode, 70 protective film, 71 interlayer insulating film, IR element region, OR termination Area, T thickness, W1, W2 to W10 width, d1, d2 spacing.

Claims (6)

　第１の主面と、前記第１の主面と反対側の第２の主面とを有し、かつ半導体素子部が設けられた素子領域と、平面視において前記素子領域を取り囲む終端領域とにより構成された炭化珪素層と、
　前記炭化珪素層の前記第１の主面に接する絶縁層とを備え、
　前記終端領域は、第１導電型を有するガードリング領域と、前記第１の主面と前記ガードリング領域との間に位置し、かつ前記ガードリング領域とは異なる導電型を有する第２導電型領域とを含む、炭化珪素半導体装置。 An element region having a first main surface and a second main surface opposite to the first main surface and provided with a semiconductor element portion; and a termination region surrounding the element region in plan view; A silicon carbide layer constituted by:
An insulating layer in contact with the first main surface of the silicon carbide layer,
The termination region is a guard ring region having a first conductivity type, and a second conductivity type located between the first main surface and the guard ring region and having a conductivity type different from the guard ring region. A silicon carbide semiconductor device including the region. 　前記第２導電型領域のドーズ量は、前記ガードリング領域のドーズ量よりも少ない、請求項１に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1, wherein a dose amount of the second conductivity type region is smaller than a dose amount of the guard ring region. 　前記第１の主面の法線方向に沿った前記ガードリング領域の不純物濃度のピーク位置から前記第１の主面までの距離は、０．１μｍ以上１．０μｍ以下である、請求項１または２に記載の炭化珪素半導体装置。 The distance from the peak position of the impurity concentration of the guard ring region along the normal direction of the first main surface to the first main surface is 0.1 μm or more and 1.0 μm or less. 2. The silicon carbide semiconductor device according to 2. 　前記ガードリング領域のドーズ量は、１×１０13ｃｍ-2以上である、請求項１～３のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein a dose amount of the guard ring region is 1 x 10 13 cm -2 or more. 　前記ガードリング領域のドーズ量は、前記炭化珪素層と前記絶縁層との界面における固定電荷密度よりも多い、請求項１～４のいずれか１項に記載の炭化珪素半導体装置。 5. The silicon carbide semiconductor device according to claim 1, wherein a dose amount of the guard ring region is larger than a fixed charge density at an interface between the silicon carbide layer and the insulating layer. 　前記第１導電型はｐ型であり、かつ前記第２導電型領域はｎ型領域である、請求項１～５のいずれか１項に記載の炭化珪素半導体装置。 6. The silicon carbide semiconductor device according to claim 1, wherein the first conductivity type is a p-type and the second conductivity type region is an n-type region.
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