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WO2014156492A1 - Nitride semiconductor element - Google Patents

Nitride semiconductor element Download PDF

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Publication number
WO2014156492A1
WO2014156492A1 PCT/JP2014/055316 JP2014055316W WO2014156492A1 WO 2014156492 A1 WO2014156492 A1 WO 2014156492A1 JP 2014055316 W JP2014055316 W JP 2014055316W WO 2014156492 A1 WO2014156492 A1 WO 2014156492A1
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Prior art keywords
insulating film
opening
nitride semiconductor
region
edge
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French (fr)
Japanese (ja)
Inventor
鈴木　貴光
哲三 永久
弘善 伊奈
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to a nitride semiconductor device.
  • HEMT High Electron Mobility Transistor
  • LED Light Emitting Diode
  • FET Field-effect transistor
  • a lateral electronic device because a source electrode, a drain electrode, and a gate electrode are formed on the surface side where a plurality of nitride semiconductor layers are stacked and current flows laterally.
  • a structure having a heterojunction made of GaN and AlGaN is generally used for a lateral electronic device using a nitride semiconductor.
  • a heterointerface between GaN and AlGaN is a region where electrons can move at high speed along the interface, and there is a two-dimensional electron gas indicating a state in which electrons are distributed two-dimensionally.
  • FIG. 5 is a cross-sectional view of a conventional field effect transistor.
  • a field effect transistor 101 shown in FIG. 5 includes a plurality of nitride semiconductor layers stacked on the surface of a substrate 102 made of a material such as sapphire or Si.
  • the plurality of nitride semiconductor layers include, for example, a buffer layer 103, a GaN channel layer 104, and an AlGaN channel layer 105. Two-dimensional electron gas is distributed at the interface between the GaN channel layer 104 and the AlGaN channel layer 105.
  • a source electrode 107, a drain electrode 108, and a gate electrode 106 disposed between these electrodes are formed on the surface side where a plurality of nitride semiconductors are stacked.
  • the semiconductor device described in Patent Document 1 includes a surface-stabilized semiconductor layer that cancels a charge on a surface of a stacked semiconductor. Thereby, the stabilization of the surface of the semiconductor is achieved, the effect of improving the withstand voltage is obtained, and the effect of suppressing the current collapse is obtained.
  • the surface of the laminated semiconductor is covered with a laminated film composed of a first insulating film and a second insulating film, and the gate electrode extends in an eave-like manner toward the drain electrode side. And a field plate portion formed on the substrate.
  • the balance between the current collapse and the gate breakdown voltage is improved by the synergistic effect of the laminated film composed of the two insulating films and the field plate portion.
  • Patent Document 1 does not give consideration for ensuring long-term reliability at the rated voltage.
  • Patent Document 2 is a technique for improving the gate breakdown voltage.
  • the electric field tends to increase at a location such as an interface between the gate electrode and the insulating film or an interface between a plurality of insulating films. It may be difficult to ensure long-term reliability.
  • the conventional technology related to the nitride semiconductor device has a problem that it cannot be configured to withstand actual use.
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a nitride semiconductor device having a structure that can withstand actual use.
  • the present invention provides a nitridation in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and two-dimensional electron gas is distributed in the nitride semiconductor
  • a first semiconductor film having an opening formed on the surface of the nitride semiconductor, and a region of the first insulating film spaced apart from the region of the opening and the edge of the opening by a predetermined distance.
  • a second insulating film formed on a surface of the first insulating film; a region of the opening of the first insulating film; and a region separated by a predetermined distance from an edge of the opening.
  • the gate electrode and the third insulation Of the field plate portion from the gate electrode on the protruding to the drain electrode surface, comprising a two-dimensional electron gas concentration of the nitride in semiconductor is at 6.5 ⁇ 10 12 / cm 2 or less, the second
  • the distance from the edge of the opening of one insulating film to the end of the field plate protruding toward the drain electrode is 1.8 ⁇ m or more and 2.2 ⁇ m or less.
  • the present invention is a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor.
  • a first insulating film having an opening formed on the surface of the nitride semiconductor; and a region of the first insulating film except for a region of the opening and a region separated by a predetermined distance from an edge of the opening.
  • the gate on the surface of the third insulating film Includes a field plate portion projecting from the electrode to the drain electrode side, and the two-dimensional electron gas concentration of nitride in the semiconductor is at 6.3 ⁇ 10 12 / cm 2 or less, the opening of the first insulating film
  • the distance from the edge of the substrate to the end of the field plate protruding toward the drain electrode is 1.6 ⁇ m or more and 2.4 ⁇ m or less.
  • the present invention is a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor.
  • a first insulating film having an opening formed on the surface of the nitride semiconductor; and a region of the first insulating film except for a region of the opening and a region separated by a predetermined distance from an edge of the opening.
  • the gate on the surface of the third insulating film Includes a field plate portion projecting from the electrode to the drain electrode side, and the two-dimensional electron gas concentration of nitride in the semiconductor is at 6.0 ⁇ 10 12 / cm 2 or less, the opening of the first insulating film
  • the distance from the edge of the substrate to the end of the field plate protruding to the drain electrode side is 1.3 ⁇ m or more and 2.9 ⁇ m or less.
  • the present invention is a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor.
  • a first insulating film having an opening formed on the surface of the nitride semiconductor; and a region of the first insulating film except for a region of the opening and a region separated by a predetermined distance from an edge of the opening.
  • the gate on the surface of the third insulating film Includes a field plate portion projecting from the electrode to the drain electrode side, and the two-dimensional electron gas concentration of nitride in the semiconductor is at 5.5 ⁇ 10 12 / cm 2 or less, the opening of the first insulating film
  • the distance from the edge of the substrate to the end of the field plate protruding to the drain electrode side is 1.0 ⁇ m or more and 3.8 ⁇ m or less.
  • a nitride semiconductor device having a configuration that can withstand actual use can be provided.
  • FIG. 3 is a graph showing the relationship between the electric field intensity at the end of the second insulating film of the field effect transistor of FIG. 1 and the lifetime of the field effect transistor.
  • 2 is a graph showing the relationship between the electric field intensity at the end of the field plate portion of the field effect transistor of FIG. 1 and the lifetime of the field effect transistor.
  • FIG. 1 is a cross-sectional view of a field effect transistor.
  • the basic structure of the field effect transistor according to this embodiment is the same as that of the conventional field effect transistor 101 shown in FIG. 5, and the drawing of the source electrode and the drain electrode in the drawing and the description thereof are omitted.
  • the field effect transistor 1 is formed by laminating a buffer layer 3 made of a nitride semiconductor, a GaN channel layer 4, and an AlGaN barrier layer 5 in this order on the surface of a substrate 2.
  • MISH Metal-Insulator-Semiconductor-Hetero-structure
  • a source electrode and a drain electrode (not shown) and a gate electrode 6 provided between these electrodes are formed.
  • a first insulating film 11, a second insulating film 12, and a third insulating film 13 are provided between the plurality of nitride semiconductor layers and the gate electrode 6.
  • a two-dimensional electron gas is distributed at a high concentration at the interface between the GaN channel layer 4 and the AlyGaN barrier layer 5 to form an electron channel between the drain and the source.
  • a sapphire substrate can be used as the substrate 2, for example.
  • a substrate made of a material such as Si, SiC, or GaN can be used.
  • the buffer layer 3 is formed in order to improve the crystallinity of the nitride semiconductor layer formed on the surface of the buffer layer 3.
  • Each of the GaN channel layer 4 and the AlyGaN barrier layer 5 can be sequentially formed on the surface of the buffer layer 3 by epitaxial growth such as MOCVD (Metal-Organic-Chemical-Vapor-Deposition) method.
  • the first insulating film 11 is formed on the surface of the AlyGaN barrier layer 5.
  • the first insulating film 11 is made of, for example, SiN in order to suppress current collapse.
  • the first insulating film 11 has an opening 11 a below the gate electrode 6 and has a region that does not cover the surface of the AlyGaN barrier layer 5 locally.
  • the second insulating film 12 is formed on the surface of the first insulating film 11.
  • the second insulating film 12 is formed on the surface of the first insulating film 11 except for the region of the opening 11a of the first insulating film 11 and the region S (see FIG. 1) separated by a predetermined distance D from the edge of the opening 11a.
  • the third insulating film 13 is formed on the surface of the second insulating film 12.
  • the third insulating film 13 is formed on the surface of the first insulating film 11 and the second insulating film 12 including the region of the opening 11a of the first insulating film 11 and the region S separated by a predetermined distance D from the edge of the opening 11a. Is done.
  • the gate electrode 6 is formed on the surface of the third insulating film 13 with the region of the opening 11a of the first insulating film 11 and the region S separated by a predetermined distance D from the edge of the opening 11a as the center.
  • the gate electrode 6 includes a field plate portion 6 a protruding from the gate electrode 6 toward the drain electrode (not shown) on the surface of the third insulating film 13.
  • a source electrode and a drain electrode are formed of recess ohmic electrodes.
  • the field plate portion 6a of the gate electrode 6 has the opening 11a of the first insulating film 11 in accordance with the concentration of the two-dimensional electron gas. It is necessary to have a length L at which the electric field strength at the end 12x (see FIG. 1) of the second insulating film 12 corresponding to the boundary with the region S separated by a predetermined distance D from the edge is equal to or less than a certain value.
  • the field plate portion 6a of the gate electrode 6 has an end on the drain electrode side of the field plate portion 6a according to the concentration of the two-dimensional electron gas. It is necessary to have a length L at which the electric field strength in the portion 6x (see FIG. 1) is a certain value or less.
  • an electric field simulator MEDICI
  • the substrate voltage is 0 V
  • the source voltage is 0 V
  • the gate voltage is ⁇ 10 V
  • the drain voltage 600 V.
  • FIG. 2 is a graph showing the relationship between the electric field strength and the life at the end 12x of the second insulating film 12 of the field effect transistor 1 of FIG. 2 indicates the lifetime (h) of the field effect transistor 1, and the horizontal axis indicates the electric field strength (MV / cm) of the end portion 12x of the second insulating film 12 in FIG.
  • the field effect transistor 1 of FIG. 2 in order to achieve an OFF drain voltage of 600 V and a lifetime of 1000 hours at a junction temperature of 150 ° C., which is an index of a configuration that can withstand actual use, the field effect transistor 1 of FIG.
  • the electric field strength at the end 12x of the second insulating film 12 corresponding to the boundary with the region S separated by a predetermined distance D from the edge of the opening 11a of the first insulating film 11 needs to be 3.1 MV / cm or less.
  • the relationship between the electric field strength at the end 6x of the part 6a and the lifetime of the field effect transistor 1 was verified.
  • an electric field simulator MEDICI
  • the substrate voltage is 0 V
  • the source voltage is 0 V
  • the gate voltage is ⁇ 10 V
  • the drain voltage 600 V.
  • FIG. 3 is a graph showing the relationship between the electric field strength and the life at the end 6x of the field plate portion 6a of the field effect transistor 1 of FIG.
  • the vertical axis in FIG. 3 represents the lifetime (h) of the field effect transistor 1
  • the horizontal axis represents the electric field strength (MV / cm) at the end 6x of the field plate portion 6a in FIG.
  • the field effect transistor 1 of FIG. 3 in order to achieve a lifetime of 1000 hours at an OFF drain voltage of 600 V and a junction temperature of 150 ° C., which is an index of a configuration that can withstand actual use, the field effect transistor 1 of FIG.
  • the electric field strength at the end 6x on the drain electrode side of the plate portion 6a needs to be 6.9 MV / cm or less.
  • 4 shows the two-dimensional electron gas concentration of the field effect transistor 1, the length L of the field plate portion 6a of the gate electrode 6, and the lifetime of the field effect transistor 1 at the end 12x and the end 6x of the field effect transistor 1 of FIG. It is a graph which shows the relationship with the restrictions regarding. 4 indicates the length ( ⁇ m) of the field plate portion 6a of the gate electrode 6, and the horizontal axis indicates the concentration of the two-dimensional electron gas ( ⁇ 10 12 / cm 2 ).
  • FIG. 4 shows a restriction regarding the lifetime of the field effect transistor 1 at the end 12x of the second insulating film 12 of the field effect transistor 1 of FIG. Further, in FIG. 4, restrictions on the lifetime of the field effect transistor 1 at the end 6 x of the field plate portion 6 a of the field effect transistor 1 of FIG.
  • the field plate portion 6 a of the gate electrode 6 includes:
  • the length L needs to correspond to the shaded area in FIG.
  • the concentration of the two-dimensional electron gas is 5.5 ⁇ 10 12 / cm 2
  • the length L of the field plate portion 6a is set to 2.0 ⁇ m in consideration of design variations. preferable.
  • the field effect transistor 1 in which the source electrode, the drain electrode, and the gate electrode 6 are formed on the surface side where a plurality of nitride semiconductors are stacked, and the two-dimensional electron gas is distributed in the nitride semiconductor, Except for the first insulating film 11 having an opening 11a formed on the surface of the semiconductor, the region of the opening 11a of the first insulating film 11 and the region S separated by a predetermined distance D from the edge of the opening 11a, the first insulating film 11 The second insulating film 12 formed on the surface and the region of the opening 11a and the region S separated from the edge of the opening 11a by a predetermined distance D are formed on the surfaces of the first insulating film 11 and the second insulating film 12.
  • the length L from the end of the field plate portion 6a protruding to the drain electrode side is 1.8 ⁇ m or more and 2.2 ⁇ m or less.
  • the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.
  • the two-dimensional electron gas concentration in the nitride semiconductor is 6.3 ⁇ 10 12 / cm 2 or less
  • the first The distance L from the edge of the opening 11a of the insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode is 1.6 ⁇ m or more and 2.4 ⁇ m or less.
  • the two-dimensional electron gas concentration in the nitride semiconductor is 6.0 ⁇ 10 12 / cm 2 or less as shown as a rectangular range F3 in FIG.
  • the distance L from the edge of the opening 11a of the insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode is 1.3 ⁇ m or more and 2.9 ⁇ m or less.
  • the two-dimensional electron gas concentration in the nitride semiconductor is not more than 5.5 ⁇ 10 12 / cm 2 as shown by a rectangular range F4 in FIG.
  • the distance L from the edge of the opening 11a of the insulating film 11 to the end of the field plate portion 6a protruding to the drain electrode side is 1.0 ⁇ m or more and 3.8 ⁇ m or less.
  • FIG. 6 is a cross-sectional view of the field effect transistor 1, and is a cross-sectional view drawn up to the drain electrode 7 and source electrode 8 regions with respect to FIG.
  • the drain electrode 7 and the source electrode 8 are formed on the surface of the AlGaN barrier layer 5 similarly to the gate electrode 6.
  • the first insulating film 11 has a non-coating portion 11 b below the drain electrode 7 and has a region that does not locally cover the surface of the AlyGaN barrier layer 5.
  • the drain electrode 7 is formed on the surface of the AlyGaN barrier layer 5, the first insulating film 11, and the second insulating film 12 above the region of the non-coating portion 11 b of the first insulating film 11.
  • the distance from the edge on the opening 11a side of the first insulating film 11 to the edge on the non-coating portion 11b side is the gate-drain distance LGD.
  • FIG. 7 shows the two-dimensional electron gas concentration of the field effect transistor 1 and the length L of the field plate portion 6a of the gate electrode 6 when the gate-drain distance LGD of the field effect transistor 1 shown in FIG. It is a graph which shows the relationship with the restrictions regarding the lifetime of the field effect transistor 1 about the edge part 12x and the edge part 6x of the field effect transistor 1 of FIG.
  • the vertical axis in FIG. 7 indicates the length ( ⁇ m) of the field plate portion 6a of the gate electrode 6, and the horizontal axis indicates the concentration of the two-dimensional electron gas ( ⁇ 10 12 / cm 2 ).
  • the electric field strength is obtained using an electric field simulator (MEDICI), and the substrate voltage is 0 V, the source voltage is 0 V, the gate voltage is ⁇ 10 V, and the drain voltage is 600 V as simulation conditions.
  • MEDICI electric field simulator
  • FIG. 7 a restriction regarding the lifetime of the field effect transistor 1 at the end 12 x of the second insulating film 12 of the field effect transistor 1 of FIG. 6 is drawn by a broken line. Further, in FIG. 7, restrictions on the lifetime of the field effect transistor 1 at the end portion 6x of the field plate portion 6a of the field effect transistor 1 in FIG.
  • the field plate portion 6a of the gate electrode 6 includes:
  • the length L needs to correspond to the shaded area in FIG.
  • the concentration of the two-dimensional electron gas is 6.5 ⁇ 10 12 / cm 2
  • the length L of the field plate portion 6a is set to 2.5 ⁇ m in consideration of design variations. preferable.
  • the gate-drain distance LGD in FIG. 6 is 15 ⁇ m or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 6 as shown as a rectangular range F5 in FIG. 5 ⁇ 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 1.1 ⁇ m or more and 4.5 ⁇ m It is as follows. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.
  • the gate-drain distance LGD in FIG. 6 is 15 ⁇ m or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 7 as shown as a rectangular range F6 in FIG. 0.0 ⁇ 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 1.4 ⁇ m or more and 3.5 ⁇ m.
  • the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x.
  • the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.
  • the gate-drain distance LGD in FIG. 6 is 15 ⁇ m or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 7 as shown as a rectangular range F7 in FIG. 3 ⁇ 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 1.8 ⁇ m or more and 2.9 ⁇ m.
  • the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x.
  • the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.
  • the gate-drain distance LGD in FIG. 6 is 15 ⁇ m or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 7 as shown as a rectangular range F8 in FIG. 5 ⁇ 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 2.0 ⁇ m or more and 2.7 ⁇ m.
  • the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x.
  • the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.
  • the field effect transistor 1 having a configuration that can withstand actual use can be provided.
  • the present invention can be used in nitride semiconductor devices.

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  • Junction Field-Effect Transistors (AREA)

Abstract

A field effect transistor (1) is provided with: a first insulating film (11) that is formed on the surface of a nitride semiconductor and has an opening (11a); a second insulating film (12) that is formed on the surface of the first insulating film (11) in regions other than the region of the opening (11a) and the region within a certain distance from the edge of the opening (11a); a third insulating film (13) that is formed on the surfaces of the first insulating film (11) and the second insulating film (12); a gate electrode (6) that is formed on the surface of the third insulating film (13); and a field plate part (6a) that protrudes from the gate electrode (6) toward the drain electrode. The two-dimensional electron gas concentration is set to 6.5 × 1012 /cm2 or less, and the length (L) from the edge of the opening (11a) to the end of the field plate part (6a) that protrudes from the gate electrode (6) toward the drain electrode is set to 1.8-2.2 μm (inclusive).

Description

窒化物半導体素子Nitride semiconductor device

　本発明は窒化物半導体素子に関する。 The present invention relates to a nitride semiconductor device.

　一般に、ＨＥＭＴ（High Electron Mobility Transistor）やＬＥＤ（Light Emitting Diode）などの様々なデバイスとして機能する、サファイア基板などの六方晶の基板上に複数の窒化物半導体層を積層して形成した機能素子が知られている。例えば、電界効果トランジスタ（Field Effect Transistor、FET）は複数の窒化物半導体層を積層したその表面側にソース電極、ドレイン電極及びゲート電極が形成されて電流が横方向に流れるため横型電子デバイスと呼ばれる。 In general, a functional element formed by laminating a plurality of nitride semiconductor layers on a hexagonal substrate such as a sapphire substrate, which functions as various devices such as HEMT (High Electron Mobility Transistor) and LED (Light Emitting Diode). Are known. For example, a field-effect transistor (Field-Effect-Transistor, FET) is called a lateral electronic device because a source electrode, a drain electrode, and a gate electrode are formed on the surface side where a plurality of nitride semiconductor layers are stacked and current flows laterally. .

　窒化物半導体を用いた横型電子デバイスにはＧａＮとＡｌＧａＮとからなるヘテロ接合を有する構造が一般的に用いられる。ＧａＮとＡｌＧａＮとのヘテロ界面には電子がその界面に沿って高速で移動できる領域であって、電子が２次元状に分布する状態を示す２次元電子ガスが存在する。 A structure having a heterojunction made of GaN and AlGaN is generally used for a lateral electronic device using a nitride semiconductor. A heterointerface between GaN and AlGaN is a region where electrons can move at high speed along the interface, and there is a two-dimensional electron gas indicating a state in which electrons are distributed two-dimensionally.

　ここで、他の従来の横型電子デバイスとしての電界効果トランジスタの構成について図面を参照して説明する。図５は従来の電界効果トランジスタの断面図である。図５に示す電界効果トランジスタ１０１はサファイアやＳｉなどの材料からなる基板１０２の表面上に積層された複数の窒化物半導体層を備える。複数の窒化物半導体層は、例えばバッファ層１０３、ＧａＮチャネル層１０４及びＡｌＧａＮチャネル層１０５からなる。ＧａＮチャネル層１０４とＡｌＧａＮチャネル層１０５との界面には２次元電子ガスが分布する。複数の窒化物半導体を積層したその表面側にはソース電極１０７、ドレイン電極１０８、及びそれら電極の間に配置されたゲート電極１０６が形成される。 Here, the configuration of a field effect transistor as another conventional lateral electronic device will be described with reference to the drawings. FIG. 5 is a cross-sectional view of a conventional field effect transistor. A field effect transistor 101 shown in FIG. 5 includes a plurality of nitride semiconductor layers stacked on the surface of a substrate 102 made of a material such as sapphire or Si. The plurality of nitride semiconductor layers include, for example, a buffer layer 103, a GaN channel layer 104, and an AlGaN channel layer 105. Two-dimensional electron gas is distributed at the interface between the GaN channel layer 104 and the AlGaN channel layer 105. A source electrode 107, a drain electrode 108, and a gate electrode 106 disposed between these electrodes are formed on the surface side where a plurality of nitride semiconductors are stacked.

　このような電界効果トランジスタなどといった窒化物半導体素子では電流コラプスという現象の発生が懸念されている。電流コラプスとは高電圧動作時のオン抵抗値が低電圧動作時のオン抵抗値と比較して高くなる現象であり、ドレイン電流が低下することにより高出力を得ることができなくなる。電流コラプスが発生する原因としては半導体中のトラップ準位の影響や、半導体とその保護膜との界面のトラップの存在などが知られている。この電流コラプスを抑制するための従来技術が特許文献１及び２に開示されている。 In such a nitride semiconductor element such as a field effect transistor, there is a concern about the phenomenon of current collapse. Current collapse is a phenomenon in which the on-resistance value during high-voltage operation is higher than the on-resistance value during low-voltage operation, and a high output cannot be obtained when the drain current decreases. Known causes of current collapse include the influence of trap levels in the semiconductor and the presence of traps at the interface between the semiconductor and its protective film. Conventional techniques for suppressing this current collapse are disclosed in Patent Documents 1 and 2.

　特許文献１に記載された半導体装置は積層した半導体の表面に、その表面における帯電荷を相殺する表面安定化半導体層を備える。これにより、半導体の表面の安定化を達成して耐電圧の向上効果を得て、電流コラプスの抑制効果を得ている。 The semiconductor device described in Patent Document 1 includes a surface-stabilized semiconductor layer that cancels a charge on a surface of a stacked semiconductor. Thereby, the stabilization of the surface of the semiconductor is achieved, the effect of improving the withstand voltage is obtained, and the effect of suppressing the current collapse is obtained.

　特許文献２に記載された電界効果トランジスタは積層した半導体の表面上を第１の絶縁膜及び第２の絶縁膜からなる積層膜で覆い、ゲート電極がドレイン電極側にひさし状に張り出し絶縁膜上に形成されたフィールドプレート部を有する。二層の絶縁膜からなる積層膜とフィールドプレート部との相乗効果により、電流コラプス及びゲート耐圧のバランスを改善している。 In the field effect transistor described in Patent Document 2, the surface of the laminated semiconductor is covered with a laminated film composed of a first insulating film and a second insulating film, and the gate electrode extends in an eave-like manner toward the drain electrode side. And a field plate portion formed on the substrate. The balance between the current collapse and the gate breakdown voltage is improved by the synergistic effect of the laminated film composed of the two insulating films and the field plate portion.

特開２００８－３４４３８号公報JP 2008-34438 A 特開２００４－２００２４８号公報JP 2004-200248 A

　ここで昨今、窒化物半導体素子の実際の使用に関して、最大ドレイン電圧定格６００Ｖ以上における長期信頼性を確保することが求められてきている。これに対して、特許文献１に記載の従来技術は上記定格電圧における長期信頼性を確保するための配慮がなされていいない。特許文献２に記載の従来技術はゲート耐圧を改善する技術であるが、ゲート電極と絶縁膜との界面や、複数の絶縁膜どうしの界面などの箇所において電界が高くなり易く、その技術だけでは長期信頼性を確保することが困難である可能性がある。 Here, recently, regarding the actual use of the nitride semiconductor device, it has been required to ensure long-term reliability at a maximum drain voltage rating of 600 V or more. On the other hand, the prior art described in Patent Document 1 does not give consideration for ensuring long-term reliability at the rated voltage. The conventional technique described in Patent Document 2 is a technique for improving the gate breakdown voltage. However, the electric field tends to increase at a location such as an interface between the gate electrode and the insulating film or an interface between a plurality of insulating films. It may be difficult to ensure long-term reliability.

　このようにして、窒化物半導体素子に係る従来技術では実際の使用に耐え得る構成にすることができないという課題があった。 Thus, the conventional technology related to the nitride semiconductor device has a problem that it cannot be configured to withstand actual use.

　本発明は、上記の点に鑑みなされたものであり、実際の使用に耐え得る構成の窒化物半導体素子を提供することを目的とする。 The present invention has been made in view of the above points, and an object of the present invention is to provide a nitride semiconductor device having a structure that can withstand actual use.

　上記の課題を解決するため、本発明は、複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、を備え、前記窒化物半導体中の２次元電子ガス濃度が６．５×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．８μｍ以上２．２μｍ以下であることを特徴としている。 In order to solve the above problems, the present invention provides a nitridation in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and two-dimensional electron gas is distributed in the nitride semiconductor A first semiconductor film having an opening formed on the surface of the nitride semiconductor, and a region of the first insulating film spaced apart from the region of the opening and the edge of the opening by a predetermined distance. A second insulating film formed on a surface of the first insulating film; a region of the opening of the first insulating film; and a region separated by a predetermined distance from an edge of the opening. A third insulating film formed on the surface of the insulating film, and formed on the surface of the third insulating film centered on a region of the opening of the first insulating film and a region spaced a predetermined distance from an edge of the opening; The gate electrode and the third insulation Of the field plate portion from the gate electrode on the protruding to the drain electrode surface, comprising a two-dimensional electron gas concentration of the nitride in semiconductor is at 6.5 × 10 12 / cm 2 or less, the second The distance from the edge of the opening of one insulating film to the end of the field plate protruding toward the drain electrode is 1.8 μm or more and 2.2 μm or less.

　また、本発明は、複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、を備え、前記窒化物半導体中の２次元電子ガス濃度が６．３×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．６μｍ以上２．４μｍ以下であることを特徴としている。 Further, the present invention is a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor. A first insulating film having an opening formed on the surface of the nitride semiconductor; and a region of the first insulating film except for a region of the opening and a region separated by a predetermined distance from an edge of the opening. A second insulating film formed on the surface; and a region of the opening of the first insulating film and a region separated from the edge of the opening by a predetermined distance on the surfaces of the first insulating film and the second insulating film. A third insulating film formed; and the gate electrode formed on a surface of the third insulating film centered on a region of the opening of the first insulating film and a region separated from an edge of the opening by a predetermined distance; The gate on the surface of the third insulating film; Includes a field plate portion projecting from the electrode to the drain electrode side, and the two-dimensional electron gas concentration of nitride in the semiconductor is at 6.3 × 10 12 / cm 2 or less, the opening of the first insulating film The distance from the edge of the substrate to the end of the field plate protruding toward the drain electrode is 1.6 μm or more and 2.4 μm or less.

　また、本発明は、複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、を備え、前記窒化物半導体中の２次元電子ガス濃度が６．０×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．３μｍ以上２．９μｍ以下であることを特徴としている。 Further, the present invention is a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor. A first insulating film having an opening formed on the surface of the nitride semiconductor; and a region of the first insulating film except for a region of the opening and a region separated by a predetermined distance from an edge of the opening. A second insulating film formed on the surface; and a region of the opening of the first insulating film and a region separated from the edge of the opening by a predetermined distance on the surfaces of the first insulating film and the second insulating film. A third insulating film formed; and the gate electrode formed on a surface of the third insulating film centered on a region of the opening of the first insulating film and a region separated from an edge of the opening by a predetermined distance; The gate on the surface of the third insulating film; Includes a field plate portion projecting from the electrode to the drain electrode side, and the two-dimensional electron gas concentration of nitride in the semiconductor is at 6.0 × 10 12 / cm 2 or less, the opening of the first insulating film The distance from the edge of the substrate to the end of the field plate protruding to the drain electrode side is 1.3 μm or more and 2.9 μm or less.

　また、本発明は、複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、を備え、前記窒化物半導体中の２次元電子ガス濃度が５．５×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．０μｍ以上３．８μｍ以下であることを特徴としている。 Further, the present invention is a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor. A first insulating film having an opening formed on the surface of the nitride semiconductor; and a region of the first insulating film except for a region of the opening and a region separated by a predetermined distance from an edge of the opening. A second insulating film formed on the surface; and a region of the opening of the first insulating film and a region separated from the edge of the opening by a predetermined distance on the surfaces of the first insulating film and the second insulating film. A third insulating film formed; and the gate electrode formed on a surface of the third insulating film centered on a region of the opening of the first insulating film and a region separated from an edge of the opening by a predetermined distance; The gate on the surface of the third insulating film; Includes a field plate portion projecting from the electrode to the drain electrode side, and the two-dimensional electron gas concentration of nitride in the semiconductor is at 5.5 × 10 12 / cm 2 or less, the opening of the first insulating film The distance from the edge of the substrate to the end of the field plate protruding to the drain electrode side is 1.0 μm or more and 3.8 μm or less.

　本発明の構成によれば、実際の使用に耐え得る構成の窒化物半導体素子を提供することができる。 According to the configuration of the present invention, a nitride semiconductor device having a configuration that can withstand actual use can be provided.

本発明の実施形態に係る窒化物半導体素子の一例としての電界効果トランジスタの断面図である。It is sectional drawing of the field effect transistor as an example of the nitride semiconductor element which concerns on embodiment of this invention. 図１の電界効果トランジスタの第２絶縁膜の端部における電界強度と電界効果トランジスタの寿命との関係を示すグラフである。3 is a graph showing the relationship between the electric field intensity at the end of the second insulating film of the field effect transistor of FIG. 1 and the lifetime of the field effect transistor. 図１の電界効果トランジスタのフィールドプレート部の端部における電界強度と電界効果トランジスタの寿命との関係を示すグラフである。2 is a graph showing the relationship between the electric field intensity at the end of the field plate portion of the field effect transistor of FIG. 1 and the lifetime of the field effect transistor. 本発明の実施形態に係る電界効果トランジスタの２次元電子ガス濃度及びゲート電極フィールドプレート長さと図１の電界効果トランジスタの第２絶縁膜の端部及びフィールドプレート部の端部についての電界効果トランジスタの寿命に関する制約との関係を示すグラフである。The two-dimensional electron gas concentration and the gate electrode field plate length of the field effect transistor according to the embodiment of the present invention, and the field effect transistor end portion of the second insulating film and the field plate portion of the field effect transistor of FIG. It is a graph which shows the relationship with the restriction | limiting regarding a lifetime. 従来の電界効果トランジスタの断面図である。It is sectional drawing of the conventional field effect transistor. 本発明の実施形態に係る窒化物半導体素子の一例としての電界効果トランジスタの断面図である。It is sectional drawing of the field effect transistor as an example of the nitride semiconductor element which concerns on embodiment of this invention. 本発明の実施形態に係る電界効果トランジスタの２次元電子ガス濃度及びゲート電極フィールドプレート長さと図６の電界効果トランジスタの第２絶縁膜の端部及びフィールドプレート部の端部についての電界効果トランジスタの寿命に関する制約との関係を示すグラフである。The two-dimensional electron gas concentration and the gate electrode field plate length of the field effect transistor according to the embodiment of the present invention, and the field effect transistor end portion of the second insulating film and the field plate portion of the field effect transistor of FIG. It is a graph which shows the relationship with the restriction | limiting regarding a lifetime.

　以下、本発明の実施形態を図に基づき説明する。なお、ここでは、本発明の窒化物半導体素子の一例として電界効果トランジスタを掲げて説明するものとする。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, a field effect transistor will be described as an example of the nitride semiconductor device of the present invention.

　最初に、本発明の実施形態に係る電界効果トランジスタについて、図１を用いてその構造を説明する。図１は電界効果トランジスタの断面図である。なお、この実施形態に係る電界効果トランジスタの基本的な構造は図５に示した従来の電界効果トランジスタ１０１と同じであり、ソース電極及びドレイン電極の図面への描画とその説明とを省略する。 First, the structure of a field effect transistor according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of a field effect transistor. The basic structure of the field effect transistor according to this embodiment is the same as that of the conventional field effect transistor 101 shown in FIG. 5, and the drawing of the source electrode and the drain electrode in the drawing and the description thereof are omitted.

　電界効果トランジスタ１は、図１に示すように基板２の表面上に、各々窒化物半導体からなるバッファ層３と、ＧａＮチャネル層４と、ＡｌＧａＮ障壁層５とがこの順に積層されて形成されるＭＩＳＨ（Metal Insulator Semiconductor Hetero-structure）構造をなす。 As shown in FIG. 1, the field effect transistor 1 is formed by laminating a buffer layer 3 made of a nitride semiconductor, a GaN channel layer 4, and an AlGaN barrier layer 5 in this order on the surface of a substrate 2. MISH (Metal-Insulator-Semiconductor-Hetero-structure) structure.

　バッファ層３、ＧａＮチャネル層４及びＡｌＧａＮ障壁層５を積層したその表面側には不図示のソース電極及びドレイン電極と、それら電極の間に設けたゲート電極６とが形成される。複数の窒化物半導体層とゲート電極６の間には第１絶縁膜１１、第２絶縁膜１２及び第３絶縁膜１３を備える。 On the surface side where the buffer layer 3, the GaN channel layer 4 and the AlGaN barrier layer 5 are stacked, a source electrode and a drain electrode (not shown) and a gate electrode 6 provided between these electrodes are formed. A first insulating film 11, a second insulating film 12, and a third insulating film 13 are provided between the plurality of nitride semiconductor layers and the gate electrode 6.

　なお、ＧａＮチャネル層４とＡｌｙＧａＮ障壁層５との界面には２次元電子ガスが高濃度にて分布しており、ドレイン－ソース間の電子チャネルとなる。 Note that a two-dimensional electron gas is distributed at a high concentration at the interface between the GaN channel layer 4 and the AlyGaN barrier layer 5 to form an electron channel between the drain and the source.

　ここで、基板２としては、例えばサファイア基板を使用することができる。また、サファイアのほかに、Ｓｉ、ＳｉＣ、ＧａＮなどの材料からなる基板を使用することもできる。 Here, as the substrate 2, for example, a sapphire substrate can be used. In addition to sapphire, a substrate made of a material such as Si, SiC, or GaN can be used.

　バッファ層３はバッファ層３の表面上に形成される窒化物半導体層の結晶性を向上させるために形成される。ＧａＮチャネル層４とＡｌｙＧａＮ障壁層５とはそれぞれ、例えばＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法などのエピタキシャル成長によって、バッファ層３の表面上に順次形成することができる。 The buffer layer 3 is formed in order to improve the crystallinity of the nitride semiconductor layer formed on the surface of the buffer layer 3. Each of the GaN channel layer 4 and the AlyGaN barrier layer 5 can be sequentially formed on the surface of the buffer layer 3 by epitaxial growth such as MOCVD (Metal-Organic-Chemical-Vapor-Deposition) method.

　第１絶縁膜１１はＡｌｙＧａＮ障壁層５の表面上に形成される。第１絶縁膜１１は電流コラプスを抑制するために、例えばＳｉＮからなる。なお、第１絶縁膜１１はゲート電極６の下方に開口１１ａを有し、ＡｌｙＧａＮ障壁層５の表面に対して局部的に覆っていない領域を有する。 The first insulating film 11 is formed on the surface of the AlyGaN barrier layer 5. The first insulating film 11 is made of, for example, SiN in order to suppress current collapse. The first insulating film 11 has an opening 11 a below the gate electrode 6 and has a region that does not cover the surface of the AlyGaN barrier layer 5 locally.

　第２絶縁膜１２は第１絶縁膜１１の表面上に形成される。なお、第２絶縁膜１２は第１絶縁膜１１の開口１１ａの領域及び開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓ（図１参照）を除き第１絶縁膜１１の表面上に形成される。 The second insulating film 12 is formed on the surface of the first insulating film 11. The second insulating film 12 is formed on the surface of the first insulating film 11 except for the region of the opening 11a of the first insulating film 11 and the region S (see FIG. 1) separated by a predetermined distance D from the edge of the opening 11a. The

　第３絶縁膜１３は第２絶縁膜１２の表面上に形成される。なお、第３絶縁膜１３は第１絶縁膜１１の開口１１ａの領域及び開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓを含み第１絶縁膜１１及び第２絶縁膜１２の表面上に形成される。 The third insulating film 13 is formed on the surface of the second insulating film 12. The third insulating film 13 is formed on the surface of the first insulating film 11 and the second insulating film 12 including the region of the opening 11a of the first insulating film 11 and the region S separated by a predetermined distance D from the edge of the opening 11a. Is done.

　ゲート電極６は第１絶縁膜１１の開口１１ａの領域及び開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓを中心とした第３絶縁膜１３の表面上に形成される。ゲート電極６は第３絶縁膜１３の表面上でゲート電極６から不図示のドレイン電極側に突き出したフィールドプレート部６ａを備える。 The gate electrode 6 is formed on the surface of the third insulating film 13 with the region of the opening 11a of the first insulating film 11 and the region S separated by a predetermined distance D from the edge of the opening 11a as the center. The gate electrode 6 includes a field plate portion 6 a protruding from the gate electrode 6 toward the drain electrode (not shown) on the surface of the third insulating film 13.

　なお、不図示のソース電極及びドレイン電極はリセスオーミック電極で形成される。 Note that a source electrode and a drain electrode (not shown) are formed of recess ohmic electrodes.

　ここで、電界効果トランジスタ１が実際の使用に耐え得る構成であるためには、ゲート電極６のフィールドプレート部６ａが、２次元電子ガスの濃度に応じて、第１絶縁膜１１の開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓとの境界に対応する第２絶縁膜１２の端部１２ｘ（図１参照）における電界強度が一定値以下となる長さＬを有する必要がある。 Here, in order for the field effect transistor 1 to have a configuration that can withstand actual use, the field plate portion 6a of the gate electrode 6 has the opening 11a of the first insulating film 11 in accordance with the concentration of the two-dimensional electron gas. It is necessary to have a length L at which the electric field strength at the end 12x (see FIG. 1) of the second insulating film 12 corresponding to the boundary with the region S separated by a predetermined distance D from the edge is equal to or less than a certain value.

　また、電界効果トランジスタ１が実際の使用に耐え得る構成であるためには、ゲート電極６のフィールドプレート部６ａが、２次元電子ガスの濃度に応じて、フィールドプレート部６ａのドレイン電極側の端部６ｘ（図１参照）における電界強度が一定値以下となる長さＬを有する必要がある。 In addition, in order for the field effect transistor 1 to be configured to withstand actual use, the field plate portion 6a of the gate electrode 6 has an end on the drain electrode side of the field plate portion 6a according to the concentration of the two-dimensional electron gas. It is necessary to have a length L at which the electric field strength in the portion 6x (see FIG. 1) is a certain value or less.

　続いて、上記構造の本実施形態の電界効果トランジスタ１を使用して、ゲート電極６のフィールドプレート部６ａの長さＬを変更したときの図１の第２絶縁膜１２の端部１２ｘにおける電界強度と電界効果トランジスタ１の寿命との関係を検証した。電界強度は電界シミュレータ（ＭＥＤＩＣＩ）を使用し、その結果を図２に示す。なお、シミュレーションの条件として、基板電圧を０Ｖとし、ソース電圧を０Ｖとし、ゲート電圧を－１０Ｖとし、ドレイン電圧を６００Ｖとしている。 Subsequently, the electric field at the end portion 12x of the second insulating film 12 of FIG. 1 when the length L of the field plate portion 6a of the gate electrode 6 is changed using the field effect transistor 1 of the present embodiment having the above structure. The relationship between the strength and the lifetime of the field effect transistor 1 was verified. For the electric field strength, an electric field simulator (MEDICI) is used, and the result is shown in FIG. As simulation conditions, the substrate voltage is 0 V, the source voltage is 0 V, the gate voltage is −10 V, and the drain voltage is 600 V.

　図２は図１の電界効果トランジスタ１の第２絶縁膜１２の端部１２ｘにおける電界強度と寿命の関係を示すグラフである。図２の縦軸は電界効果トランジスタ１の寿命（ｈ）を示し、横軸は図１の第２絶縁膜１２の端部１２ｘの電界強度（ＭＶ／ｃｍ）を示している。 FIG. 2 is a graph showing the relationship between the electric field strength and the life at the end 12x of the second insulating film 12 of the field effect transistor 1 of FIG. 2 indicates the lifetime (h) of the field effect transistor 1, and the horizontal axis indicates the electric field strength (MV / cm) of the end portion 12x of the second insulating film 12 in FIG.

　図２によれば、実際の使用に耐え得る構成の指標となるＯＦＦ時のドレイン電圧６００Ｖ、ジャンクション温度１５０℃における寿命時間１０００時間を達成するためには、図１の電界効果トランジスタ１の、第１絶縁膜１１の開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓとの境界に対応する第２絶縁膜１２の端部１２ｘの電界強度が３．１ＭＶ／ｃｍ以下となる必要がある。 According to FIG. 2, in order to achieve an OFF drain voltage of 600 V and a lifetime of 1000 hours at a junction temperature of 150 ° C., which is an index of a configuration that can withstand actual use, the field effect transistor 1 of FIG. The electric field strength at the end 12x of the second insulating film 12 corresponding to the boundary with the region S separated by a predetermined distance D from the edge of the opening 11a of the first insulating film 11 needs to be 3.1 MV / cm or less.

　続いて、上記構造の本実施形態の電界効果トランジスタ１を使用して、ゲート電極６のフィールドプレート部６ａの長さＬを一定として２次元電子ガスの濃度を変更したときの図１のフィールドプレート部６ａの端部６ｘにおける電界強度と電界効果トランジスタ１の寿命との関係を検証した。電界強度は電界シミュレータ（ＭＥＤＩＣＩ）を使用し、その結果を図３に示す。なお、シミュレーションの条件として、基板電圧を０Ｖとし、ソース電圧を０Ｖとし、ゲート電圧を－１０Ｖとし、ドレイン電圧を６００Ｖとしている。 Subsequently, the field plate of FIG. 1 when the concentration of the two-dimensional electron gas is changed while the length L of the field plate portion 6a of the gate electrode 6 is made constant by using the field effect transistor 1 of the present embodiment having the above-described structure. The relationship between the electric field strength at the end 6x of the part 6a and the lifetime of the field effect transistor 1 was verified. For the electric field strength, an electric field simulator (MEDICI) is used, and the result is shown in FIG. As simulation conditions, the substrate voltage is 0 V, the source voltage is 0 V, the gate voltage is −10 V, and the drain voltage is 600 V.

　図３は図１の電界効果トランジスタ１のフィールドプレート部６ａの端部６ｘにおける電界強度と寿命の関係を示すグラフである。図３の縦軸は電界効果トランジスタ１の寿命（ｈ）を示し、横軸は図１のフィールドプレート部６ａの端部６ｘの電界強度（ＭＶ／ｃｍ）を示している。 FIG. 3 is a graph showing the relationship between the electric field strength and the life at the end 6x of the field plate portion 6a of the field effect transistor 1 of FIG. The vertical axis in FIG. 3 represents the lifetime (h) of the field effect transistor 1, and the horizontal axis represents the electric field strength (MV / cm) at the end 6x of the field plate portion 6a in FIG.

　図３によれば、実際の使用に耐え得る構成の指標となるＯＦＦ時のドレイン電圧６００Ｖ、ジャンクション温度１５０℃における寿命時間１０００時間を達成するためには、図１の電界効果トランジスタ１の、フィールドプレート部６ａのドレイン電極側の端部６ｘにおける電界強度が６．９ＭＶ／ｃｍ以下となる必要がある。 According to FIG. 3, in order to achieve a lifetime of 1000 hours at an OFF drain voltage of 600 V and a junction temperature of 150 ° C., which is an index of a configuration that can withstand actual use, the field effect transistor 1 of FIG. The electric field strength at the end 6x on the drain electrode side of the plate portion 6a needs to be 6.9 MV / cm or less.

　続いて、これらの検証を総合した結果を、図４を用いて説明する。 Subsequently, the result of integrating these verifications will be described with reference to FIG.

　図４は電界効果トランジスタ１の２次元電子ガス濃度及びゲート電極６のフィールドプレート部６ａの長さＬと図１の電界効果トランジスタ１の端部１２ｘ及び端部６ｘについての電界効果トランジスタ１の寿命に関する制約との関係を示すグラフである。図４の縦軸はゲート電極６のフィールドプレート部６ａの長さ（μｍ）を示し、横軸は２次元電子ガスの濃度（×１０12／ｃｍ2）を示している。 4 shows the two-dimensional electron gas concentration of the field effect transistor 1, the length L of the field plate portion 6a of the gate electrode 6, and the lifetime of the field effect transistor 1 at the end 12x and the end 6x of the field effect transistor 1 of FIG. It is a graph which shows the relationship with the restrictions regarding. 4 indicates the length (μm) of the field plate portion 6a of the gate electrode 6, and the horizontal axis indicates the concentration of the two-dimensional electron gas (× 10 12 / cm 2 ).

　図４に、図１の電界効果トランジスタ１の第２絶縁膜１２の端部１２ｘについての電界効果トランジスタ１の寿命に関する制約を破線で描画している。さらに図４に、図１の電界効果トランジスタ１のフィールドプレート部６ａの端部６ｘについての電界効果トランジスタ１の寿命に関する制約を一点鎖線で描画している。 FIG. 4 shows a restriction regarding the lifetime of the field effect transistor 1 at the end 12x of the second insulating film 12 of the field effect transistor 1 of FIG. Further, in FIG. 4, restrictions on the lifetime of the field effect transistor 1 at the end 6 x of the field plate portion 6 a of the field effect transistor 1 of FIG.

　図４によれば、実際の使用に耐え得る構成の指標となるＯＦＦ時のドレイン電圧６００Ｖ、ジャンクション温度１５０℃における寿命時間１０００時間を達成するためには、ゲート電極６のフィールドプレート部６ａが、２次元電子ガスの濃度に応じて、図４の網掛け領域に対応した長さＬである必要がある。例えば、２次元電子ガスの濃度を５．５×１０12／ｃｍ2とした場合、図４によればフィールドプレート部６ａの長さＬは設計のバラツキを考慮して２．０μｍとすることが好ましい。 According to FIG. 4, in order to achieve a lifetime of 1000 hours at an OFF drain voltage of 600 V and a junction temperature of 150 ° C., which is an index of a configuration that can withstand actual use, the field plate portion 6 a of the gate electrode 6 includes: Depending on the concentration of the two-dimensional electron gas, the length L needs to correspond to the shaded area in FIG. For example, when the concentration of the two-dimensional electron gas is 5.5 × 10 12 / cm 2 , according to FIG. 4, the length L of the field plate portion 6a is set to 2.0 μm in consideration of design variations. preferable.

　上記のように、複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極６を形成し、窒化物半導体中に２次元電子ガスが分布する電界効果トランジスタ１において、窒化物半導体の表面上に形成した開口１１ａを有する第１絶縁膜１１と、第１絶縁膜１１の開口１１ａの領域及び開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓを除き第１絶縁膜１１の表面上に形成した第２絶縁膜１２と、開口１１ａの領域及び開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓを含み第１絶縁膜１１及び第２絶縁膜１２の表面上に形成した第３絶縁膜１３と、開口１１ａの領域及び開口１１ａの縁部から所定距離Ｄ離隔した領域Ｓを中心とした第３絶縁膜１３の表面上に形成したゲート電極６と、第３絶縁膜１３の表面上でゲート電極６からドレイン電極側に突き出したフィールドプレート部６ａと、を備える。そして、図４に矩形の範囲Ｆ１として示したように、窒化物半導体中の２次元電子ガス濃度が６．５×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極側に突き出したフィールドプレート部６ａの端部までの長さＬが１．８μｍ以上２．２μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 As described above, in the field effect transistor 1 in which the source electrode, the drain electrode, and the gate electrode 6 are formed on the surface side where a plurality of nitride semiconductors are stacked, and the two-dimensional electron gas is distributed in the nitride semiconductor, Except for the first insulating film 11 having an opening 11a formed on the surface of the semiconductor, the region of the opening 11a of the first insulating film 11 and the region S separated by a predetermined distance D from the edge of the opening 11a, the first insulating film 11 The second insulating film 12 formed on the surface and the region of the opening 11a and the region S separated from the edge of the opening 11a by a predetermined distance D are formed on the surfaces of the first insulating film 11 and the second insulating film 12. The third insulating film 13, the gate electrode 6 formed on the surface of the third insulating film 13 around the region S of the opening 11a and the region S separated from the edge of the opening 11a by a predetermined distance D, and the third insulating film 13 On the surface It includes a field plate portion 6a protruding to the drain electrode side from the gate electrode 6, a. 4, the two-dimensional electron gas concentration in the nitride semiconductor is 6.5 × 10 12 / cm 2 or less, and the edge of the opening 11a of the first insulating film 11 is shown as a rectangular range F1. The length L from the end of the field plate portion 6a protruding to the drain electrode side is 1.8 μm or more and 2.2 μm or less. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　また、上記構成の電界効果トランジスタ１において、図４に矩形の範囲Ｆ２として示したように、窒化物半導体中の２次元電子ガス濃度が６．３×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極側に突き出したフィールドプレート部６ａの端部までの距離Ｌが１．６μｍ以上２．４μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above configuration, as shown as a rectangular range F2 in FIG. 4, the two-dimensional electron gas concentration in the nitride semiconductor is 6.3 × 10 12 / cm 2 or less, and the first The distance L from the edge of the opening 11a of the insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode is 1.6 μm or more and 2.4 μm or less. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　また、上記構成の電界効果トランジスタ１において、図４に矩形の範囲Ｆ３として示したように、窒化物半導体中の２次元電子ガス濃度が６．０×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極側に突き出したフィールドプレート部６ａの端部までの距離Ｌが１．３μｍ以上２．９μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above-described configuration, the two-dimensional electron gas concentration in the nitride semiconductor is 6.0 × 10 12 / cm 2 or less as shown as a rectangular range F3 in FIG. The distance L from the edge of the opening 11a of the insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode is 1.3 μm or more and 2.9 μm or less. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　また、上記構成の電界効果トランジスタ１において、図４に矩形の範囲Ｆ４として示したように、窒化物半導体中の２次元電子ガス濃度が５．５×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極側に突き出したフィールドプレート部６ａの端部までの距離Ｌが１．０μｍ以上３．８μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above-described configuration, the two-dimensional electron gas concentration in the nitride semiconductor is not more than 5.5 × 10 12 / cm 2 as shown by a rectangular range F4 in FIG. The distance L from the edge of the opening 11a of the insulating film 11 to the end of the field plate portion 6a protruding to the drain electrode side is 1.0 μm or more and 3.8 μm or less. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　次に、図６に示す電界効果トランジスタ１のゲートドレイン間距離ＬＧＤを１５μｍ以上とした場合について説明する。図６は電界効果トランジスタ１の断面図であって、図１に対してドレイン電極７及びソース電極８の領域まで描画した断面図である。 Next, a case where the gate-drain distance LGD of the field effect transistor 1 shown in FIG. 6 is set to 15 μm or more will be described. FIG. 6 is a cross-sectional view of the field effect transistor 1, and is a cross-sectional view drawn up to the drain electrode 7 and source electrode 8 regions with respect to FIG.

　ドレイン電極７及びソース電極８はゲート電極６と同様にＡｌＧａＮ障壁層５の表面に形成される。第１絶縁膜１１はドレイン電極７の下方に非被膜部１１ｂを有し、ＡｌｙＧａＮ障壁層５の表面に対して局部的に覆っていない領域を有する。ドレイン電極７は第１絶縁膜１１の非被膜部１１ｂの領域の上方であってＡｌｙＧａＮ障壁層５、第１絶縁膜１１及び第２絶縁膜１２の表面上に形成される。そして、第１絶縁膜１１の開口１１ａ側の縁部から非被膜部１１ｂ側の縁部までの距離がゲートドレイン間距離ＬＧＤである。 The drain electrode 7 and the source electrode 8 are formed on the surface of the AlGaN barrier layer 5 similarly to the gate electrode 6. The first insulating film 11 has a non-coating portion 11 b below the drain electrode 7 and has a region that does not locally cover the surface of the AlyGaN barrier layer 5. The drain electrode 7 is formed on the surface of the AlyGaN barrier layer 5, the first insulating film 11, and the second insulating film 12 above the region of the non-coating portion 11 b of the first insulating film 11. The distance from the edge on the opening 11a side of the first insulating film 11 to the edge on the non-coating portion 11b side is the gate-drain distance LGD.

　続いて、図６に示す電界効果トランジスタ１のゲートドレイン間距離ＬＧＤを１５μｍ以上とした場合の検証を総合した結果を、図７を用いて説明する。 Subsequently, a result obtained by integrating the verification in the case where the gate-drain distance LGD of the field effect transistor 1 shown in FIG. 6 is set to 15 μm or more will be described with reference to FIG.

　図７は、図６に示す電界効果トランジスタ１のゲートドレイン間距離ＬＧＤを１５μｍ以上とした場合の、電界効果トランジスタ１の２次元電子ガス濃度及びゲート電極６のフィールドプレート部６ａの長さＬと図６の電界効果トランジスタ１の端部１２ｘ及び端部６ｘについての電界効果トランジスタ１の寿命に関する制約との関係を示すグラフである。図７の縦軸はゲート電極６のフィールドプレート部６ａの長さ（μｍ）を示し、横軸は２次元電子ガスの濃度（×１０12／ｃｍ2）を示している。この領域は電界強度を電界シミュレータ（ＭＥＤＩＣＩ）を使用し求め、シミュレーションの条件として基板電圧を０Ｖとし、ソース電圧を０Ｖとし、ゲート電圧を－１０Ｖとし、ドレイン電圧を６００Ｖとしている。 7 shows the two-dimensional electron gas concentration of the field effect transistor 1 and the length L of the field plate portion 6a of the gate electrode 6 when the gate-drain distance LGD of the field effect transistor 1 shown in FIG. It is a graph which shows the relationship with the restrictions regarding the lifetime of the field effect transistor 1 about the edge part 12x and the edge part 6x of the field effect transistor 1 of FIG. The vertical axis in FIG. 7 indicates the length (μm) of the field plate portion 6a of the gate electrode 6, and the horizontal axis indicates the concentration of the two-dimensional electron gas (× 10 12 / cm 2 ). In this region, the electric field strength is obtained using an electric field simulator (MEDICI), and the substrate voltage is 0 V, the source voltage is 0 V, the gate voltage is −10 V, and the drain voltage is 600 V as simulation conditions.

　図７に、図６の電界効果トランジスタ１の第２絶縁膜１２の端部１２ｘについての電界効果トランジスタ１の寿命に関する制約を破線で描画している。さらに図７に、図６の電界効果トランジスタ１のフィールドプレート部６ａの端部６ｘについての電界効果トランジスタ１の寿命に関する制約を一点鎖線で描画している。 In FIG. 7, a restriction regarding the lifetime of the field effect transistor 1 at the end 12 x of the second insulating film 12 of the field effect transistor 1 of FIG. 6 is drawn by a broken line. Further, in FIG. 7, restrictions on the lifetime of the field effect transistor 1 at the end portion 6x of the field plate portion 6a of the field effect transistor 1 in FIG.

　図７によれば、実際の使用に耐え得る構成の指標となるＯＦＦ時のドレイン電圧６００Ｖ、ジャンクション温度１５０℃における寿命時間１０００時間を達成するためには、ゲート電極６のフィールドプレート部６ａが、２次元電子ガスの濃度に応じて、図７の網掛け領域に対応した長さＬである必要がある。例えば、２次元電子ガスの濃度を６．５×１０12／ｃｍ2とした場合、図７によればフィールドプレート部６ａの長さＬは設計のバラツキを考慮して２．５μｍとすることが好ましい。 According to FIG. 7, in order to achieve a lifetime of 1000 hours at an OFF drain voltage of 600 V and a junction temperature of 150 ° C., which is an index of a configuration that can withstand actual use, the field plate portion 6a of the gate electrode 6 includes: Depending on the concentration of the two-dimensional electron gas, the length L needs to correspond to the shaded area in FIG. For example, when the concentration of the two-dimensional electron gas is 6.5 × 10 12 / cm 2 , according to FIG. 7, the length L of the field plate portion 6a is set to 2.5 μm in consideration of design variations. preferable.

　また、上記構成の電界効果トランジスタ１において、図６のゲートドレイン間距離ＬＧＤが１５μｍ以上であり、図７に矩形の範囲Ｆ５として示したように、窒化物半導体中の２次元電子ガス濃度が６．５×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極７側に突き出したフィールドプレート部６ａの端部までの距離Ｌが１．１μｍ以上４．５μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above configuration, the gate-drain distance LGD in FIG. 6 is 15 μm or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 6 as shown as a rectangular range F5 in FIG. 5 × 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 1.1 μm or more and 4.5 μm It is as follows. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　また、上記構成の電界効果トランジスタ１において、図６のゲートドレイン間距離ＬＧＤが１５μｍ以上であり、図７に矩形の範囲Ｆ６として示したように、窒化物半導体中の２次元電子ガス濃度が７．０×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極７側に突き出したフィールドプレート部６ａの端部までの距離Ｌが１．４μｍ以上３．５μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above configuration, the gate-drain distance LGD in FIG. 6 is 15 μm or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 7 as shown as a rectangular range F6 in FIG. 0.0 × 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 1.4 μm or more and 3.5 μm. It is as follows. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　また、上記構成の電界効果トランジスタ１において、図６のゲートドレイン間距離ＬＧＤが１５μｍ以上であり、図７に矩形の範囲Ｆ７として示したように、窒化物半導体中の２次元電子ガス濃度が７．３×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極７側に突き出したフィールドプレート部６ａの端部までの距離Ｌが１．８μｍ以上２．９μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above configuration, the gate-drain distance LGD in FIG. 6 is 15 μm or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 7 as shown as a rectangular range F7 in FIG. 3 × 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 1.8 μm or more and 2.9 μm. It is as follows. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　また、上記構成の電界効果トランジスタ１において、図６のゲートドレイン間距離ＬＧＤが１５μｍ以上であり、図７に矩形の範囲Ｆ８として示したように、窒化物半導体中の２次元電子ガス濃度が７．５×１０12／ｃｍ2以下であり、第１絶縁膜１１の開口１１ａの縁部からドレイン電極７側に突き出したフィールドプレート部６ａの端部までの距離Ｌが２．０μｍ以上２．７μｍ以下である。これにより、端部１２ｘにおいて、第１絶縁膜１１及び第３絶縁膜１３にかかる電界強度を低減させることができる。さらに、端部６ｘにおいて、第１絶縁膜１１及び第２絶縁膜１２にかかる電界強度を低減させることができる。したがって、長時間使用しても絶縁破壊の生じない信頼性の高い電界効果トランジスタ１を提供することができる。 Further, in the field effect transistor 1 having the above configuration, the gate-drain distance LGD in FIG. 6 is 15 μm or more, and the two-dimensional electron gas concentration in the nitride semiconductor is 7 as shown as a rectangular range F8 in FIG. 5 × 10 12 / cm 2 or less, and the distance L from the edge of the opening 11a of the first insulating film 11 to the end of the field plate portion 6a protruding toward the drain electrode 7 is 2.0 μm or more and 2.7 μm. It is as follows. Thereby, the electric field intensity concerning the 1st insulating film 11 and the 3rd insulating film 13 can be reduced in the edge part 12x. Furthermore, the electric field strength applied to the first insulating film 11 and the second insulating film 12 can be reduced at the end 6x. Therefore, it is possible to provide a highly reliable field effect transistor 1 that does not cause dielectric breakdown even when used for a long time.

　このようにして、本発明の上記実施形態の構成によれば、実際の使用に耐え得る構成の電界効果トランジスタ１を提供することができる。 Thus, according to the configuration of the above-described embodiment of the present invention, the field effect transistor 1 having a configuration that can withstand actual use can be provided.

　以上、本発明の実施形態及び実施例につき説明したが、本発明の範囲はこれらに限定されるものではなく、発明の主旨を逸脱しない範囲で種々の変更を加えて実施することができる。 Although the embodiments and examples of the present invention have been described above, the scope of the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the invention.

　本発明は窒化物半導体素子において利用可能である。 The present invention can be used in nitride semiconductor devices.

　　　１　　電界効果トランジスタ（窒化物半導体素子）
　　　２　　基板
　　　３　　バッファ層
　　　４　　ＧａＮチャネル層
　　　５　　ＡｌＧａＮ障壁層
　　　６　　ゲート電極
　　　６ａ　　フィールドプレート部
　　　６ｘ　　端部
　　　１１　　第１絶縁膜
　　　１１ａ　　開口
　　　１２　　第２絶縁膜
　　　１２ｘ　　端部
　　　１３　　第３絶縁膜 1 Field Effect Transistor (Nitride Semiconductor Device)
2 substrate 3 buffer layer 4 GaN channel layer 5 AlGaN barrier layer 6 gate electrode 6a field plate portion 6x end portion 11 first insulating film 11a opening 12 second insulating film 12x end portion 13 third insulating film

Claims (8)

　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が６．５×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．８μｍ以上２．２μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 6.5 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film toward the drain electrode side A nitride semiconductor device, wherein the distance to the portion is 1.8 μm or more and 2.2 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が６．３×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．６μｍ以上２．４μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 6.3 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film toward the drain electrode side A nitride semiconductor device, wherein a distance to the portion is 1.6 μm or more and 2.4 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が６．０×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．３μｍ以上２．９μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 6.0 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film toward the drain electrode side A nitride semiconductor device having a distance to the portion of 1.3 μm or more and 2.9 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が５．５×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．０μｍ以上３．８μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 5.5 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film toward the drain electrode side A nitride semiconductor device, wherein the distance to the portion is 1.0 μm or more and 3.8 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が６．５×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．１μｍ以上４．５μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 6.5 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film toward the drain electrode side A nitride semiconductor device, wherein a distance to the portion is 1.1 μm or more and 4.5 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が７．０×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．４μｍ以上３．５μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 7.0 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film toward the drain electrode side A nitride semiconductor device, wherein a distance to the portion is 1.4 μm or more and 3.5 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が７．３×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が１．８μｍ以上２．９μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 7.3 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film to the drain electrode side A nitride semiconductor device, wherein the distance to the portion is 1.8 μm or more and 2.9 μm or less. 　複数の窒化物半導体を積層したその表面側にソース電極、ドレイン電極及びゲート電極を形成し、前記窒化物半導体中に２次元電子ガスが分布する窒化物半導体素子であって、
　前記窒化物半導体の表面上に形成した開口を有する第１絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を除き前記第１絶縁膜の表面上に形成した第２絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を含み前記第１絶縁膜及び前記第２絶縁膜の表面上に形成した第３絶縁膜と、
　前記第１絶縁膜の前記開口の領域及び前記開口の縁部から所定距離離隔した領域を中心とした前記第３絶縁膜の表面上に形成した前記ゲート電極と、
　前記第３絶縁膜の表面上で前記ゲート電極から前記ドレイン電極側に突き出したフィールドプレート部と、
を備え、
　前記窒化物半導体中の２次元電子ガス濃度が７．５×１０12／ｃｍ2以下であり、前記第１絶縁膜の前記開口の縁部から前記ドレイン電極側に突き出した前記フィールドプレート部の端部までの距離が２．０μｍ以上２．７μｍ以下であることを特徴とする窒化物半導体素子。 A nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a surface side of a plurality of nitride semiconductors stacked, and a two-dimensional electron gas is distributed in the nitride semiconductor,
A first insulating film having an opening formed on the surface of the nitride semiconductor;
A second insulating film formed on the surface of the first insulating film excluding a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
A third insulating film formed on the surface of the first insulating film and the second insulating film, including a region of the opening of the first insulating film and a region separated by a predetermined distance from an edge of the opening;
The gate electrode formed on the surface of the third insulating film centered on the region of the opening of the first insulating film and a region separated by a predetermined distance from the edge of the opening;
A field plate portion protruding from the gate electrode to the drain electrode side on the surface of the third insulating film;
With
The two-dimensional electron gas concentration in the nitride semiconductor is 7.5 × 10 12 / cm 2 or less, and an end of the field plate portion protruding from the edge of the opening of the first insulating film to the drain electrode side A nitride semiconductor device, wherein the distance to the portion is 2.0 μm or more and 2.7 μm or less.
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JP2011142182A (en) * 2010-01-06 2011-07-21 Sharp Corp Field-effect transistor
JP2011243978A (en) * 2010-04-23 2011-12-01 Advanced Power Device Research Association Nitride semiconductor device

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