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WO2014008160A3 - Mise à l'échelle d'une pile à structure ono sonos - Google Patents

Mise à l'échelle d'une pile à structure ono sonos Download PDF

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Publication number
WO2014008160A3
WO2014008160A3 PCT/US2013/048874 US2013048874W WO2014008160A3 WO 2014008160 A3 WO2014008160 A3 WO 2014008160A3 US 2013048874 W US2013048874 W US 2013048874W WO 2014008160 A3 WO2014008160 A3 WO 2014008160A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
scaling
oxygen
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2013/048874
Other languages
English (en)
Other versions
WO2014008160A2 (fr
Inventor
Fredrick Jenne
Sagy Levy
Krishnaswamy Ramkumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/539,461 external-priority patent/US9299568B2/en
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Priority to KR1020147035194A priority Critical patent/KR102159845B1/ko
Priority to CN201380032545.4A priority patent/CN104769721A/zh
Publication of WO2014008160A2 publication Critical patent/WO2014008160A2/fr
Publication of WO2014008160A3 publication Critical patent/WO2014008160A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

La présente invention a trait à un procédé permettant de mettre à l'échelle un dispositif de mémoire à charge piégée non volatile et au dispositif obtenu au moyen dudit procédé. Selon un mode de réalisation, le procédé inclut une étape consistant à former une région de canal qui inclut du polysilicium et qui est électriquement connectée à une région de source et à une région de drain dans un substrat. Une couche à effet tunnel est formée sur le substrat au-dessus de la région de canal grâce à l'oxydation du substrat en vue de former un film d'oxyde et à la nitruration du film d'oxyde. Une couche de piégeage de charge multicouche qui inclut une première couche riche en oxygène et une seconde couche pauvre en oxygène et formée sur la couche à effet tunnel, et une couche d'appauvrissement est déposée sur la couche de piégeage de charge multicouche. Selon un mode de réalisation, le procédé inclut en outre une oxydation humide diluée permettant de densifier un oxyde de blocage déposé et d'oxyder une partie de la seconde couche pauvre en oxygène.
PCT/US2013/048874 2012-07-01 2013-07-01 Mise à l'échelle d'une pile à structure ono sonos Ceased WO2014008160A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020147035194A KR102159845B1 (ko) 2012-07-01 2013-07-01 Ｓｏｎｏｓ ｏｎｏ 스택 스케일링
CN201380032545.4A CN104769721A (zh) 2012-07-01 2013-07-01 Sonos ono 叠层改进

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/539,461 2012-07-01
US13/539,461 US9299568B2 (en) 2007-05-25 2012-07-01 SONOS ONO stack scaling

Publications (2)

Publication Number Publication Date
WO2014008160A2 WO2014008160A2 (fr) 2014-01-09
WO2014008160A3 true WO2014008160A3 (fr) 2014-02-27

Family

ID=49882582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/048874 Ceased WO2014008160A2 (fr) 2012-07-01 2013-07-01 Mise à l'échelle d'une pile à structure ono sonos

Country Status (4)

Country Link
KR (1) KR102159845B1 (fr)
CN (1) CN104769721A (fr)
TW (1) TWI604595B (fr)
WO (1) WO2014008160A2 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6420614B2 (ja) * 2014-09-30 2018-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10256288B2 (en) * 2015-10-20 2019-04-09 National Institute Of Advanced Industrial Science And Technology Nonvolatile memory device
EP4009361B1 (fr) * 2016-12-05 2025-02-19 GlobalWafers Co., Ltd. Structure de silicium sur isolant à haute résistivité
JP2018157035A (ja) * 2017-03-16 2018-10-04 東芝メモリ株式会社 半導体装置、およびその製造方法
CN109003879B (zh) * 2017-06-06 2021-03-19 中芯国际集成电路制造(上海)有限公司 栅介质层的形成方法
CN110838496B (zh) * 2018-08-17 2023-04-07 旺宏电子股份有限公司 存储器元件及其制造方法
CN109346528B (zh) * 2018-09-27 2022-03-29 上海华力微电子有限公司 闪存结构及对应的编程、擦除和读取方法
KR102653530B1 (ko) * 2018-12-27 2024-04-02 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그 제조 방법
US12195846B2 (en) 2019-08-07 2025-01-14 Applied Materials, Inc. Modified stacks for 3D NAND
CN114242732A (zh) * 2020-01-14 2022-03-25 长江存储科技有限责任公司 包括具有经调节的氮重量百分比的隧穿层的沟道结构及其形成方法
TWI812974B (zh) * 2020-09-04 2023-08-21 日商鎧俠股份有限公司 半導體記憶裝置
JP2022043897A (ja) 2020-09-04 2022-03-16 キオクシア株式会社 半導体記憶装置
CN114300471A (zh) * 2021-12-30 2022-04-08 长江存储科技有限责任公司 三维存储器及其制作方法
US20240266414A1 (en) * 2023-02-07 2024-08-08 Applied Materials, Inc. Multi-vt integration scheme for semiconductor devices

Citations (8)

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Publication number Priority date Publication date Assignee Title
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
US6469343B1 (en) * 1998-04-02 2002-10-22 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US20080290400A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation SONOS ONO stack scaling
US20080290399A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US20110018053A1 (en) * 2007-12-07 2011-01-27 Agency For Science, Technology And Research Memory cell and methods of manufacturing thereof
US20110163371A1 (en) * 2005-09-15 2011-07-07 Song Ki-Whan Methods of fabricating nonvolatile semiconductor memory devices
US20120068159A1 (en) * 2010-09-16 2012-03-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
US8163660B2 (en) * 2008-05-15 2012-04-24 Cypress Semiconductor Corporation SONOS type stacks for nonvolatile change trap memory devices and methods to form the same

Family Cites Families (3)

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Publication number Priority date Publication date Assignee Title
KR100501457B1 (ko) * 2003-02-04 2005-07-18 동부아남반도체 주식회사 양자 트랩 디바이스를 위한 에스오엔오엔오에스 구조를 갖는 반도체 소자
KR100885910B1 (ko) * 2003-04-30 2009-02-26 삼성전자주식회사 게이트 적층물에 ｏｈａ막을 구비하는 비 휘발성 반도체메모리 장치 및 그 제조방법
KR102061253B1 (ko) * 2012-03-27 2019-12-31 롱지튜드 플래쉬 메모리 솔루션즈 리미티드 스플릿 질화물 메모리 층을 갖는 ｓｏｎｏｓ 스택

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
US6469343B1 (en) * 1998-04-02 2002-10-22 Nippon Steel Corporation Multi-level type nonvolatile semiconductor memory device
US20110163371A1 (en) * 2005-09-15 2011-07-07 Song Ki-Whan Methods of fabricating nonvolatile semiconductor memory devices
US20080290400A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation SONOS ONO stack scaling
US20080290399A1 (en) * 2007-05-25 2008-11-27 Cypress Semiconductor Corporation Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
US20110018053A1 (en) * 2007-12-07 2011-01-27 Agency For Science, Technology And Research Memory cell and methods of manufacturing thereof
US8163660B2 (en) * 2008-05-15 2012-04-24 Cypress Semiconductor Corporation SONOS type stacks for nonvolatile change trap memory devices and methods to form the same
US20120068159A1 (en) * 2010-09-16 2012-03-22 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device

Also Published As

Publication number Publication date
KR102159845B1 (ko) 2020-09-25
TWI604595B (zh) 2017-11-01
TW201405717A (zh) 2014-02-01
KR20150040805A (ko) 2015-04-15
WO2014008160A2 (fr) 2014-01-09
CN104769721A (zh) 2015-07-08

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