WO2014007583A1 - Apparatus and method for enhancing performance of fpga-based true random number generator - Google Patents

Description

Apparatus and Method for Improving the Performance of FXP-based True Random Number Generator

The present invention relates to a random number generator, and in particular, when generating a random bit sequence using a field-programmable gate array (FPGA), an FPGA-based true random number generator for improving random characteristics and increasing throughput The present invention relates to an apparatus and a method for improving performance.

Random numbers are an essential element in encryption and are used in generating secret values, generating public keys in public key infrastructure (PKI), creating digital signatures, or in authentication protocols. In this case, there are two methods for generating random: a method of generating pseudorandom numbers similar to a random number, and a method of generating a true randon number that generates a true random value that is unpredictable and unreproducible. do.

The pseudo-random number is not enough to be used in a similar form to random numbers in a non-encryption general application program, but care should be taken when used in encryption. In other words, pseudorandom numbers are only numbers that are similar to random numbers and are predictable and reproducible, which can be a serious vulnerability when used in encryption. Therefore, in order for a random number to be used for encryption, it must be generated from a true random number generator (TRNG).

The true random number generator (TRNG) can also be implemented using a field-programmable gate array (FPGA). FPGAs can be developed quickly and are frequently used due to their ease of use. In particular, there are many ways to implement a true random number generator using an FPGA, but a ring-oscillator that forms loops using an odd number of inverters and samples the loop output at a specific point in time. The way is typical.

In contrast, a method of using a metastabillty caused by the setup time and hold time characteristics of the D flip-flop (FF) has emerged. This is a method of applying a clock signal to the D pin and the CLK pin of the D flip-flop at the same time, so that the same signal is applied to the two pins almost simultaneously, so that the output value is determined by the minute difference between the two signals.

Among the recently proposed methods, a method of using a delay as an adjustable buffer (or inverter) using a look up table (LUT) inside an FPGA chip has been proposed.

1 is a circuit diagram showing the abstract architecture of the LUT that may be to produce two to ^three output via the three input signals, the structure of the LUT such as that shown in Figure 1, 2 that can store one bit according to the value in the ^three space in the input signal I _1, I _2, I _3, and structure for selecting and outputting each bit, is to implement a number of logic gates through which.

FIG. 2 is a block diagram illustrating a delay-adjustable buffer utilizing the structure of FIG. 1, and a value '0101 0101' should be set in the SRAM of the LUT. When the I ₁ input becomes a portion corresponding to the input of the buffer, the output O becomes '0' or '1' by the I ₁ value regardless of I ₂ and I ₃ . I ₂ and I ₃ do not affect the output value, but determine the path through which the value selected by I ₁ is delivered to the output (O), which is the delay from the input I ₁ to the output (O). Is the element that changes.

The total number of paths determined by I ₂ and I ₃ is four. Recently developed FPGA chips also include LUTs with six inputs. An LUT with N input signal LUT indicated as _N, and if _N is the LUT have the 2 ^N-1 of paths at the time of implementation by PDB. The path control signal, which can be made of signals other than I ₁ , is designated as I, and I = (I ₂ , I ₃ , ..., I _N ). The input value with the longest delay of the path is denoted as I _L , and the input value with the shortest delay is called I _S. When the inputs are I _L and I _S , the largest delay difference can be obtained. If a plurality of them are connected in series as shown in FIG.

In general, in the implementation of a LUT in an FPGA chip, the LUT is fabricated using the same transistor-level cell for constructing the LUT. Therefore, the change according to the position of the LUT in the chip is small and the chip in the semiconductor die is small. Depending on the location, the effect is small. Therefore, the characteristics of the delay according to the input value tend to be similar in almost all cells.

4 is a diagram illustrating a true random number generator implemented using the PDB described above. As shown in FIG. 4, a PDB is serially connected to the D input and the CLK input path of FF to configure a path, respectively. If the number of PDBs arranged in two paths is the same and the paths are routed identically, the same clock signal is applied to both paths at the same time. Therefore, in the FF, which signal comes in due to the minute difference between the upper path and the lower path. In some cases, the output of FF may be zero or 1. If the rising edge of the clock reaches the upper path first, the output of FF will be 1, and if it reaches the lower path first, the output will be zero.

5A and 5B are diagrams for describing a metastabillty that may occur in the FF. By using the characteristics as shown in FIGS. 5A and 5B to make the FF pseudo-stable, a random bit output can be obtained. In FIG. 4, a binary counter and a decoder are necessary elements for PI-Control. The binary counter is a counter that increments if the output of FF is 1 and decrements if it is zero. In the ideal case, when the value of the counter is 0, the upper path and the lower path have the same length, and thus, the state becomes pseudo stable. If the counter value is increased here, the increased counter value acts as an error of pseudo-stable state, and again increases the delay of the upper path or decreases the delay of the lower path so that the counter value decreases. The control is to turn to the stable state. In addition, when the counter value decreases in the pseudo-stable state, control is performed to reduce the delay of the upper path or increase the delay of the lower path to return to the pseudo-stable state. By doing this, you maintain a stable state. At this time, the form of the counter and the form of the decoder may exist in various ways and are not specific.

However, in the operation of the above circuit, since the upper path and the lower path are not exactly the same, the pseudo stable state occurs at the counter value other than 0, and the pseudo stable state is maintained through PI-Control. The counter value continues to increase and decrease at the counter value, and rises and falls at the counter value in the specified range.

As described above, in the case of the FPGA-based TRNG proposed by the PDB and PI-Control, the similar stability is maintained by going up and down in the specific counter range as described above due to the characteristics of the PI-Control. As a result, a problem arises that a fixed value is always output at the edge value of the range where the counter increases or decreases, rather than the value of the pseudo stable state. For example, the maximum value of the counter tends to always output 1, and the minimum value tends to always output 0. Therefore, in a general case, it is difficult to obtain a random sequence to be obtained due to the output of the non-metastable state, and a filter for removing the output of the non-stable state is used. However, when such a filter is used, some sequences of the output cannot be used, which reduces the overall throughput and makes the TRNG inefficient.

Accordingly, the present invention has been made to solve the above problems, when generating a random bit sequence using a field-programmable gate array (FPGA), FPGA for improving the random characteristics and increase the throughput (throughput) An object of the present invention is to provide an apparatus and method for improving the performance of a true random number generator.

It is another object of the present invention to provide an apparatus and method for improving the performance of an FPGA-based true random number generator that can guarantee sufficient randomness by allowing a TRNG to remain in a metastable state for a long time without a filter. .

Another object of the present invention is to ensure randomness by minimizing the number of outputs deflected and outputted in the present invention, unlike the technique used in the existing true random number generator, which prevents the output of the outputs deflected and outputted. To provide an apparatus and method for improving the performance of an FPGA-based true random number generator.

A feature of the apparatus for improving the performance of an FPGA-based true random number generator capable of guaranteeing randomness according to the present invention for achieving the above object is the input of the data pin path and clock pin path of the flip-flop. A TRNG module for injecting clock signals at the same time and controlling the delay time of each path through feedback to generate a random sequence that is metastable according to the time difference of the corresponding signal reaching each pin; and the TRNG It includes a TRNG output control unit that stores the state information output from the module, and controls the time it is possible to maintain the quasi-stable state (metastable) output of the TRNG module through this.

Preferably, the TRNG module includes a flip-flop (FF) for outputting a random value, a PDB path unit for controlling delay times of the data pin path and the clock pin path of the flip-flop, and an output of the flip-flop. The binary counter outputs a counter value that increases or decreases depending on whether it is 1 or 0, and the delay of the data pin path and the clock pin path is controlled by the feedback control from the counter value output from the binary counter. It characterized in that it comprises a decoder for adjusting the delay in the same direction.

Preferably, the TRNG output control unit includes a memory for storing a history of a current state and an output according to the state of the TRNG module, a memory for storing a history of a random sequence output for a counter value of the binary counter, An address predictor that predicts what the next counter value is by checking the counter value of the binary counter and the random output value of the current flip-flop, and the history of the corresponding counter value output from the address predictor. Hamming weight calculator that analyzes how evenly the counter values are distributed, and down counter initializer that allocates time slots that can be used by counter values output from binary counters using information analyzed by Hamming weight calculator. And a time slot allocated from the down counter initializer as an initial value. It characterized in that the input received comprises a down counter, and a comparator to zero when the output from the down counter value of 0 is to update the counter value of the binary counter for every clock each time decrement the value by one.

Preferably, the TRNG output controller receives a counter value output from a binary counter and outputs a row enable signal of a memory so that a value can be stored in a storage of a corresponding memory whenever an output is output from a flip-flop for random output. And a mux outputting the row enable decoder and a history of the counter value predicted by the address predictor 210 to the hamming weight calculator.

Preferably, the memory is configured as a storage space of the cache memory, so that the history of the output can be stored for some states, the history is stored in the memory using only some information of each state, and this value is restored using only the state partial information. It is characterized by recovering.

In order to achieve the above object, a method for improving performance of an FPGA-based true random number generator capable of guaranteeing randomness according to the present invention is characterized by (A) data pin path and clock pin path of flip-flop. Injecting clock signals and simultaneously injecting clock signals, and controlling delay times of the respective paths through feedback to output random sequences which are metastable according to the time difference between the signals reaching each pin; (B) storing the state information of the output random sequence, and controlling the time to maintain the quasi-stable state of the output of the random sequence output through it.

Preferably, in step (A), the TOP path and the BOTTOM path provided using a PDB are disposed on a flip-flop (FF), and the output of the flip-flop is increased to 1, and decreased to 0. Outputting a counter value, and outputting a pseudostable random sequence based on a time difference at which a corresponding signal reaches each pin by adjusting a delay between a TOP path and a BOTTOM path based on the output counter value. Characterized in that comprises a step.

Preferably, the step (B) comprises the steps of storing a history of the random sequence output for the counter value, checking the current counter value and the current random output value to predict what the next counter value is; Selecting and outputting the history of the predicted counter value, and analyzing how much the counter value is evenly distributed based on the history of the counter value outputted, and outputting the counter value by using the analyzed information Allocating a usable time slot, receiving the allocated time slot as an initial value, decreasing the value by one for each clock, and updating the counter value when the reduced value reaches zero. It is done.

Preferably, when the value of the counter increases in a positive direction, the ratio of 1 in the output is high, which means that the delay of the TOP path is relatively shorter than that of the BOTTOM path, so that the delay of the TOP path is longer or the BOTTOM path is longer. It is characterized in that the control in the direction in which the delay is shortened.

Preferably, the analyzing may include detecting how many 1s of N bits are selected from the Hamming weights for which the selected history value is calculated, and analyzing that the Hamming weights are similarly stable as the Hamming weights are closer to N / 2. It is done.

As described above, an apparatus and method for improving performance of an FPGA-based true random number generator according to the present invention have the following effects.

In the conventional random number generation method, when the counter change trend is very regular and the counter at the edge appears, it is recognized as a factor that destroys randomness, and in this case, the output is not output. However, in the present invention, the edge counter appears. Since the pattern is irregular, it is also absorbed by the elements constituting random and can continue to output in this case, and sufficient randomness is ensured even without a filter, thereby eliminating the decrease in throughput caused by filtering the edge counter value. can do.

1 is a circuit diagram showing the structure of a LUT by abstraction that can be generated by the ²³ output through the third input signal

FIG. 2 is a diagram illustrating a delay adjustable buffer utilizing the structure of FIG. 1. FIG.

3 is a diagram illustrating the structure of FIG. 2 by connecting M PDBs in series;

4 is a block diagram showing a true random number generator implemented using the PDB described above

5A and 5B are diagrams for explaining the metastable state (metastabillty) that may occur in the FF

6 is a block diagram showing a configuration for improving performance of an FPGA-based true random number generator according to an embodiment of the present invention.

7 is a circuit diagram showing in detail the structure of the PDB path portion of FIG.

8 is a diagram showing the structure of a PDB path part of FIG. 1 using LUT3;

9 is a diagram showing the structure of LUT3 of FIG. 8

10A and 10B are graphs showing a method of proposing a probability of outputting 1 for each counter and a conventional method

11A and 11B are graphs showing how many times each counter appeared in the total distribution

12A and 12B are graphs showing the change in the counter value according to the period

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of the apparatus and method for improving performance of an FPGA-based true random number generator according to the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and complete the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various equivalents that may be substituted for them at the time of the present application It should be understood that there may be water and variations.

6 is a block diagram showing a configuration for improving performance of an FPGA-based true random number generator according to an embodiment of the present invention.

As shown in FIG. 6, a true random number generator (TRNG) is a TRNG module 100 for generating a random sequence using a physical data base (PDB) and a PI control, and a stream and a current counter value output from the TRNG module 100. Stored, and based on the TRNG output control unit 200 for controlling the output of the TRNG module 100.

The TRNG module 100 configures a PDB path unit 110 that provides a TOP path and a BOTTOM path using a PDB, and a flip-flop (FF) at the next stage of the PDB path unit 110 ( 120). When the output of the FF 120 is 1, the output is increased. If the output of the FF 120 is 0, the binary counter 140 outputs a counter value, and the counter value is output from the binary counter 140. The decoder 130 is configured to adjust the delay of the TOP path and the BOTTOM path of the PDB path unit 110.

The TRNG output control unit 200 stores a history of the random sequence outputted with respect to the counter value of the binary counter 140 and whenever an output is output from the FF 120 for random output. A row enable decoder 240 for receiving a counter value output from the binary counter 140 and outputting a low enable signal of the memory 250 to store a value in a storage of the corresponding memory 250; The address predictor 210 predicts what the next counter value is by checking the counter value of the binary counter 140 and the random output value of the current FF 120, and the counter value predicted by the address predictor 210. Hamming weight to check the history of the MUX (260) to select and output the history of the corresponding counter value output through the mux 260, and analyzes how evenly distributed the counter value based on this Output (hamming weight calculator) 270 and a down counter initializer 280 that allocates a time slot that can be used by the counter value output from the binary counter 140 using information analyzed by the hamming weight calculator 270. And a down counter 230 that receives a time slot allocated from the down counter initializer 280 as an initial value and decreases the value by one every clock, and when the value output from the down counter 230 becomes 0, And a zero comparator 220 for activating the EN signal to update the counter value of the binary counter 140.

FIG. 7 is a circuit diagram illustrating in detail the structure of the PDB path unit of FIG. 1. FIG.

As shown in FIG. 7, the PDB path unit 110 connects a plurality of PDBs 111 in series to form a TOP path 112 at an upper level and a BOTTOM path 113 at a lower level. In addition, the delay paths 112 and 113 of the PBD may adjust the delay of the entire path by the delay control signals 116 of the respective PDBs 111. Each of the delay control signals 116 is collectively used as a control signal 114 of the TOP path 112 and a control signal 115 of the BOTTOM path 113, which is connected to the decoder 130 and is connected to the TOP path 112. And the delay of the BOTTOM path 113 are controlled from the decoder 130.

FIG. 8 is an embodiment showing the structure of the PDB path portion of FIG. 1 using the LUT3, and FIG. 9 is an embodiment showing the structural diagram of the LUT3 of FIG.

As shown in FIG. 8, LUT3 is a 3-input LUT (Look Up Table) provided by an FPGA chip. The LUT is one of the basic building blocks of an FPGA, and is used to construct combinational circuits required for the chip configuration. Using this, it is possible to create a buffer with adjustable delay.

Referring to FIG. 9, the structural principle of LUT3 is described. If the LUTs have X inputs 111-1, 111-2, and 111-3, LUTX has 2 ^X SRAM storage spaces 111-6. . This value is output to the output O (111-4) through the mux (111-5) of the X stage. At this time, if the value of the SRAM storage space 111-6 is set to '1010 1010' and the inputs I ₁ (111-1), I ₂ (111-2), and I ₃ (111-3) are adjusted, The value at each SRAM address can be output via output O111-4. At this time, whether the output is 0 or 1 is determined by the input I ₁ 111-1, and the I ₂ 111-2 and I ₃ (111-3) do not affect the output value. That is, if the input I ₁ (111-1) is 0, the output is 0, and if it is 1, the output is 1, so that it is in the form of a buffer. However, although the inputs I ₂ (111-2) and I ₃ (111-3) do not affect the output value, the input I ₂ (111-2) and the I ₃ (111-3) cause a different path for outputting the value output from each SRAM. Even though the paths determined by I ₂ (111-2) and I ₃ (111-3) have almost the same length, physically minute differences in paths occur, which are values from the input to the output of the buffer. This can affect the time it passes. This symbolized is shown in FIG. A buffer capable of adjusting such a delay can be shaped as shown in FIG. 8.

The flip-flop (FF) 120 is a general D flip-flop. At this time, the input of the D pin is connected to the TOP path 112 of the PDB path unit 110, the input of the CLK pin is connected to the BOTTOM path 113. In addition, the input pins of the TOP path 112 and the BOTTOM path 113 of the PDB path unit 110 are tied together, and the clock signal is supplied through the pin. In addition, if the lengths of the TOP path 112 and the BOTTOM path 113 are substantially the same, it can be said that the time when the rising edge of the clock arrives at the FF 120 is almost the same. If the FF 120 uses the rising edge of the clock, the output of the FF 120 becomes 1 when the rising edge is first input through the TOP path 112, and in the opposite case, the output becomes 0. Becomes

The binary counter 140 increases / decreases the value according to the output of the FF 120. If the output of the FF 120 is 1, the value of the counter is increased and vice versa. The value of the counter can be used separately from the sign bit, can represent negative numbers in the form of two's complement, and the implementation is not limited. The negative representation method affects the design of the decoder 130. In general, in the hardware implementation, it is easier to implement the decoder 130 by having a sign bit.

The decoder 130 adjusts the delay of the TOP path 112 and the BOTTOM path 113 in the PDB path unit 110 based on the counter value, which includes the sign bit, from the binary counter 140. It converts into a signal that can be. If the value of the counter is increased in the positive direction, this means that the ratio of 1 of the output is high, which means that the delay of the TOP path 112 is relatively short compared to the BOTTOM path 113, and thus the A signal for controlling the PDBs 111 is output in a direction in which the delay is longer or the delay of the BOTTOM path 113 is short. On the contrary, the control signal is output in a direction in which the delay of the TOP path 112 is shortened or the delay of the BOTTOM path 113 is long.

The memory 250 is composed of N × M flip-flops 252 to store the history. In this case, N is the history number of outputs stored for each counter, and M is the number of counters. Assuming that the bit length of the counter including the sign of the binary counter 140 is C bits, M should be composed of 2 ^C pieces. In this case, however, more storage is needed than necessary. However, when we found the actual TRNG, we found that since the counter value converges to a specific value by PI control, then it repeats up and down a specific range of the value, so that it does not need so much storage space. Therefore, the present invention proposes a storage space in the form of a cache memory. The actual number of storage spaces required is sufficient for the range of values to change after convergence. When this size is set to P, M is set to P, and the low enable decoder 240 receives only ₂ P LSB (Least Significant Bit) logs among the counter values output from the binary counter 140 as input. The history at the address it is assigned to. In the beginning of the TRNG operation, the counter tends to increase steadily from the initial value to the convergence value. Therefore, the wrong history may be stored due to the cache-type storage space. Since it is updated with information again, this is not a big problem. Each flip-flop 252 is grouped by N and used as a storage 251 corresponding to each counter. This part consists of a right shifter type storage in FIG. 6, and when a value is input to the leftmost FF 251, the stored values are shifted one bit to the right and the rightmost The value is discarded. In this way, you can remember the output history for each counter.

The address predictor 210 predicts the value of the next binary counter 140 by using the output value of the current FF 120 and the counter value of the binary counter 140. This may consist of logic that is already being used to determine the next counter value inside the binary counter 140. Therefore, the address predictor 210 may use logic inside the binary counter 140 or may configure and use separate logic as shown in FIG. 6. In addition, the address predictor 210 is a part necessary to retrieve the counter of the counter to be changed from the stored output history to allocate a time slot to the counter value to be changed next.

The address predicted by the address predictor 210 is used to extract one of the P counter values again using only LSB log ₂ P bits, which are supplied to the N mux 260 under the memory 250. It is used to select one of the P outputs. The selected history value is supplied to a hamming weight calculator 270 to calculate a hamming weight. The hamming weight is a measure of how many 1 of the N bits are present. Thus, the closer the Hamming weight is to N / 2, the more likely it is to be metastable.

The down counter initializer 280 decodes the hamming weight by the number of time slots allocated to the next counter using this characteristic. That is, if the Hamming weight is close to N / 2, it converts to a large time slot, otherwise it converts a small value. The converted value is supplied to the down counter 230, which is decremented every clock.

The zero comparator 220 determines whether the value of the down counter 230 is 0 as a simple comparator, and activates an enable signal to the binary counter 140 only when the counter is updated.

As such, when the random bit sequence is generated by using a field-programmable gate array (FPGA), the present invention provides an FPGA-based true random number generation apparatus for improving random characteristics and increasing throughput. Performance improvement can be provided, and the experimental result can be confirmed as follows.

FIG. 10A illustrates a method for proposing a probability of outputting 1 for each counter, and FIG. 10B is a graph showing a probability of outputting 1 for each counter with respect to the conventional method. In FIGS. 10A and 10B, the closer the probability is to 0.5, the more output the counter is in a metastable state. When the probability is close to 0, the frequency of outputting 0 is high, or when the probability is close to 1, 1 is output. It means that it is a high frequency counter value. FIG. 11A is a graph showing how many times each counter appeared in the total distribution when the proposed method was applied, and FIG. 11B is a graph showing how many times each counter appeared in the total distribution when the existing method was applied. It is a graph expressed as a ratio.

Referring to the drawing, in the case of the conventional method, as shown in FIG. 10B, the counters having a probability between 0.4 and 0.6 can be arranged to about 118, 120, and 121. Looking at the appearance probability of these counters in Figure 11b, it can be seen that the distribution is approximately between 0.15 ~ 0.25. The sum of these is about 0.6.

Meanwhile, in the case of the present invention as shown in FIG. 10A, the counters having a probability distributed between 0.4 and 0.6 may be defined as 434, 437, and 438. Referring to FIG. 11A, the counters have an appearance ratio of approximately 0.15, 0.25, and 0.35, respectively. have. Their sum is about 0.75, and the ratio of the random number is higher than the existing method.

12A and 12B are graphs showing a change in counter value over time, FIG. 12A is a graph showing a counter change in the conventional method, and FIG. 12B is a graph showing a counter change in the present invention.

Looking at Figure 12a, you can see that the counter is going up and down the section between 112 and 125 very regularly, and looking at Figure 12b, the output is concentrated around 438, and is intermittently concentrated around 434 You can check it. In addition, it can be seen from the graph that the frequency of output of the counters 430 and 441 of the output range is much smaller than that of the conventional method. Most importantly, in the case of the existing method, the counter change trend is very regular, and when the counter on the edge appears, it is recognized as a factor that destroys randomness, and in this case, the output is not output. However, in the proposed method, since the pattern in which the edge counter appears is irregular, it is also absorbed as a constituent element of the random, and the output can be continued even in this case. Therefore, the throughput caused by filtering the edge counter value is reduced. There will be no.

Meanwhile, embodiments of the present invention can be written as a program that can be executed on a computer. That is, the various steps included in the method according to the invention can be stored on a computer readable recording medium. The media may include magnetic storage media (e.g., ROM, floppy disk, hard disk, etc.), optical read media (e.g., CD-ROM, DVD), digital storage media (e.g., USB memory, memory card (SD, CF, MS, XD), etc.) and carrier waves (eg, transmission over the Internet).

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (16)

The data pin path of the flip-flop and the input of the clock pin path are tied together, and the clock signal is injected at the same time, and the delay time of each path is controlled by feedback, so that the similarly stable state can be met by the time difference that the corresponding signal reaches each pin. TRNG module for generating a random sequence, FPGA-based true random number comprising the TRNG output control unit for storing the state information output from the TRNG module, and controls the time it is possible to maintain the stable output (metastable) output of the TRNG module Device for improving the performance of the generator. The method of claim 1, wherein the TRNG module Flip-Flop (FF) to output random values, A PDB path unit configured to control delay times of the data pin path and the clock pin path of the flip-flop; A binary counter for outputting a counter value that increases or decreases according to whether the output of the flip-flop is 1 or 0; And a decoder configured to adjust a delay in a direction in which a delay between the data pin path and the clock pin path is the same through a feedback control from a counter value output from the binary counter of the FPGA-based true random number generator. Device for better performance. 3. The apparatus of claim 2, wherein the TRNG output control unit A memory for storing a history of the current state and the output according to the state of the TRNG module; A memory for storing a history of the random sequence outputted with respect to the counter value of the binary counter; An address predictor that checks the counter value of the current binary counter and the random output value of the current flip-flop to predict what is the next counter value; A hamming weight calculator for checking the history of the counter value output from the address predictor, and analyzing how much the counter value is evenly distributed based on the history; A down counter initializer for allocating a time slot that can be used by a counter value output from a binary counter using information analyzed by a hamming weight calculator; A down counter which receives a time slot allocated from the down counter initializer as an initial value and decreases the value by one every clock; And a zero comparator for updating a counter value of a binary counter (140) when the value output from the down counter becomes 0. The apparatus for improving performance of an FPGA-based true random number generator. The method of claim 3, wherein the TRNG output control unit A row enable decoder which receives a counter value output from a binary counter and outputs a low enable signal of a memory so that a value can be stored in a storage of a corresponding memory whenever an output is output from a flip-flop for a random output; The apparatus for improving the performance of the FPGA-based true random number generator, characterized in that further comprising a mux to select the history of the counter value predicted by the address predictor (210) and output to the Hamming weight calculator. The method of claim 2, wherein the PDB path portion Connect several PDBs in series to form a TOP path at the top, a BOTTOM path at the bottom, Device for improving the performance of an FPGA-based true random number generator, comprising a buffer and an inverter with an adjustable delay via input control of a look up table (LUT) inside the FPGA chip. The method of claim 2, And the flip-flop is a D flip-flop. The method of claim 6, The flip-flop is characterized in that the input of the D pin is connected to the TOP path of the PDB path portion, the input of the CLK pin is connected to the BOTTOM path, and the input pins of the TOP path and the BOTTOM path are tied together to receive a clock signal. A device for improving the performance of FPGA-based true random number generators. The method of claim 2, The memory is configured as a storage space of the cache memory, so that the output history can be stored for some states, the history is stored in the memory using only some information of each state, and the value is retrieved again using only the state partial information. Device for improving the performance of FPGA-based true random number generator, characterized in that. The method of claim 2, And the address predictor uses logic inside a binary counter, or configures and uses separate logic to improve performance of an FPGA-based true random number generator. The method of claim 2, And said down counter initializer decodes a hamming weight by the number of time slots allocated to the next counter. (A) The data pin path of the flip-flop and the input of the clock pin path are tied together, and a clock signal is injected at the same time, and the delay time of each path is controlled by feedback, so that similar stability is achieved by the time difference of the corresponding signal reaching each pin. Outputting a metastable random sequence, (B) storing the state information of the output random sequence, and controlling the time it is possible to maintain the quasi-stable state of the output of the output random sequence through the FPGA-based How to improve the performance of a true random number generator. The method of claim 11, wherein step (A) Placing a TOP path and a BOTTOM path on a flip-flop (FF) using a PDB, Outputting a counter value that increases if the output of the flip-flop is 1 and decreases if the output of the flip-flop is 0; And controlling a delay between the TOP path and the BOTTOM path based on the output counter value, and outputting a random sequence that is similarly stable due to a time difference at which a corresponding signal reaches each pin. A method for improving the performance of FPGA-based true random number generators. The method of claim 11, wherein step (B) Storing a history of the random sequence output for the counter value; Checking the current counter value and the current random output value to predict what the next counter value is; Selecting and outputting a history of the predicted counter value, and analyzing how evenly the counter values are evenly distributed based on the history of the corresponding counter value output; Allocating a time slot that can be used by the output counter value using the analyzed information; Improving the performance of the FPGA-based true random number generator, comprising the step of receiving the allocated time slot as an initial value and decreasing the value by one every clock, and updating the counter value when the reduced value becomes 0. Way for you. The method of claim 13, If the value of the counter increases in a positive direction, the ratio of 1 in the output is high, which means that the delay of the TOP path is relatively short compared to the BOTTOM path, so that the delay of the TOP path is longer or the delay of the BOTTOM path is increased. A method for improving the performance of an FPGA-based true random number generator, characterized by controlling in a shorter direction. The method of claim 13, The analyzing may include detecting how many 1's of N bits are selected by calculating the selected history value, and analyzing that the hamming weights are similarly stable as the Hamming weights are closer to N / 2. How to improve the performance of FPGA-based true random number generators. A computer-readable recording medium having recorded thereon a program for executing each step of the method for improving the performance of an FPGA-based true random number generator according to any one of claims 11 to 15.

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