WO2014053838A1

WO2014053838A1 - Signal processing apparatus and method using llr and a priori probability

Info

Publication number: WO2014053838A1
Application number: PCT/GB2013/052576
Authority: WO
Inventors: Paul Fletcher
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-10-03
Filing date: 2013-10-03
Publication date: 2014-04-10
Anticipated expiration: 2015-04-03
Also published as: GB201217695D0; GB2508132A

Description

SIGNAL PROCESSING APPARATUS AND METHOD USING LLR

AND A PRIORI PROBABILITY

TECHNICAL FIELD This invention relates to a signal processing apparatus and a method of signal processing. More particularly, but not exclusively, the invention relates to a signal processing apparatus and method of signal processing for use in multiple-input and multiple-output (MIMO) communication systems. As such it has applicability to all 3G and 4G enabled mobile phone, tablet and other mobile communication enabled devices.

BACKGROUND

Wireless communications is becoming ubiquitous as the mode of communication in the modern world with increasing number of devices becoming wireless communication enabled. There is ever-increasing demand for the rate of data communication to increase to enable users to experience data hungry applications, such a video and multi-media applications, on a range of platforms, including mobile phones and tablets devices. Wreless communications data rates can be increased by increasing transmission bandwidth - but this is inefficient and usually expensive. Alternatively, advanced communication systems employ a Multiple-Input Multiple-Output (MIMO) architecture with multiple transmit and multiple receive antennas and can increase the data throughput rate with no increase in bandwidth. Such approaches to increased data throughput have been adopted for third generation UMTS (otherwise known as 3G) and fourth generation Long Term Evolution (LTE, otherwise known as 4G) mobile communication systems. Furthermore, MIMO is a key enabling technology for proposed 4G evolution technology, such as LTE-Advanced.

A further aspect of relevance to the invention is the fact that mobile communications systems, such as 3G and 4G, transmit data in packets. The receiver will detect whether a packet has been received in error and if it has then a request is sent back to the transmitter to re-transmit the data packet. The packet may either be sent again in exactly the same form, whereby the receiver can simply combine the received retransmitted packet to previously received packets before attempting to decode, a process known as chase combining. Or alternatively, the packet may be sent in a different form (a different redundancy version) and combined with previously received versions of the same packet before attempting to decode, a process known as incremental redundancy. The process of re-transmitting data packets received in error and combining with previously received packets is known as Hybrid ARQ (HARQ). The invention describes a receiver processing method that dramatically improves the reliability with which data packets are received and therefore decreases the number of re-transmissions required with a commensurate improvement system performance.

Figure 1 and Figure 2 illustrate the essential concept of Multiple-Input and Multiple- Output (MIMO) systems. The essential component being that the transmitter and receiver have multiple transmit antenna 105 a-c and multiple receive antennas 201 a-c respectively. The transmitter has a means 103 to take a stream of bits and divide stream into parallel streams, each of which is mapped to a constellation alphabet and transmitted after conversion to a radio frequency (RF) 105 a-c. Additionally, Figure 1 shows a specific prior art realisation of a MIMO transmitter which comprises an outer channel encoder 101 for encoding a packet of input bits and an interleaver 102 to simply re-order the bit sequence. The channel encoder 101 codes the source data using, for example, a Parallel Concatenated Convolutional Code (PCCC) or Low Density Parity Check (LDPC) code, or any other code which facilitates iterative decoding at the receiver, which is performed in the usual manner according to prior art.

The transmitted signals pass across a channel, either line-of-sight (LOS) or multiple scatters, or a mixture of the two. The environment may be stationary or moving with respect to the transmitting or receiving devices.

The key observation to be made is that a MIMO transmitter of the form shown in figure 1 , which includes the components of outer encoder, interleaver and multiple transmitted data streams allows a specific form of receiver processing, namely iterative MIMO receiver processing, which is shown in Figure 2. The receiver comprises a plurality of receive antennas 201 a-c, and receiver chains 202 a-c, a MIMO detector device 203. For each transmitted bit the MIMO detector is able to calculate reliability metrics, typically in the form of log-likelihood values (usually referred to as soft LLR values). A deinterleaver device 205 reverses the sequence re-ordering performed by the interleaver at the transmitter and supplies the LLR values to an outer decoding device 206, which performs the reverse decoding operation performed by the outer encoding device at the transmitter. Therefore, under favourable conditions, the receiver is able to recover the transmitted packet bit sequence without error.

However, should errors occur in the recovered decoded bit packet, this processing scheme allows that the additional information about the reliability of each transmitted bit, the so-called extrinsic information, may be extracted by subtracting the reliability LLR value from the output of the decoder from the reliability and the input of the decoder for each bit, 207. This information is passed through an interleaver, which reorders the sequence of reliability information for each transmitted bit in exactly the same way as the interleaver in the transmitter. The information can then be used as a priori reliability information by the MIMO detector to enhance its decision as to the polarity of a particular transmitted bit. The new reliability information is provided to the outer decoder after removal of a priori information and deinterleaving once more. This complete cycle is one inner iteration, to distinguish it from the outer iterations performed by the outer decoding device. The system may perform multiple inner iterations and outer iterations, each time improving the reliability of the decoded transmitted bit sequence. The key observation, that iterative MIMO decoding can be utilised for a MIMO transmitter which is composed of an outer encoder and interleaver, will be exploited for the invention described below.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a receiver comprising: a plurality of receiver modules, each receiver module receiving, substantially simultaneously, a symbol of a composite signal, each symbol comprising a plurality of bits, the bits of the symbols being received in a predetermined

transmission order; a detector configured to determine reliability information of each received bit based on a priori reliability information; a feedback stage configured to provide a priori reliability information to the detector in the predetermined transmission order. The receiver may further comprise a decoder configured to iteratively decode each received bits in response to the determined reliability information of each received bit. The decoder may be further configured to CRC check of each code block of decoded bits. The decoder may be further configured to desegment each code block of decoded bits. The feedback stage may be further configured to scale the a priori reliability information for code blocks that passes the CRC check. The scaling may be based on a linear function or a nonlinear function.

The detector may be further configured to apply iterative soft-input soft-output, SISO, decoding to determine the reliability information for each received bit.

The detector may be further configured to determine reliability information for each received bit within a stream for each code block. The detector may be further configured to determine the reliability information on each transmitted bit in the form of log likelihood ratios (LLR).

The feedback stage may be further configured to code block concatenate the reliability information of the received bits.

The feedback stage may be further configured to code block rate match the reliability information of the received bits.

According to another aspect of the present invention, there is provided a method of operating a receiver, the receiver comprising a plurality of receiver modules, the method comprising: receiving, substantially simultaneously, a plurality of bits of a symbol of a composite signal in a predetermined transmission order; determining reliability information of each received bit based on a priori reliability information, the a priori reliability information being provided in the predetermined transmission order.

The method may further comprise iteratively decoding each received bits in response to the determined reliability information of each received bit. The step of iteratively decoding may comprise CRC checking each code block of decoded bits. The step of iteratively decoding may further comprise desegmenting each code block of decoded bits. The step of determining reliability information may comprise applying iterative soft-input soft-output, SISO, decoding to determine the reliability information for each received bit. The step of determining reliability information may comprise determining reliability information for each received bit within a stream for each received block of bits.

The step of determining reliability information may comprise determining the reliability information on each transmitted bit in the form of log likelihood ratios (LLR).

The a priori reliability information may be provided by code block concatenation of the reliability information of the received bits. The a priori reliability information may be provided by code block rate matching the reliability information of the received bits. According to another aspect of the present invention, there is provided a signal processing apparatus consisting of a plurality of receiving means to receive a composite signal indicative of a plurality of symbols transmitted substantially simultaneously, from a plurality of remote transmission means, and processing means to iteratively decode each transmitted bit in said composite signal.

The processing detecting means may be arranged to determine reliability information on each transmitted bit. The processing detecting means may be arranged to exchange reliability information with a processing decoding means. The processing decoding means may be arranged to exchange reliability information with a processing detecting means.

Reliability information may be iteratively exchanged between the detecting means and decoding means.

The apparatus may include detecting means arranged to calculate reliability

information for each transmitted bit.

The apparatus may include decoding means arranged to apply iterative soft-input soft- output (SISO) decoding to calculate reliability information for each transmitted bit. The apparatus may be further arranged to provide reliability information for each transmitted bit within a stream for each transmitted block of bits.

The apparatus may be further arranged to calculate reliability information on each transmitted bit in the form of log likelihood ratios (LLR).

According to another aspect of the present invention, there is provided a method of detecting each transmitted symbol and bits within each symbol making use of a priori information on the reliability of each transmitted bit in the form of log likelihood ratios (LLRs).

The bit reliability values may be re-ordered into streams according to each transmit chain such that reliability information of each transmitted bit from each transmit chain is output separately for each transmit chain and in a known order, typically the order of transmission.

According to another aspect of the present invention, there is provided a method of code block deconcatenation of bit reliability values. According to another aspect of the present invention, there is provided a method of code block reverse rate matching of bit reliability values.

According to another aspect of the present invention, there is provided a method of channel decoding to provide reliability values for every coded bit.

According to another aspect of the present invention, there is provided a method of CRC checking of each code block of decoded reliability values.

According to another aspect of the present invention, there is provided a method of desegmenting code block reliability values.

The method may include decoding, the reliability information of bits which reverses the processing steps undertaken at the transmitter. According to another aspect of the present invention, there is provided a method of scaling reliability values for code blocks with CRC pass according to some function, linear or non-linear. According to another aspect of the present invention, there is provided a method to remove a priori reliability information from detected or decoded reliability information, either by subtraction or other mathematical function.

The method may provide rate matching on feedback reliability information.

According to another aspect of the present invention, there is provided a method to provide code block on concatenation feedback reliability information.

The method may include processing the reliability information of bits output from a decoder which performs essentially the same processing as the transmitter, which enables a priori reliability information to be provided for bits at the detector.

The method of selecting the reliability information of bits output from a decoder which matches the same bits as transmitted in the case where a re-transmission may be performed with a different redundancy version than the decoded bits of a previous transmission.

The method may include combining reliability information from the current transmission with reliability information from a previously decoded transmission.

According to another aspect of the present invention, there is provided a method to feedback reliability information to a detector from a current or previous transmission for use as a priori information. According to another aspect of the present invention, there is provided a computable readable storage medium storing instructions executable by a computer according to the aspects above.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described, by way of example only, with reference to the following drawings, in which:

Figure 1 and Figure 2 illustrate the essential concept of Multiple-Input and Multiple- Output (Ml MO) systems;

Figure 3 is a schematic representation of a transmitter architecture of the prior art;

Figure 4 is a schematic representation of a MIMO receiver which allows reception of the transmissions from a transmitter of the type shown in Figure 3;

Figure 5 illustrates example architecture of rate matching and reverse rate matching;

Figure 6 is a flow chart of the typical processing flow of one embodiment the invention; and

Figure 7 illustrates a typically processing flow of one embodiment of the invention DETAILED DESCRIPTION

The invention is described by way of an example. Figure 3 is a schematic

representation of a transmitter architecture of the prior art, in particular for the example of the transmitter functions of LTE (4G) communications standard. However, the invention is applicable to the 3G communications standard.

Figure 3 shows all the processing steps which compose the transmitter functions of an LTE (4G) transmitter to take incoming bit streams and perform the functions of cyclic redundancy attachment, code block segmentation, channel coding, rate-matching, code block concatenation, modulation mapping, layer mapping, waveform generation and RF transmission from multiple antennas. All these processing steps are well known and understood by someone skilled in the art of mobile communications.

For the invention, of vital importance is the presence of the rate matching processing stage. The purpose of this stage is to provide a match between the number of bits that are generated by the channel coder as its output and the number of bits which may be transmitted at any particular time through the availability the transmit channel physical resource. The process of rate matching is well understood, and defined by the 3G and 4G standard specifications, for example.

By way of example, the rate matching used specifically by LTE (4G) mobile

communications is described detail later in the description. Here it is noted that the rate matching processing includes a number of interleaving blocks which operate on the coded bits output from the channel coding processing. Therefore, whilst the transmitter of Figure 3 does not appear to have the prerequisite features of a channel encoded and interleaver (Figure 1) to allow iterative MIMO processing at the receiver (Figure 2), in fact due to the processing undertaken by the rate matching process it does possess the required features.

Figure 4 is a schematic representation of a receiver 400 of an embodiment of the present invention, for example a MIMO receiver, which allows reception of the transmissions from a transmitter of the type shown in Figure 3, The receiver 400 comprises a plurality of receiver modules, each comprising a receive antenna 401 a-b and a RF receiver 402a-b. The receiver 400 further comprises demodulation and channel estimation 403a-b, 404, a detector 405, code block de-concatenation 407a-b, reverse rate matching 408a-b, channel decoding 409a-b, code block de-segmentation and CRC checking 410a-b. These constituent processing functions allow the reception of the transmitted bits from a transmitter of Figure 3 by essentially reversing the processing steps to recover the transmitted bits. This is well-known and understood by persons skilled in the art of mobile communications. Figure 4 also contains additional processing features, a feedback stage or path 413a-b, 414a-b which is able to take the output of the channel decoder of each receiver chain, subtract information that was available at the input of the decoder and provide the steps of ratematching and block concatenation on this information and feed it back to the detector and a device to subtract this information from the output of the detector. These additional processing functions therefore allow the conventional receiver to resemble the iterative MIMO receiver of Figure 2, where the reverse rate matching processing contains the function of a de-interleaver and the rate matching function on the feedback path contains the function of an interleaver. A detailed description of the transmitter shown in Figure 3 and receiver in Figure 4 follows. The functionality shown in Figure 3 is described for each transmit chain, where the number of transmit chains may be 1 , 2, 4 or any integer number. Bits a₀ , a_x , a₂ , a_A__x comprise a transport block of A bits and are input to each transmit processing chain. A cyclic redundancy check (CRC) bit calculation is performed 301 a-b and the CRC bits, typically 24 but not restricted to this number, are appended to the input bits such that the output bits are b₀ , b_l , b₂ , b_B__x i.e. B bits in total. A code block segmentation stage 302 a-b segments the bits into r segments and appends calculated CRC bits for each of the r segments such that the number of bits in each code block segment is K_r . The output bits from code block segmentation are denoted c_r0 , c_rl , c_r2 , c_r(K __1} , where the code block is r and the number of bits in code block r is K_r , which may require padding bits to be added to one or more code block segments. Parameters r and K_r are determined by the system. A channel coding stage 303 a-b turbo encodes the bits of each code block. Turbo encoding is typically performed using a PCCC encoder which generated three encoded bit streams, a systematic stream of bits and two parity streams of bits. Encoded the bits are denoted by d^ , d^ , d_r ⁽ ₂ , d^_D __1} , where i = 0 denotes the systematic stream and 1 , 2 denotes the two parity streams. For the th encoded stream and D_r is the number of bits in the f th encoded stream. Typically, tail bits are appended to the streams such that D_r > K_r . A rate matching stage 304 a-b provides interleaving and bit puncturing, repetition or neither. The output from the rate matching stage is denoted e_r0 , e_rl , e_r2 , e_r(E __1} where r is the code block number and E_r is the number of rate matched output bits for code block number r . The input to the code block concatenation stage 305 a-b are the rate matched bits e_r0 , e_rl , e_r2 , e_r(E __1} which are concatenated together in ascending code block order. The output coded bits from the concatenation stage are denoted /„ , f_x , f₂ , f_G__x , where G is the number of coded bits for transmission from each transmit chain. The coded bits are mapped to a modulation alphabet in groups of Q bits in the modulation mapper stage 306 a-b. The modulation alphabet is typically BSPK (g = l ), QPSK (£> = 2 ), 16QAM (Q = 4 ) or 64QAM

(2 = 6 ), although is not restricted to this set. The output symbols from each transmit chain are denoted _l , where S = ¾ . the number of transmitted symbols.

Referring to Figure 3, modulated symbols output from the modulation mappers 306 a-b of each transmitter chain are mapped to layers. For clarity, the superscript t is added to the description of the symbols output from the th transmit chain i.e. these are denoted by s₀' , s[ , s₂' , s -_i■ Each symbol is mapped to one of a possible L layers in the layer mapper stage 307, where a layer feeds a single or multiple antennas. The transmitted symbol vector is denoted x = [x₀ · · · x_L J , where a transmitted symbol for layer / , x is mapped according to some predetermined rule to a symbol s_s' . Multiple transmit symbol vectors are constructed such that all symbols from all transmit chains are transmitted. The predetermined mapping rule may take the form of selecting each symbol from each transmit chain in turn, precoding according to some rule (e.g. space- time block coded) or some other mapping rule of prior art. There is a one-to-one mapping between the transmitted symbol vector x and a vector of coded bits f from which the mapped symbols were derived.

The output from the layer mapper is a plethora of output signals which are provided each to a waveform generation stage 308 a-b followed by an RF stage 309 a-b and an antenna 310 a-b.

The transmitted signals propagate through the environment and impinge on a plethora of receive antennas, 401 a-b, referring to Figure 4, where the number of receive antennas may be any integer number. Each received signal is down-converted to baseband in the usual way according to prior art 402 a-b, and the waveform

demodulated 403 a-b.

Estimates of the channel complex gain are estimated by a channel estimator, 404. An equivalent baseband model for the transmission symbols and reception of signals is y = Hx = n (1) where y is the received signal vector, H is the channel state information (CSI) matrix, n is the noise vector and x is the transmit symbol vector whose elements are the symbols formed by the modulation mapper stage 306 a-b and layer mapper stage 307.

The channel response h_i} is the complex gain from the f th transmit antenna to the th receive antenna. Equation 2 describes a systems where the number of transmit antennas is n_T and the number of receive antennas is n_R .

Channel estimates and received demodulated symbol values are provided to a soft- input soft-output detector stage 405. The detector stage provides output on each coded bit of the transmissions from each transmit chain at the transmitter in the form of a log- likelihood ratio. The a posteriori log-likelihood ratio is defined as:

where

been added to the coded bits to denote the output from the t'th transmit chain. The soft-input soft- output detector stage 405 is able to accept a priori log-likelihood information L_A{f ) on each coded bit and applying Baye's rule may be written as:

where

where σ ² is the noise variance, / denotes the mapping 2f - 1 , / e {θ,ΐ} and F_; k,0 denotes the set of vectors f for which the k'th bit position is 0 and similarly, F_k denotes the set of vectors f for which the k'th bit position is 1.

Equation 4 describes the mathematical solution for the detector. The detector may be implemented in a lower complexity form, for example as a sphere detector or some other lower complexity implementation. Referring to Figure 4, the detector 405 re-orders the output soft values such that streams are output separately corresponding to the transmit chains. In this way, each stream can be processed separately in the stages 407 to 414 a-b. The superscript t is therefore dropped from the processing description, but is understood.

Referring to Figure 4, the a priori is removed from the log-likelihood value, 406, calculated by the soft-input soft-output detector

L»_et (f_k ) = L_Det (f_k ) - L_A (f_k ) (6)

A code block de-concatenation stage 407 a-b performs the reverse of the code block concatenation at the transmitter working with soft LLR values. The soft LLR values

L^* _Det (f_k ) are placed into r code blocks of length 3 x (D_r + 7 ) (one for each stream, systematic and two parity streams), assuming T_l appended tail bits per encoded stream. Each of the code blocks of LLR values is reverse rate matched, 408, to provide 3 x r code block streams of soft LLR values each consisting of D_r + T_l soft values.

Each of the r stream sets of soft LLR values is decoded by the channel decoder which takes the form of a turbo decoder consisting of two soft-input and soft-output decoders whose extrinsic information, gleaned as a result of the decoding process, is exchanged between the decoders in the turbo decoding fashion according to prior art.

The aspects of processing shown in Figure 4 that represent the key implementation features are described. First, the channel turbo decoder computes soft LLR values for each of the code block bits, irrespective of whether the particular bit corresponds to a systematic bit or parity bit from the turbo encoded stream. Using the terminology of the previous section this can be written

which for the case of P

(8)

where the summations are over probabilities for transitions from states where d_r'_k = 1 and d_r'_k = 0 respectively, and y is the vector of received symbols or soft LLR values of the whole received sequence. Equation (8) represents a well-known manifestation of the BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm for iterative decoding.

Hard decisions for the information bits of the code blocks are made according to the polarity of the soft LLR values and a CRC check is made for each code block 410 a-b and code block de-segmented to give the transport block bits plus CRC bits. A CRC check 41 1 a-b is used to determine whether the transport block is received in error.

According to one feature and aspect of the invention, a feedback path is provided which takes as its input soft LLR values L_E (d_r'_k ) which according to equation 9 is the output soft LLR values from the decoder stage J_Bec ) with the detector stage soft

LLR values ^* _Det (d_r ⁽ _k ) subtracted.

L_E (d^ ) = L_Dec (d^ ) - I^_et (d ) (9)

According to another feature and aspect of the invention, a rate matching processing stage 413 a-b is provided which performs identical rate matching as the rate matching stage in the transmitter 304 a-b except that processing is performed in the soft LLR value domain.

Described above, the reverse rate matching processing and rate matching processing on the feedback path contain deinterleaver and interleaver functions respectively. Interleaving and de-interleaving are key functions for iterative MIMO processing.

Example architecture of rate matching and reverse rate matching is shown in Figure 5. This represents one embodiment of rate matching and does not exclude other methods. Figure 5 shows that rate matching and reverse rate matching can be performed on either bit values or soft LLR values. In the rate matching embodiment of Figure 5 the three encoded bit or soft LLR value streams are input to the rate matching as three separate blocks, each block is separately interleaved according to some predefined interleaving function, and the interleaved output used to populate a virtual circular buffer according to some predetermined manner. The rate matched output, bits or soft LLR values, is obtained by reading from the virtual circular buffer from an offset starting index. Should the number of rate matched bits or soft LLR values required be such that the end of the virtual circular buffer is reached then the indexing wraps to the start of the buffer. According to prior art, adjusting the offset start index and the number of rate matched bits or soft LLR values output, allows for puncturing or repetition of the bits or soft LLR values. As illustrated in Figure 5, the rate matching process is operating in puncturing mode.

The reverse rate matching stage operates in the opposite direction to the rate matching stage. The complete virtual circular buffer is initialised with zeros at every index. Soft LLR values of rate matched bits are taken in order of transmission and are added to existing values in the virtual circular buffer at indexes within the virtual circular buffer starting from the known offset starting index. The writing to the virtual circular buffer wraps if the end is reached. Blocks of interleaved soft LLR values are formed by performing the reverse population pattern as used in the rate matching process and each block is de-interleaved using the reverse predefined interleaving function. This produces the three encoded bit or soft LLR values streams.

According to prior art, repeated transmissions of the same transport block may be made when an error is detected at the receiver. The error is typically detected by the CRC processing of the decoded transport block bits. A retransmission may be a repeat of the original transmission and chase combining of the reverse rate matched soft LLR values be performed before further decoding attempts. Also, according to prior art, the repeated transmissions may be for different offset starting indices for the virtual circular buffer. In this case, each retransmission will have a different set of systematic and parity bits and corresponding received soft LLR values. Each retransmission represents a different redundancy version and the combining technique is termed incremental redundancy.

Soft LLR values for each coded bit (systematic, parity and tail bits) are calculated by the decoding function. As a consequence, for inner iterations after the first iteration soft LLR values are available for all coded bits. According to one aspect of the invention the soft LLR values may be scaled according to:

(10)

where the function a(|..|jcan be a linear function or a non-linear hardlimiting function, or some other function, and may be used in subsequent iterations of the

detector/decoding processing. According to a further aspect of the invention, a code block concatenation processing stage 414 a-b is provided which performs identical code block concatenation processing as the code block concatenation stage in the transmitter 305 a-b except that processing is performed in the soft LLR value domain. The output of the code block concatenation processing stage 414 a-b is L_A (f ) .

According to one aspect of the invention, all receiver chains operate independently. Each receiver chain functions can be performed in a sequential fashion, and in any order. Alternatively, each receiver chain can be operated simultaneously and in parallel. From the calculation of the soft LLR values for all receiver chains to the calculation of all a priori information for all receiver chains is termed one inner iteration. The iteration cycles performed by the channel decoder 409 a-b are termed outer iterations. The number of outer and inner iterations performed may be determined in advance. The number of outer and inner iterations performed may stopped if the code block CRC check (410 a-b) or transport block CRC check (41 1 a-b) is passed.

A code block CRC check passing indicates that the decoding of that block has been successful in determining the transmitted bits of that code block. From equation 4, the detector gleans a reliability metric for a particular bit by using all bits transmitted in the transmitted symbol vector. According to another aspect of the invention, when a code block CRC check reports a pass, the reliability metrics for bits in that code block are put to extreme values (highest reliability), or hard limited at the extreme values, such that the detector is assisted to the maximum amount in making reliability decisions about other bits transmitted at the same time on the next inner iteration loop.

A flow chart of the typical processing flow of one embodiment the invention is shown in Figure 6, where T is the number of transmit chains, / is the number of inner processing iterations and C is the number of code blocks. Figure 7 illustrates a typically processing flow of one embodiment of the invention. Two transmit chains each transmit a series code blocks. In the first inner iteration all code blocks are decoded by the channel decoder and their CRC values calculated. For those pairs that pass no further processing is required. For those with a single pass in the pair, a further processing iteration is required, where the soft LLR values for the passed code block can be hard limited to ensure the other code block will pass on the next iteration with high probability. Where both code blocks fail, both are further processed by further iterations. In the example of Figure 7, after four inner iterations all code blocks pass.

The number of inner iterations is limited to / . If a transport block CRC failure is indicated after / inner iterations then a re-transmission of the data may be undertaken.

Soft LLR information from the detector from a re-transmission may be combined with soft LLR information from a decoded previous transmission for all coded bits or for corresponding coded bits which are present in the re-transmission and previous transmission in the case of a re-transmission having a different redundancy version.

According to one aspect of the invention soft LLR a priori values available from the feedback path of a previous transmission or transmissions may be used as soft LLR a priori information for re-transmissions and this may include processing to ensure that feedback a priori LLR information for a particular coded bit corresponds to the same coded bit in the re-transmitted bit sequence in the case of a re-transmission with a different redundancy version.

According to a further aspect of the invention the soft LLR values for each bit which are available after the decoding process are evaluated to derive a metric which determines whether further processing according to the invention will achieve further improvement and error-free reception. The metric may take the form of evaluating the mean magnitude of the soft LLR values. If the mean magnitude of the soft values is above a predetermined threshold then further processing is deemed likely to achieve error-free reception.

Although various examples have been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the examples disclosed, but is capable of numerous modifications without departing from the scope of the invention as set out in the following claims.

Claims

1. A receiver comprising:

a plurality of receiver modules, each receiver module receiving, substantially simultaneously, a symbol of a composite signal, each symbol comprising a plurality of bits, the bits of the symbols being received in a predetermined transmission order;

a detector configured to determine reliability information of each received bit based on a priori reliability information;

a feedback stage configured to provide a priori reliability information to the detector in said predetermined transmission order.

2. A receiver according to claim 1 , wherein the receiver further comprises:

a decoder configured to iteratively decode each received bits in response to the determined reliability information of each received bit.

3. A receiver according to claim 2, wherein the decoder is further configured to CRC check of each code block of decoded bits.

4. A receiver according to claim 3, wherein the decoder is further configured to desegment each code block of decoded bits.

5. A receiver according to claims 3 or 5, wherein the feedback stage is further configured to scale the a priori reliability information for code blocks that passes the

CRC check.

6. A receiver according to claim 5, wherein the scaling is based on a linear function.

7. A receiver according to claim 5, wherein the scaling is based on a nonlinear function.

8. A receiver according to any one of the preceding claims, wherein the detector is further configured to apply iterative soft-input soft-output, SISO, decoding to determine the reliability information for each received bit.

9. A receiver according to any one of the preceding claims, wherein the detector is further configured to determine reliability information for each received bit within a stream for each code block.

10. A receiver according any one of the preceding claims, wherein the detector is further configured to determine the reliability information on each transmitted bit in the form of log likelihood ratios (LLR).

1 1. A receiver according to any one of the preceding claims, wherein the feedback stage is further configured to code block concatenate the reliability information of the received bits.

12. A receiver according to any one of the preceding claims, wherein the feedback stage is further configured to code block rate match the reliability information of the received bits.

13. A method of operating a receiver, the receiver comprising a plurality of receiver modules, the method comprising:

receiving, substantially simultaneously, a plurality of bits of a symbol of a composite signal in a predetermined transmission order;

determining reliability information of each received bit based on a priori reliability information, the a priori reliability information being provided in said predetermined transmission order.

14. A method according to claim 13, wherein the method further comprises:

iteratively decoding each received bits in response to the determined reliability information of each received bit.

15. A method according to claim 14, wherein the step of iteratively decoding comprises

CRC checking each code block of decoded bits.

16. A method according to claim 15, wherein the step of iteratively decoding further comprises

desegmenting each code block of decoded bits.

17. A method according to claims 14 or 15, wherein the a priori reliability information is scaled for code blocks that passes the CRC check.

18. A method according to claim 17, wherein the scaling is based on a linear function.

19. A method according to claim 17, wherein the scaling is based on a nonlinear function.

20. A method according to any one of claims 13 to 19, wherein the step of determining reliability information comprises

applying iterative soft-input soft-output, SISO, decoding to determine the reliability information for each received bit.

21. A method according to any one of claims 13 to 20, wherein the step of determining reliability information comprises

determining reliability information for each received bit within a stream for each received block of bits.

22. A method according any one of claims 13 to 21 , wherein the step of determining reliability information comprises

determining the reliability information on each transmitted bit in the form of log likelihood ratios (LLR).

23. A method according to any one of claims 13 to 22, wherein the a priori reliability information is provided by code block concatenation of the reliability information of the received bits.

24. A method according to any one of claims 13 to 23, wherein the a priori reliability information is provided by code block rate matching the reliability information of the received bits.