WO2014045193A1

WO2014045193A1 - Method for reducing contact resistances of screen printed contacts

Info

Publication number: WO2014045193A1
Application number: PCT/IB2013/058605
Authority: WO
Inventors: Victor Prajapati; Jörg Horzel; Joachim John
Original assignee: Katholieke Universiteit Leuven; Interuniversitair Microelektronica Centrum vzw IMEC
Current assignee: Katholieke Universiteit Leuven; Interuniversitair Microelektronica Centrum vzw IMEC
Priority date: 2012-09-21
Filing date: 2013-09-17
Publication date: 2014-03-27
Anticipated expiration: 2015-03-21

Description

Method for reducing contact resistances of screen printed contacts Technical field

The disclosed technology relates to methods for reducing the contact resistance of screen printed contacts, e.g. emitter contacts, of silicon photovoltaic cells.

Background art

Current front side metallization of industrial silicon photovoltaic cells is based on screen printing of a silver paste that is typically fired through a PECVD SiN_x:H antireflection coating (ARC) for contact formation. These contacts may limit the solar cell efficiency in several ways. The relatively wide metal lines combined with a rather limited line conductivity require a compromise to be made between shading losses and resistive losses. Due to contact resistance issues the range of compatible homogeneous emitters is limited to emitters having a surface doping concentration above 10 20 atoms/cm . This results in emitter sheet resistance values typically below 90 Ohms per square.

A possible solution can be found in using a selective emitter structure with highly doped regions at the location of the metal contacts (leading to reduced recombination under the contacts and lower contact resistance) and with emitter regions having a higher sheet resistance (allowing good surface passivation) in between the metal contacts. However, those advantages come at a cost of an increased number of processing steps and a higher degree of accuracy (alignment) needed for the

metallization step. A selective emitter design allows more freedom in selecting the type of diffusion to be used under the contacts versus in between the contacts. Homogenous emitters on the other hand offer much less freedom, since the emitter needs to be both well passivated and be able to be contacted with low contact resistance.

Summary of the disclosure

Certain inventive aspects relate to methods for fabricating silicon photovoltaic cells with screen printed emitter contacts, wherein the contact resistance of the emitter contacts is reduced as compared to prior art methods and/or wherein the emitter sheet resistance can be higher than in prior art methods, such as higher than about 90 Ohm per square, without providing a selective emitter structure.

Certain inventive aspects relate to silicon photovoltaic cells with a homogeneous emitter structure and screen printed emitter contacts, the emitter contacts having a lower contact resistance as compared to prior art cells with a same emitter sheet resistance and/or wherein the homogeneous emitter can have a higher sheet resistance, such as higher than about 90 Ohms per square, as compared to prior art cells with a same low contact resistance.

One inventive aspect relates to a method for fabricating silicon photovoltaic cells, wherein the method comprises: forming an emitter region, preferably a

homogeneous emitter region, having a first doping type at a front side of a crystalline silicon substrate having a second doping type opposite to the first doping type;

providing a doped dielectric layer of the first doping type on the front surface of the silicon substrate; depositing an antireflection coating on the doped dielectric layer; screen printing a metal pattern on the antireflection coating; and firing the screen printed metal pattern through the antireflection coating and the doped dielectric layer, thereby forming screen printed emitter contacts.

The first doping type can be n-type and the second doping type can be p-type or vice versa, the first doping type can be p-type and the second doping type can be n-type. In one embodiment, the front surface of the crystalline silicon substrate can be a textured surface. The substrate can for instance be a p-type silicon substrate. A n-type emitter region (e.g. an n+ region) at its front (and optionally back) surface can for example be formed by POCI₃ diffusion.

The doped dielectric layer can for example be a doped oxide layer such as a doped silicon oxide layer, a doped nitride layer such as a doped silicon nitride layer, or any other suitable doped dielectric layer known to a person skilled in the art.

The antireflection coating can be or comprise a layer comprising or consisting of for instance SiN_x:H (hydrogenated SiN).

The metal pattern can comprise for instance Ag.

The step of firing can comprise performing a temperature step with a

temperature in the range of 500°C to 1100°C. The firing step can be performed under an inert atmosphere such as a N₂ atmosphere. It can also be performed in an atmosphere comprising N₂ and/or 0₂, or in ambient air. The firing step can be performed according to a firing temperature profile comprising a temperature ramp up phase, a phase at constant peak temperature (this phase can for example have a duration between 0 minutes and 1 hour depending on the peak temperature), and a temperature ramp down phase.

In the context of the present disclosure, the front surface or front side of a photovoltaic cell is the surface or side adapted for being oriented towards a light source and thus for receiving illumination. In case of bifacial photovoltaic cells, both surfaces are adapted to receive impinging light. In such case, the front surface or front side is the surface or side adapted for receiving the largest fraction of the light or illumination. The back surface, back side, rear surface or rear side of a photovoltaic cell is the surface or side opposite to the front surface. The front side of a substrate is the side of the substrate corresponding to the front side of the photovoltaic cell, while the rear side or back side of the substrate corresponds to the back side of the photovoltaic cell.

In one inventive aspect, providing the doped dielectric layer can comprise providing the doped dielectric layer on the entire front surface of the silicon substrate, i.e. on the entire emitter surface of the photovoltaic cell.

In one inventive aspect, providing the doped dielectric layer can comprise providing the doped dielectric layer selectively, at least at locations where the screen printed contacts are to be formed. In other words, the doped dielectric layer can be a patterned dielectric layer having a pattern corresponding to the pattern of the screen printed contacts, such as a pattern comprising a plurality of narrow lines (fingers). The lines of the dielectric layer pattern can have the same width as the lines of the contact pattern, about the same width, at least the same width, or a larger width or a smaller width. It is an advantage of providing a patterned dielectric layer only at, or at least at, locations corresponding to the location of the contacts that the contact resistance can be reduced without negatively affecting the front surface reflection of the photovoltaic cell.

In one inventive aspect, an undoped dielectric layer can be provided on the entire emitter surface of the photovoltaic cell and the dielectric layer can be selectively doped at the locations where screen printed contacts are to be provided.

In one inventive aspect, providing a doped dielectric layer can comprise depositing a doped dielectric layer, for example by means of chemical vapor deposition (CVD), for example by means of atomic layer deposition (ALD). In another inventive aspect, providing a doped dielectric layer can comprise depositing an undoped dielectric layer, for example by means of CVD, for example by means of ALD, and doping the dielectric layer afterwards, such as by ion implantation.

In one inventive aspect, providing a doped dielectric layer can comprise thermally growing a dielectric layer, e.g. oxide layer. The oxide layer can for example be grown by dry oxidation or by wet oxidation.

In one inventive aspect, providing a doped dielectric layer can comprise doing a chemical oxidation, such as during a cleaning step after the emitter diffusion.

In one inventive aspect, providing a doped dielectric layer can comprise providing a patterned doped dielectric layer by selectively removing a phosphosilicate glass (PSG) layer, e.g. a PSG layer that is formed on the entire front surface during emitter diffusion. Selectively removing the PSG layer can comprise removing the PSG layer only at locations where no screen printed contacts are to be formed. In other words, in this aspect the PSG layer remains on the silicon surface only at locations where screen printed contacts are to be formed. It is an advantage of this approach that there is no need for providing a dedicated doped dielectric layer. It is an additional advantage of this approach that the location of the PSG regions can be detected by a camera, resulting in an easy alignment of the metal contacts to the PSG regions.

Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Brief description of the drawings In Figure 1, an illustration is provided of a Front-Side lifetime investigation structure comprising a textured wafer, which is diffused and passivated symmetrically.

Figure 2 is a graph illustrating emitter saturation current density versus oxidation time for a 65 Ω/square emitter.

Figure 3 is a graph illustrating SIMS and SRP results for different oxidation conditions.

In Figure 4, an illustration is provided of a Rear-Side lifetime investigation structure, whereby a wafer is chemically polished and passivated symmetrically.

Figure 5 is a graph illustrating oxide thickness versus oxidation time for 10, 30 and 60 min oxidations respectively, comparing diffused and non diffused wafers.

Figure 6 shows reflectance curves of 60 Ω/square cells with 0, 10, 30 and 60min thermal oxidation and adapted SiN_x (minimum reflectance @ 620nm for all conditions).

Figure 7 gives an overview of the process flow for p-type PERC solar cells including thermal oxidation times of 0, 10, 30 and 60min respectively. Figure 8 illustrates the relation between short circuit current density and oxidation time.

Figure 9 illustrates the relation between open circuit voltage and oxidation time.

Figure 10 illustrates the relation between fill factor and oxidation time.

Figure 11 illustrates the relation between efficiency and oxidation time.

Figure 12 gives an overview of the process flow for p-type PERL solar cells, which allows comparing cells that have the oxide etched from the front side and cells that have the oxide remaining.

Figure 13 illustrates the relation between Fill factor and sheet resistance for cells with oxide and without oxide.

Figure 14 illustrates the relation between Fill factor and contact resistivity for cells with oxide and without oxide. Figure 15 illustrates results of secondary ion mass spectroscopy measurements of 80 Ω/square emitters in function of varying oxidation conditions.

Figure 16 illustrates the relation between contact resistance and sheet resistance as a function of varying relative levels of phosphorus content in the oxide (considering as a reference 100% = 60min oxidation).

Detailed description of preferred embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be practiced in particular embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present disclosure. While the present disclosure will be described with respect to particular embodiments and with reference to certain drawings, the disclosure is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the disclosure. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes.

Furthermore, the terms first, second, third and the like in the description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising" should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B.

The present description discloses a method for fabricating silicon photovoltaic cells, comprising

forming an emitter region having a first doping type at a front side of a crystalline silicon substrate having a second doping type opposite to the first doping type;

providing a doped dielectric layer of the first doping type on the front surface of the silicon substrate;

depositing an antireflection coating on the doped dielectric layer; screen printing a metal pattern on the antireflection coating; and firing the screen printed metal pattern through the antireflection coating and the doped dielectric layer, thereby forming screen printed emitter contacts.

Thermal oxide is well known to the microelectronics industry as one of the best dielectrics to passivate silicon surfaces. The further description relates to the front side (diffused side) of passivated emitter rear contacted (PERC) silicon solar cells and to the enhancement brought upon by a thin thermal oxide formed at 800°C in a POCI₃ furnace. The resulting emitters are characterized by secondary ion mass spectroscopy (SIMS) as well as scanning spreading resistance profiling (SRP) measurements (Fig. 3) and emitter saturation current densities (see Fig. 2). Increasing oxidation growth (or time) significantly decreases phosphorus surface concentration (N_s) while increasing junction depth. The resulting profiles after oxidation have surface concentrations in the range of l-2xl(T 207cm 3^J which are fully activated and can be contacted with industrially available silver screen printing pastes. Using a thin thermal oxide, a lower contact resistance can be obtained especially when considering emitter sheet resistances in the 85+ Ω/square range. The low contact resistance from the front metallization is attributed to the presence of phosphorous in the thermal oxide. The final cell results show that increasing oxidation growth (or time) increases open circuit voltage as well as fill factor, but if the oxide is left on the cell, the short circuit current is reduced partly due to optical loss.

The cells studied are 148.8cm cells made on 155μιη thick 1.5 ohm-cm p-type Cz-Si wafers, the cells having screen printed Ag front contacts and a thin thermal oxide on both sides with a rear deposited oxide/nitride stack. The highest efficiency of the cells studied is 19.9% with an open-circuit voltage V_oc of 654mV, a short-circuit current density J_sc of 38.4 mA/cm² and a fill factor of 79.3%.

The solar cells investigated in the further description are industrially applicable passivated emitter and rear locally Al doped Si cells. These types of cells have an excellent rear reflectance as well as an effective rear surface recombination velocity of under lOOcm/sec.

I PASSIVATION CHARACTERIZATION

1.1 Front-Side Investigation

The front- side of a PERC cell can be mimicked by the structure 1 depicted in Figure 1. Both sides of the wafer 2 (a silicon substrate or wafer) are textured, diffused to generate emitter regions 3 and passivated. In the experiments, passivation is provided by PECVD SiN_x layer 5 on top of a thermal oxide 4 generated by a 800°C dry oxidation for 0 to 60 minutes.

Figure 2 shows emitter saturation current densities as measured on the structure of Figure 1, for samples with 65 Ω/square emitter regions 3 and with different dry oxidation times (0 minutes, 10 minutes, 30 minutes and 60 minutes) at 800°C. It is shown that the emitter saturation current density decreases as a function of oxidation time and also shows a drastic difference in passivation before and after the firing step. In these experiments, the firing step was done with a peak temperature of 885°C in ambient air. To further understand why the emitter is better passivated with increasing oxidation time, SIMS and SRP was measured on each of the samples, as shown in Figure 3. Figure 3 shows each SIMS (dots) and SRP (cross sign) for different oxidation times (0 minutes, 10 minutes, 30 minutes, 60 minutes). SIMS measures the total amount of phosphorus per unit depth into the silicon whereas the SRP measures the amount of electrically active phosphorus per unit depth into the silicon. Electrically inactive phosphorus contributes to significant recombination and thus a decrease of the concentration of electrically inactive phosphorus may be preferred. From the results shown in Figure 3 it can be concluded that phosphorus surface concentration decreases as a function of oxidation time; dopants are driven in deeper and become electrically active which yields comparable sheet resistances. The best results were obtained for a 60min oxidation where the surface concentration is reduced to the limit of electrically active phosphorus (-2.5x10 20 /cm 3 ). As shown in Figure 2, the emitter saturation current density for a sample with 60 minutes oxidation is significantly reduced to 176 fA/cm 2 before annealing (as deposited) and 158 fA/cm 2 after annealing; this indicates that this emitter can be used in a "fire-free" process. As indicated in Figure 3, the sheet resistance initially increases with a 10 minute oxidation and then stays relatively constant for increasing oxidation times. The inactive phosphorus is significantly reduced after 60min oxidation and the resulting profile is almost completely active. This supports that in Figure 2 the emitter saturation current density is lowest with a 60min oxidation time.

1.2 Rear-Side Investigation

The rear-side of a PERC cell was mimicked by the structure shown in Figure 4. The 155μιη thick 1.5 ohm-cm p-type Cz-Si wafers wafer 2 was first chemically polished and then cleaned and passivated with or without a thermal oxide 41. Thermal oxidation was done at 800°C for 10 to 60 minutes. This was combined with a deposited PECVD SiO_x/SiN stack (42/5).

Minority carrier lifetime results of structures as depicted in Figure 4 have been analysed. The data suggests that increasing oxidation time increases lifetime. Lifetime was found to increase by a factor of two when comparing no oxidation to a 60 minute oxidation.

II CELL EXPERIMENTATION II.1 Introduction of thermal oxide in PERC cells

Figure 5 shows oxide thicknesses that were measured on mirror polished wafers of the <100> orientation using a single wavelength ellipsometer, both for oxides on the diffused side of the wafer (comprising a 65 Ω/square emitter region) and for oxides on the non-diffused side of the wafer, for different oxidation times (10 minutes, 30 minutes, 60 minutes) at 800°C. This is representative for the rear side but differs from the <111> random pyramid textured front-side of real solar cell devices. According to the data above (Figure 5), the PECVD SiN_x anti-reflective coating was adapted for the different oxidation times to achieve similar antireflective properties. This was done by depositing less PECVD oxide on the 60 minutes oxidized wafer vs. the 10 minutes oxidized wafer. The wavelength at which the reflectance was minimum for each of the conditions was about 630nm. Transmission electron microscopy (TEM) images of solar cell devices confirmed that the 60min oxidation resulted in a thermal oxide thickness of close to 13nm on textured <111> facets. Generally, thermal oxidation growth rates on <111> surfaces are lower than on <100> oriented surfaces. However, the thermal oxidation rate on highly phosphorus doped surfaces is significantly higher than on weakly doped test structure wafers.

Figure 6 shows reflectance curves of cells fabricated with different oxidation times. This measurement was done using an aperture size of 3.75mm x 3.75mm, which included two Ag fingers in finished cells. The data shows that increasing oxidation time increases reflection (specifically in the sub 500nm wavelengths). This is expected due to the low refractive index of silicon oxide compared to hydrogenated SiN (SiN:H).

Figure 7 gives an overview of the process flow for p-type PERC solar cells including thermal oxidation times of 0, 10, 30 and 60 minutes respectively as used in the experiments. After texturing and rear side polishing of a silicon wafer, a cleaning step was performed and an emitter diffusion process was done in a POCl₃ furnace, resulting in a 65 Ω/square emitter region at both sides of the wafer. Next the emitter region at the rear side was removed and a cleaning step was performed. This was optionally followed by a dry oxidation step at 800°C (oxidation time 0 minutes, 10 minutes, 30 minutes or 60 minutes). At the front side a silicon nitride antireflection coating (ARC) was deposited and at the rear side an PECVD silicon oxide / silicon nitride stack was provided. Laser ablation was then used to make local contact openings through the PECVD stack at the rear side and next a 2 micrometer thick Al layer was deposited on the rear surface. At the front surface a silver paste was provided by screen printing, followed by a firing step at 885°C, resulting in the penetration of the patterned silver paste through the antireflection coating to the underlying silicon and the formation of front side metal contacts. In the same firing process good Al contacts and back surface field (BSF) regions are formed at the rear side.

Figure 8 shows the evolution of the short-circuit current density J_sc with oxidation time, for cells fabricated in accordance with the process flow of Figure 7. The short-circuit current density decreases as a function of oxidation time, which can be expected since the reflectance in the sub 500nm range is significantly higher for higher oxide thicknesses as shown in Figure 6.

Figure 9 shows the progression of V_oc with oxidation time. As expected from the emitter saturation current density results (Figure 2) the 60 minute oxidation out performs the rest and the open-circuit voltage increases with increasing oxide thickness. The gain can be attributed to a reduced phosphorus concentration at the front surface and also to the enhanced passivation from the rear side.

The most surprising result from this experiment was that the fill factor increases significantly with oxidation growth, as shown in figure 10. Considering that the surface concentration of the phosphorus is greatly reduced and the emitter sheet resistance is 5% higher in the 60 minute oxide case, this trend is a surprise. Further experimentation has been done in order to understand if the fill factor enhancement is related to an effect at the front side or at the rear side of the cells.

More oxidation seems to improve cell results; the major improvement is in fill factor as shown in Figure 10. The improvement in efficiency is illustrated in Figure 11. The reason for the performance gain in open circuit voltage is due to the enhanced passivation from the oxide.

II.2 Front Oxide Etched

In order to further investigate to which level the oxide enhances performance, an experiment has been done wherein first a thermal oxide was grown for 60 minutes as in the previous experiments, and wherein the front oxide was then etched as illustrated in Figure 12 ("front oxide etched"). As a reference, "standard' cells were fabricated wherein the thermal oxide remained on the front surface (as illustrated in figure 12). This experiment allows for the emitters of the "standard" cells and the "front oxide etched" cells to have exactly the same diffusion profile, the same active profile as well as for the rear sides to have exactly the same passivation. The only difference between cells that are "Front Oxide Etched" and cells that are "Standard" is the oxide is etched or kept on the front side.

Table 1 shows the cell characteristics measured on both types of cells, for cells with a 65 Ω/square emitter and for cells with a 80 Ω/square emitter.

TABLE 1

AVERAGE CELL RESULTS CONDITION JSC VOC FF PSEUDO EFFICIENCY

(EMITTER) [MA/CM²] [MV] [%] FF [%]

[ ]

Front Oxide Etched 37^~8 642 79 832 Ϊ92

(65Ω/α)

Standard 37.6 644 79.9 83.5 19.4

(65Ω/α)

Front Oxide Etched 38 643 76/7 83^~Ί ΠΓδ

(80Ω/α)

Standard 38.2 651 79.1 83.4 19.7

(80Ω/α)

Etching the oxide off the front-side clearly results in a lower cell efficiency, and the effect is more pronounced for cells with an 80 Ω/square (Ω /□) emitter than for cells with a 65 Ω/square emitter. A 0.9% and a 0.2% absolute difference in cell efficiency can be observed respectively.

The fill factor is significantly degraded especially for the 80 Ω/square cells when the front oxide is etched. This is the major contributor to the lower cell performance. Just as in Figure 10 where it is observed that more oxidation increases fill factor, it is shown here that one way to achieve a high fill factor is keeping the oxide on the front side. This experiment proves that the fill factor enhancement is coming from the oxide itself rather than for instance from the difference in the emitter profile or from the rear side.

The relative differences in current densities between etching the front-side oxide off and keeping it are insignificant; at most there is a 0.2mA/cm difference. Lower reflectance in the UV is most likely the cause of the gain in short circuit current for the group of cells with 65 Ω/square emitter. As for the group of cells with an 80 Ω/square emitter, the opposite trend of the short circuit current can be explained by the fact that the oxide thickness is not as large, thus minimizing the loss in reflectance in the UV. Besides, the reduced dead layer in the 80 Ω/square emitter in conjunction with thermal oxide passivation enable more minority carrier collection in this region and thus higher short circuit current density.

The open circuit voltage difference in the group of cells with a 65 Ω/square emitter is insignificant which further explains why the current is increased when the front oxide is etched. But this is not true for the group of cell with the 80 Ω/square emitter: there is a clear 8mV gain and the emitter is clearly better passivated with the oxide.

There is a slight difference in pseudo fill factor, but this small difference does not account for the larger difference shown in the measured fill factor. If the emitter was significantly scratched, this would cause a localized shunt and thus a lower pseudo fill factor. This measurement proves that the protection (from scratches) and passivation aspect of the thermal oxide provides a maximal gain of 0.3% in fill factor. It is clear that the oxide is causing a gain in fill factor regardless of the small difference in pseudo fill factor.

Figure 13 shows the two distributions of fill factor vs. sheet resistance that correspond to the oxide being present or not. The graph clearly shows that a relatively high fill factor is achieved even at high sheet resistances when oxide is used. The decrease in fill factor as a function of sheet resistance is much more rapid in the case where there is no oxide. Since Table 1 shows that the pseudo fill factors are similar, the only explanation for fill factor increase is a decrease in series resistance.

The major contributor to the difference in series resistance between cells with oxide and without oxide is shown in Figure 14. The contact resistivity is shown to be much lower (by almost an order of magnitude) for cells with oxide. This data suggests that the major contributor to the increase in series resistance is that the contacting mechanism is being altered with an oxide. Material analysis was done to further understand. II.3 Varying phosphorus content in Si0₂

Figure 15 shows the SIMS profile for varying oxidation conditions of an 80 Ω/square emitter. The first of which is the "standard" 60 minutes oxidation condition. It is shown that a large phosphorus peak is located inside the about 14nm thick silicon oxide. In the second profile, the 60min oxide is etched back by 75% such that about 4nm of the originally about 14nm thick oxide remains. What remains is the large phosphorus peak in the oxide. The third profile is an emitter that has been oxidized with the full 60min oxidation; the oxide was then completely stripped in HF and then re-grown for lOmin. The resulting oxide thickness is about 4nm and the profile of the emitter has not been significantly altered, the profiles between the etched back oxide cell and the re-grown oxide are almost identical. The purpose of this experiment was to vary the amount of phosphorus in the oxide in order to understand the relationship between the peak concentrations of phosphorus in the oxide vs. contact resistance. Measurement results for the different conditions are shown in table 2.

TABLE 2

AVERAGE CELL RESISTANCE VALUES

CONDITION RsHEET CONTACT RESISTIVITY RsERIES FF PSEUDO FF

[ιηΩ-cm²] [%]

[Ω/α] [ιηΩ-cm ] [%]

60min Oxidation 78.0 3.24 567 79.9 83.5

60min Oxidation 84.9 7.56 754 78.3 83.4

+75% Etched Back

60min Oxidation 80.2 26.8 1405 75.3 83.6

+HF

+ lOmin Oxidation

Table 2 shows that the re-oxidized cells have a very high (26.8 mH'cm²) contact resistance compared to the other cells having their original oxide. There is a large difference in contact resistance and thus fill factor between the etched back cells with the cells that are re-oxidized. This is an indication that the phosphorus level in the oxide is the primary reason for a low contact resistance. In order to further investigate this hypothesis, more cells were re-oxidized with different times in order to vary the level of phosphorus in the oxide. The results are shown in Figure 16.

Figure 16 shows the contact resistance vs. sheet resistance with varying levels of phosphorus in the oxide. The 100% level for this graph is the amount of phosphorous in the oxide grown for 60 minutes. It is shown that decreasing the level of phosphorus in the oxide clearly increases contact resistance for any given sheet resistance. Also, no oxide is shown to be the worst case scenario, where the contact resistance increases by roughly an order of magnitude. Contrarily, if more phosphorus is used in the "oxide" such as in the PSG case, the contact resistance is shown to be further reduced. This is an indication that the phosphorus level in the oxide can indeed decrease the contact resistance.

It has been shown that a large peak of phosphorus in the thermal oxide can enable contacting high resistance emitters (for example about 95 Ohm/square) with industrially available pastes. Although thermal oxide is not the only way to incorporate phosphorus in the oxide, PSG (PhosphoSilicateGlass) can also be used. It has been found that PSG is not adequate for passivation, but from the contacting mechanism it works similarly in the sense that it can be used to contact e.g. up to 95 Ω/square emitters with contact resistances below 3 mH'cm².

The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the scope of the invention.

Claims

1. A method for fabricating silicon photovoltaic cells, the method comprising:

providing a doped dielectric layer of the first doping type on the front surface of the crystalline silicon substrate;

2. A method according to claim 1, wherein forming an emitter region comprises forming a homogeneous emitter region.

3. A method according to claim 1 or 2, wherein said doped dielectric layer is a doped silicon oxide layer or a doped silicon nitride layer.

4. A method according to any of the previous claims, comprising providing the doped dielectric layer on the entire front surface of the silicon substrate.

5. A method according to any of the previous claims 1 to 3, wherein providing the doped dielectric layer comprises providing the doped dielectric layer selectively, at least at locations where the screen printed contacts are to be formed.

6. A method according to claim 5, wherein providing the doped dielectric layer comprises providing the doped dielectric layer selectively, only at locations where the screen printed contacts are to be formed.

7. A method according to claim 6, wherein the doped dielectric layer is a patterned dielectric layer having a pattern corresponding to the pattern of the screen printed contacts.

8. A method according to claim 7, wherein said pattern of screen printed contacts comprises a plurality of narrow lines (fingers), the patterned dielectric layer having corresponding lines of the dielectric layer which have at least the same width as the lines of the contact pattern.

9. A method according to any of the previous claims, wherein providing said doped dielectric layer comprises providing an undoped dielectric layer on the entire emitter surface of the photovoltaic cell and selectively doping said undoped dielectric layer at locations where screen printed contacts are to be provided.

10. A method according to any of the previous claims 1 to 9, wherein providing a doped dielectric layer comprises thermally growing a dielectric layer.

11. A method according to any of the previous claims 1 to 9, wherein providing a doped dielectric layer comprises doing a chemical oxidation, such as during a cleaning step after the emitter diffusion.

12. A method according to any of the previous claims 1 to 9, wherein providing a doped dielectric layer comprises patterning a doped dielectric layer by selectively removing a phosphosilicate glass (PSG) layer that is formed on the entire front surface during emitter diffusion.