[go: up one dir, main page]

WO2014041822A1 - Substrat semi-conducteur et élément semi-conducteur - Google Patents

Substrat semi-conducteur et élément semi-conducteur Download PDF

Info

Publication number
WO2014041822A1
WO2014041822A1 PCT/JP2013/050117 JP2013050117W WO2014041822A1 WO 2014041822 A1 WO2014041822 A1 WO 2014041822A1 JP 2013050117 W JP2013050117 W JP 2013050117W WO 2014041822 A1 WO2014041822 A1 WO 2014041822A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
semiconductor
substrate
semiconductor layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2013/050117
Other languages
English (en)
Japanese (ja)
Inventor
小野　瑞城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Publication of WO2014041822A1 publication Critical patent/WO2014041822A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675—Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium

Definitions

  • Embodiments described herein relate generally to a semiconductor substrate in which a semiconductor layer is formed on a support substrate via a buried insulating film, and a semiconductor element using the semiconductor substrate.
  • the buried insulating film is formed of a material having a higher dielectric constant than that of conventional silicon oxide.
  • forming the buried insulating film with a material having a high dielectric constant also enhances the capacitive coupling between the source / drain region and the channel region through the buried insulating film.
  • a problem to be solved by the present invention is to provide a semiconductor substrate and a semiconductor element using the substrate, which can contribute to improvement of controllability of a threshold voltage by substrate bias and improvement of controllability of a gate electrode with respect to a potential of a channel region. That is.
  • the semiconductor substrate of the embodiment is formed in contact with the embedded insulating film on the opposite side of the supporting substrate, the embedded insulating film formed in contact with one main surface of the supporting substrate, and the supporting insulating substrate. And a semiconductor layer having a thickness smaller than that of the support substrate.
  • the dielectric constant of the region in contact with the semiconductor layer of the buried insulating film is lower than the dielectric constant of the region in contact with the support substrate.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor substrate used for manufacturing the semiconductor element of the first embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor element of the first embodiment.
  • FIG. 4 is a characteristic diagram for explaining the performance of the semiconductor device of the first embodiment.
  • FIG. 5 is a characteristic diagram for explaining the performance of the semiconductor device of the first embodiment.
  • FIG. 6 is a cross-sectional view showing the manufacturing process of the first modification of the first embodiment.
  • FIG. 7 is a cross-sectional view showing the manufacturing process of the second modified example of the first embodiment.
  • FIG. 8 is a cross-sectional view showing the manufacturing process of the third modified example of the first embodiment.
  • FIG. 9 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the second embodiment.
  • FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor substrate used for manufacturing the semiconductor element of the second embodiment.
  • FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device of the second embodiment.
  • FIG. 12 is a cross-sectional view showing the manufacturing process of the first modification of the second embodiment.
  • FIG. 13 is a cross-sectional view showing the manufacturing process of the second modification of the second embodiment.
  • FIG. 14 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the third embodiment.
  • FIG. 15 is a cross-sectional view showing a manufacturing process of a semiconductor substrate used for manufacturing the semiconductor device of the third embodiment.
  • FIG. 16 is a cross-sectional view showing a manufacturing process of the semiconductor device of the third
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment.
  • a buried insulating film 2 is formed on a support substrate 1 made of silicon.
  • the buried insulating film 2 has a laminated structure in which a hafnium oxide film 3 having a thickness of 19 nm is formed on the support substrate 1 side, and a silicon oxide film 4 having a thickness of 1 nm is formed thereon.
  • a semiconductor layer 5 made of silicon is formed on the buried insulating film 2.
  • a source region 6 containing As (arsenic) and a drain region 7 are formed, and a channel region 8 containing B (boron) is formed between the source / drain regions 6, 7.
  • a gate electrode 10 is formed on the channel region 8 via a gate insulating film 9 having a laminated structure of hafnium oxide and silicon oxide. Gate sidewall insulating films 11 are formed on both sides of the gate electrode 10.
  • FIG. 1 the wiring metal, the interlayer insulating film, etc. are omitted. Further, FIG. 1 is for easy understanding of the structure of the element, and the scale in FIG. 1 is not accurate. Further, the present invention is not limited to the following embodiments, and various modifications can be used.
  • a hafnium oxide film 3 having a thickness of 19 nm is formed on a support substrate 1 such as silicon by a method such as chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • a silicon oxide film 4 having a thickness of 1 nm is formed on the silicon substrate 12 by a method such as a thermal oxidation method.
  • the hafnium oxide film 3 formed on the support substrate 1 and the silicon oxide film 4 formed on the silicon substrate 12 are bonded together by a method such as heating. Through this process, the hafnium oxide film 3 and the silicon oxide film 4 have a laminated structure, and the buried insulating film 2 is formed.
  • the silicon substrate 12 becomes the semiconductor layer 5.
  • a silicon oxide film (not shown) having a thickness of 1 nm is formed on the semiconductor layer 5 by a method such as thermal oxidation.
  • a hafnium oxide film having a thickness of 5 nm is formed by a method such as CVD, thereby forming a laminated insulating film 13 of a silicon oxide film and a hafnium oxide film.
  • a tungsten film 14 having a thickness of 50 nm is formed on the laminated insulating film 13 by a method such as CVD.
  • a part of the tungsten film 14 is selectively removed by processing such as an active ion etching method, thereby forming the gate electrode 10 made of a tungsten film.
  • a part of the stacked insulating film 13 is selectively removed by performing a process such as a wet process, thereby forming the gate insulating film 9 made of the stacked insulating film.
  • the extension region 15 is formed by implanting As into the semiconductor layer 5 using the gate electrode 10 as a mask.
  • a gate sidewall insulating film 11 is formed on the side portion of the gate electrode 10. Specifically, after a silicon oxide film having a thickness of 20 nm is formed on the entire surface by a method such as CVD, a part of the silicon oxide film is selectively removed using a method such as an active ion etching method. As a result, the silicon oxide film remains only on the side surface of the gate electrode 10.
  • the source region 6 and the drain region 7, and the channel region 8 sandwiched between them are formed together with the extension region 15. Thereby, the structure shown in FIG. 1 is obtained. Thereafter, an n-type MOS transistor is completed through an interlayer insulating film formation process, a wiring process, and the like in the same manner as in the prior art.
  • n-type MOS transistor In this embodiment, the case of an n-type MOS transistor has been described as an example. However, if an impurity is introduced only into a specific region in the substrate using a method such as a photo-etching method or a lithography process, the n-type MOS transistor In addition to this, it is also possible to construct a p-type MOS transistor. That is, it is possible to manufacture a CMOS semiconductor device having an n-type MOS transistor and a p-type MOS transistor.
  • the process of forming only a single MOS transistor has been described.
  • the present invention is not limited to this, and active elements such as field effect transistors, bipolar transistors, and single electron transistors, resistors, diodes, and the like.
  • the present invention can also be applied to the case where a semiconductor element is formed as a part of a semiconductor device including a passive element such as an inductor or a capacitor, or a semiconductor memory element.
  • the present invention can also be used when a semiconductor element is formed as a part of a semiconductor device including an element using a ferroelectric material and an element using a magnetic material.
  • OEIC Opt-Electrical-Integrated-Circuit
  • MEMS Micro-Electro-Mechanical System
  • the impurity for forming the n-type semiconductor layer As is used as the impurity for forming the n-type semiconductor layer, and B is used as the impurity for forming the p-type semiconductor layer. However, the impurity for forming the n-type semiconductor layer is used. Another group V impurity may be used as the impurity, and another group III impurity may be used as the impurity for forming the p-type semiconductor layer. Further, the introduction of Group III group or Group V impurities may be carried out in the form of a compound containing them.
  • the introduction of impurities into the source / drain regions is performed using ion implantation, but may be performed using a method other than ion implantation such as solid phase diffusion or vapor phase diffusion.
  • a method of depositing or growing a semiconductor containing impurities may be used.
  • the ion implantation method there is an advantage that it is easy to form a complementary semiconductor device including an n-type semiconductor element and a p-type semiconductor element.
  • a semiconductor containing impurities is deposited or impurities are introduced using a method such as solid phase diffusion or vapor phase diffusion, there is an advantage that a high impurity concentration can be easily realized.
  • a stressor may be formed on the source / drain regions. In this case, it is preferable to apply strain to the channel region because the mobility of current carriers is improved.
  • the impurity for adjusting the threshold voltage is different from the introduction of the impurity into the silicon substrate before forming the gate electrode. You may introduce. In this way, there is an advantage that the threshold voltage can be easily set to a desired value. Further, according to the present embodiment, there is an advantage that the process can be simplified.
  • silicon is used as a semiconductor layer for forming an element.
  • the semiconductor layer is not limited to silicon, and germanium or a mixed crystal of silicon and germanium may be used. Germanium or a mixed crystal of silicon and germanium is preferable because it has an advantage of higher mobility of current carriers than silicon.
  • a semiconductor that is a compound of a group III element and a group V element may be used as a semiconductor layer forming the element. Such compounds are also preferred because they have the advantage of higher current carrier mobility than silicon.
  • InAs indium arsenide
  • InGaAs indium gallium arsenide
  • InSb indium antimony
  • strain to the channel region because the mobility can be improved.
  • the conventional manufacturing process can be used as it is, and thus there is another advantage that the manufacturing process can be easily constructed.
  • the source / drain regions are formed after the processing of the gate electrode or the gate insulating film.
  • the order is not essential, and the order may be reversed.
  • the gate electrode is formed using tungsten, but may be formed using another metal. You may form by semiconductors, such as a single crystal silicon and an amorphous silicon, the compound containing a metal, etc., or those lamination
  • the gate electrode is formed using a semiconductor, there is an advantage that the threshold voltage can be easily controlled.
  • another advantage is that it is easy to set the threshold voltage to a desired value for both the n-type semiconductor element and the p-type semiconductor element.
  • the gate electrode is formed of metal, the oxidation reaction does not easily proceed, so that there is an advantage that the controllability of the interface is good, for example, the level at the interface between the gate electrode and the insulating film is suppressed.
  • the gate electrode is formed by using a method in which anisotropic etching is performed after depositing the material.
  • a method such as embedding such as a damascene process is used. May be formed.
  • the length of the gate electrode measured in the main direction of the current flowing through the element is equal to the upper part and the lower part of the gate electrode, but this is not essential.
  • the length of the upper part of the gate electrode measured in the shape of an alphabet “T” may be longer than the length measured in the lower part. In this case, there is an advantage that the gate resistance can be reduced.
  • the process such as silicide or germanide is not mentioned, but a silicide or germanide layer or the like may be formed on the source / drain region. Further, a method of depositing or growing a layer containing a metal on the source / drain regions may be used. This is preferable because the resistance of the source / drain regions is reduced.
  • a process such as silicide or germanide may be performed on the gate electrode. In that case, it is preferable to perform a process such as silicide or germanide because the gate resistance is reduced. Further, an elevator structure may be used. The resistance of the source / drain region is also reduced by the elevated structure.
  • the upper part of the gate electrode has a structure in which the electrode is exposed, but an insulator such as silicon oxide, silicon nitride, or silicon oxynitride may be provided on the upper part.
  • an insulator such as silicon oxide, silicon nitride, or silicon oxynitride may be provided on the upper part.
  • the gate electrode is formed of a material containing a metal and a silicide or germanide layer is formed on the source / drain region, it is necessary to protect the gate electrode during the manufacturing process. In this case, it is essential to provide a protective material such as silicon oxide, silicon nitride, or silicon oxynitride on the gate electrode.
  • a stacked insulating film of a hafnium oxide film and a silicon oxide film is used as a gate insulating film.
  • an insulating film such as a silicon oxide film or a silicon oxynitride film, or other stacked films such as a stacked film thereof.
  • An insulating film may be used.
  • nitrogen is present in the insulating film, the diffusion of the threshold voltage is suppressed because the diffusion of the impurity into the substrate is suppressed when polycrystalline silicon containing the impurity is used as the gate electrode.
  • the interface state at the interface with the gate electrode and the fixed charge in the insulating film are small, so that there is an advantage that variation in device characteristics is suppressed.
  • a method of first forming a film of the material and oxidizing it may be used. Moreover, you may expose to the oxygen gas of the excitation state which does not necessarily accompany temperature rising.
  • a silicon oxide film may be formed first, and then nitrogen may be introduced into the insulating film by exposure to a gas containing nitrogen in a heated state or an excited state. If formed by using a method of exposing to an excited nitrogen gas that is not accompanied by an increase in temperature, it is possible to prevent the impurity in the channel region from changing its concentration distribution due to diffusion.
  • a silicon nitride film may be formed, and then oxygen may be introduced into the insulating film by exposure to a gas containing oxygen in a heated state or an excited state. If formed by using a method of exposing to an excited oxygen gas that is not accompanied by an increase in temperature, the concentration distribution of impurities in the channel region can be suppressed from changing due to diffusion.
  • a gate insulating film material Hf (hafnium), Zr (zirconium), Ti (titanium), Sc (scandium), Y (yttrium), Ta (tantalum), Al (aluminum), La (lanthanum), Ce ( Cerium), Pr (praseodymium), oxides of metals such as lanthanoid series elements including others, silicate materials containing various elements including these elements, etc., or even nitrogen
  • a high dielectric film such as an insulating film contained may be used.
  • other insulating films such as a laminate thereof may be used.
  • the method for forming the insulating film is not limited to the CVD method, and other methods such as a thermal oxidation method, a vapor deposition method, a sputtering method, or an epitaxial growth method may be used.
  • a stacked insulating film of a hafnium oxide film and a silicon oxide film is used as the buried insulating film.
  • hafnium oxide Hf, Zr, Ti, Sc Y, Ta, Al, La, Ce, Pr, or oxides of metals such as lanthanoid series elements including others, silicate materials containing various elements including these elements, or the like, or A high dielectric film such as an insulating film containing nitrogen may also be used.
  • other insulating films such as a laminate thereof may be used.
  • an insulating film such as a silicon nitride film or a silicon oxynitride film, or another insulating film such as a stacked layer thereof may be used.
  • silicon oxide is used, the interface state at the interface with the semiconductor layer and the fixed charge in the insulating film are small, so that there is an advantage that variation in device characteristics is suppressed.
  • a method of first forming a film of the substance and oxidizing it may be used. Moreover, you may expose to the oxygen gas of the excitation state which does not necessarily accompany temperature rising.
  • silicon oxynitride first, a silicon oxide film may be formed, and then nitrogen may be introduced into the insulating film by exposure to a gas containing nitrogen in a heated state or an excited state.
  • a silicon nitride film may be formed, and then oxygen may be introduced into the insulating film by exposure to a gas containing oxygen in a heated or excited state.
  • the method for forming the insulating film is not limited to the CVD method, and other methods such as a thermal oxidation method, a vapor deposition method, a sputtering method, or an epitaxial growth method may be used.
  • post-oxidation after the formation of the gate electrode is not mentioned, but a post-oxidation step may be performed if possible in view of the material of the gate electrode.
  • the process is not necessarily limited to post-oxidation, and a process of rounding the corners of the gate electrode may be performed using a method such as chemical treatment or exposure to a reactive gas. If these steps are possible, the electric field at the lower end corner of the gate electrode is relaxed, which improves the reliability of the gate insulating film, which is preferable.
  • a silicon oxide film may be used as the interlayer insulating film.
  • a substance other than silicon oxide such as a low dielectric constant material may be used for the interlayer insulating film.
  • contact holes it is possible to form self-aligned contacts.
  • the use of the self-aligned contact is preferable because the area of the element can be reduced, and the degree of integration can be improved.
  • the formation of the metal layer for wiring may be performed using, for example, a sputtering method or a method such as a deposition method. Further, a method such as selective metal growth may be used, or a method such as damascene method may be used.
  • the wiring metal material may be Al containing silicon or a metal such as Cu (copper). In particular, Cu is preferable because of its low resistivity.
  • the gate length is 25 nm
  • the gate insulating film is silicon oxide having a thickness of 1 nm
  • the semiconductor layer is silicon having a thickness of 10 nm.
  • the relative dielectric constant of the buried insulating film was 3.9 assuming silicon oxide in the element shown in FIG. 4A, and 20 in the element shown in FIG. 4B assuming hafnium oxide.
  • the oxide equivalent film thickness (a value obtained by dividing the product of the film thickness and the dielectric constant of silicon oxide (3.9) by the dielectric constant of the insulating film) is 3.
  • the thickness was 9 nm. That is, the thickness of the buried insulating film was set to 3.9 nm in the element shown in FIG. 4A and 20 nm in the element shown in FIG.
  • FIG. 4C shows the result of the element having a buried insulating film having a dielectric constant of 3.9 and a thickness of 20 nm. That is, the element shown in FIG. 4A is an element whose thickness is reduced to 3.9 nm without changing the dielectric constant of the buried insulating film of the element shown in FIG. 4C, and the element shown in FIG. This corresponds to the element having a relative dielectric constant of 20 without changing the thickness of the buried insulating film of the element shown in FIG. In all cases, the drain voltage is 1V. Comparing FIGS. 4A and 4B to FIG.
  • the dependence of the threshold voltage on the substrate bias is shown in FIG.
  • the elements replaced with a material having a dielectric constant of 3.9 as an interface layer only on the semiconductor layer side of the buried insulating film having a rate of 20 are also shown side by side.
  • the interface layer has a thickness of 1 nm and 2 nm.
  • the equivalent oxide thickness of the buried insulating film is set to 3.9 nm as in the element shown in FIGS.
  • the threshold voltage is defined as the gate voltage at which the drain current per 1 ⁇ m width of the element is 100 nA. Therefore, there is no threshold voltage depending on the value of the substrate bias.
  • the slope of the graph is larger for the element having the dielectric constant of the buried insulating film indicated by the long broken line of 20 than the element having the dielectric constant of the buried insulating film indicated by the solid line of 3.9. That is, it can be seen that the dependency of the threshold voltage on the substrate bias is large.
  • An element having an interface layer thickness of 1 nm indicated by an alternate long and short dash line and an element having an interface layer thickness of 2 nm indicated by an alternate long and two short dashes line are indicated by an element having a dielectric constant of 3.9 and a long broken line. It can be seen that the buried insulating film has a dielectric constant of 20 elements.
  • FIG. 5B the dependency of the S factor on the substrate bias is shown in FIG.
  • the buried insulating film shown in FIG. 4B shown by a broken line is compared with the element in which the dielectric constant of the buried insulating film shown in FIG. 4A shown by a solid line is 3.9.
  • the element having a dielectric constant of 20 has a significantly larger S factor.
  • the increase in the S factor is effectively suppressed in the element having the interface layer thickness of 1 nm indicated by the one-dot chain line and the element having the interface layer thickness of 2 nm indicated by the two-dot chain line.
  • FIG. 5C shows the relationship between the average value obtained by differentiating the threshold voltage by the substrate bias and the average value of the S factor.
  • the result of the above element is shown by a solid line, and the result of an element in which a region having a relative dielectric constant of 3.9 is provided at 1 nm to 2 nm on the support substrate side of the buried insulating film is also shown by a dotted line. Show. As shown in FIG.
  • the variation amount of the threshold voltage with respect to the substrate bias is equal.
  • the S factor is suppressed to a low value when the low dielectric constant region is provided on the semiconductor layer side. That is, it is essential to provide a low dielectric constant region on the semiconductor layer side. Therefore, it can be seen that the element having the structure of the present embodiment can suppress the increase of the S factor and increase the dependency of the threshold voltage on the substrate bias.
  • the capacitive coupling between the support substrate 1 and the element forming semiconductor layer 5 is increased, and the threshold voltage due to the substrate bias is increased. Controllability can be improved. Further, by using a material having a low dielectric constant on the element forming semiconductor layer 5 side of the buried insulating film 2, capacitive coupling between the channel region 8 and the source / drain regions 6 and 7 through the buried insulating film 2 is reduced. Can do. For this reason, FIBL can be suppressed and controllability of the gate electrode 10 with respect to the potential of the channel region 8 can be improved.
  • a 1 nm thick silicon oxide film 4 is formed on the hafnium oxide film 3 on the support substrate 1 by a method such as CVD. To do.
  • the silicon substrate 12 is bonded onto the silicon oxide film 4 by a method such as heating.
  • the hafnium oxide film 3 and the silicon oxide film 4 become a buried insulating film 2 having a laminated structure.
  • the buried insulating film 2 is a laminate of the hafnium oxide film 3 and the silicon oxide film 4, but a plurality of types of films are not sequentially formed in this way, but, for example, a material gas used for the CVD method Alternatively, the film may be continuously formed by a method such as switching. Further, for example, a buried insulating film whose dielectric constant continuously changes in the film thickness direction may be formed by a method such as continuously changing a material gas used for the CVD method.
  • a hafnium oxide film 3 having a thickness of 19 nm is formed on the silicon oxide film 4 on the silicon substrate 12 by a method such as CVD. To do.
  • the support substrate 1 is bonded onto the hafnium oxide film 3 by a method such as heating.
  • the hafnium oxide film 3 and the silicon oxide film 4 become a buried insulating film 2 having a laminated structure.
  • hydrogen ions 16 are implanted into the silicon substrate 12 by a method such as ion implantation.
  • a method such as ion implantation.
  • defects are introduced into the ion implanted region, and the silicon substrate 12 is easily broken at this portion.
  • the hafnium oxide film 3 formed on the support substrate 1 and the silicon oxide film 4 formed on the silicon substrate 12 are bonded by a method such as heating. Match.
  • the hafnium oxide film 3 and the silicon oxide film 4 become the buried insulating film 2 having a laminated structure.
  • a part of the silicon substrate 12 is removed by a method such as a temperature rise. Specifically, the upper portion of the silicon substrate 12 is removed with the ion-implanted region as a boundary. Thereafter, the surface of the silicon substrate 12 is polished and flattened by, for example, a mechanical polishing method, thereby forming the semiconductor substrate of the present embodiment. By this step, the silicon substrate 12 becomes the semiconductor layer 5.
  • FIG. 9 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the second embodiment.
  • symbol is attached
  • a buried insulating film 2 having a stacked structure of a hafnium oxide film 3 and a silicon oxide film 4 is formed on a support substrate 1 made of, for example, silicon, and a semiconductor made of germanium is formed thereon.
  • Layer 25 is formed.
  • a source region 6 containing As and a drain region 7 are formed, and a channel region 8 containing B is formed between them.
  • a gate electrode 10 is formed on the channel region 8 via a gate insulating film 9 having a laminated structure of hafnium oxide and silicon oxide.
  • Gate sidewall insulating films 11 are formed on both sides of the gate electrode 10.
  • FIG. 9 is for easy understanding of the element structure, and the scale in FIG. 9 is not accurate. Further, the present invention is not limited to the following embodiments, and various modifications can be used.
  • FIGS. 10 (a) to 10 (d) The manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS. 10 (a) to 10 (d) and FIGS. 11 (a) to 11 (d).
  • a hafnium oxide film 3 having a thickness of 19 nm is formed on a support substrate 1 by a method such as CVD.
  • a silicon oxide film 4 having a thickness of 1 nm is formed on the hafnium oxide film 3 by a method such as CVD. Up to this point, the process is the same as that shown in FIG.
  • a germanium substrate 20 is bonded to the hafnium oxide film 3 and the silicon oxide film 4 formed on the support substrate 1 by a method such as heating.
  • the hafnium oxide film 3 and the silicon oxide film 4 become a buried insulating film 2 having a laminated structure.
  • the germanium substrate 20 becomes the semiconductor layer 25.
  • a silicon oxide film having a thickness of 1 nm is formed on the semiconductor layer 25 by a method such as CVD (FIG. 11). (Not shown). Subsequently, a hafnium oxide film having a thickness of 5 nm is formed by a method such as CVD, and a laminated insulating film 13 of a silicon oxide film and a hafnium oxide film is formed.
  • a tungsten film 14 having a thickness of 50 nm is formed by a method such as CVD.
  • a part of the tungsten film 14 is selectively removed by, for example, a treatment such as an active ion etching method, and the gate electrode 10 made of the tungsten film is formed.
  • a part of the stacked insulating film 13 is selectively removed by performing a process such as a wet process, and a gate insulating film 9 made of the stacked insulating film is formed.
  • the extension region 15 is formed by implanting As into the semiconductor layer 25 using the gate electrode 10 as a mask.
  • a silicon oxide film (not shown) having a thickness of 20 nm is formed by a method such as CVD. Subsequently, a part of the silicon oxide film is selectively removed by using a method such as an active ion etching method, and the gate sidewall insulating film 11 is formed.
  • silicon is used as the semiconductor layer 5 forming the element
  • germanium is used as the semiconductor layer 25 forming the element.
  • the semiconductor layer 25 is not limited to germanium, and a mixed crystal of silicon and germanium may be used. Germanium or a mixed crystal of silicon and germanium is preferable because it has an advantage of higher mobility of current carriers than silicon.
  • a mixed crystal layer 22 of silicon and germanium with relaxed lattice strain is formed on the silicon substrate 12 by a method such as epitaxial growth. Form.
  • the germanium layer 25 is formed by lattice matching on the mixed crystal layer 22 by a method such as an epitaxial growth method.
  • the germanium layer 25 is bonded together by a method such as heating.
  • the hafnium oxide film 3 and the silicon oxide film 4 become a buried insulating film 2 having a laminated structure.
  • the silicon substrate 12 is removed by a method such as a mechanical polishing method, and the mixed crystal layer 22 is further removed.
  • a part of the germanium layer 25 may be removed following the removal of the silicon substrate 12 and the mixed crystal layer 22.
  • a mixture of silicon and germanium is formed on the hafnium oxide film 3 and the silicon oxide film 4 formed on the support substrate 1.
  • the crystal substrate 23 is bonded by a method such as heating. Through this step, the hafnium oxide film 3 and the silicon oxide film 4 become a buried insulating film 2 having a laminated structure.
  • the mixed crystal substrate 23 of silicon and germanium becomes the mixed crystal layer (semiconductor layer) 24.
  • a part of the mixed crystal layer 24 is oxidized by a method such as thermal oxidation, and the formed oxide layer (not shown) is removed by a method such as wet processing.
  • the mixed crystal layer 24 is thinned.
  • the germanium concentration in the mixed crystal layer 24 is increased, and a semiconductor layer or germanium layer 25 containing a high concentration of germanium is formed.
  • FIG. 14 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the third embodiment.
  • symbol is attached
  • a buried insulating film 2 having a stacked structure of a hafnium oxide film 3 and a silicon oxide film 4 is formed on a support substrate 1 made of, for example, silicon, and an In (indium) film is formed thereon.
  • a semiconductor layer 35 made of a mixed crystal of Al, Ga (gallium), and As is formed.
  • a source region 6 containing silicon and a drain region 7 are formed, and a channel region 8 containing Zn (zinc) is formed therebetween.
  • a gate electrode 10 is formed on the channel region 8 via a gate insulating film 39 made of a laminate of hafnium oxide and aluminum oxide. Gate sidewall insulating films 11 are formed on both sides of the gate electrode 10.
  • a hafnium oxide film 3 having a thickness of 19 nm is formed on a support substrate 1 by a method such as CVD.
  • a silicon oxide film 4 having a thickness of 1 nm is formed on the hafnium oxide film 3 by a method such as CVD. Up to this point, the process is the same as that shown in FIG.
  • a mixed crystal substrate 30 of In, Ga, and As is heated, for example, on the hafnium oxide film 3 and the silicon oxide film 4 formed on the support substrate 1. Affix by the method such as. Through this process, the hafnium oxide film 3 and the silicon oxide film 4 become the buried insulating film 2 having a laminated structure.
  • the mixed crystal substrate 30 of In, Ga, and As is removed by a method such as a mechanical polishing method to form the semiconductor substrate of this embodiment.
  • the mixed crystal substrate 30 of In, Ga, and As becomes the semiconductor layer 35.
  • an aluminum oxide film having a thickness of 2 nm is formed on the semiconductor layer 35 by a method such as deposition. (Not shown). Subsequently, a hafnium oxide film having a thickness of 5 nm is formed by a method such as CVD, and a laminated insulating film 33 of an aluminum oxide film and a hafnium oxide film is formed.
  • a tungsten film 14 having a thickness of 50 nm is formed by a method such as CVD.
  • a part of the tungsten film 14 is selectively removed by subjecting the tungsten film 14 to a process such as an active ion etching method to form the gate electrode 10 made of a tungsten film.
  • a part of the stacked insulating film 33 is selectively removed by performing a process such as a wet process to form a gate insulating film 39 made of the stacked insulating film.
  • the extension region 15 is formed by implanting silicon, for example.
  • a silicon oxide film (not shown) having a thickness of 20 nm is formed by a method such as CVD. Subsequently, a part of the silicon oxide film is selectively removed by using a method such as an active ion etching method, and the gate sidewall insulating film 11 is formed.
  • a mixed crystal of In, Ga, and As is used as a semiconductor layer for forming an element.
  • the semiconductor layer is not limited to these mixed crystals, and other group III elements and group V elements are used.
  • Such a compound is also preferable because it has an advantage of higher carrier mobility than silicon.
  • InAs indium arsenide
  • InGaAs indium gallium arsenide
  • InSb indium antimony
  • silicon when silicon is used as the semiconductor layer, the conventional manufacturing process can be used as it is, and thus there is another advantage that the manufacturing process can be easily constructed.
  • the present invention is not limited to the above-described embodiments.
  • silicon is used as the support substrate.
  • the support substrate is not necessarily limited to silicon, and any semiconductor that can provide a substrate bias may be used. Further, it may be a semiconductor substrate whose surface is doped with impurities.
  • the material, film thickness, etc. of each part shown to embodiment are only examples, and can be suitably changed according to a specification. Furthermore, the manufacturing method shown in the embodiment is not limited at all, and can be appropriately changed.
  • Germanium layer (semiconductor layer) 30 Mixed crystal substrate of In, Ga and As 33 ...
  • Laminated insulating film of aluminum oxide film and hafnium oxide film 35 ... InGaAs layer (semiconductor layer) 39.

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
PCT/JP2013/050117 2012-09-14 2013-01-08 Substrat semi-conducteur et élément semi-conducteur Ceased WO2014041822A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012202513A JP2014057029A (ja) 2012-09-14 2012-09-14 半導体基板及び半導体素子
JP2012-202513 2012-09-14

Publications (1)

Publication Number Publication Date
WO2014041822A1 true WO2014041822A1 (fr) 2014-03-20

Family

ID=50277962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/050117 Ceased WO2014041822A1 (fr) 2012-09-14 2013-01-08 Substrat semi-conducteur et élément semi-conducteur

Country Status (3)

Country Link
JP (1) JP2014057029A (fr)
TW (1) TW201411774A (fr)
WO (1) WO2014041822A1 (fr)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11274500A (ja) * 1998-03-19 1999-10-08 Toshiba Corp 半導体基板、並びに半導体装置及びその製造方法
JP2001298171A (ja) * 2000-03-16 2001-10-26 Internatl Business Mach Corp <Ibm> シリコン・オン・インシュレータ（ｓｏｉ）技術の高ｋおよび低ｋ埋込酸化物のための方法および構造
JP2005109203A (ja) * 2003-09-30 2005-04-21 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
WO2006011369A1 (fr) * 2004-07-29 2006-02-02 Nec Corporation Substrat pour transistor à effet de champ, transistor à effet de champ, et procédé de fabrication dudit
JP2006108468A (ja) * 2004-10-07 2006-04-20 Sony Corp 半導体装置および半導体装置の製造方法
JP2007123823A (ja) * 2005-09-28 2007-05-17 Denso Corp 半導体装置およびその製造方法
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP2011176295A (ja) * 2010-01-26 2011-09-08 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP2012160637A (ja) * 2011-02-02 2012-08-23 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法、並びにｓｏｉ基板及びその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11274500A (ja) * 1998-03-19 1999-10-08 Toshiba Corp 半導体基板、並びに半導体装置及びその製造方法
JP2001298171A (ja) * 2000-03-16 2001-10-26 Internatl Business Mach Corp <Ibm> シリコン・オン・インシュレータ（ｓｏｉ）技術の高ｋおよび低ｋ埋込酸化物のための方法および構造
JP2005109203A (ja) * 2003-09-30 2005-04-21 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
WO2006011369A1 (fr) * 2004-07-29 2006-02-02 Nec Corporation Substrat pour transistor à effet de champ, transistor à effet de champ, et procédé de fabrication dudit
JP2006108468A (ja) * 2004-10-07 2006-04-20 Sony Corp 半導体装置および半導体装置の製造方法
JP2007123823A (ja) * 2005-09-28 2007-05-17 Denso Corp 半導体装置およびその製造方法
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP2011176295A (ja) * 2010-01-26 2011-09-08 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP2012160637A (ja) * 2011-02-02 2012-08-23 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法、並びにｓｏｉ基板及びその製造方法

Also Published As

Publication number Publication date
TW201411774A (zh) 2014-03-16
JP2014057029A (ja) 2014-03-27

Similar Documents

Publication Publication Date Title
CN109801878B (zh) 半导体装置及为其多个组件提供栅极结构的方法
JP4004040B2 (ja) 半導体装置
US9281390B2 (en) Structure and method for forming programmable high-K/metal gate memory device
US9343372B1 (en) Metal stack for reduced gate resistance
CN102804387A (zh) 薄box金属背栅极薄soi器件
WO2014185085A1 (fr) Dispositif de stockage à semi-conducteur
CN1236999A (zh) “绝缘体上的硅”半导体装置及其制造方法
KR20150056036A (ko) 상이한 채널 재료를 갖는 다층 반도체 디바이스 구조물
JP2002368225A (ja) 半導体装置及びその製造方法
US9570318B1 (en) High-k and p-type work function metal first fabrication process having improved annealing process flows
KR20120018064A (ko) 인장 스트레스 막과 수소 플라즈마 처리를 이용한 ｃｍｏｓ 트랜지스터의 형성방법
TW201801309A (zh) 具有非鬆弛應變通道之場效電晶體
US8815669B2 (en) Metal gate structures for CMOS transistor devices having reduced parasitic capacitance
JP2007019177A (ja) 半導体装置
TWI538060B (zh) 藉由單步驟沉積完成閘極包覆
CN101981674A (zh) 包括缩减高度的金属栅极堆栈的半导体器件及形成该半导体器件的方法
US12471322B2 (en) Horizontal GAA nano-wire and nano-slab transistors
JP3658564B2 (ja) 半導体装置
JP7678082B2 (ja) ゲートオールアラウンドナノシート入出力デバイスのためのコンフォーマル酸化
JP2004247341A (ja) 半導体装置
WO2009113427A1 (fr) Dispositif semi-conducteur, procédé de fabrication d&#39;un dispositif semi-conducteur et dispositif d&#39;affichage
JP5719381B2 (ja) 低寄生容量ボディ・コンタクト・トランジスタ
WO2014041822A1 (fr) Substrat semi-conducteur et élément semi-conducteur
KR102844697B1 (ko) 반도체 디바이스 및 제조 방법
CN106158630B (zh) 晶体管的形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13837459

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13837459

Country of ref document: EP

Kind code of ref document: A1