WO2013136259A3 - Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing - Google Patents
Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing Download PDFInfo
- Publication number
- WO2013136259A3 WO2013136259A3 PCT/IB2013/051929 IB2013051929W WO2013136259A3 WO 2013136259 A3 WO2013136259 A3 WO 2013136259A3 IB 2013051929 W IB2013051929 W IB 2013051929W WO 2013136259 A3 WO2013136259 A3 WO 2013136259A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- architecture
- ultra
- power
- bio
- low power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, several (one or more] shared multi-banked instruction and data memories, and flexible crossbar interconnects. The interconnect includes a selective broadcasting mechanism, enabling coordinated multiple accesses to the shared memories, thus energy savings in the memory hierarchy and in the interconnects. The memory hierarchy enables power gating of the unused banks to lower leakage power. The core instruction set of the novel architecture has been customized to exploit the specific features of bio-signal events, as well as the highly parallel computation opportunities of bio-signal processing characteristics. In addition to near threshold computing, the proposed architecture also exploits other advanced low-power features, which lead to further energy savings. The architecture has a synchronization method and unit that allows power- efficient handling of data dependencies when code is parallelized across the multiple processing cores.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IBPCT/IB2012/051150 | 2012-03-12 | ||
| IB2012051150 | 2012-03-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2013136259A2 WO2013136259A2 (en) | 2013-09-19 |
| WO2013136259A3 true WO2013136259A3 (en) | 2014-10-30 |
Family
ID=48446412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2013/051929 Ceased WO2013136259A2 (en) | 2012-03-12 | 2013-03-12 | Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2013136259A2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2542853B (en) * | 2015-10-02 | 2021-12-15 | Cambridge Consultants | Processing apparatus and methods |
| CN115576664B (en) * | 2022-09-05 | 2025-09-02 | 山东大学 | A multi-core processor task migration and power consumption adjustment method and architecture based on performance monitoring mechanism |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5522083A (en) * | 1989-11-17 | 1996-05-28 | Texas Instruments Incorporated | Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors |
| US6480941B1 (en) * | 1999-02-23 | 2002-11-12 | International Business Machines Corporation | Secure partitioning of shared memory based multiprocessor system |
-
2013
- 2013-03-12 WO PCT/IB2013/051929 patent/WO2013136259A2/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5522083A (en) * | 1989-11-17 | 1996-05-28 | Texas Instruments Incorporated | Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors |
| US6480941B1 (en) * | 1999-02-23 | 2002-11-12 | International Business Machines Corporation | Secure partitioning of shared memory based multiprocessor system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013136259A2 (en) | 2013-09-19 |
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| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
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