WO2013132667A1 - Synchronization data processing circuit and mobile terminal apparatus - Google Patents

Abstract

The objective of the invention is to provide a synchronization data processing circuit, which achieves a stable circuit operation, and a mobile terminal apparatus. A synchronization data processing circuit comprises: first circuits each of which is driven by a constant voltage on the basis of a clock outputted from a clock generation source; second circuits the drive voltage of each of which is variable and which perform one-way or two-way synchronous-transfers of data to the first circuits or together with the first circuits on the basis of a clock outputted from the clock generation source; a delay adjustment unit which adjusts the delay amount of the clock inputted to the first or second circuits; a test data generation unit which generates test data to be transferred between the first and second circuits; and a determination unit which determines the transferred test data and adjusts the delay amount in the delay adjustment unit on the basis of the determination result indicating whether the test data have been synchronously transferred.

Description

Synchronous data processing circuit and portable terminal

The present invention relates to a synchronous data processing circuit and a portable terminal.

Conventionally, there has been a circuit that includes a first logic circuit unit whose power supply voltage is controlled and a second logic circuit unit that operates according to an external clock, and corrects clock skew. The adjustment circuit of the circuit includes a first delay circuit to which an external clock is supplied, a first clock output from the first logic circuit unit, and a second clock output from the second logic circuit unit. And a detection circuit for detecting the amount of timing deviation. The adjustment circuit adjusts the delay time of the first delay circuit according to the detection result of the detection circuit, and supplies the output signal of the first delay circuit to the first logic circuit unit as the third clock signal.

JP 2006-086455 A

By the way, since the circuit for correcting the clock skew as described above corrects the clock skew according to the clock phase shift, the data phase is not compensated, and the data phase is shifted. The circuit operation may become unstable.

Therefore, an object is to provide a synchronous data processing circuit and a portable terminal capable of realizing a stable circuit operation.

A synchronous data processing circuit according to an embodiment of the present invention includes a first circuit driven at a constant voltage based on a clock output from a clock generation source, and a clock output from the clock generation source with a drive voltage varied. And a second circuit for synchronously transferring data to or from the first circuit in either direction or a delay for adjusting a delay amount of a clock input to the first circuit or the second circuit. An adjustment unit, a test data generation unit that generates test data transferred between the first circuit and the second circuit, and the transferred test data are determined, and whether or not the test data is transferred synchronously And a determination unit that adjusts a delay amount in the delay adjustment unit based on a determination result representing the above.

It is possible to provide a synchronous data processing circuit that can realize stable circuit operation and a portable terminal.

It is a perspective view which shows the smart phone terminal 10 of a comparative example. It is a figure which shows the internal structure of the smart phone terminal of a comparative example. It is a figure which shows an example of the relationship between the load mode at the time of not applying DVFS to a core, a clock frequency, and a supply voltage. It is a figure which shows the operable area | region and inoperable area | region of a core by the relationship between a clock frequency and supply voltage. It is a figure which shows an example of the relationship between the load mode at the time of applying DVFS to a core, a clock frequency, and a supply voltage. It is a figure which shows the connection relation of the core 0, the core 1, PMU, and a bus | bath, and a supply voltage. It is a figure which shows typically a mode that the relationship of the transmission time of the data in the core clock tree contained in a core and the bus clock tree contained in a bus | bath changes with the difference in the supply voltage to a core. It is a figure which shows the data processing circuit 90 of a comparative example. 5A is a diagram illustrating an example of an operation in which the voltage detection unit 94 illustrated in FIG. 5A switches the data transfer format from a state in which asynchronous transfer is performed according to a supply voltage to the core 0 to a state in which synchronous transfer is performed. In the synchronous data processing circuit of Embodiment 1, it is a figure which shows typically a mode that delay time is adjusted with a variable delay part according to the change of the transmission time of the core clock tree by DVFS. 1 is a diagram illustrating a synchronous data processing circuit 100 according to a first embodiment. FIG. 3 is a diagram illustrating a circuit configuration of a core 110, a bus 120, and a synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment. FIG. 3 is a diagram illustrating a variable delay unit 130 of the synchronous data processing circuit 100 according to the first embodiment. FIG. 3 is a diagram illustrating a pattern generation unit 141 and a determination unit 144 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment. FIG. 6 is a timing chart illustrating an operation example of the pattern generation unit 141 and the determination unit 144 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment. 3 is a diagram illustrating a determination unit 142 and a pattern generation unit 143 of the synchronization determination unit 140 of the synchronization data processing circuit 100 according to the first embodiment. FIG. 4 is a timing chart illustrating an example of operations of a determination unit 142 and a pattern generation unit 143 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment. FIG. 6 is a diagram illustrating a circuit configuration of a core 110, a bus 120, and a synchronization determination unit 240 of a synchronous data processing circuit according to a second embodiment. 3 is a diagram illustrating a pattern generation unit 241 and a determination unit 244 of a synchronization determination unit 240 of the synchronous data processing circuit 100 according to the first embodiment. FIG. 10 is a timing chart illustrating an operation example of the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 of the synchronous data processing circuit according to the second embodiment. 10 is a timing chart illustrating an operation example of the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 of the synchronous data processing circuit according to the second embodiment. 11 is a timing chart showing an operation when returning from a state in which the FFs 113A to 113D and 123A to 123D are fixed by the freeze signal frz in the synchronous data processing circuit of the second embodiment.

Hereinafter, embodiments in which the synchronous data processing circuit and the mobile terminal of the present invention are applied will be described.

First, before describing the synchronous data processing circuit of the embodiment, a portable terminal, a synchronous data processing circuit of a comparative example, and problems thereof will be described.

<Comparative example>
FIG. 1 is a perspective view showing a smartphone terminal 10 of a comparative example.

The smart phone terminal 10 including the connector device according to the first embodiment includes a touch panel 11, operation buttons 12, a call speaker 13, a call microphone 14, and a digital camera 15 disposed on the front side. The smartphone terminal 10 is an example of a mobile terminal.

The smartphone terminal 10 may include an accessory device such as a proximity communication device (infrared communication device, electronic money communication device, etc.).

In addition, although the smart phone terminal 10 is shown in FIG. 1 as an example of a portable terminal, a terminal is not limited to the smart phone terminal 10, For example, even if it is a mobile telephone terminal or a game machine etc. Good.

FIG. 2 is a diagram illustrating an internal configuration of the smartphone terminal 10 of the comparative example.

The smart phone terminal 10 includes an application processing unit 20, a modem unit 30, a user interface 41, a system controller 42, an LCD (Liquid Crystal Display) 43, and a battery 44.

The application processing unit 20 includes a memory 21, a variable voltage supply unit 22, and an application processor 50. The application processing unit 20 is a processing unit that performs processing other than communication of the smartphone terminal 10, and performs, for example, encoding / combining processing of data such as audio, video, images, and photos.

As the memory 21, for example, a synchronous DRAM (Synchronous Dynamic Random Access Memory) can be used. For example, various application programs are stored in the memory 21.

The variable voltage supply unit 22 is, for example, a converter that can variably control the output voltage. When the variable voltage supply unit 22 supplies the power supplied from the battery 44 to the core 0 and the core 1 of the application processor 50, the voltage command input from the PMU (Power Management Unit) of the application processor 50 Based on this, the output voltage is variably controlled.

Application processor 50 includes core 0, core 1, and PMU. The application processor 50 is an example of a dual core processor. The core 0 and the core 1 are processor cores that can perform arithmetic processing independently of each other, and are treated as having the same processing capability here. In FIG. 2, the bus connecting the core 0, the core 1, and the PMU in the application processor 50 is not shown.

The core 0 and the core 1 have a drive voltage input from the variable voltage supply unit 22 varied by DVFS (Dynamic Voltage and Frequency Frequency Scaling), thereby reducing power consumption.

The PMU inputs a voltage command for controlling the input voltage of the core 0 and the core 1 to the variable voltage supply unit 22 in accordance with the operation status of the core 0 and the core 1.

The modem unit 30 is a processing unit that performs processing related to communication of the smartphone terminal 10. The modem unit 30 includes a baseband module 60 and an RF module 80.

The baseband module 60 includes a memory 61, a variable voltage supply unit 62, and an AFE (Analog Front End) 63. A SIM (Subscriber Identity Module) card 82 is inserted into the baseband module 60. In the SIM card 82, for example, data representing information unique to the contractor of the smartphone terminal 10 such as a telephone number is written.

As the memory 61, for example, a synchronous DRAM (Synchronous Dynamic Random Access Memory) can be used. For example, the memory 61 stores a program for executing communication processing, a program necessary for encryption and decryption of communication, and the like.

The variable voltage supply unit 62 is, for example, a converter that can variably control the output voltage. The variable voltage supply unit 62 is input from a PMU (Power Management Unit) of the baseband processor 70 when supplying power supplied from the battery 44 to the core 0 and the core 1 of the baseband processor 70. Based on the voltage command, the output voltage is variably controlled.

The AFE 63 performs digital conversion and analog conversion of communication data between the baseband processor 70 and the RF module 80. The AFE 63 analog-converts digital communication data input from the baseband processor 70 and inputs the analog communication data to the transmission unit TX of the RF module 80. The AFE 63 digitally converts analog communication data input from the receiving unit RX of the RF module 80 and inputs the analog communication data to the baseband processor 70.

The baseband processor 70 includes a core 0, a core 1, and a PMU. The baseband processor 70 is an example of a dual core processor. The core 0 and the core 1 are processor cores that can perform arithmetic processing independently of each other, and are treated as having the same processing capability here. In FIG. 2, the bus connecting the core 0, the core 1, and the PMU in the baseband processor 70 is not shown.

The core 0 and the core 1 have a driving voltage input from the variable voltage supply unit 62 varied by DVFS (Dynamic Voltage and Frequency Frequency Scaling), thereby reducing power consumption.

The PMU inputs a voltage command for controlling the input voltage of the core 0 and the core 1 to the variable voltage supply unit 62 according to the operation status of the core 0 and the core 1.

The RF module 80 includes a transmission unit TX, a reception unit RX, and a power amplifier PA. An antenna 81 is connected to the RF module 80. The transmission unit TX is a circuit that inputs analog communication data (transmission data) input from the AFE 63 to the power amplifier PA.

The receiving unit RX is a circuit that inputs analog communication data (received data) received by the antenna 81 to the AFE 63. The power amplifier PA is an amplifier that amplifies analog communication data (transmission data) input from the transmission unit TX and outputs the amplified data to the antenna 81.

The antenna 81 is an antenna that transmits and receives communication data of the modem unit 30, and for example, a monopole antenna can be used. For example, the length of the antenna 81 may be set to ¼ (λ / 4) of the wavelength λ of the operating frequency.

The user interface 41 is connected to an input unit of the touch panel 11 (see FIG. 1) of the smartphone terminal 10, an operation button 12 (see FIG. 1), an S / D card port, and an input / output terminal of a digital camera. It is an output unit. The touch panel, the S / D card port, the digital camera, and the like are connected to the application processing unit 20 and the system controller 42 via the user interface 41.

If the smartphone terminal 10 includes a keyboard instead of the touch panel 11 or in addition to the touch panel 11, the keyboard is connected to the user interface 41.

The system controller 42 is driven by power supplied from the battery 44 and controls the entire system of the smartphone terminal 10.

The LCD 43 is a liquid crystal display unit included in the touch panel 11 (see FIG. 1) of the smartphone terminal 10. The LCD 43 is driven by the system controller 42 and the application processing unit 20.

The battery 44 is a power source of the smartphone terminal 10, and for example, a lithium ion battery can be used.

Next, the DVFS of the core 0 and the core 1 included in the application processor 50 and the baseband processor 70 will be described with reference to FIGS. 3A to 3C. Here, when the core 0 and the core 1 are not particularly distinguished, they are simply referred to as a core.

FIG. 3A is a diagram illustrating an example of a relationship between a load mode, a clock frequency, and a supply voltage when DVFS is not applied to the core. FIG. 3B is a diagram illustrating a core operable region and an inoperable region in relation to a clock frequency and a supply voltage. FIG. 3C is a diagram illustrating an example of a relationship among a load mode, a clock frequency, and a supply voltage when DVFS is applied to the core.

Here, the case where DVFS is not applied to the core means that power of a constant voltage is supplied to the core 0 and the core 1 without using the variable voltage supply units 22 and 62 in FIG. The case where DVFS is applied to the core means that the voltage of power supplied to the core 0 and the core 1 via the variable voltage supply units 22 and 62 in FIG. 2 is made variable.

Also, the load mode 3 is a case where the core is driven at a clock frequency of 400 MHz, and the load mode 2 is a case where the core is driven at a clock frequency of 200 MHz. The load mode 1 is a case where the core is driven at a clock frequency of 100 MHz, and the load mode 0 is a case where the clock frequency is 0 MHz and the core is not driven.

As shown in FIG. 3A, when DVFS is not applied, in all cases of load mode 3 (400 MHz), load mode 2 (200 MHz), load mode 1 (100 MHz), and load mode 0 (0 MHz) The supply voltage to 0 and core 1 is constant at 1.2V.

Since the core can be driven with a supply voltage corresponding to the clock frequency, if the supply voltage at the operating point can be reduced by applying DVFS, power saving can be achieved according to the load.

Here, the operable region of the core is a region surrounded by a broken line in FIG. 3B, and the operating points in modes 0 to 3 when DVFS is not applied are as indicated by black circles. The region where the supply voltage is lower than the operable region is an inoperable region where the core cannot operate.

As shown in FIG. 3B, in mode 3 (400 MHz), there is almost no margin for lowering the supply voltage below 1.2V, but in mode 2 (200 MHz), the supply voltage is reduced to about 1.0V. However, as indicated by white circles, the operating point enters the operable region.

In the case of mode 1 (100 MHz), even if the supply voltage is lowered to about 0.8 V, the operating point enters the operable region as indicated by white circles.

In mode 0 (0 MHz), since the core is not operated, the supply voltage can be set to 0 V as indicated by a white circle regardless of the operable region.

Therefore, when DVFS is applied, as shown in FIG. 3C, the supply voltages to the core in the load mode 2, the load mode 1, and the load mode 0 are 1.0 V, 0.8 V, and It can be lowered to 0V.

When the core load is light, there is no problem even if the processing speed is lowered by lowering the clock frequency. Therefore, the power consumption of the core is reduced by applying DVFS to lower the supply voltage according to the core load. can do.

By the way, in a mobile terminal such as the smartphone terminal 10 (see FIGS. 1 and 2), a circuit that can vary the supply voltage, such as a core, and a supply voltage that cannot be varied, must be driven at a constant voltage. There is a circuit with. Examples of the circuit that needs to be driven at a constant voltage include a bus connected to the core, a PMU, or a memory.

Here, if the supply voltage is changed by changing the operating frequency of the core, the phase in which data is output from the core changes, and there may be a case where synchronization cannot be achieved with a circuit driven at a constant voltage.

FIG. 4A is a diagram showing the connection relationship between the core 0, the core 1, the PMU, and the bus, and the supply voltage. FIG. 4B is a diagram schematically illustrating a state in which the relationship between the data transmission times of the core clock tree included in the core and the bus clock tree included in the bus varies depending on the difference in supply voltage to the core.

As shown in FIG. 4A, the core 0, the core 1, and the PMU are connected to the bus and transfer data via the bus.

Here, since DVFS is applied to the core 0 and the core 1, the supply voltage to the core 0 and the core 1 is variable and is 0.8V to 1.2V. The supply voltage to the PMU and the bus is constant at 1.2V.

The core 0, core 1, PMU, and bus shown in FIG. 4A are obtained by adding a bus that actually exists to the core 0, core 1, and PMU included in the application processor 50 and the baseband processor 70 shown in FIG. It is.

It should be noted that such core 0, core 1, PMU, and bus can be realized on a single chip as an LSI (Large Scale Integrated circuit).

Here, data is synchronously transferred between the core 0 and core 1 and the bus. Since the core 0 and the core 1 perform synchronous transfer between the buses in the same manner, the data transmission time in the core 0 and the bus will be described here.

As shown in FIG. 4B, the core 0 and the bus include a core clock tree and a bus clock tree for aligning the phases of output data by synchronous transfer, respectively.

Each of the core clock tree and the bus clock tree includes a plurality of buffers connected in series so that input terminals and output terminals are alternately connected, and an FF (Flip Flop) connected to the last stage of the serially connected buffers. ).

The same clock is input to the core clock tree and the bus clock tree, for example, from a PLL (Phase Locked Loop).

As shown in the upper diagram of FIG. 4B, the core clock tree and the bus clock tree have the same relationship between the FFs in the final stage when the supply voltage to the core 0 is 1.2 V, which is the same as the supply voltage to the bus. It is assumed that the propagation times are aligned so that data can be transferred simultaneously. For this reason, in the upper diagram of FIG. 4B, the lengths of the core clock tree and the bus clock tree are shown aligned.

In this case, if DVFS is applied to the core 0 and the supply voltage is lowered to 0.8 V, the propagation time in the core clock tree becomes longer. Therefore, as shown in the lower diagram of FIG. The propagation time of the tree is longer than that of the bus clock tree.

For this reason, the timing at which data is transferred from the final stage FF of the core clock tree and the timing at which data is transferred from the final stage FF of the bus clock tree are not matched, and data cannot be transferred synchronously. Occurs.

In order to solve such a problem, there is a method in which an asynchronous bridge is provided on the bus and data is transferred via the asynchronous bridge without performing the synchronous transfer when the supply voltage to the core 0 is lowered.

FIG. 5A is a diagram showing a data processing circuit 90 of a comparative example.

The data processing circuit 90 of the comparative example includes a core clock tree 91, a data transmission unit 92, a data reception unit 93, a voltage detection unit 94, a bus clock tree 95, a data transmission unit 96, a data reception unit 97, and an asynchronous bridge 98. .

Among these components, the core clock tree 91, the data transmission unit 92, and the data reception unit 93 are included in the core 0. The bus clock tree 95, the data transmission unit 96, the data reception unit 97, and the asynchronous bridge 98 are included in the bus.

The data transmission units 92 and 96 and the data reception units 93 and 97 shown in FIG. 5A correspond to the FFs of the core clock tree and the bus clock tree shown in FIG. 4A. A clock is input from the core clock tree 91 to the data transmission unit 92 and the data reception unit 93, and a clock is input from the bus clock tree 95 to the data transmission unit 96 and the data reception unit 97.

The voltage detector 94 is connected to the core 0. The voltage detection unit 94 detects a supply voltage from the variable voltage supply unit (22 or 62 (see FIG. 2)) to the core 0, and inputs a synchronous transfer command or an asynchronous transfer command to the asynchronous bridge 98 in the bus.

FIG. 5B is a diagram illustrating an example of an operation in which the voltage detection unit 94 illustrated in FIG. 5A switches the data transfer format from a state in which asynchronous transfer is performed to a state in which synchronous transfer is performed in accordance with a supply voltage to the core 0. is there. In addition, the vertical axis | shaft in FIG. 5B is a supply voltage to the core 0, and a horizontal axis is time.

As shown in FIG. 5B, since the supply voltage to the core 0 detected by the voltage detector 94 is 0.8 V from time t0 to t1, the voltage detector 94 outputs an asynchronous transfer command.

Further, the supply voltage to the core 0 increases from time t1, but the voltage detection unit 94 outputs an asynchronous transfer command until the supply voltage stabilizes at 1.2 V at time t2. This is because the transmission time of the core clock tree 91 of the core 0 is not stable until the voltage is stabilized, and it is difficult to perform synchronous transfer.

When the supply voltage to the core 0 is stabilized at time t2, the voltage detection unit 94 determines that the supply voltage to the core 0 is a stable and normal voltage, and outputs a synchronous transfer command.

FIG. 5B shows a case where the supply voltage to the core 0 increases with time, but when the supply voltage decreases from 1.2 V to 0.8, the supply voltage becomes less than 1.2 V. At this point, the voltage detection unit 94 switches the output from the synchronous transfer command to the asynchronous transfer command.

The asynchronous bridge 98 is inserted on the output side of the data transmission unit 96 of the bus and on the input side of the data reception unit 97, and in response to a synchronous transfer command or an asynchronous transfer command input from the voltage detection unit 94, The data transfer format between the bus and the bus.

The asynchronous bridge 98 incorporates a FIFO (First-In-First-Out) processing unit. When a synchronous transfer command is input from the voltage detection unit 94, the asynchronous bridge 98 outputs the input data as it is without passing through the FIFO processing unit. On the other hand, when an asynchronous transfer command is input from the voltage detection unit 94, the asynchronous bridge 98 inputs input data to the FIFO processing unit, and the FIFO processing outputs data in the order of input.

Therefore, when the asynchronous transfer command is input from the voltage detection unit 94, the asynchronous bridge 98 transfers the data input from the bus data transmission unit 96 to the data reception unit 93 of the core 0 at the same timing. The asynchronous bridge 98 outputs the data input from the data transmission unit 92 of the core 0 to the data reception unit 97 of the bus at the same timing. That is, when a synchronous transfer command is input from the voltage detection unit 94 to the asynchronous bridge 98, data is synchronously transferred between the core 0 and the bus without passing through the FIFO processing unit in the asynchronous bridge 98. The

In addition, when an asynchronous transfer command is input from the voltage detection unit 94, the asynchronous bridge 98 outputs data in the order of input to the FIFO processing unit.

That is, when an asynchronous transfer command is input to the asynchronous bridge 98, data input from the bus data transmission unit 96 to the FIFO processing unit in the asynchronous bridge 98 is transferred to the data reception unit 93 of the core 0 in the order of input. . Data input from the data transmission unit 92 of the core 0 to the FIFO processing unit of the asynchronous bridge 98 is output to the data reception unit 97 of the bus in the order of input. This enables data transfer in an asynchronous state between the bus and the core 0.

As described above, the data processing circuit 90 of the comparative example transfers data via the FIFO processing unit of the asynchronous bridge 98 when transferring data in an asynchronous state. The FIFO processing unit of the asynchronous bridge 98 outputs data in the order of input.

For this reason, when transferring data in an asynchronous state, there was a problem that the data transfer rate was reduced. The data transfer rate through the FIFO processing unit is about 50%. When the data transfer rate is reduced by about 50%, there arises a problem that the performance of the system is remarkably deteriorated.

Further, the data processing circuit 90 of the comparative example includes the asynchronous bridge 98 having the FIFO processing unit, so that the problem of circuit design becomes complicated and the development man-hour required for the verification work for guaranteeing the operation increases. There was a problem.

As described above, the data processing circuit 90 of the comparative example has problems that the data transfer speed is reduced, the circuit design is complicated, and the development man-hour is increased.

Therefore, hereinafter, a synchronous data processing circuit that solves such a problem will be described.

<Embodiment 1>
FIG. 6 is a diagram schematically illustrating how the delay time is adjusted by the variable delay unit in accordance with the change in the transmission time of the core clock tree by DVFS in the synchronous data processing circuit of the first embodiment.

FIG. 6 shows a variable delay unit, a core clock tree, a fixed delay unit, and a bus clock tree in the synchronous data processing circuit of the first embodiment. Among these, the core clock tree is included in a core described later using FIG. 7, and the bus clock tree is included in a bus described later using FIG.

The same clock is input from the PLL, for example, to the variable delay unit and the fixed delay unit.

As shown in FIG. 6, in the synchronous data processing circuit of the first embodiment, a variable delay unit is connected in series to the core clock tree of the core, and the variable delay unit uses the variable delay unit according to the change in the supply voltage to the core by DVFS. By adjusting the delay time, the data can be transferred synchronously even if the supply voltage to the core changes.

Also, a fixed delay unit is connected in series with the bus clock tree in order to align the clock transmission time on the core side and the bus side when realizing synchronous transfer.

That is, as shown in the upper diagram of FIG. 6, when the supply voltage to the core is 1.2V, the transmission time in the core clock tree is shorter than when the supply voltage is 0.8V. The delay time given to the clock is made longer by the variable delay unit than when the voltage is 0.8V.

Therefore, in the upper diagram of FIG. 6, the variable delay unit is shown longer. The total length of the lengthened variable delay section and the shortened core clock tree is substantially equal to the total length of the fixed delay section and the bus clock tree.

This indicates that the clock propagation time by the variable delay unit and the core clock tree is substantially equal to the clock propagation time by the fixed delay unit and the bus clock tree.

Also, as shown in the lower diagram of FIG. 6, when the supply voltage to the core is 0.8V, the transmission time in the core clock tree becomes longer than when the supply voltage is 1.2V. The delay time given to the clock by the variable delay unit is made shorter than when the supply voltage is 1.2V.

For this reason, the variable delay section is shown briefly in the lower diagram of FIG. The total length of the shortened variable delay section and the lengthened core clock tree is substantially equal to the total length of the fixed delay section and the bus clock tree.

This indicates that the clock propagation time by the variable delay unit and the core clock tree is substantially equal to the clock propagation time by the fixed delay unit and the bus clock tree.

As shown in the upper and lower diagrams of FIG. 6, the synchronous data processing circuit according to the first embodiment has a variable delay unit in both cases where the supply voltage to the core is 1.2V and 0.8V. And the clock propagation time by the core clock tree is made substantially equal to the clock propagation time by the fixed delay unit and the bus clock tree.

In this way, the clock propagation time by the variable delay unit and the core clock tree is made substantially equal to the clock propagation time by the fixed delay unit and the bus clock tree in order to enable synchronous transfer. This is because when data is transferred between the buses, a setup time and a hold time are secured to realize synchronous transfer.

In the above description, the same clock is input from the PLL to the variable delay unit and the fixed delay unit. For example, a frequency divider is provided on the input side of the variable delay unit or the fixed delay unit to divide the frequency. The synchronous transfer may be performed in a state where the clock is input to the variable delay unit or the fixed delay unit.

Next, the configuration of the synchronous data processing circuit according to the first embodiment will be described with reference to FIG.

FIG. 7 is a diagram illustrating the synchronous data processing circuit 100 according to the first embodiment.

The synchronous data processing circuit 100 includes cores 110A and 110B, a bus 120, variable delay units 130A and 130B, synchronization determination units 140A and 140B, and a fixed delay unit 150.

For example, a PLL (Phase Locked Loop) 160 is connected to the variable delay units 130A and 130B and the fixed delay unit 150. Note that the synchronous data processing circuit 100 may include the PLL 160 as a constituent element.

The synchronous data processing circuit 100 according to the first embodiment is applied to, for example, the smart phone terminal 10 shown in FIGS.

Hereinafter, a mode in which the synchronous data processing circuit 100 according to the first embodiment is used as the application processor 50 or the baseband processor 70 of the smartphone terminal 10 illustrated in FIGS. 1 and 2 will be described.

For this reason, the cores 110A and 110B shown in FIG. 7 will be described as cores similar to the cores 0 and 1 included in the application processor 50 and the baseband processor 70, respectively.

In the following, FIG. 1 and FIG. 2 showing the smartphone terminal 10 will be cited.

The cores 110A and 110B are processor cores that can perform arithmetic processing independently of each other, and are treated as having the same processing capability here. The cores 110A and 110B operate based on the clock CKin input from the variable delay units 130A and 130B, respectively.

In the cores 110A and 110B, the drive voltage input from the variable voltage supply unit 22 (refer to FIG. 2) is varied by DVFS (Dynamic Voltage and Frequency Frequency Scaling), thereby reducing power consumption.

Although the illustration of the PMU (see FIG. 2) is omitted in FIG. 7, the PMU provides a voltage command for controlling the input voltage of the cores 110A and 110B according to the operating state of the cores 110A and 110B. 22 input.

The bus 120 transfers (transmits / receives) data between the cores 110A and 110B. The bus 120 operates based on the clock CKin input from the fixed delay unit 150.

The variable delay units 130A and 130B delay the clock CK input from the PLL 160, and output the clock CKin. The clocks CKin output from the variable delay units 130A and 130B are input to the cores 110A and 110B, respectively. The delay amount given to the clock CK input from the PLL 160 by the variable delay units 130A and 130B is determined according to the delay control command input from the synchronization determination units 140A and 140B, respectively.

The synchronization determination units 140A and 140B are disposed across the core 110A and the bus 120, and the core 110B and the bus 120, respectively.

The synchronization determination unit 140A determines the data transfer status between the core 110A and the bus 120, and determines the delay amount to be given to the clock CK by the variable delay unit 130A. The synchronization determination unit 140A inputs a delay control command representing the delay amount to the variable delay unit 130A.

By controlling the delay amount of the variable delay unit 130A according to the delay control command output from the synchronization determination unit 140A, the data transmission time between the variable delay unit 130A and the core clock tree in the core 110A is The transmission time of data in the bus clock tree in the bus 120 is approximately equal.

The synchronization determination unit 140B determines a data transfer state between the core 110B and the bus 120, and determines a delay amount to be given to the clock CK by the variable delay unit 130B. The synchronization determination unit 140B inputs a delay control command representing the delay amount to the variable delay unit 130B.

By controlling the delay amount of the variable delay unit 130B according to the delay control command output from the synchronization determination unit 140B, the data transmission time between the variable delay unit 130B and the core clock tree in the core 110B is The transmission time of data in the bus clock tree in the bus 120 is approximately equal.

That is, the synchronization determination units 140A and 140B control the delay amounts of the variable delay units 130A and 130B, respectively, so that the variable delay unit 130A and the core clock tree in the core 110A, and the variable delay unit 130B and the core clock tree in the core 110B. In addition, the data transmission times in the three routes of the fixed delay unit 150 and the bus clock tree are substantially equal.

The fixed delay unit 150 gives a predetermined fixed delay amount to the clock CK input from the PLL 160 and outputs the clock CKin. The clock CKin output from the fixed delay unit 150 is input to the bus 120.

When the delay amount in the variable delay unit 130A is increased or decreased, the fixed delay unit 150 approximates the clock propagation time by the variable delay unit 130A and the core clock tree to the clock propagation time by the fixed delay unit 150 and the bus clock tree. It is provided for adjustment to equalize.

Further, when the delay amount in the variable delay unit 130B is increased or decreased, the fixed delay unit 150 determines the clock propagation time by the variable delay unit 130B and the core clock tree, and the clock propagation time by the fixed delay unit 150 and the bus clock tree. And is provided for adjustment to be substantially equal.

The PLL 160 generates and outputs a clock CK to be input to the variable delay units 130A and 130B and the fixed delay unit 150. For example, the PLL 160 multiplies the frequency of a reference clock input from a crystal oscillator (not shown) and outputs a clock CK having a desired frequency. Note that any clock generator other than the PLL may be used as long as the clock generator can generate the clock CK to be input to the variable delay units 130A and 130B and the fixed delay unit 150.

The cores 110A and 110B are examples of the second circuit, the bus 120 is an example of the first circuit, and the variable delay units 130A and 130B are examples of the delay adjustment unit.

In the above description, the same clock is input from the PLL 160 to the variable delay units 130A and 130B and the fixed delay unit 150. However, for example, the variable delay units 130A and 130B or the fixed delay unit 150 can be distributed to the input side. Synchronous transfer may be performed in a state where a frequency divider is provided and the divided clock is input to the variable delay units 130A and 130B or the fixed delay unit 150.

That is, the cores 110A and 110B and the bus 120 need only be driven based on the clock output from the PLL 160, which is the same clock generation source, and the cores 110A and 110B or the clock input to the bus 120. May be a clock obtained by dividing the clock output from the PLL 160.

Generally, the cores 110A and 110B require a higher frequency than the bus 120. For this reason, for example, the 400 MHz clock CKin is input to the cores 110A and 110B from the PLL 160 via the variable delay units 130A and 130B, and the 400 MHz clock CK output from the PLL 160 is divided to the bus 120. The frequency may be divided into 200 MHz by a device and input as a clock CKin via the fixed delay unit 150.

Thus, even if the frequency of the clock CKin input to the cores 110A and 110B is different from the frequency of the divided clock CKin input to the bus 120, the clock CKin input to the cores 110A and 110B and the bus 120 is different. Are clocks based on the clock CK output from the PLL 160.

Next, a circuit configuration of the synchronization determination units 140A and 140B and a method for generating a delay control command will be described with reference to FIG. Hereinafter, the cores 110A and 110B, the variable delay units 130A and 130B, and the synchronization determination units 140A and 140B will be described without distinction, and will be referred to as the core 110, the variable delay unit 130, and the synchronization determination unit 140, respectively. .

FIG. 8 is a diagram illustrating a circuit configuration of the core 110, the bus 120, and the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment. The circuit configuration of the variable delay unit 130 will be described later with reference to FIG.

The core 110 includes a core clock tree 111, buffers 112A and 112B, FFs 113A to 113D, combinational circuits 114A and 114B, and buffers 115A and 115B.

The core clock tree 111 is arranged inside the core 110, and is a data transmission path inside the core 110, and has a configuration in which a plurality of buffers are connected in series for adjusting the transmission time. The input terminal of the core clock tree 111 is connected to the output terminal of the variable delay unit 130, and receives the clock CKin. The output terminal of the core clock tree 111 is connected to the buffers 112A and 112B.

When the clock CKin is input from the variable delay unit 130, the core clock tree 111 adds a predetermined delay amount and inputs the clock to the buffers 112A and 112B.

The buffers 112A and 112B are connected to the output terminal of the core clock tree 111 in parallel with each other. The output terminal of the buffer 112A is connected to the clock input terminals of the FFs 113A and 113B. The output terminal of the buffer 112B is connected to the clock input terminals of the FFs 113C and 113D and the synchronization determination unit 140.

When the clock is input from the core clock tree 111, the buffers 112A and 112B input the clock CCK to the clock input terminals of the FFs 113A to 113D.

FFs 113A and 113B are FFs on the data output side from the core 110, and the data input terminal D is connected to an internal circuit (not shown) of the core 110. Data generated by arithmetic processing, for example, is input from an internal circuit (not shown) of the core 110 to the data input terminals D of the FFs 113A and 113B.

The combination circuit 114A and the buffer 115A are connected to the data output terminals Q of the FFs 113A and 113B, respectively. The output terminal of the buffer 112A is connected to the clock input terminals of the FFs 113A and 113B.

The FFs 113A and 113B reflect the data in the data input terminal D to the data output terminal D when the clock CCK is input from the buffer 112A to the clock input terminal.

FFs 113C and 113D are FFs on the side of inputting data to the core 110, and the data input terminal D is connected to the combinational circuit 114B and the buffer 115B, respectively. Data output from the combinational circuit 114B and the buffer 115B are input to the data input terminals D of the FFs 113C and 113D, respectively.

The data output terminals Q of the FFs 113C and 113D are connected to an internal circuit (not shown) of the core 110. Data output from the clock output terminals Q of the FFs 113C and 113D is transmitted to an internal circuit (not shown) of the core 110.

The FFs 113C and 113D reflect the data in the data input terminal D to the data output terminal D when the clock CCK is input from the buffer 112B to the clock input terminal.

The combination circuit 114A has an input terminal connected to the data output terminal Q of the FF 113A and an output terminal connected to the data input terminal D of the FF 123A of the bus 120. The combinational circuit 114A is, for example, a logic circuit such as AND and OR, performs a predetermined operation on the data input from the FF 113A, and transfers the data to the FF 123A of the bus 120.

The combination circuit 114B has an input terminal connected to the data output terminal Q of the FF 123C of the bus 120 and an output terminal connected to the data input terminal D of the FF 113. The combinational circuit 114B is, for example, a logic circuit such as AND or OR, and performs a predetermined operation on the data transferred from the FF 123C of the bus 120 and outputs it to the internal circuit of the core 110.

The buffer 115A has an input terminal connected to the data output terminal Q of the FF 113B and an output terminal connected to the data input terminal D of the FF 123B of the bus 120. The buffer 115A transfers the data output from the FF 113B to the FF 123B of the bus 120.

The buffer 115B has an input terminal connected to the data output terminal Q of the FF 123D of the bus 120, and an output terminal connected to the data input terminal D of the FF 113D. The buffer 115B outputs the data transferred from the FF 123D of the bus 120 to the FF 113D.

The bus 120 includes a bus clock tree 121, buffers 122A and 122B, and FFs 123A to 123D.

The bus clock tree 121 is arranged inside the bus 120 and has a configuration in which a plurality of buffers are connected in series for adjusting the transmission time as well as a data transmission path inside the bus 120. The input terminal of the bus clock tree 121 is connected to the output terminal of the fixed delay unit 150, and receives the clock CKin. The output terminal of the bus clock tree 121 is connected to the buffers 122A and 122B.

When the clock CKin is input from the fixed delay unit 150, the bus clock tree 121 adds a predetermined delay amount and inputs the clock to the buffers 122A and 122B.

The buffers 122A and 122B are connected to the output terminal of the bus clock tree 121 in parallel with each other. The output terminal of the buffer 122A is connected to the clock input terminals of the FFs 123A and 123B. The output terminal of the buffer 122B is connected to the clock input terminals of the FFs 123C and 123D and the synchronization determination unit 140.

When the clock is input from the bus clock tree 121, the buffers 122A and 122B input the clock BCK to the clock input terminals of the FFs 123A to 123D.

The FFs 123A and 123B are FFs on the side that inputs data transferred from the core 110 to the bus 120. The data input terminal D is connected to the combinational circuit 114A of the core 110 and the output terminal of the buffer 115, respectively. .

The data output terminals Q of the FFs 123A and 123B are connected to an internal circuit (not shown) of the bus 120.

The FFs 123A and 123B reflect the data in the data input terminal D to the data output terminal D when the clock BCK is input from the buffer 122A to the clock input terminal.

FFs 123C and 123D are FFs on the data output side from the bus 120, and the data input terminal D is connected to an internal circuit (not shown) of the bus 120. The data output terminals Q of the FFs 123C and 123D are connected to the combinational circuit 114B of the core 110 and the input terminals of the buffer 115B, respectively.

The FFs 123C and 123D reflect the data in the data input terminal D to the data output terminal D when the clock BCK is input from the buffer 122B to the clock input terminal.

The synchronization determination unit 140 is disposed across the core 110 and the bus 120. The synchronization determination unit 140 includes a pattern generation unit 141, a determination unit 142, a pattern generation unit 143, a determination unit 144, and an output unit 145. Here, the pattern generation units 141 and 143 are examples of test data generation units, and the determination units 142 and 145 are examples of determination units.

The pattern generator 141 is provided on the bus 120 side. The pattern generation unit 141 generates test data td0 based on the clock BCK input from the buffer 122B. Test data td0 generated by the pattern generation unit 141 is input to the determination unit 144. The test data td0 is a replica of normal data transferred from the FFs 123C and 123D of the bus 120 to the FFs 113C and 113D of the core 110.

The determination unit 142 is provided on the bus 120 side. The determination unit 142 determines the phase difference between the clock BCK input from the buffer 122B and the test data td1 input from the pattern generation unit 143, and is a phase difference that allows synchronous transfer from the core 110 to the bus 120. It is determined whether or not.

If the determination unit 142 determines that the phase of the test data td1 input from the pattern generation unit 143 is delayed with respect to the phase of the clock BCK input from the buffer 122B and it is difficult to perform synchronous transfer, the variable delay unit At 130, a delay control command dwn1 for advancing the phase of the clock CKin is output. As a result, the amount of delay applied to the clock CK input to the variable delay unit 130 is reduced, and the clock CKin with the advanced phase is output. The delay control command dwn1 is input to the variable delay unit 130 via the output unit 145.

On the other hand, when the determination unit 142 determines that the phase of the test data td1 input from the pattern generation unit 143 is advanced with respect to the phase of the clock BCK input from the buffer 122B, it is difficult to perform synchronous transfer. The delay unit 130 outputs a delay control command up1 for delaying the phase of the clock CKin. As a result, the amount of delay applied to the clock CK input to the variable delay unit 130 is increased, and the clock CKin with the phase delayed is output. The delay control command up1 is input to the variable delay unit 130 via the output unit 145.

The pattern generator 143 is provided on the core 110 side. The pattern generator 143 generates test data td1 based on the clock CCK input from the buffer 112B. Test data td1 generated by the pattern generation unit 143 is input to the determination unit 142. The test data td1 is a replica of normal data transferred from the FFs 113A and 113B of the core 110 to the FFs 123A and 123B of the bus 120.

The determination unit 144 is provided on the core 110 side. The determination unit 144 determines the phase difference between the clock CCK input from the buffer 112B and the test data td0 input from the pattern generation unit 141, and is a phase difference that allows synchronous transfer from the bus 120 to the core 110. It is determined whether or not.

If the determination unit 144 determines that the phase of the clock CCK input from the buffer 112B is delayed with respect to the phase of the test data td0 input from the pattern generation unit 141 and that synchronous transfer is difficult, the variable delay unit At 130, a delay control command dwn0 for advancing the phase of the clock CKin is output. As a result, the amount of delay applied to the clock CK input to the variable delay unit 130 is reduced, and the clock CKin with the advanced phase is output. The delay control command dwn0 is input to the variable delay unit 130 via the output unit 145.

On the other hand, when the determination unit 144 determines that the phase of the clock CCK input from the buffer 112B is advanced with respect to the phase of the test data td0 input from the pattern generation unit 141 and that synchronous transfer is difficult, the determination unit 144 is variable. The delay unit 130 outputs a delay control command up0 for delaying the phase of the clock CKin. As a result, the amount of delay applied to the clock CK input to the variable delay unit 130 is increased, and the clock CKin with the phase delayed is output. The delay control command up0 is input to the variable delay unit 130 via the output unit 145.

The output unit 145 is realized by a pair of OR (logical sum) circuits. The output unit 145 is one OR circuit, and outputs a delay control command up representing a logical sum of the delay control command up1 input from the determination unit 142 and the delay control command up0 input from the determination unit 144. The output unit 145 is the other OR circuit, and outputs a delay control command dwn representing the logical sum of the delay control command dwn1 input from the determination unit 142 and the delay control command dwn0 input from the determination unit 144. . Delay control commands up and dwn output from the output unit 145 are input to the variable delay unit 130.

Here, although the synchronization determination unit 140 is described as being disposed across the core 110 and the bus 120, the pattern generation unit 141 and the determination unit 142 of the synchronization determination unit 140 are included in the bus 120. It can be handled as a thing. Similarly, the pattern generation unit 143 and the determination unit 144 in the synchronization determination unit 140 can be handled as being included in the core 110.

Next, the circuit configuration of the variable delay unit 130 will be described with reference to FIG.

FIG. 9 is a diagram illustrating the variable delay unit 130 of the synchronous data processing circuit 100 according to the first embodiment.

The variable delay unit 130 includes inverters 131A and 131B, n delay stages 132-1 to 132-n, inverters 133A and 133B, and a shift register 134.

The inverters 131A and 131B are provided at the input section of the variable delay section 130 and are connected in series with each other. The clock CK is input from the PLL 160 (see FIG. 7) to the input terminal of the inverter 131A, and is input to the NAND circuits 132B of the delay stages 132-1 to 132-n from the output terminal of the inverter 131B.

Each delay stage 132-1 to 132-n includes an inverter 132A and NAND circuits 132B and 132C. Note that n is an arbitrary integer, for example, about 100 to 300.

The predetermined VSS (L) level voltage VSS is input to the inverter 132A of the delay stage 132-1. The output terminal of the inverter 132A is connected to one input terminal of the NAND circuit 132C.

The NAND circuit 132B of the delay stage 132-1 has one input terminal connected to the output terminal of the inverter 131B, and the other input terminal connected to the first stage output terminal of the shift register 134. The output terminal of the NAND circuit 132B is connected to the other input terminal of the NAND circuit 132C.

The output terminal of the inverter 132A is connected to one input terminal of the NAND circuit 132C of the delay stage 132-1, and the output terminal of the NAND circuit 132B is connected to the other input terminal. The output terminal of the NAND circuit 132C is connected to the input terminal of the inverter 132A of the next delay stage 132-2.

The inverter 132A and the NAND circuits 132B and 132C of the delay stages 132-2 to 132- (n-1) are all connected in the same manner. The input terminal of the inverter 132A is connected to the output terminal of the NAND circuit 132C of the previous delay stage. The output terminal of the inverter 132A is connected to one input terminal of the NAND circuit 132C.

In the NAND circuit 132B, the output terminal of the inverter 131B is connected to one input terminal, and the output terminal of the shift register 134 is connected to the other input terminal. The output terminal of the NAND circuit 132B is connected to the other input terminal of the NAND circuit 132C.

The output terminal of the inverter 132A is connected to one input terminal of the NAND circuit 132C, and the output terminal of the NAND circuit 132B is connected to the other input terminal. The output terminal of the NAND circuit 132C is connected to the input terminal of the inverter 132A of the next delay stage.

The input terminal of the inverter 132A of the delay stage 132-n is connected to the output terminal of the NAND circuit 132C of the delay stage 132- (n-1). The output terminal of the inverter 132A is connected to one input terminal of the NAND circuit 132C.

The NAND circuit 132B of the delay stage 132-n has one input terminal connected to the output terminal of the inverter 131B, and the other input terminal connected to the n-th output terminal of the shift register 134. The output terminal of the NAND circuit 132B is connected to the other input terminal of the NAND circuit 132C.

The output terminal of the inverter 132A is connected to one input terminal of the NAND circuit 132C of the delay stage 132-n, and the output terminal of the NAND circuit 132B is connected to the other input terminal. The output terminal of the NAND circuit 132C is connected to the input terminal of the inverter 133A.

The inverter 133A is connected to the output terminal of the NAND circuit 132C of the delay stage 132-n, and the output terminal is connected to the input terminal of the inverter 133B.

The input terminal of the inverter 133B is connected to the output terminal of the inverter 133A, and the output terminal is connected to the output terminal of the variable delay unit 130. From the inverter 133B, the clock CKin delayed by the variable delay unit 130 is output.

The shift register 134 has n output terminals, and each output terminal is connected to the other input terminal of the NAND circuit 132B of the delay stages 132-1 to 132-n. The shift register 134 outputs “1” to any one of the n output terminals, and outputs “0” to the other output terminals.

The shift register 134 switches the output terminal that outputs “1” among the n output terminals based on the delay control commands up and dwn input from the output unit 145 of the synchronization determination unit 140.

Further, the output terminal of the inverter 131B is connected to the clock input terminal of the shift register 134, and the shift register 134 operates in accordance with the clock input from the inverter 131B.

When the delay control commands up and dwn are “0” and “0”, the shift register 134 holds the delay amount without changing it. In addition, when the delay control commands up and dwn are “0” and “1”, the shift register 134 moves the output terminal that outputs “1” one right in order to reduce the amount of delay given to the clock CK. Shift to That is, in this case, the shift register 134 shifts the output terminal that outputs “1” by one in the direction (right) indicated by the arrow down.

When the delay control commands up and dwn are “1” and “0”, the shift register 134 shifts the output terminal that outputs “1” to the left in order to increase the amount of delay applied to the clock CK. .

Note that the delay control commands up and dwn are not “1” or “1”.

As shown in FIG. 9, when “1” is output from the output terminal of the shift register 134 corresponding to the second delay stage 132-2, the H (High) level of the clock CK input to the inverter 131A This pulse is inverted twice by the inverters 131A and 131B and output as an H level pulse, and is input to one input terminal of the NAND circuit 132B of the delay stage 132-2. At this time, since “1” is input from the output terminal of the shift register 134 to the other input terminal of the NAND circuit 132B of the delay stage 132-2, the output of the NAND circuit 132B becomes “0”, and the NAND circuit It is input to the other input terminal of 132C.

At this time, since “1” is input to one input terminal of the NAND circuit 132C of the delay stage 132-2, the output of the NAND circuit 132C becomes “1”, and the next delay stage 132-3 Is input.

In the delay stages 132-3 to 132-n, an H level pulse is input from the inverter 1131B to one input terminal of the OR circuit 132B, and “0” is output from the output terminal of the shift register 134 to the other input terminal. Therefore, the output of the NAND circuit 132B becomes “1” and is input to the other input terminal of the NAND circuit 132C.

That is, in the delay stage 132-3, “0” inverted by the inverter 132A is input to one input terminal of the NAND circuit 132C, and “1” is input to the other input terminal of the NAND circuit 132C. Therefore, the output of the NAND circuit 132C becomes “1” and is input to the next delay stage.

In this way, the delay stages 132-3 to 132-n transmit the output "1", and the output "1" of the delay stage 132-n is output as the H level pulse CKin via the inverters 133A and 133B. The

That is, the H level pulse of the clock CK input to the variable delay unit 130 is delayed by the delay stages 132-2 to 133-n and output as the clock CKin.

Therefore, if the output of the shift register 134 is controlled by the delay control signals up and dwn as described above, the delay amount given to the clock CK by the variable delay unit 130 can be controlled. That is, the delay amount of the clock CKin output from the variable delay unit 130 can be controlled.

Next, the circuit configuration of the pattern generation unit 141 and the determination unit 144 of the synchronization determination unit 140 will be described with reference to FIG.

FIG. 10 is a diagram illustrating the pattern generation unit 141 and the determination unit 144 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment.

The pattern generator 141 includes an FF 141A and an inverter 141B. The clock BCK is input from the buffer 122B (see FIG. 8) to the clock input terminal of the FF 141A.

The output terminal of the inverter 141B is connected to the data input terminal D of the FF 141A, and the input terminal of the inverter 141B and the input terminal of the determination unit 144 are connected to the data output terminal Q of the FF 141A.

Since the inverter 141B has an input terminal connected to the data output terminal Q of the FF 141A and an output terminal connected to the data input terminal D of the FF 141A, each time the FF 141A is moved by the clock BCK, the data input terminal D has its own terminal. The value of the data output terminal Q is inverted and input.

Therefore, since the pattern generator 141 alternately outputs “1” and “0” every time the clock BCK is input, the test data td0 generated by the pattern generator 141 is “1”, “0”. The data is repeated alternately.

The determination unit 144 includes delay units 171A, 171B, 171C, FFs 172A, 172B, 172C, and EOR (exclusive OR) circuits 173A, 173B.

The delay units 171A, 171B, and 171C are connected in parallel to the data input terminal D of the FF 141A of the pattern generation unit 141. The delay unit 171A is an example of a first delay unit, and the delay unit 171C is an example of a second delay unit.

The delay unit 171A is a circuit in which five buffers are connected in series, and the output terminal is connected to the data input terminal D of the FF 172A. The delay time of the delay unit 171A is set to the delay time given to the test data td0 in order to realize the worst case setup time (setup worst) when data is synchronously transferred by the FFs 113C and 113D of the core 110.

Here, the worst-case setup time (setup worst) is set to, for example, a time obtained by adding a predetermined margin time to the shortest setup time for synchronously transferring data in the path passing through the FFs 113C and 113D of the core 110. The In other words, the worst-case setup time (setup worst) is obtained by adding a predetermined margin time to the shortest setup time obtained by the longest FF among the paths passing through the FFs 113C and 113D of the core 110, for example. Set to time.

The shortest setup time for synchronously transferring data in the path passing through the FFs 113C and 113D of the core 110 is the shortest time in which synchronous transfer cannot be performed if the setup time is further shortened in the path passing through the FFs 113C and 113D of the core 110. Say.

FIG. 10 shows two FFs 113C and 113D as data reception flip-flops on the core 110 side. However, since the core 110 actually has a large number of flip-flops for data reception, the worst-case setup time (setup worst) may be determined using the shortest setup time in a path passing through all the flip-flops. .

The delay unit 171B is a circuit in which three buffers are connected in series, and the output terminal is connected to the data input terminal D of the FF 172A. The delay time of the delay unit 171B is set to the nominal time of the FFs 113C and 113D of the core 110.

Here, the nominal time (nominal) is set to a time representing the center of the window of valid data transmitted through the path passing through the FFs 113C and 113D of the core 110.

The delay unit 171C is a circuit realized by one buffer, and the output terminal is connected to the data input terminal D of the FF 172A. The delay time of the delay unit 171C is set to the delay time given to the test data td0 in order to realize the worst case hold time (hold worst) when data is synchronously transferred by the FFs 113C and 113D of the core 110.

Here, the worst case hold time (hold worst) is set to, for example, a time obtained by adding a predetermined margin time to the shortest hold time for synchronously transferring data in the path passing through the FFs 113C and 113D of the core 110. The In other words, the worst case hold time (hold worst) is obtained by adding a predetermined margin time to the shortest hold time obtained by the FF having the longest path among the paths passing through the FFs 113C and 113D of the core 110, for example. Set to time.

The shortest hold time when data is synchronously transferred in the path passing through the FFs 113C and 113D of the core 110 is the shortest time in which synchronous transfer cannot be performed if the hold time is further shortened in the path passing through the FFs 113C and 113D of the core 110. Say.

Since the core 110 actually has many flip-flops for data transmission, the worst case hold time (hold （worst) is used by using the shortest hold time among the hold times in the paths passing through all the flip-flops. Can be determined.

Note that the number of buffers in the delay units 171A to 171C is an example.

In the FF 172A, the data input terminal D is connected to the output terminal of the delay unit 171A, the data output terminal Q is connected to one input terminal of the EOR circuit 173A, and the clock CCK is input to the clock input terminal. Here, data output from the data output terminal Q of the FF 172A is represented as sd0.

In the FF 172B, the data input terminal D is connected to the output terminal of the delay unit 171B, the data output terminal Q is connected to the other input terminal of the EOR circuit 173A and one input terminal of the EOR circuit 173B, and the clock input terminal is clocked. CCK is input. Here, data output from the data output terminal Q of the FF 172B is represented as nd0.

In the FF 172C, the data input terminal D is connected to the output terminal of the delay unit 171C, the data output terminal Q is connected to the other input terminal of the EOR circuit 173C, and the clock CCK is input to the clock input terminal. Here, data output from the data output terminal Q of the FF 172C is represented as hd0.

In the EOR circuit 173A, the data output terminal Q of the FF 172A is connected to one input terminal, the data output terminal Q of the FF 172B is connected to the other input terminal, and the delay control command up0 is output from the output terminal.

In the EOR circuit 173B, the data output terminal Q of the FF 172B is connected to one input terminal, the data output terminal Q of the FF 172C is connected to the other input terminal, and the delay control command dwn0 is output from the output terminal.

Next, operations of the pattern generation unit 141 and the determination unit 144 of the synchronization determination unit 140 will be described with reference to FIG.

FIG. 11 is a timing chart illustrating an operation example of the pattern generation unit 141 and the determination unit 144 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment.

FIG. 11 shows clocks BCK, CCK, test data td0, output data of delay unit 171A (setup 部 worst), output data of delay unit 171B (nominal), output data of delay unit 171C (hold worst), and FFs 172A to 172C. The transition of output data sd0, nd0, hd0 and delay control commands up0, dwn0 is shown.

Here, the output data (setup worst) of the delay unit 171A is data obtained by delaying the test data td0 by the delay unit 171A. The output data (nominal) of the delay unit 171B is data obtained by delaying the test data td0 by the delay unit 171B. The output data (hold worst) of the delay unit 171C is data obtained by delaying the test data td0 by the delay unit 171C. A delay time given to the test data td0 by the delay units 171A to 171C is indicated by an arrow in FIG.

FIG. 11A is a timing chart in a state where data is synchronously transferred from the bus 120 to the core 110.

As shown in FIG. 11A, when the phases of the clocks BCK and CCK are equal, the rising phase of the test data td0 output from the pattern generator 141 is equal to the rising phase of the clock CCK.

In this case, the rise of the output data (hold worst) of the delay unit 171C is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured, so the output hd0 of the FF 172C is the time At t1, the L level is equal to the test data td0.

Also, the output data (nominal) of the delay unit 171B is sufficiently later than the rising edge of the clock CCK at time t1, and the output nd0 of the FF 172B is at the L level equal to the test data td0 at time t1.

Also, the rise of the output data (setuprstworst) of the delay unit 171A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sd0 of the FF 172A is at time t1. The L level is equal to the test data td0.

Therefore, the outputs of the EOR circuits 173A and 173B are both “0”, and the delay control commands up0 and dwn0 are both at the L level.

Next, as shown in FIG. 11B, a case where the clock CCK input to the determination unit 144 on the core 110 side is delayed with respect to the clock BCK input to the pattern generation unit 141 on the bus 120 side. explain. This case corresponds to a case where the clock CCK is delayed due to a drop in the supply voltage to the core 110 due to DVFS.

As shown in FIG. 11B, when the phase of CCK is delayed with respect to the clock BCK, the rising timing of the clock CCK at the time t1 is the rising edge of the test data td0 output from the pattern generator 141. It is behind the timing.

In this case, the rise of the output data (hold worst) of the delay unit 171C is prior to the rise of the clock CCK at time t1 (timing violated), and the output data of the delay unit 171C is already at the rise of the clock CCK at time t1. (Hold worst) is at the H level. This is a case where the hold time is insufficient and the hold time constraint is violated.

Therefore, the L level of the output data (hold low) of the delay unit 171C cannot be acquired, and the output hd0 of the FF 172C becomes an H level different from the test data td0 at time t1.

Also, the rise of the output data (nominal) of the delay unit 171B is sufficiently later than the rise of the clock CCK at time t1, and the output nd0 of the FF 172B is at L level equal to the test data td0 at time t1.

Further, the rise of the output data (setuprstworst) of the delay unit 171A is before the time t2 when the clock CCK rises after the rise of the clock CCK at time t1 (timing met), and the setup time is secured. The output sd0 of the FF 172A is at the L level equal to the test data td0 at time t1.

Therefore, the output of the EOR circuit 173A becomes “0” and the output of the EOR circuit 173B becomes “1”, so that the delay control command up0 becomes L level and the delay control command dwn0 becomes H level. That is, in order to advance the phase of the clock CCK, an H level delay control command dwn is output from the determination unit 144.

Next, as shown in FIG. 11C, the clock CCK input to the determination unit 144 on the core 110 side is advanced with respect to the clock BCK input to the pattern generation unit 141 on the bus 120 side. explain. This case corresponds to the case where the clock CCK is advanced by raising from the state where the supply voltage to the core 110 has been lowered by DVFS.

As shown in FIG. 11C, when the phase of the CCK is advanced with respect to the clock BCK, the rising timing of the clock CCK at the time t1 is the rising edge of the test data td0 output from the pattern generation unit 141. More advanced than timing.

In this case, the rise of the output data (hold worst) of the delay unit 171C is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured. The H level of the output data (hold worst) of the delay unit 171C is acquired at the rising edge of the clock CCK at time t1. Therefore, the output hd0 of the FF 172C becomes H level equal to the test data td0 at time t1.

Also, the rise of the output data (nominal) of the delay unit 171B is sufficiently before the rise of the clock CCK at time t1, and the output nd0 of the FF 172B becomes H level equal to the test data td0 at time t1.

The rising edge of the output data (setup worst) of the delay unit 171A is later than the rising edge of the clock CCK at time t1 (timing violated), and when the clock CCK rises at time t1, it has not switched to the H level. However, it remains at the L level. This is a case where the setup time constraint is violated. Therefore, the output sd0 of the FF 172A is held at the L level different from the test data td0 at time t1.

Therefore, since the output of the EOR circuit 173A becomes “1” and the output of the EOR circuit 173B becomes “0”, the delay control command up0 becomes the H level and the delay control command dwn0 becomes the L level. That is, an H-level delay control command up is output from the determination unit 144 in order to delay the phase of the clock CCK.

As described above, in the determination unit 144, the clock CCK input to the determination unit 144 is delayed with respect to the clock BCK input to the pattern generation unit 141, and the output data (hold worst) of the delay unit 171C is correctly set. If it cannot be obtained, an H level delay control command dwn is output to advance the phase of the clock CCK.

Further, the determination unit 144 is not able to correctly acquire the output data (setup 判定 worst) of the delay unit 171A because the clock CCK input to the determination unit 144 is advanced with respect to the clock BCK input to the pattern generation unit 141. Outputs a delay control command up0 of H level to delay the phase of the clock CCK.

Note that the determination unit 144 obtains the output data (hold worst) of the delay unit 171C and the output data (setup worst) of the delay unit 171A correctly and correctly with the output data (nominal) of the delay unit 171B. Both output L level delay control commands up0 and dwn0.

Next, the circuit configuration of the determination unit 142 and the pattern generation unit 143 of the synchronization determination unit 140 will be described with reference to FIG.

FIG. 12 is a diagram illustrating the determination unit 142 and the pattern generation unit 143 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment.

The pattern generator 143 includes an FF 143A and an inverter 143B. The clock CCK is input from the buffer 122B (see FIG. 8) to the clock input terminal of the FF 143A.

The output terminal of the inverter 143B is connected to the data input terminal D of the FF 143A, and the input terminal of the inverter 143B and the input terminal of the determination unit 142 are connected to the data output terminal Q of the FF 143A.

Since the input terminal of the inverter 143B is connected to the data output terminal Q of the FF 143A and the output terminal is connected to the data input terminal D of the FF 143A, each time the FF 143A is moved by the clock CCK, the data input terminal D has its own terminal. The value of the data output terminal Q is inverted and input.

Therefore, since the pattern generator 143 alternately outputs “1” and “0” every time the clock CCK is input, the test data td1 generated by the pattern generator 143 is “1”, “0”. The data is repeated alternately.

The determination unit 142 includes delay units 181A, 181B, 181C, FFs 182A, 182B, 182C, and EOR (exclusive OR) circuits 183A, 183B.

The delay units 181A, 181B, 181C are connected in parallel to the data input terminal D of the FF 141A of the pattern generation unit 143. The delay unit 181A is an example of a first delay unit, and the delay unit 181C is an example of a second delay unit.

The delay unit 181A is a circuit in which five buffers are connected in series, and the output terminal is connected to the data input terminal D of the FF 182A. The delay time of the delay unit 181A is set to the delay time given to the test data td1 in order to realize the worst-case setup time (setup worst) when data is synchronously transferred by the FFs 113A and 113B of the core 110.

Here, the worst-case setup time (setup worst) is set to, for example, a time obtained by adding a predetermined margin time to the shortest setup time for synchronously transferring data in the path passing through the FFs 113A and 113B of the core 110. The In other words, the worst-case setup time (setup worst) is obtained by adding a predetermined margin time to the shortest setup time obtained by the longest FF among the paths passing through the FFs 113A and 113B of the core 110, for example. Set to time.

The shortest setup time for synchronously transferring data in the path passing through the FFs 113A and 113B of the core 110 is the shortest time in which synchronous transfer cannot be performed if the setup time is further shortened in the path passing through the FFs 113A and 113B of the core 110. Say.

In FIG. 12, two FFs 113A and 113B are shown as flip-flops for data transmission on the core 110 side. However, since the core 110 actually has a large number of data transmission flip-flops, the worst-case setup time (setup worst) may be determined using the shortest setup time in a path passing through all the flip-flops. .

The delay unit 181B is a circuit in which three buffers are connected in series, and the output terminal is connected to the data input terminal D of the FF 182A. The delay time of the delay unit 181B is set to the delay time given to the test data td1 in order to realize the nominal time of the FFs 113A and 113B of the core 110.

Here, the nominal time (nominal) is set to a time representing the center of the window of valid data transmitted through the path passing through the FFs 113A and 113B of the core 110.

The delay unit 181C is a circuit realized by one buffer, and its output terminal is connected to the data input terminal D of the FF 182A. The delay time of the delay unit 181C is set to the delay time given to the test data td0 in order to realize the worst case hold time (hold 際 worst) when data is synchronously transferred by the FFs 113A and 113B of the core 110.

Here, the worst case hold time (hold worst) is set to, for example, a time obtained by adding a predetermined margin time to the shortest hold time for synchronously transferring data in the path passing through the FFs 113A and 113B of the core 110. The In other words, the worst case hold time (hold worst) is obtained by adding a predetermined margin time to the shortest hold time obtained by the FF having the longest path among the paths passing through the FFs 113A and 113B of the core 110, for example. Set to time.

The shortest hold time when data is synchronously transferred in the path passing through the FFs 113A and 113B of the core 110 is the shortest time in which synchronous transfer cannot be performed if the hold time is further shortened in the path passing through the FFs 113A and 113B of the core 110. Say.

Since the core 110 actually has many flip-flops for data transmission, the worst case hold time (hold （worst) is used by using the shortest hold time among the hold times in the paths passing through all the flip-flops. Can be determined.

Note that the number of buffers in the delay units 181A to 181C is an example.

In the FF 182A, the data input terminal D is connected to the output terminal of the delay unit 181A, the data output terminal Q is connected to one input terminal of the EOR circuit 183A, and the clock BCK is input to the clock input terminal. Here, the data output from the data output terminal Q of the FF 182A is represented as sd1.

In the FF 182B, the data input terminal D is connected to the output terminal of the delay unit 181B, the data output terminal Q is connected to the other input terminal of the EOR circuit 183A and one input terminal of the EOR circuit 183B, and the clock input terminal is clocked. BCK is input. Here, data output from the data output terminal Q of the FF 182B is represented as nd1.

In the FF 182C, the data input terminal D is connected to the output terminal of the delay unit 181C, the data output terminal Q is connected to the other input terminal of the EOR circuit 183C, and the clock BCK is input to the clock input terminal. Here, data output from the data output terminal Q of the FF 182C is represented by hd1.

In the EOR circuit 183A, the data output terminal Q of the FF 182A is connected to one input terminal, the data output terminal Q of the FF 182B is connected to the other input terminal, and the delay control command dwn1 is output from the output terminal.

In the EOR circuit 183B, the data output terminal Q of the FF 182B is connected to one input terminal, the data output terminal Q of the FF 182C is connected to the other input terminal, and the delay control command up1 is output from the output terminal.

Next, the operations of the determination unit 142 and the pattern generation unit 143 of the synchronization determination unit 140 will be described with reference to FIG.

FIG. 13 is a timing chart illustrating an operation example of the determination unit 142 and the pattern generation unit 143 of the synchronization determination unit 140 of the synchronous data processing circuit 100 according to the first embodiment.

FIG. 13 shows clocks BCK, CCK, test data td1, output data of delay unit 181A (setup worst), output data of delay unit 181B (nominal), output data of delay unit 181C (hold worst), and FFs 182A to 182C. The transition of the output data sd1, nd1, hd1, and delay control commands up1, dwn1 is shown.

FIG. 13A is a timing chart in a state where data is synchronously transferred from the core 110 to the bus 120.

As shown in FIG. 13A, when the phases of the clocks BCK and CCK are equal, the rising phase of the test data td1 output from the pattern generator 143 is equal to the rising phase of the clock BCK.

In this case, the rise of the output data (hold worst) of the delay unit 181C is later than the rise of the clock BCK at time t1 (timing met), and the hold time is secured, so the output hd1 of the FF 182C is the time At t1, the L level is equal to the test data td1.

The output data (nominal) of the delay unit 181B is sufficiently later than the rising edge of the clock BCK at time t1, and the output nd1 of the FF 182B is at L level equal to the test data td1 at time t1.

The rise of the output data (setup worst) of the delay unit 181A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sd1 of the FF 182A is at time t1. The L level is equal to the test data td1.

Therefore, the outputs of the EOR circuits 183A and 183B are both “0”, and the delay control commands up1 and dwn1 are both at the L level.

Next, as shown in FIG. 13B, the clock CCK input to the determination unit 142 on the core 110 side is advanced with respect to the clock BCK input to the pattern generation unit 143 on the bus 120 side. explain. This case corresponds to the case where the clock CCK is advanced by raising from the state where the supply voltage to the core 110 has been lowered by DVFS.

As shown in FIG. 13B, when the phase of the CCK is advanced with respect to the clock BCK, the rising timing of the clock BCK at the time t1 is the rising timing of the test data td1 output from the pattern generator 143. It is behind the timing.

In this case, the rise of the output data (hold worst) of the delay unit 181C is prior to the rise of the clock BCK at time t1 (timing violated), and the output data of the delay unit 181C is already at the rise of the clock BCK at time t1. (Hold worst) is at the H level. This is a case where the hold time is insufficient and the hold time constraint is violated.

Therefore, the L level of the output data (hold low) of the delay unit 181C cannot be acquired, and the output hd1 of the FF 182C becomes an H level different from the test data td1 at time t1.

Also, the rise of the output data (nominal) of the delay unit 181B is sufficiently later than the rise of the clock BCK at time t1, and the output nd1 of the FF 182B is at the L level equal to the test data td1 at time t1.

Also, the rise of the output data (setuprstworst) of the delay unit 181A is before the rise of the clock BCK at time t2 (timing met), and the setup time is secured, so the output sd1 of the FF 182A is at time t1. The L level is equal to the test data td1.

Therefore, the output of the EOR circuit 183A becomes “0” and the output of the EOR circuit 183B becomes “1”, so that the delay control command dwn1 becomes L level and the delay control command up1 becomes H level. That is, in order to delay the phase of the clock CCK, an H level delay control command up 1 is output from the determination unit 142.

Next, as shown in FIG. 13C, the clock CCK input to the determination unit 142 on the core 110 is delayed with respect to the clock BCK input to the pattern generation unit 143 on the bus 120 side. explain. This case corresponds to a case where the clock CCK is delayed due to a drop in the supply voltage to the core 110 due to DVFS.

As shown in FIG. 13C, when the phase of the CCK is delayed with respect to the clock BCK, the rising timing of the clock BCK at the time t1 is the rising edge of the test data td1 output from the pattern generator 143. More advanced than timing.

In this case, the rise of the output data (hold worst) of the delay unit 181C is later than the rise of the clock BCK just before the rise of the clock BCK at time t1 (timing met), and the hold time is secured. The H level of the output data (hold worst) of the delay unit 181C is acquired at the rising edge of the clock BCK at time t1. For this reason, the output hd1 of the FF 182C becomes H level equal to the test data td1 at time t1.

Also, the rise of the output data (nominal) of the delay unit 181B is sufficiently before the rise of the clock BCK at time t1, and the output nd1 of the FF 182B becomes H level equal to the test data td1 at time t1.

The rise of the output data (setup worst) of the delay unit 181A is later than the rise of the clock BCK at time t1 (timing violated), and when the clock BCK rises at time t1, it has not been switched to the H level. However, it remains at the L level. This is a case where the setup time constraint is violated. Therefore, the output sd1 of the FF 182A is held at an L level different from the test data td1 at time t1.

Therefore, the output of the EOR circuit 183A becomes “1” and the output of the EOR circuit 183B becomes “0”, so that the delay control command dwn1 becomes the H level and the delay control command up1 becomes the L level. That is, in order to advance the phase of the clock CCK, an H level delay control command dwn1 is output from the determination unit 142.

As described above, in the determination unit 142, the clock CCK input to the determination unit 142 is advanced with respect to the clock BCK input to the pattern generation unit 143, and the output data (hold worst) of the delay unit 181C is correctly set. If it cannot be obtained, an H level delay control command up1 is output to delay the phase of the clock CCK.

Further, the determination unit 142 is unable to correctly acquire the output data (setup worst) of the delay unit 181A because the clock CCK input to the determination unit 142 is delayed with respect to the clock BCK input to the pattern generation unit 143. Outputs an H level delay control command dwn1 to advance the phase of the clock CCK.

Note that when the output data (hold worst) of the delay unit 181C and the output data (setup worst) of the delay unit 181A are correctly acquired equally to the output data (nominal) of the delay unit 181B, the determination unit 142 Both output L level delay control commands up1 and dwn1.

As described above, according to the synchronous data processing circuit 100 of the first embodiment, the phase difference between the clock BCK on the bus 120 side and the clock CCK on the core 110 side is a predetermined value (worst case hold time (hold （worst) or worst). When it becomes longer than the setup time (setup worst) of the case, the phase of the clock CCK is adjusted by the delay control commands up1 and dwn1.

Therefore, it is possible to provide the synchronous data processing circuit 100 that can stably perform the synchronous transfer of data between the core 110 and the bus 120.

In addition, by reducing the power consumption by DVFS and adjusting the phase of the clock input to the core 110 by the variable delay unit 130 as described above, the data is synchronously transferred even when the power supplied to the core 110 is reduced. can do.

As described above, according to the synchronous data processing circuit 100 of the first embodiment, it is possible to stably perform synchronous data transfer while reducing power consumption.

The synchronous data processing circuit 100 according to the first embodiment is suitable for, for example, LTE (Long Term Evolution), which is a high-speed data communication standard with a communication speed exceeding 100 Mbps.

In recent years, for example, in a portable terminal such as the smartphone terminal 10 shown in FIG. 1, in order to extend the duration of the battery as much as possible, the demand for low power consumption of the entire system has become strict.

On the other hand, with the adoption of LTE, which is a high-speed data communication standard exceeding 100 Mbps, requirements for high-speed processing of LSIs used in baseband modules are becoming stricter. In addition, since the number of base stations corresponding to the current LTE is small, the range in which LTE can be used is narrow. Therefore, W-CDMA (Wideband-CDMA), which is a 3G communication standard that is automatically spreading in places where LTE cannot be used. ) Etc. are required.

In a mobile terminal such as the smartphone terminal 10 shown in FIG. 1, for example, in the baseband module 60, if a signal cannot be received by the antenna 81 even after searching for an LTE base station, the baseband is received by an instruction from the system controller 42. The function of the module 60 is switched from LTE to W-CDMA.

Here, since the communication speed of W-CDMA is lower than that of LTE, the data processing performance is not as high as that of LTE. Further, when both LTE and W-CDMA communication are possible, the baseband module 60 is set to a specification that enables high-speed data processing in accordance with the LTE standard.

When such a baseband module 60 is switched to W-CDMA communication, the performance is excessive, so that there is a problem that power consumption becomes larger than when a baseband module designed for W-CDMA is used. is there.

Also, there is a problem that the power consumption becomes larger than when a baseband module designed for W-CDMA is used because high-speed processing performance is not required even during voice processing during standby or during standby.

In order to solve such a problem, the power consumption of the baseband module 60 is reduced by adopting DVFS.

However, as described with reference to FIGS. 4A and 4B, when the supply voltage to the cores 0 and 1 included in the application processor 50 and the baseband processor 70 is lowered, the delay time becomes longer, so that the synchronous transfer is performed. The problem that it becomes impossible to occur.

Further, as described with reference to FIG. 5, by using the asynchronous bridge 98 (see FIG. 5A), data can be transferred asynchronously when synchronous transfer is not possible, but the transfer rate is reduced by about 50%. In addition, there is a problem that the number of development steps for guaranteeing the operation increases.

On the other hand, if the synchronous data processing circuit 100 of the first embodiment is applied to the application processor 50 or the baseband processor 70 of the smartphone terminal 10 shown in FIGS. Therefore, low power consumption can be achieved.

Further, even if the supply voltage to the core 110 is lowered by DVFS, the variable delay unit 130 adjusts the delay time so that the data can be transferred synchronously, and the asynchronous bridge 98 of the comparative example (see FIG. 5A). As in the case of using, it is possible to suppress a decrease in transfer speed.

Furthermore, since there is no need to use the asynchronous bridge 98, it is possible to suppress an increase in the development man-hours for guaranteeing the operation, and to provide a synchronous data processing circuit capable of performing synchronous transfer with a smaller development man-hour. it can.

In the above description, the mode in which data is synchronously transferred in both directions between the core 110 and the bus 120 has been described. However, the same applies to the case where data is synchronously transferred in one way from the core 110 to the bus 120. be able to. On the other hand, when data is synchronously transferred by one-way from the bus 120 to the core 110, the same operation can be performed.

In the above description, the variable delay unit 130 is connected to the core 110 and the fixed delay unit 150 is connected to the bus 120 (see FIG. 7) to adjust the phase of the clock CCK of the core 110.

However, the phase of the clock BCK of the bus 120 may be adjusted by connecting the variable delay unit 130 to the bus 120 and connecting the fixed delay unit 150 to the core 110.

<Embodiment 2>
The synchronous data processing circuit according to the second embodiment should be noted before the phase difference between the clocks BCK and CCK reaches the worst case hold time (hold worst) or the worst case setup time (setup worst) in the first embodiment. The processing is different from the synchronous data processing circuit 100 of the first embodiment.

Further, in the synchronous data processing circuit of the second embodiment, when the phase difference between the clocks BCK and CCK reaches the worst case hold time (hold worst) or the worst case setup time (setup worst) in the first embodiment, The difference from the synchronous data processing circuit 100 of the first embodiment is that a freeze process for freezing the system is performed until the phase difference is relaxed.

Other components are the same as those of the synchronous data processing circuit 100 of the first embodiment, and thus similar components are denoted by the same reference numerals and description thereof is omitted.

FIG. 14 is a diagram illustrating a circuit configuration of the core 110, the bus 120, and the synchronization determination unit 240 of the synchronous data processing circuit according to the second embodiment.

The core 110 includes a core clock tree 111, buffers 112B, FFs 113A to 113D, combinational circuits 114A and 114B, buffers 115A and 115B, and gate lock buffers 212A and 212B.

The core clock tree 111 is arranged inside the core 110, and is a data transmission path inside the core 110, and has a configuration in which a plurality of buffers are connected in series for adjusting the transmission time. The input terminal of the core clock tree 111 is connected to the output terminal of the variable delay unit 130, and receives the clock CKin. The output terminal of the core clock tree 111 is connected to the buffer 112B and the clock input terminals of the gate lock buffers 212A and 212B.

When the clock CKin is input from the variable delay unit 130, the core clock tree 111 gives a predetermined delay amount and inputs the clock to the buffer 112B and the clock input terminals of the gate lock buffers 212A and 212B.

The buffer 112B is connected to the output terminal of the core clock tree 111. The output terminal of the buffer 112B is connected to the synchronization determination unit 240. The buffer 112B is different from the buffer 112B of the first embodiment in that the output terminal is connected only to the synchronization determination unit 240.

The gate lock buffer 212A has a clock input terminal connected to the output terminal of the core clock tree 111, and a freeze signal input terminal connected to the freeze signal output unit of the output unit 245 of the synchronization determination unit 240. The output terminal of the gate lock buffer 212A is connected to the clock input terminals of the FFs 113A and 113B.

When the freeze signal frz input from the output unit 245 to the freeze signal input terminal is “0”, the gate lock buffer 212A outputs the clock input to the clock input terminal as it is. Therefore, the gate lock buffer 212A outputs the clock CCK1 when the freeze signal frz is “0”.

Here, the clock CCK1 is a clock having the same phase as the clock CCK output from the buffer 112B, but in the second embodiment, it is distinguished from the clock CCK output from the buffer 112B.

On the other hand, when the freeze signal frz is “1”, the gate lock buffer 212A fixes the clock output from the output terminal and freezes the data transfer.

In the gate lock buffer 212B, the clock input terminal is connected to the output terminal of the core clock tree 111, and the freeze signal input terminal is connected to the freeze signal output unit of the output unit 245 of the synchronization determination unit 240. The output terminal of the gate lock buffer 212B is connected to the clock input terminals of the FFs 113C and 113D.

When the freeze signal frz input from the output unit 245 to the freeze signal input terminal is “0”, the gate lock buffer 212B outputs the clock input to the clock input terminal as it is. Therefore, the gate lock buffer 212B outputs the clock CCK1 when the freeze signal frz is “0”.

On the other hand, when the freeze signal frz is “1”, the gate lock buffer 212B fixes the clock output from the output terminal and freezes the data transfer.

The FFs 113A and 113B are different from the FFs 113A and 113B of the first embodiment in that the output terminal of the gate lock buffer 212A is connected to the clock input terminal. Other configurations and operations of the FFs 113A and 113B of the second embodiment are the same as those of the FFs 113A and 113B of the first embodiment.

The FFs 113C and 113D are different from the FFs 113C and 113D of the first embodiment in that the output terminal of the gate lock buffer 212B is connected to the clock input terminal. Other configurations and operations of the FFs 113C and 113D of the second embodiment are the same as those of the FFs 113C and 113D of the first embodiment.

The bus 120 includes a bus clock tree 121, a buffer 122B, FFs 123A to 123D, and gate lock buffers 222A and 222B.

The output terminal of the bus clock tree 121 is connected to the buffer 122B and the clock input terminals of the gate lock buffers 222A and 222B.

When the clock CKin is input from the fixed delay unit 150, the bus clock tree 121 gives a predetermined delay amount and inputs the clock to the buffer 122B and the clock input terminals of the gate lock buffers 222A and 222B.

The buffer 122B is connected to the output terminal of the bus clock tree 121. The output terminal of the buffer 122B is connected to the synchronization determination unit 240. The buffer 122B is different from the buffer 122B of the first embodiment in that the output terminal is connected only to the synchronization determination unit 240.

The gate lock buffer 222A has a clock input terminal connected to the output terminal of the bus clock tree 121 and a freeze signal input terminal connected to the freeze signal output section of the output section 245 of the synchronization determination section 240. The output terminal of the gate lock buffer 222A is connected to the clock input terminals of the FFs 123A and 123B.

When the freeze signal frz input from the output unit 245 to the freeze signal input terminal is “0”, the gate lock buffer 222A outputs the clock input to the clock input terminal as it is. Therefore, the gate lock buffer 222A outputs the clock BCK1 when the freeze signal frz is “0”.

Here, the clock BCK1 is a clock having the same phase as the clock BCK output from the buffer 122B, but in the second embodiment, the clock BCK1 is distinguished from the clock CCK output from the buffer 122B.

On the other hand, when the freeze signal frz is “1”, the gate lock buffer 222A fixes the clock output from the output terminal and freezes the data transfer.

The gate lock buffer 222B has a clock input terminal connected to the output terminal of the bus clock tree 121 and a freeze signal input terminal connected to the freeze signal output section of the output section 245 of the synchronization determination section 240. The output terminal of the gate lock buffer 222B is connected to the clock input terminals of the FFs 123C and 123D.

When the freeze signal frz input from the output unit 245 to the freeze signal input terminal is “0”, the gate lock buffer 222B outputs the clock input to the clock input terminal as it is. Therefore, the gate lock buffer 222B outputs the clock BCK1 when the freeze signal frz is “0”.

On the other hand, when the freeze signal frz is “1”, the gate lock buffer 222B fixes the clock output from the output terminal and freezes the data transfer.

The FFs 123A and 123B are different from the FFs 123A and 123B of the first embodiment in that the output terminal of the gate lock buffer 222A is connected to the clock input terminal.

The FFs 123C and 123D are different from the FFs 123C and 123D of the first embodiment in that the output terminal of the gate lock buffer 222B is connected to the clock input terminal.

The synchronization determination unit 240 is disposed across the core 110 and the bus 120. The synchronization determination unit 240 includes a pattern generation unit 241, a determination unit 242, a pattern generation unit 243, a determination unit 244, and an output unit 245.

The pattern generator 241 is provided on the bus 120 side. The pattern generator 241 generates test data td0 based on the clock BCK input from the buffer 122B. Test data td0 generated by the pattern generation unit 241 is input to the determination unit 244.

The determination unit 242 is provided on the bus 120 side. The determination unit 242 determines a phase difference between the clock BCK input from the buffer 122B and the test data td1 input from the pattern generation unit 243, and performs attention processing and freeze processing.

The determination unit 242 reaches the attention hold time (hold warning) in which the phase of the test data td1 is delayed with respect to the phase of the clock BCK and the phase difference is smaller than the worst case hold time (hold worst) by a predetermined phase difference. Then, the delay control command dwn1 for advancing the phase of the clock CKin by the variable delay unit 130 is output.

Thus, the amount of delay applied to the clock CK input to the variable delay unit 130 is reduced, and the clock CKin with the advanced phase is output. The delay control command dwn1 is input to the variable delay unit 130 via the output unit 245.

In addition, when the phase of the test data td1 is delayed with respect to the phase of the clock BCK and the phase difference reaches the worst case hold time (hold worst), the determination unit 242 fixes the FFs 113A to 113D and 123A to 123D to fix the data. The freeze signal frz1 for freezing the transfer of.

On the other hand, the determination unit 242 has a test setup time (setupｔwarning) in which the phase of the test data td1 is advanced with respect to the phase of the clock BCK and the phase difference is larger by a predetermined phase difference than the worst-case setup time (setup worst). Is reached, the variable delay unit 130 outputs a delay control command up1 for delaying the phase of the clock CKin.

Thereby, the amount of delay given to the clock CK input to the variable delay unit 130 is increased, and the clock CKin with the phase delayed is output. The delay control command up1 is input to the variable delay unit 130 via the output unit 245.

Further, when the phase of the test data td1 advances with respect to the phase of the clock BCK and the phase difference reaches the worst-case setup time (setup worst), the determination unit 242 fixes the FFs 113A to 113D and 123A to 123D to fix the data. The freeze signal frz1 for freezing the transfer of.

The pattern generator 243 is provided on the core 110 side. The pattern generator 243 generates test data td1 based on the clock CCK input from the buffer 112B. Test data td1 generated by the pattern generation unit 243 is input to the determination unit 242.

The determination unit 244 is provided on the bus 120 side. The determination unit 244 determines the phase difference between the clock CCK input from the buffer 112B and the test data td0 input from the pattern generation unit 241, and performs attention processing and freeze processing.

The determination unit 244 reaches the attention hold time (hold warning) in which the phase of the test data td0 is delayed with respect to the phase of the clock CCK, and the phase difference is smaller than the worst case hold time (hold worst) by a predetermined phase difference. Then, the delay control command dwn0 for advancing the phase of the clock CKin by the variable delay unit 130 is output.

As described above, when the phase difference reaches a warning hold time (hold warning) that is smaller than the worst case hold time (hold worst) by a predetermined phase difference, the delay control for advancing the phase of the clock CKin by the variable delay unit 130 The process of outputting the command dwn0 is a caution process when the phase of the clock CCK is delayed.

Thus, the amount of delay applied to the clock CK input to the variable delay unit 130 is reduced, and the clock CKin with the advanced phase is output. The delay control command dwn0 is input to the variable delay unit 130 via the output unit 245.

In addition, when the phase of the test data td0 is delayed with respect to the phase of the clock CCK and the phase difference reaches the worst case hold time (hold worst), the determination unit 244 fixes the FFs 113A to 113D and 123A to 123D to fix the data. The freeze signal frz0 for freezing the transfer of.

Thus, when the phase difference reaches the worst case hold time (hold （worst), the process of outputting the freeze signal frz0 for fixing the FFs 113A to 113D and 123A to 123D to freeze the data transfer is performed by the clock CCK. This is a freezing process when the phase is delayed.

On the other hand, in the determination unit 244, the phase of the test data td0 with respect to the phase of the clock CCK is advanced, and the phase difference is larger than the worst case setup time (setup worst) by a predetermined phase difference (setup warning). Is reached, the variable delay unit 130 outputs a delay control command up0 for delaying the phase of the clock CKin.

In this way, when the phase difference reaches the setup time for warning (setup warning), which is larger than the worst-case setup time (setup worst) by a predetermined phase difference, delay control for delaying the phase of the clock CKin by the variable delay unit 130 The process of outputting the command up0 is a caution process when the phase of the clock CCK is advanced.

Thereby, the amount of delay given to the clock CK input to the variable delay unit 130 is increased, and the clock CKin with the phase delayed is output. The delay control command up0 is input to the variable delay unit 130 via the output unit 245.

Further, when the phase of the test data td0 advances with respect to the phase of the clock CCK and the phase difference reaches the worst-case setup time (setup worst), the determination unit 244 fixes the FFs 113A to 113D and 123A to 123D to fix the data. The freeze signal frz0 for freezing the transfer of.

Thus, when the phase difference reaches the worst case setup time (setup worst), the freeze signal frz0 for fixing the FFs 113A to 113D and 123A to 123D and freezing the data transfer is outputted by the phase of the clock CCK. This is a freezing process in the case of progressing.

The pattern generator 241 is provided on the core 110 side. The pattern generator 241 generates test data td0 based on the clock CCK input from the buffer 112B. Test data td0 generated by the pattern generation unit 241 is input to the determination unit 244.

The output unit 245 is realized by three OR (logical sum) circuits. The output unit 245 is a single OR circuit, and outputs a delay control command up representing the logical sum of the delay control command up1 input from the determination unit 242 and the delay control command up0 input from the determination unit 244. The output unit 245 is a second OR circuit, and outputs a delay control command dwn representing a logical sum of the delay control command dwn1 input from the determination unit 242 and the delay control command dwn0 input from the determination unit 244. Output. The output unit 245 is a third OR circuit, and outputs a freeze signal frz representing the logical sum of the freeze signal frz1 input from the determination unit 242 and the freeze signal frz0 input from the determination unit 244.

The delay control commands up and dwn output from the output unit 245 are input to the variable delay unit 130, and the freeze signal frz is input to the freeze signal input terminals of the gate lock buffers 212A, 212B, 222A, and 222B.

Here, although the synchronization determination unit 240 is described as being disposed across the core 110 and the bus 120, the pattern generation unit 241 and the determination unit 242 of the synchronization determination unit 240 are included in the bus 120. It can be handled as a thing. Similarly, the pattern generation unit 243 and the determination unit 244 in the synchronization determination unit 240 can be handled as being included in the core 110.

Next, the circuit configuration of the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 will be described with reference to FIG.

FIG. 15 is a diagram illustrating the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 of the synchronous data processing circuit 100 according to the first embodiment.

The pattern generation unit 241 is the same as the pattern generation unit 141 of the first embodiment, and includes an FF 141A and an inverter 141B.

Since the pattern generation unit 241 alternately outputs “1” and “0” every time the clock BCK is input, the test data td0 generated by the pattern generation unit 241 alternates between “1” and “0”. It will be repeated data.

In addition to the delay units 171A, 171B, 171C, FFs 172A, 172B, 172C, EOR (exclusive OR) circuits 173A, 173B, the determination unit 244 includes delay units 271A, 271B, FFs 272A, 272B, EOR circuits 273A, 273B, And OR circuits 274A, 274B, 274C.

Among these, the connection relationship of the delay units 171A, 171B, FFs 172A, 172B, 172C, and EOR (exclusive OR) circuits 173A, 173B is the same as that of each component of the determination unit 144 of the first embodiment. However, the delay unit 171C is different from the delay unit 171C of the determination unit 144 of Embodiment 1 in that the delay unit 171C is connected to the data output terminal Q of the FF 141 via the delay unit 271B.

The delay time of the delay unit 171C is the same as the delay time given to the test data td0 in order to realize the worst case time (hold worst) of the hold time of the FFs 113C and 113D of the core 110 together with the delay time of the delay unit 271B. It is set to be.

The FF 172A is different from the FF 172A of the first embodiment in that the data output terminal Q is connected to one input terminal of the EOR circuit 173A and the other input terminal of the EOR circuit 273A.

The FF 172C is different from the FF 172C of the first embodiment in that the data output terminal Q is connected to the other input terminal of the EOR circuit 173C and one input terminal of the EOR circuit 273B.

The EOR circuit 173A is different from the EOR circuit 173A of Embodiment 1 in that an output terminal is connected to the other input terminal of the OR circuit 274A and one input terminal of the OR circuit 274B.

The EOR circuit 173B is different from the EOR circuit 173A of Embodiment 1 in that an output terminal is connected to the other input terminal of the OR circuit 274B and one input terminal of the OR circuit 274C.

The delay unit 271A has an input terminal connected to the output terminal of the delay unit 171A and an output terminal connected to the data input terminal D of the FF 272A. The delay time in the delay unit 271A is a delay time given to the test data td0 in order to realize a caution setup time (setup warning) having a predetermined phase difference larger than the worst case setup time (setup worst).

When a delay time obtained by adding the delay time in the delay unit 271A to the delay time in the delay unit 171A is given to the test data td0, a setup time for warning (setup warning) is realized. The delay units 171A and 271A are an example of a first preliminary delay unit.

The delay unit 271B has an input terminal connected to the data output terminal Q of the FF 141A of the pattern generation unit 241, and an output terminal connected to the input terminal of the delay unit 171C and the data input terminal D of the FF 272B. The delay unit 271B is an example of a second preliminary delay unit.

The delay time in the delay unit 271B is a delay time given to the test data td0 in order to realize a hold time for attention (hold warning).

When the time obtained by adding the delay time of the delay unit 171C to the delay time in the delay unit 271B is given to the test data td0, the worst case hold time (hold worst) is set to be actually supplied. Therefore, in the second embodiment, the delay units 171C and 271B are an example of the second delay unit.

The ratio between the delay time in the delay unit 271B and the delay time in the delay unit 171C is set to 1: 2, for example. This ratio can be set to an arbitrary ratio in accordance with the circuit characteristics of the synchronous data processing circuit.

In the FF 272A, the data input terminal D is connected to the output terminal of the delay unit 271A, the data output terminal Q is connected to one input terminal of the EOR circuit 273A, and the clock CCK is input to the clock input terminal. The output data of FF272A is represented as sw0.

In the FF 272B, the data input terminal D is connected to the output terminal of the delay unit 271B, the data output terminal Q is connected to one input terminal of the EOR circuit 273B, and the clock CCK is input to the clock input terminal. The output data of FF272B is represented as hw0.

In the EOR circuit 273A, the data output terminal Q of the FF 272A is connected to one input terminal, and the data output terminal Q of the FF 172A is connected to the other input terminal.

In the EOR circuit 273B, the data output terminal Q of the FF 172C is connected to one input terminal, and the data output terminal Q of the FF 272B is connected to the other input terminal.

The OR circuit 274A has one input terminal connected to the output terminal of the EOR circuit 273A and the other input terminal connected to the output terminal of the EOR circuit 173A. The OR circuit 274A outputs the logical sum of the outputs of the EOR circuits 273A and 173A as a delay control command up0.

The OR circuit 274B has one input terminal connected to the output terminal of the EOR circuit 173A and the other input terminal connected to the output terminal of the EOR circuit 173B. The OR circuit 274B outputs the logical sum of the outputs of the EOR circuits 173A and 173B as the freeze signal frz0.

The OR circuit 274C has one input terminal connected to the output terminal of the EOR circuit 173B and the other input terminal connected to the output terminal of the EOR circuit 273B. The OR circuit 274C outputs the logical sum of the outputs of the EOR circuits 173B and 273B as a delay control command dwn0.

Note that the circuit configurations of the pattern generation unit 242 and the determination unit 243 of the synchronization determination unit 240 are the same as those of the pattern generation unit 142 and the determination unit 143 of the first embodiment, but are the delay units 271A, 271B, FF272A, 272B, and the EOR circuits 273A, 273B. , And OR circuits 274A, 274B, 274C.

In the pattern generation unit 242 and the determination unit 243, the clock BCK is input to the pattern generation unit 242, and the clock CCK is input to the determination unit 243.

The determination unit 243 outputs output data sw1, sd1, nd1, hd1, and hw1 from five FFs corresponding to the FFs 272A, 173A, 173B, 173C, and 272B, respectively.

The determination unit 243 outputs a delay control command dwn1, a freeze signal frz1, and a delay control command up1 from the three OR circuits corresponding to the OR circuits 274A, 274B, and 274C, respectively. For this reason, illustration of the circuit configurations of the pattern generation unit 242 and the determination unit 243 is omitted here.

In FIG. 15, the configuration in which the delay unit 271A is connected to the output terminal of the delay unit 171A has been described. However, instead of the delay unit 271A, a delay unit having a delay time obtained by combining the delay times of the delay units 271A and 171A is used. You may connect between the data input terminal D of FF272A, and the data output terminal Q of FF141A.

In addition, although the configuration in which the delay unit 171C is connected to the output terminal of the delay unit 271B has been described, instead of the delay unit 171C, a delay unit having a delay time that is the sum of the delay times of the delay units 171C and 271B You may connect between the terminal D and the data output terminal Q of FF141A.

Next, operations of the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 will be described with reference to FIG.

FIG. 16 is a timing chart illustrating an operation example of the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 of the synchronous data processing circuit according to the second embodiment.

FIG. 16 shows clocks BCK, CCK, test data td0, output data (setup warning) of the delay unit 271A, output data (setup worst) of the delay unit 171A, output data (nominal) of the delay unit 171B, and the delay unit 171C. Output data (hold worst) and output data (hold warning) of the delay unit 271B are shown. FIG. 16 further shows output data sd0, nd0, hd0 and delay control commands up0, dwn0 of the FFs 172A to 172C.

Here, the output data (setup warning) of the delay unit 271A is data obtained by delaying the test data td0 by the delay units 171A and 271A. The output data (setup worst) of the delay unit 171A is data obtained by delaying the test data td0 by the delay unit 171A. The output data (nominal) of the delay unit 171B is data obtained by delaying the test data td0 by the delay unit 171B. The output data (hold worst) of the delay unit 171C is data obtained by delaying the test data td0 by the delay units 271B and 171C. The output data (hold warning) of the delay unit 271B is data obtained by delaying the test data td0 by the delay unit 271B.

The delay time given to the test data td0 is indicated by an arrow in FIG.

FIG. 16A is a timing chart in a state where data is synchronously transferred from the bus 120 to the core 110.

As shown in FIG. 16A, when the phases of the clocks BCK and CCK are equal, the rising phase of the test data td0 output from the pattern generator 241 is equal to the rising phase of the clock CCK.

In this case, the rise of the output data (hold warning) of the delay unit 271B is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured, so the output hw0 of the FF 272B is the time At t1, the L level is equal to the test data td0.

The rise of the output data (hold worst) of the delay unit 171C is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured, so the output hd0 of the FF 172C is at time t1. The L level is equal to the test data td0.

Also, the output data (nominal) of the delay unit 171B is sufficiently later than the rising edge of the clock CCK at time t1, and the output nd0 of the FF 172B is at the L level equal to the test data td0 at time t1.

The rise of the output data (setup worst) of the delay unit 171A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sd0 of the FF 172A is at time t1. The L level is equal to the test data td0.

Further, the rise of the output data (setup warning) of the delay unit 271A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sw0 of the FF 172A is at time t1. The L level is equal to the test data td0.

Therefore, since the outputs of the EOR circuits 273A, 173A, 173B, 273B are all “0”, the delay control commands up0, dwn0 and the freeze signal frz0 are all at the L level.

Next, as shown in FIG. 16B, when the clock CCK input to the determination unit 244 on the core 110 side is slightly delayed from the clock BCK input to the pattern generation unit 241 on the bus 120 side. Will be described. This case corresponds to a case where the clock CCK is delayed due to a drop in the supply voltage to the core 110 due to DVFS.

As shown in FIG. 16B, when the phase of CCK is delayed with respect to the clock BCK, the rising timing of the clock CCK at the time t1 is the rising edge of the test data td0 output from the pattern generator 241. It is behind the timing.

In this case, the rise of the output data (hold warning) of the delay unit 271B is before the rise of the clock CCK at time t1 (timing violated), and the output data of the delay unit 271B is already at the rise of time t1 of the clock CCK. (Hold warning) is at the H level. This is a case one step before the hold time is insufficient.

Therefore, the L level of the output data (hold warning) of the delay unit 271B cannot be acquired, and the output hw0 of the FF 272B becomes an H level different from the test data td0 at time t1.

Further, the rise of the output data (hold worst) of the delay unit 171C is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured, so the output hd0 of the FF 172C is at time t1. The L level is equal to the test data td0.

Also, the rise of the output data (nominal) of the delay unit 171B is sufficiently later than the rise of the clock CCK at time t1, and the output nd0 of the FF 172B is at L level equal to the test data td0 at time t1.

The rise of the output data (setup worst) of the delay unit 171A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sd0 of the FF 172A is at time t1. The L level is equal to the test data td0.

The rise of the output data (setup （warning) of the delay unit 271A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sw0 of the FF 272A is at time t1. The L level is equal to the test data td0.

For this reason, the outputs of the EOR circuits 273A, 173A, 173B all become “0”, and only the output of the EOR circuit 273B becomes “1”, so that the delay control command up0 and the freeze signal frz0 are at the L level. Delay control command dwn0 is at the H level.

Therefore, an H level delay control command dwn0 is output from the determination unit 244 in order to advance the phase of the clock CCK.

In this case, data from the bus 120 to the core 110 is transferred synchronously.

Next, as shown in FIG. 16C, the clock CCK input to the determination unit 244 on the core 110 side is compared with the clock BCK input to the pattern generation unit 241 on the bus 120 side. The case where it is further delayed than the case shown in FIG. This case corresponds to a case where the clock CCK is delayed due to a further drop in the supply voltage to the core 110 as compared to the case shown in FIG.

As shown in FIG. 16C, when the phase of the CCK is delayed with respect to the clock BCK, the rising timing of the clock CCK at the time t1 is the rising timing of the test data td0 output from the pattern generator 241. It is behind the timing.

In this case, the rise of the output data (hold warning) of the delay unit 271B is before the rise of the clock CCK at time t1 (timing violated), and the output data of the delay unit 271B is already at the rise of time t1 of the clock CCK. (Hold warning) is at the H level.

Therefore, the L level of the output data (hold warning) of the delay unit 271B cannot be acquired, and the output hw0 of the FF 272B becomes an H level different from the test data td0 at time t1.

The rise of the output data (hold worst) of the delay unit 171C is before the rise of the clock CCK at time t1 (timing violated), and the output data (hold) of the delay unit 271B has already been reached at the rise of the clock CCK at time t1. warning) is at the H level. This is a case where the hold time is insufficient.

Therefore, the L level of the output data (hold warning) of the delay unit 271B cannot be acquired, and the output hw0 of the FF 272B becomes an H level different from the test data td0 at time t1.

Also, the rise of the output data (nominal) of the delay unit 171B is sufficiently later than the rise of the clock CCK at time t1, and the output nd0 of the FF 172B is at L level equal to the test data td0 at time t1.

The rise of the output data (setup worst) of the delay unit 171A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sd0 of the FF 172A is at time t1. The L level is equal to the test data td0.

The rise of the output data (setup （warning) of the delay unit 271A is before the rise of the clock CCK at time t2 (timing met), and the setup time is secured, so the output sw0 of the FF 272A is at time t1. The L level is equal to the test data td0.

Therefore, the outputs of the EOR circuits 273A, 173A, 273B all become “0”, and only the output of the EOR circuit 173B becomes “1”, so that the delay control command up0 is at the L level. The freeze signal frz0 and the delay control command dwn0 are at the H level.

Accordingly, an H level delay control command dwn0 is output from the determination unit 244 in order to advance the phase of the clock CCK, and at the H level, the FFs 113A to 113D and 123A to 123D are fixed to freeze the data transfer. A freeze signal frz is output.

FIG. 17 is a timing chart illustrating an operation example of the pattern generation unit 241 and the determination unit 244 of the synchronization determination unit 240 of the synchronous data processing circuit according to the second embodiment.

FIG. 17 shows clocks BCK, CCK, test data td0, output data (setup warning) of delay unit 271A, output data (setup worst) of delay unit 171A, output data (nominal) of delay unit 171B, and output of delay unit 171C. Data (hold worst) and output data (hold warning) of the delay unit 271B are shown. FIG. 17 further shows output data sd0, nd0, hd0 and delay control commands up0, dwn0 of the FFs 172A to 172C.

FIG. 17A is a timing chart in a state where data is synchronously transferred from the bus 120 to the core 110.

As shown in FIG. 17A, when the phases of the clocks BCK and CCK are equal, the rising phase of the test data td0 output from the pattern generator 241 is equal to the rising phase of the clock CCK at time t1. The case shown in FIG. 17A is the same as the case shown in FIG.

Therefore, since the outputs of the EOR circuits 273A, 173A, 173B, 273B are all “0”, the delay control commands up0, dwn0 and the freeze signal frz0 are all at the L level.

Next, as shown in FIG. 17B, the clock CCK input to the determination unit 244 on the core 110 side is slightly advanced with respect to the clock BCK input to the pattern generation unit 241 on the bus 120 side. Will be described. This case corresponds to the case where the clock CCK is advanced by raising from the state where the supply voltage to the core 110 has been lowered by DVFS.

As shown in FIG. 17B, when the phase of the CCK is advanced with respect to the clock BCK, the rising timing of the clock CCK at the time t1 is the rising edge of the test data td0 output from the pattern generator 241. More advanced than timing.

In this case, the rise of the output data (hold warning) of the delay unit 271B is later than the rise of the clock CCK just before the rise of the clock CCK at time t1 (timing met), and the hold time is secured. The H level of the output data (hold warning) of the delay unit 271B is acquired at the rising edge of the clock CCK at time t1. For this reason, the output hd0 of the FF 272B becomes H level equal to the test data td0 at time t1.

The rise of the output data (hold worst) of the delay unit 171C is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured, so that the clock The H level of the output data (hold worst) of the delay unit 171C is acquired at the rising edge of time C1 of CCK. Therefore, the output hd0 of the FF 172C becomes H level equal to the test data td0 at time t1.

Also, the rise of the output data (nominal) of the delay unit 171B is sufficiently before the rise of the clock CCK at time t1, and the output nd0 of the FF 172B becomes H level equal to the test data td0 at time t1.

The rise of the output data (setup worst) of the delay unit 171A is before the rise of the clock CCK at time t1 (timing met), and the setup time is secured, so the clock CCK rises at time t1. At that time, it is switched to the H level. Therefore, the output sd0 of the FF 172A is held at the H level equal to the test data td0 at time t1.

The rising edge of the output data (setup warning) of the delay unit 271A is later than the rising edge of the clock CCK at time t1 (timing violated). When the clock CCK rises at time t1, it has not been switched to the H level. However, it remains at the L level. Therefore, the output sw0 of the FF 272A is held at the L level different from the test data td0 at time t1.

As described above, the outputs of the EOR circuits 173A, 173B, and 273B all become “0”, and only the output of the EOR circuit 273A becomes “1”, so that the delay control command up0 is at the H level. The freeze signal frz0 and the delay control command dwn0 are at the L level.

Therefore, an H-level delay control command up0 is output from the determination unit 244 in order to delay the phase of the clock CCK.

In this case, data from the bus 120 to the core 110 is transferred synchronously.

Next, as shown in FIG. 17C, the clock CCK input to the determination unit 244 on the core 110 side is compared with the clock BCK input to the pattern generation unit 241 on the bus 120 side. A case where the process is further advanced than the case shown in FIG. This case corresponds to the case where the clock CCK is advanced from the state in which the supply voltage to the core 110 has been lowered by DVFS and further increased from the case shown in FIG.

As shown in FIG. 17C, when the phase of the CCK is advanced with respect to the clock BCK, the rising timing of the clock CCK at time t1 is the rising timing of the test data td0 output from the pattern generator 241. More advanced than timing.

In this case, the rise of the output data (hold warning) of the delay unit 271B is later than the rise of the clock CCK just before the rise of the clock CCK at time t1 (timing met), and the hold time is secured. The H level of the output data (hold warning) of the delay unit 271B is acquired at the rising edge of the clock CCK at time t1. For this reason, the output hd0 of the FF 272B becomes H level equal to the test data td0 at time t1.

The rise of the output data (hold worst) of the delay unit 171C is later than the rise of the clock CCK at time t1 (timing met), and the hold time is secured, so that the clock The H level of the output data (hold worst) of the delay unit 171C is acquired at the rising edge of time C1 of CCK. Therefore, the output hd0 of the FF 172C becomes H level equal to the test data td0 at time t1.

Also, the rise of the output data (nominal) of the delay unit 171B is sufficiently before the rise of the clock CCK at time t1, and the output nd0 of the FF 172B becomes H level equal to the test data td0 at time t1.

The rising edge of the output data (setup worst) of the delay unit 171A is later than the rising edge of the clock CCK at time t1 (timing violated), and when the clock CCK rises at time t1, it has not switched to the H level. However, it remains at the L level. This is a case where the setup time constraint is violated. Therefore, the output sd0 of the FF 172A is held at the L level different from the test data td0 at time t1.

The rise of the output data (setup warning) of the delay unit 271A is later than the rise of the clock CCK at time t1 (timing violated), and when the clock CCK rises at time t1, it has not switched to the H level. However, it remains at the L level. Therefore, the output sw0 of the FF 272A is held at the L level different from the test data td0 at time t1.

From the above, since the outputs of the EOR circuits 273A, 173B, 273B all become “0” and only the output of the EOR circuit 173A becomes “1”, the delay control command up0 and the freeze signal frz0 are at the H level. Delay control command dwn0 is at the L level.

Accordingly, an H level delay control command up0 is output from the determination unit 244 in order to delay the phase of the clock CCK, and at the H level, the FFs 113A to 113D and 123A to 123D are fixed to freeze the data transfer. A freeze signal frz0 is output.

As described above, the determination unit 244 determines that the determination unit 244 has a worst hold time although the clock CCK input to the determination unit 244 is delayed with respect to the clock BCK input to the pattern generation unit 241. If the time has not been reached and the caution hold time has been reached, an H level delay control command dwn0 is output to advance the phase of the clock CCK. In this case, since it is a caution level, data from the bus 120 to the core 110 is synchronously transferred.

In addition, the determination unit 244 determines that the clock CCK input to the determination unit 244 is delayed with respect to the clock BCK input to the pattern generation unit 241, and the clock CCK is input when the hold time reaches the worst hold time. Output the delay control command dwn at the H level. In this case, the determination unit 244 outputs the H level freeze signal frz0 in order to freeze the data transfer with the FFs 113A to 113D and 123A to 123D fixed.

In addition, the determination unit 244 uses a clock CCK input to the determination unit 244 that is advanced with respect to the clock BCK input to the pattern generation unit 241, but the setup time has not reached the worst setup time. When the set-up time is reached, an H-level delay control command up0 is output to delay the phase of the clock CCK. In this case, since it is a caution level, data from the bus 120 to the core 110 is synchronously transferred.

In addition, the determination unit 244 advances the clock CCK when the clock CCK input to the determination unit 244 advances with respect to the clock BCK input to the pattern generation unit 241 and the hold time reaches the worst hold time. In order to delay the phase of H, the H level delay control command up0 is output. In this case, the determination unit 244 outputs the H level freeze signal frz0 in order to freeze the data transfer with the FFs 113A to 113D and 123A to 123D fixed.

The determination unit 244 obtains the output data (hold （worst) of the delay unit 171C and the output data (setup worst) of the delay unit 171A equally and correctly with the output data (nominal) of the delay unit 171B. Both output L level delay control commands up0 and dwn0.

Next, the operation when returning from the state in which the FFs 113A to 113D and 123A to 123D are fixed by the H level freeze signal frz will be described with reference to FIG.

FIG. 18 is a timing chart showing an operation in the case of returning from the state in which the FFs 113A to 113D and 123A to 123D are fixed by the freeze signal frz in the synchronous data processing circuit of the second embodiment.

FIG. 18 shows the clock Bus_CKin input to the bus 120, the Core_CKin input to the core 110, and the clocks BCK and CCK. A freeze signal frz, clocks BCK1, CCK1, and transfer data are shown.

When the freeze signal frz becomes H level at time t1, the clock BCK1 and the clock CCK1 are held at L level. As a result, the data in the FFs 113A to 113D and 123A to 123D are frozen, and the data transfer state is switched from the state where the synchronous transfer is performed to the state where the data transfer is frozen.

However, at this time, the phase of the clock CCK1 is continuously adjusted by the delay control command up or dwn.

At time t2, the freeze signal frz returns to the L level. The freeze signal frz returns to the L level when the phase of the clock CCK1 returns to some extent and the phase difference from the clock BCK1 returns to the caution level. That is, for example, when the state shown in FIG. 16C returns to the state shown in FIG. 16B, or when the state shown in FIG. 17C returns to the state shown in FIG. 17B. Applicable.

At a later time t3, the clock BCK1 and the clock CCK1 are restored, and the data transfer state is restored from the state where the data transfer is frozen to the state where the synchronous transfer is performed.

As described above, in the synchronous data processing circuit of the second embodiment, when the data cannot be transferred synchronously, the data of the FFs 113A to 113D and 123A to 123D are frozen, but the phase of the clock CCK returns to the caution level after freezing. Then, release the data freeze and restore the operation.

For this reason, it is possible to provide a synchronous data processing circuit capable of stably performing synchronous transfer of data between the core 110 and the bus 120.

The synchronous data processing circuit and the portable terminal according to the exemplary embodiment of the present invention have been described above. However, the present invention is not limited to the specifically disclosed embodiment, and is claimed. Various modifications and changes can be made without departing from the scope.

DESCRIPTION OF SYMBOLS 10 Smartphone terminal 20 Application processing part 30 Modem part 41 User interface 42 System controller 43 LCD
44 battery 50 application processor 60 baseband module 70 baseband processor 80 RF module 100 synchronous data processing circuit 110A, 110B core 120 bus 130A, 130B variable delay unit 140A, 140B synchronization determination unit 150 fixed delay unit 160 PLL
212A, 212B, 222A, 222B Gate lock buffer 240 Synchronization determination unit 241 Pattern generation unit 242 Determination unit 243 Pattern generation unit 244 Determination unit 245 Output unit

Claims (13)

A first circuit driven at a constant voltage based on a clock output from a clock generation source;
A second circuit for changing the driving voltage and synchronously transferring data to or from the first circuit based on a clock output from the clock generation source;
A delay adjusting unit for adjusting a delay amount of a clock input to the first circuit or the second circuit;
A test data generation unit for generating test data transferred between the first circuit and the second circuit;
A determination unit that determines the transferred test data and adjusts a delay amount in the delay adjustment unit based on a determination result indicating whether or not the test data is synchronously transferred. A plurality of the second circuits and the plurality of delay adjustment units are included, and each of the plurality of delay adjustment units is disposed in each of the plurality of second circuits and is input to each of the plurality of second circuits. The synchronous data processing circuit according to claim 1, wherein a delay amount of a clock to be adjusted is adjusted. The test data generation unit is provided on the first circuit side, the determination unit is provided on the second circuit side, and the test data generated by the test data generation unit is transmitted from the first circuit side to the second circuit. Transferred to the circuit side,
The determination unit includes a first delay unit having a delay time for realizing a worst-case setup time of the second circuit, and when the test data delayed by the first delay unit is not synchronously transferred, the delay The synchronous data processing circuit according to claim 1, wherein the delay amount in the adjustment unit is increased. The determination unit further includes a first preliminary delay unit having a delay time longer than a delay time of the first delay unit by a first margin delay time, and the test data delayed by the first preliminary delay unit is synchronized. 4. When not transferred, the delay amount in the delay adjustment unit is increased, and when the test data delayed by the first delay unit is not transferred synchronously, the first circuit and the second circuit are frozen. The synchronous data processing circuit described. The determination unit includes a second delay unit having a delay time that realizes a worst-case hold time of the second circuit, and when the test data delayed by the second delay unit is not transferred synchronously, the delay The synchronous data processing circuit according to claim 1, wherein a delay amount in the adjustment unit is reduced. The determination unit further includes a second preliminary delay unit having a delay time shorter by a second margin delay time than a delay time of the second delay unit, and the test data delayed by the second preliminary delay unit is synchronized 6. When not transferred, the delay amount in the delay adjustment unit is decreased, and when the test data delayed by the second delay unit is not transferred synchronously, the first circuit and the second circuit are frozen. The synchronous data processing circuit described. The test data generation unit is provided on the second circuit side, the determination unit is provided on the first circuit side, and the test data generated by the test data generation unit is transmitted from the second circuit side to the first circuit. Transferred to the circuit side,
The determination unit includes a first delay unit having a delay time for realizing a worst-case setup time of the first circuit, and when the test data delayed by the first delay unit is not transferred synchronously, the delay The synchronous data processing circuit according to claim 1, wherein the amount of delay in the adjustment unit is reduced. The determination unit further includes a first preliminary delay unit having a delay time longer than a delay time of the first delay unit by a first margin delay time, and the test data delayed by the first preliminary delay unit is synchronized. 8. If not transferred, the delay amount in the delay adjusting unit is reduced, and if the test data delayed by the first delay unit is not transferred synchronously, the first circuit and the second circuit are frozen. The synchronous data processing circuit described. The determination unit includes a second delay unit having a delay time that realizes a worst-case hold time of the first circuit, and when the test data delayed by the second delay unit is not transferred synchronously, the delay The synchronous data processing circuit according to claim 1, wherein the delay amount in the adjustment unit is increased. The determination unit further includes a second preliminary delay unit having a delay time shorter by a second margin delay time than a delay time of the second delay unit, and the test data delayed by the second preliminary delay unit is synchronized When the data is not transferred, the delay amount in the delay adjustment unit is decreased or increased, and when the test data delayed by the second delay unit is not transferred synchronously, the first circuit and the second circuit are frozen. Item 10. A synchronous data processing circuit according to Item 9. A fixed delay that gives a predetermined fixed delay amount to a clock that is input to a circuit that is opposite to a circuit that receives a clock whose delay amount is adjusted by the delay adjustment unit, of the first circuit or the second circuit. The synchronous transfer circuit according to claim 1, further comprising a unit. The data is synchronously transferred in both directions between the first circuit and the second circuit,
The test data generation unit
A first test data generation unit for generating first test data based on a clock used by the first circuit;
A second test data generation unit that generates second test data based on a clock used by the second circuit,
The determination unit
A first determination unit that determines a phase of the first test data and adjusts a delay amount in the delay adjustment unit based on a determination result;
The synchronous data processing circuit according to claim 1, further comprising: a second determination unit that determines a phase of the second test data and adjusts a delay amount in the delay adjustment unit based on a determination result. A processor having the synchronous data processing circuit according to any one of claims 1 to 12,
And a variable voltage supply unit that varies a drive voltage supplied to the second circuit of the synchronous data processing circuit.

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