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WO2013100085A1 - Élément de cellule solaire, procédé de fabrication d'élément de cellule solaire, et module de cellule solaire - Google Patents

Élément de cellule solaire, procédé de fabrication d'élément de cellule solaire, et module de cellule solaire Download PDF

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Publication number
WO2013100085A1
WO2013100085A1 PCT/JP2012/083957 JP2012083957W WO2013100085A1 WO 2013100085 A1 WO2013100085 A1 WO 2013100085A1 JP 2012083957 W JP2012083957 W JP 2012083957W WO 2013100085 A1 WO2013100085 A1 WO 2013100085A1
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Prior art keywords
solar cell
layer
passivation layer
cell element
main surface
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English (en)
Japanese (ja)
Inventor
彰了 村尾
伊藤　憲和
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar cell element, a method for manufacturing a solar cell element, and a solar cell module including the solar cell element.
  • a passivation film is provided on the surface of the silicon substrate in order to reduce minority carrier recombination.
  • the passivation film use of an oxide film made of silicon oxide, aluminum oxide, or the like, or a nitride film made of a silicon nitride film or the like has been studied (see, for example, JP-A-2009-164544).
  • the solar cell elements having the above-described configuration may not be improved enough to contribute to power generation efficiency. Therefore, a solar cell element, a manufacturing method thereof, and a solar cell module in which output characteristics are further improved by reducing carrier recombination are desired.
  • a solar cell element has an n-type semiconductor region on a first main surface, and a second main surface located on the side opposite to the first main surface.
  • an antireflection layer having a fixed charge density larger than that of the first passivation layer on the positive side.
  • a solar cell element has an n-type semiconductor region on a first main surface, and a p-type semiconductor region on a second main surface located on the opposite side to the first main surface.
  • a semiconductor substrate made of silicon and having a first passivation layer which is disposed on the n-type semiconductor region and is made of at least one selected from aluminum oxide, hafnium oxide and zirconium oxide, and It may be provided with an antireflection layer made of silicon oxide or silicon nitride disposed on one passivation layer.
  • the first main surface has an n-type semiconductor region
  • the second main surface located on the side opposite to the first main surface is p.
  • a solar cell module includes the solar cell element having the above-described configuration.
  • FIG. 2 is a schematic view showing an example of a solar cell element according to an embodiment of the present invention, and is a cross-sectional view taken along line AA in FIG. It is the plane schematic diagram which looked at an example of the solar cell element concerning one form of the present invention from the 2nd principal surface side.
  • ⁇ Basic configuration of solar cell element> 1 to 3 show a solar cell element 10 according to the present embodiment.
  • the solar cell element 10 has an n-type semiconductor region on the first main surface 10a, and a semiconductor having a p-type semiconductor region on the second main surface 10b located on the opposite side of the first main surface 10a.
  • the basic configuration is that the antireflection layer 5 having a fixed charge density larger on the positive side than the layer 8 is provided.
  • the solar cell element 10 has an n-type semiconductor region on the first main surface 10a, and has a p-type semiconductor region on the second main surface 10b located on the opposite side to the first main surface 10a.
  • a semiconductor substrate 1 made of silicon, a first passivation layer 8 disposed on the n-type semiconductor region and made of at least one selected from aluminum oxide, hafnium oxide and zirconium oxide, and a first passivation layer
  • an antireflection layer 5 made of silicon oxide or silicon nitride.
  • the solar cell element 10 includes a light receiving surface (a top surface in FIG. 3 and hereinafter referred to as a first main surface) 10a on which light is incident, and the first main surface 10a. It has a non-light-receiving surface (a lower surface in FIG. 3, hereinafter referred to as a second main surface) 10b corresponding to a surface (back surface) located on the opposite side, and a side surface 10c.
  • the solar cell element 10 includes a semiconductor substrate 1 which is a plate-like polycrystalline silicon substrate, for example.
  • the semiconductor substrate 1 is provided, for example, on the first semiconductor layer 2 that is a one-conductivity type semiconductor region (p-type semiconductor region) and on the first main surface 10 a side in the first semiconductor layer 2. And a second semiconductor layer 3 which is a reverse conductivity type semiconductor region (n-type semiconductor region).
  • the solar cell element 10 is disposed on the second semiconductor layer 3 (specifically, on the first main surface 10a side of the second semiconductor layer 3), and the first passivation layer 8 made of aluminum oxide or the like.
  • an antireflection layer 5 made of silicon nitride, for example, on the first passivation layer 8.
  • the solar cell element 10 is disposed on the first semiconductor layer 2 (specifically, on the second main surface 10b side of the first semiconductor layer 2), and the second passivation layer 9 made of aluminum oxide or the like. It has.
  • the solar cell element 10 includes a semiconductor substrate 1 (first semiconductor layer 2 and second semiconductor layer 3), a third semiconductor layer 4, an antireflection layer 5, a first electrode 6, A second electrode 7, a first passivation layer 8 and a second passivation layer 9 are provided.
  • the semiconductor substrate 1 is a polycrystalline silicon substrate, and includes the first semiconductor layer 2 and the second semiconductor layer 3 provided on the first main surface 10a side of the first semiconductor layer 2. .
  • the first semiconductor layer 2 As the first semiconductor layer 2, as described above, a plate-like semiconductor exhibiting a p-type can be used.
  • a polycrystalline silicon substrate As the semiconductor constituting the first semiconductor layer 2, a polycrystalline silicon substrate can be used.
  • the average thickness of the first semiconductor layer 2 can be, for example, 250 ⁇ m or less, and further 150 ⁇ m or less.
  • the shape of the 1st semiconductor layer 2 is not specifically limited, From a viewpoint on a manufacturing method, it is good also as a square shape by planar view. If the first semiconductor layer 2 made of a polycrystalline silicon substrate is p-type, for example, boron or gallium can be used as the dopant element.
  • the second semiconductor layer 3 is a semiconductor layer that forms a pn junction with this and the first semiconductor layer 2.
  • the second semiconductor layer 3 is a layer having a conductivity type opposite to that of the first semiconductor layer 2, that is, an n-type, and is provided on the first main surface 10 a side in the first semiconductor layer 2.
  • the second semiconductor layer 3 can be formed by diffusing impurities such as phosphorus on the first main surface 10a side of the silicon substrate.
  • a pyramidal uneven shape 1 a is provided on the first main surface 10 a side of the semiconductor substrate 1.
  • the height of the convex portion of the concavo-convex shape 1a is about 0.1 to 10 ⁇ m, and the width of the convex portion is about 0.1 to 20 ⁇ m.
  • the shape of the concavo-convex shape 1a is not limited to the pyramid shape, and may be a concavo-convex shape in which the concave portion is substantially spherical.
  • the height of the convex portion here refers to, for example, a straight line passing through the bottom surface of the concave portion in the cross-sectional view of FIG. 3, and from the reference line to the top surface of the convex portion in a direction perpendicular to the reference line. Is the distance.
  • the width of the convex portion is a distance between the top surfaces of adjacent convex portions in a direction parallel to the reference line.
  • the first passivation layer 8 is formed on the first main surface 10a side of the semiconductor substrate 1.
  • the first passivation layer 8 is composed of a layer containing at least one selected from aluminum oxide, hafnium oxide, and zirconium oxide.
  • the first passivation layer 8 can be an aluminum oxide layer, a hafnium oxide layer, or a zirconium oxide layer.
  • the n-type second semiconductor layer 3 has minority carriers (holes) at the interface with the first passivation layer. ) The band near the interface bends in the direction of rising. This has the problem of increased surface recombination.
  • the antireflection layer 5 that is larger on the positive side than the negative fixed charge density of this layer is formed.
  • the antireflection layer 5 having a large fixed charge density on the positive side is the antireflection layer 5 having a positive fixed charge density or the antireflection layer 5 having a negative fixed charge density smaller than that of the first passivation layer 8.
  • the average thickness of the first passivation layer 8 can be about 30 to 1000 mm, for example.
  • the antireflection layer 5 is formed of, for example, a silicon nitride layer or a silicon oxide layer.
  • the thickness of the antireflection layer 5 can be appropriately selected depending on the type of material, and may be a thickness that can realize non-reflection conditions with respect to appropriate incident light.
  • the antireflective layer 5 can have a refractive index of about 1.8 to 2.3 and an average thickness of about 200 to 1200 mm.
  • the fixed charge density of the aluminum oxide layer is about ⁇ 1 ⁇ 10 11 to ⁇ 1 ⁇ 10 13 cm ⁇ 2 , and the fixed charge densities of hafnium oxide and zirconium oxide are ⁇ 1 ⁇ 10 11 to ⁇ 5 ⁇ 10 12 cm ⁇ 2.
  • the fixed charge density of the silicon nitride layer is about + 1 ⁇ 10 12 cm ⁇ 2 , and the fixed charge density of the silicon oxide layer is about + 6 ⁇ 10 10 cm ⁇ 2 .
  • the fixed charge density of the passivation layer can be calculated by, for example, a capacitance-voltage measurement method (CV measurement method).
  • an aluminum electrode is disposed on the passivation layer disposed on the surface of the semiconductor substrate, and an aluminum electrode disposed on the back surface of the semiconductor substrate is disposed and applied by changing within a certain range between the aluminum electrodes. It can be calculated from a CV characteristic curve obtained by measuring each capacity at each voltage.
  • the second passivation layer 9 is formed on the second main surface 10b side of the semiconductor substrate 1.
  • the second passivation layer 9 is composed of a layer containing one or more selected from aluminum oxide, hafnium oxide and zirconium oxide. According to the said structure, the open circuit voltage is high and the solar cell element excellent in output characteristics can be obtained. This is presumably because surface recombination could be reduced by the surface passivation effect.
  • the aluminum oxide layer, the hafnium oxide layer, and the zirconium oxide layer all have a negative fixed charge density
  • the semiconductor substrate 1 At the interface between the first semiconductor layer 2) and the second passivation layer 9, the band near the interface is bent in the direction in which minority carriers (electrons) decrease, so that surface recombination can be further reduced.
  • the average thickness of the second passivation layer 9 can be about 30 to 1000 mm, for example.
  • the first passivation layer 8 and the second passivation layer 9 are mainly made of an amorphous aluminum oxide layer, for example, so that a large amount of hydrogen is contained in the aluminum oxide, and hydrogen is easily diffused into the semiconductor substrate. Become.
  • the above “mainly amorphous aluminum oxide layer” means that the crystallization rate in the aluminum oxide layer is less than 50%.
  • the dangling bonds are terminated with hydrogen due to the presence of the aluminum oxide layer, and surface recombination can be further reduced.
  • the crystalline aluminum oxide layer tends to grow perpendicular to the growth interface. Therefore, when using a substrate having a grain boundary and a crystal grain having a different crystal orientation such as a polycrystalline silicon substrate, the growth interface of the crystalline aluminum oxide layer has a grain boundary and crystal orientation of the substrate surface. It is easily affected and the growth interface of the aluminum oxide layer tends to have a random direction.
  • the semiconductor substrate 1 when a polycrystalline silicon substrate is used as the semiconductor substrate 1, an amorphous aluminum oxide layer is mainly used. Under the influence of crystal grain boundaries and crystal orientations on the surface of the polycrystalline silicon substrate, the crystalline aluminum oxide layer grows in random directions, and the crystal grains that have started to interfere with each other cause this interference. It is possible to reduce the occurrence of defects on the surface. As a result, the first passivation layer 8 and the second passivation layer 9 can have an excellent passivation effect.
  • the average thickness of the first passivation layer 8 thinner than the average thickness of the antireflection film layer 5, it is possible to reduce the loss of light due to reflection, and to reduce the deterioration of output characteristics.
  • what is necessary is just to average the result of having measured 5 places, for example using said ellipsometer (SE-400adv by SENTECH) for said average thickness.
  • first passivation layer 8 and the second passivation layer 9 can have a further excellent passivation effect by being composed of layers having a negative fixed charge density, such as the same aluminum oxide layer. .
  • the generation of leakage current can be further reduced and the fabrication can be performed easily.
  • the side surface 10c of the semiconductor substrate 1 has a third passivation layer having a negative fixed charge density such as an aluminum oxide layer. 11 may be provided.
  • the antireflection layer 5 may be provided on the side surface of the semiconductor substrate 1, and at this time, the antireflection layer 5 is preferably formed using an insulating material.
  • the antireflection layer 5 fills the opening and comes into contact with the first semiconductor layer 2. Therefore, since the antireflection layer 5 is made of an insulating material, the generation of leakage current can be reduced.
  • the third semiconductor layer 4 is disposed on the second main surface 10b side of the semiconductor substrate 1 and has the same conductivity type as the first semiconductor layer 2, that is, p-type.
  • the concentration of the dopant contained in the third semiconductor layer 4 is higher than the concentration of the dopant contained in the first semiconductor layer 2. That is, the dopant element is present in the third semiconductor layer 4 at a concentration higher than the concentration of the dopant element doped to exhibit one conductivity type in the first semiconductor layer 2.
  • the third semiconductor layer 4 has a role of reducing a decrease in conversion efficiency due to carrier recombination in the vicinity of the second main surface 10b of the semiconductor substrate 1, and the second main surface 10b of the semiconductor substrate 1 is used. An internal electric field is formed on the side.
  • the third semiconductor layer 4 can be formed, for example, by diffusing a dopant element such as boron or aluminum on the second main surface 10b side of the semiconductor substrate 1. At this time, the concentration of the dopant element contained in the third semiconductor layer 4 can be about 1 ⁇ 10 18 to 5 ⁇ 10 21 atoms / cm 3 .
  • the third semiconductor layer 4 is preferably formed at a contact portion between a second electrode 7 and a semiconductor substrate 1 described later.
  • the first electrode 6 is an electrode provided on the first main surface 10a side of the semiconductor substrate 1, and as shown in FIG. 1, the first output extraction electrode 6a and a plurality of linear first current collecting electrodes 6b. And have. At least a part of the first output extraction electrode 6a intersects the first current collecting electrode 6b and is electrically connected.
  • the first current collecting electrode 6b is linear and has a width of, for example, about 50 to 200 ⁇ m in the lateral direction.
  • the first output extraction electrode 6a has a width of, for example, about 1.3 to 2.5 mm in the short direction. And the width
  • a plurality of first current collecting electrodes 6b are provided with an interval of about 1.5 to 3 mm.
  • the thickness of the first electrode 6 is about 10 to 40 ⁇ m.
  • Such a first electrode 6 can be formed by, for example, applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it.
  • the second electrode 7 is an electrode provided on the second main surface 10b side of the semiconductor substrate 1, and has, for example, the same form as the first electrode, that is, as shown in FIG. 2, the second output extraction electrode 7a and And a plurality of linear second collector electrodes 7b. At least a part of the second output extraction electrode 7a intersects the second collector electrode 7b and is electrically connected.
  • the second current collecting electrode 7b is linear and has a width of, for example, about 50 to 300 ⁇ m in the short direction.
  • the second output extraction electrode 7a has a width of, for example, about 1.3 to 3 mm in the short direction.
  • the width of the second collector electrode 7b in the short direction is smaller than the width of the second output extraction electrode 7a in the short direction.
  • a plurality of second current collecting electrodes 7b are provided with an interval of about 1.5 to 3 mm.
  • the thickness of the second electrode 7 is about 10 to 40 ⁇ m.
  • Such a second electrode 7 can be formed by, for example, applying a conductive paste containing silver as a main component into a desired shape by screen printing or the like and then baking it.
  • the 2nd electrode 7 can make the width
  • aluminum may be mainly used as the material of the second collector electrode 7b, and silver may be mainly used as the material of the second output extraction electrode 7a.
  • the manufacturing method of the solar cell element 10 of this embodiment has an n-type semiconductor region on the first main surface 10a, and a p-type semiconductor on the second main surface 10b located on the opposite side to the first main surface 10a.
  • the semiconductor substrate preparation process of the semiconductor substrate 1 having the first semiconductor layer 2 which is a p-type semiconductor region will be described.
  • the semiconductor substrate 1 is formed by, for example, an existing casting method.
  • an example in which a p-type polycrystalline silicon substrate is used as the semiconductor substrate 1 will be described.
  • an ingot of polycrystalline silicon is produced by a casting method.
  • the ingot is sliced to a thickness of 250 ⁇ m or less, for example.
  • the surface of the semiconductor substrate 1 may be etched by a very small amount with an aqueous solution such as NaOH, KOH, hydrofluoric acid or hydrofluoric nitric acid.
  • the uneven shape 1 a is formed on the first main surface 10 a of the semiconductor substrate 1.
  • a wet etching method using an alkali solution such as NaOH or an acid solution such as hydrofluoric acid, or a dry etching method using RIE (Reactive Ion Etching) or the like can be used.
  • a step of forming the second semiconductor layer 3 which is an n-type semiconductor region is performed on the first main surface 10a of the semiconductor substrate 1 having the concavo-convex shape 1a formed by the above steps. Specifically, the n-type second semiconductor layer 3 is formed in the surface layer on the first main surface 10a side in the semiconductor substrate 1 having the uneven shape 1a.
  • Such a second semiconductor layer 3 may be formed by applying a thermal diffusion method in which phosphorus pentoxide (P 2 O 5 ) in a paste state is applied to the surface of the semiconductor substrate 1 and thermally diffused, or in a gas state. It is formed by a vapor phase thermal diffusion method using (POCl 3 ) as a diffusion source.
  • the second semiconductor layer 3 is formed to have a depth of about 0.2 to 2 ⁇ m and a sheet resistance value of about 40 to 200 ⁇ / ⁇ .
  • the semiconductor substrate 1 is heat-treated at a temperature of about 600 ° C. to 800 ° C.
  • the second semiconductor layer 3 is formed on the first main surface side of the semiconductor substrate 1.
  • the second semiconductor layer 3 formed on the second main surface 10b side is also formed on the second main surface 10b side. Only etch away. Thereby, the p-type conductivity type region is exposed on the second main surface 10b side.
  • the second semiconductor layer 3 formed on the second main surface 10b side is removed by immersing only the second main surface 10b side of the semiconductor substrate 1 in a hydrofluoric acid solution. Thereafter, the phosphor glass adhering to the surface (first main surface 10a side) of the semiconductor substrate 1 when forming the second semiconductor layer 3 is removed by etching.
  • the phosphorous glass remains on the first major surface 10a side, and the second semiconductor layer 3 formed on the second major surface 10b side is removed, so that the first glass on the first major surface 10a side is removed by phosphorous glass. 2 It is possible to reduce the semiconductor layer 3 from being removed or damaged. Further, the second semiconductor layer 3 formed on the side surface of the semiconductor substrate 1 may also be removed.
  • a diffusion mask is formed in advance on the second main surface 10b side, the second semiconductor layer 3 is formed by vapor phase thermal diffusion or the like, and then the diffusion mask. May be removed. Even by such a process, it is possible to form a similar structure. In this case, since the second semiconductor layer 3 is not formed on the second main surface 10b side, the second main surface 10b side is formed. A step of removing the second semiconductor layer 3 is not necessary.
  • the method for forming the second semiconductor layer 3 is not limited to the above method.
  • a thin film technique is used to form an n-type hydrogenated amorphous silicon film or a crystalline silicon film including a microcrystalline silicon film. May be.
  • an i-type silicon region may be formed between the first semiconductor layer 2 and the second semiconductor layer 3.
  • the semiconductor substrate 1 of the polycrystalline silicon substrate in which the second semiconductor layer 3 which is the n-type semiconductor region is disposed on the first main surface 10a side and which includes the first semiconductor layer 2 which is the p-type semiconductor region. Can be prepared.
  • a passivation layer forming step for forming a passivation layer on the first main surface 10a side and the second main surface 10b side of the semiconductor substrate 1 will be described.
  • a first passivation layer 8 is formed on the second semiconductor layer 3, and a second passivation layer 9 is formed on the first semiconductor layer 2.
  • the first passivation layer 8 and the second passivation layer 9 can be simultaneously formed on the entire periphery of the semiconductor substrate 1 by using, for example, an ALD (Atomic Layer Deposition) method. That is, the third passivation layer 11 made of, for example, an aluminum oxide layer is also formed on the side surface 10 c of the semiconductor substrate 1.
  • the above-described semiconductor substrate 1 is placed in the deposition chamber, and the substrate temperature is heated to 100 to 300 ° C.
  • an aluminum raw material such as trimethylaluminum is supplied onto the semiconductor substrate 1 together with a carrier gas such as argon gas or nitrogen gas for 0.5 seconds so that the aluminum raw material is adsorbed on the entire periphery of the semiconductor substrate 1 (step 1). ).
  • a carrier gas such as argon gas or nitrogen gas for 0.5 seconds
  • the aluminum raw material in the space is removed, and among the aluminum raw material adsorbed on the semiconductor substrate 1, components other than those adsorbed at the atomic layer level are removed ( Step 2).
  • an oxidizing agent such as water or ozone gas is supplied into the film formation chamber for 4 seconds to remove CH 3 that is an alkyl group of trimethylaluminum that is an aluminum raw material, and to oxidize dangling bonds of aluminum, thereby producing a semiconductor.
  • An atomic layer of aluminum oxide is formed on the substrate 1 (step 3).
  • purging the film formation chamber with nitrogen gas for 1.5 seconds removes the oxidant in the space and removes the oxidant that did not contribute to the reaction other than aluminum oxide at the atomic layer level.
  • the aluminum oxide layer which has predetermined thickness can be formed by repeating the said process 1 to the process 4.
  • hydrogen is easily contained in the aluminum oxide layer by containing hydrogen in the oxidizing agent used in step 3, and the hydrogen passivation effect can be increased.
  • the antireflection layer 5 is formed using, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition) method, vapor deposition method, sputtering method, or the like.
  • PECVD Pulsma Enhanced Chemical Vapor Deposition
  • vapor deposition method vapor deposition method
  • sputtering method or the like.
  • a mixed gas of silane (SiH 4 ) and ammonia (NH 3 ) is diluted with nitrogen (N 2 ), and glow discharge is performed.
  • the antireflection layer 5 is formed by forming the plasma by decomposition and depositing it.
  • the film formation chamber at this time can be set to about 500 ° C.
  • first electrode 6 first output extraction electrode 6a, first collector electrode 6b
  • second electrode 7 second output extraction electrode 7a, second collector electrode 7b
  • the first electrode 6 is manufactured using a conductive paste containing, for example, a metal powder made of silver or the like, an organic vehicle, and glass frit. This conductive paste is applied to the first main surface 10a of the semiconductor substrate 1, and then fired at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes to form the first electrode 6.
  • a screen printing method or the like can be used as the coating method. After coating, the solvent may be evaporated at a predetermined temperature and dried.
  • the first electrode 6 includes a first output extraction electrode 6a and a first current collection electrode 6b. However, by using screen printing, the first extraction electrode 6a and the first current collection electrode 6b are one It can be formed in a process.
  • An aluminum paste containing glass frit is applied directly onto the second passivation layer 9 in a predetermined region, and the applied paste component is applied to the second paste by a fire-through method in which a heat treatment at a maximum temperature of 600 to 800 ° C. is performed. Passing through the passivation layer 9, the third semiconductor layer 4 is formed on the second main surface 10b side of the semiconductor substrate 1, and an aluminum layer is formed thereon.
  • This aluminum layer can be used as the second electrode 7, and as its formation region, for example, as shown in FIG. 4, the second current collecting electrode 7b and the second output of the second main surface 10b are used.
  • the 2nd output extraction electrode 7a is produced using the electrically conductive paste containing the metal powder which consists of silver etc., an organic vehicle, and glass frit, for example.
  • This conductive paste is applied to the second passivation layer 9 and then baked at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes to form the second output extraction electrode 7a.
  • the coating method a screen printing method or the like can be used. After coating, the solvent may be evaporated at a predetermined temperature and dried.
  • the second output extraction electrode 7a made of silver is connected to the second collector electrode 7b by contacting the aluminum layer.
  • the second output extraction electrode 7a made of silver may be formed first, and then the second current collecting electrode 7b made of aluminum may be formed. Further, the second output extraction electrode 7 a does not need to be in direct contact with the semiconductor substrate 1, and the second passivation layer 9 may exist between the second output extraction electrode 7 a and the semiconductor substrate 1.
  • the aluminum layer formed on the third semiconductor layer 4 may be removed, and the second extraction electrode 7a and the second current collecting electrode 7b may be formed using the same conductive paste. Further, the first electrode 6 and the second electrode 7 may be formed by applying the respective conductive pastes and firing them simultaneously.
  • these electrodes can also be formed using thin film formation, such as vapor deposition and sputtering, and plating formation. is there.
  • the hydrogen passivation effect can be increased by setting the maximum temperature heat treatment in each step to 800 ° C. or less. it can.
  • the heat history by heat treatment at 300 to 500 ° C. may be 5 to 30 minutes.
  • the solar cell element 10 can be manufactured as described above.
  • the third semiconductor layer 4 may be formed before the second passivation layer 9 is formed.
  • boron or a predetermined region in the second main surface 10b is formed before forming the second passivation layer 9. What is necessary is just to diffuse aluminum. Boron is diffused by heating at a temperature of about 800 to 1100 ° C. using a thermal diffusion method using boron tribromide (BBr 3 ) as a diffusion source.
  • BBr 3 boron tribromide
  • a p-type hydrogenated amorphous silicon film or a crystalline silicon film including a microcrystalline silicon film may be formed as the third semiconductor layer 4 using thin film technology.
  • an i-type silicon region may be formed between the semiconductor substrate 1 and the third semiconductor layer 4.
  • the semiconductor substrate 1 may be cleaned before forming the first passivation layer 8 and the second passivation layer 9.
  • the cleaning process include hydrofluoric acid treatment, RCA cleaning (cleaning method developed by RCA, USA, high temperature / high concentration sulfuric acid / hydrogen peroxide solution, dilute hydrofluoric acid (room temperature), ammonia water / hydrogen peroxide. Cleaning method using water or hydrochloric acid / hydrogen peroxide solution) and hydrofluoric acid treatment after the cleaning, or SPM (Sulfuric Acid / Hydrogen Peroxide / Water Mixture) cleaning and cleaning method using hydrofluoric acid treatment after the cleaning Can be used.
  • RCA cleaning cleaning method developed by RCA, USA, high temperature / high concentration sulfuric acid / hydrogen peroxide solution, dilute hydrofluoric acid (room temperature), ammonia water / hydrogen peroxide. Cleaning method using water or hydrochloric acid / hydrogen peroxide solution) and hydrofluoric acid treatment after the cleaning, or SPM (Sulfuric Acid / Hydro
  • annealing is performed using a gas containing hydrogen, and the recombination speed in the semiconductor substrate 1 is further increased. It can be reduced.
  • the solar cell module 20 includes one or more solar cell elements 10 of the present embodiment described above. Specifically, in the solar cell module 20, a plurality of the solar cell elements 10 are electrically connected.
  • the solar cell module 20 is configured by connecting a plurality of solar cell elements 10 in series and in parallel, such as when the electric output of a single solar cell element 10 is small. By combining a plurality of solar cell modules 20, a practical electrical output can be taken out.
  • the solar cell module 20 includes, for example, a transparent member 22 such as glass, a front filler 24 made of transparent EVA or ethylene- ⁇ -olefin copolymer, and a plurality of solar cells.
  • Battery element 10 wiring member 21 connecting the plurality of solar battery elements 10, back side filler 25 made of EVA or ethylene- ⁇ -olefin copolymer, polyethylene terephthalate (PET) or polyvinyl fluoride resin ( It is made of a material such as PVF, and mainly includes a back surface protective material 23 having a single layer or a laminated structure.
  • Adjacent solar cell elements 10 are electrically connected in series with each other by connecting the first electrode 6 of one solar cell element 10 and the second electrode 7 of the other solar cell element 10 by a wiring member 21. It is connected.
  • the wiring member 21 for example, a member in which the entire surface of a copper foil having a thickness of about 0.1 to 0.2 mm and a width of about 2 mm is covered with a solder material is used.
  • the solar cell module 20 may include a frame 28 made of aluminum or the like.
  • the solar cell module 20 it is possible to realize a highly functional back surface reflection structure by using the white backside filler 25.
  • EVA contains vinyl acetate as its component
  • EVA tends to be hydrolyzed with time due to permeation of moisture or water at a high temperature to easily generate acetic acid.
  • an acid acceptor made of magnesium hydroxide or calcium hydroxide may be added to the front side filler 24 or the back side filler 25.
  • the generation of acetic acid can be reduced, the durability of the solar cell module can be improved, and acid damage to the first passivation layer 8 and the second passivation layer 9 can be further reduced. Can do. Therefore, long-term reliability of the solar cell module can be ensured.
  • the solar cell module 20 since the solar cell module 20 according to the present embodiment includes the solar cell element 10 having the above-described passivation layer, the solar cell module 20 is excellent in output characteristics.
  • the solar cell element 10 may be a back contact solar cell element having a metal wrap through structure in which the first output extraction electrode 6a is provided on the second main surface 10b side.
  • the back contact solar cell element 30 having a metal wrap through structure includes a first semiconductor layer 2 and a second semiconductor provided on the first main surface 10 a side of the first semiconductor layer 2.
  • a plurality of through holes 31 are provided in the semiconductor substrate 1 including the layer 3. Further, in the through hole 31, a first current collecting electrode 6b provided on the first main surface 10a side and a first output extraction electrode 6a provided on the second main surface 10b side are electrically connected.
  • a connection electrode 6c is formed.
  • the first connection electrode 4 c may be formed directly on the through hole 31, but the fourth passivation layer 32 made of aluminum oxide may be formed on the inner wall of the through hole 31. By providing the fourth passivation layer 32 also on the inner wall of the through hole 31, the passivation effect can be further enhanced.
  • the fourth passivation layer 32 functions as an insulating layer, so that the occurrence of leakage is reduced. can do.
  • the antireflection layer 5 may be formed on the fourth passivation layer 32.
  • a negative fixed charge density such as an aluminum oxide layer on the fourth passivation layer 32. It is suitable to provide the antireflection layer 5 which is larger on the positive side than the layer having s.
  • the first passivation layer 8, the second passivation layer 9, and the fourth passivation layer 32 are all formed of a layer having a negative fixed charge density such as the same aluminum oxide layer, thereby further enhancing the passivation effect. it can. It is more preferable to provide a layer having a negative fixed charge density such as an aluminum oxide layer around the entire periphery of the semiconductor substrate 1. That is, the third passivation layer 11 having a negative fixed charge density such as an aluminum oxide layer is formed not only on the first main surface 10a, the second main surface 10b, and the through hole 31 of the semiconductor substrate 1 but also on the side surface of the semiconductor substrate 1. It is good to provide.
  • a concavo-convex structure 1a as shown in FIG. 3 was formed on the first main surface 10a side of each prepared polycrystalline silicon substrate by using the RIE method.
  • phosphorus atoms were diffused to form an n-type second semiconductor layer 3 having a sheet resistance of about 90 ⁇ / ⁇ on the surface of the substrate 1.
  • the second semiconductor layer 3 formed on the side surface and the second main surface 10b side was removed with a hydrofluoric acid solution, and thereafter the phosphorous glass remaining on the second semiconductor layer 3 was removed with a hydrofluoric acid solution.
  • a first passivation layer 8, a second passivation layer 9, and a third passivation layer 11 made of an aluminum oxide layer are formed on the entire periphery of the semiconductor substrate 1 by the ALD method, and the first passivation layer 8 is formed on the first passivation layer 8.
  • An antireflection layer 5 made of a silicon nitride layer was formed by plasma CVD.
  • a silver paste is applied in a linear pattern as shown in FIG. 1 on the first main surface 10a side, and an aluminum paste is applied on the second main surface 10b side as a second current collecting electrode 7b as shown in FIG. 2 and a part of the second output extraction electrode 7a, and further silver paste was applied to the pattern of the second output extraction electrode 7a as shown in FIG. Thereafter, the patterns of these pastes were baked to form the third semiconductor layer 4, the first electrode 6, and the second electrode 7, as shown in FIGS. The first electrode 6 and the second collector electrode 7b were in contact with the semiconductor substrate 1 by the fire-through method, respectively.
  • Example 1 the average thickness of the first passivation layer 8, the second passivation layer 9, and the third passivation layer 11 is 35 nm, and the average thickness of the antireflection layer 5 is 45 nm. 2, the average thickness of the first passivation layer 8, the second passivation layer 9, and the third passivation layer 11 was 45 nm, and the average thickness of the antireflection layer 5 was 35 nm.
  • a solar cell element (Comparative Example 1) in which only a silicon nitride layer having an average thickness of 80 nm is formed on the first main surface 10a side.
  • a solar cell element (Comparative Example 2) in which only an aluminum oxide layer having an average thickness of 80 nm is formed on the first main surface 10a side, and a silicon nitride layer having an average thickness of 45 nm are formed on the first main surface 10a side.
  • said average thickness was calculated
  • the solar cell element output characteristics (short-circuit current Isc, open-circuit voltage Voc, fill factor (FF) and photoelectric conversion efficiency) were measured and evaluated. Table 1 shows the measurement results of these characteristics. In addition, the measurement of these characteristics was measured on the conditions of irradiation of AM (Air Mass) 1.5 and 100 mW / cm ⁇ 2 > based on JISC8913.
  • Example 1 had a higher short circuit current Isc and higher photoelectric conversion efficiency than Example 2.

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JP2015144243A (ja) * 2013-12-25 2015-08-06 東京応化工業株式会社 表面被覆膜の形成方法及び表面被覆膜を有する太陽電池
JP2015191907A (ja) * 2014-03-27 2015-11-02 京セラ株式会社 太陽電池素子
JP2016006869A (ja) * 2014-05-28 2016-01-14 京セラ株式会社 太陽電池素子および太陽電池モジュール
JP2016092424A (ja) * 2014-11-04 2016-05-23 エルジー エレクトロニクス インコーポレイティド 太陽電池
JP2017059763A (ja) * 2015-09-18 2017-03-23 シャープ株式会社 光電変換素子及びその製造方法
EP4002495A4 (fr) * 2019-07-19 2023-07-19 Shangrao Jinko solar Technology Development Co., LTD Cellule solaire et son procédé de fabrication
CN118553798A (zh) * 2024-07-30 2024-08-27 隆基绿能科技股份有限公司 一种太阳能电池及其制备方法、光伏组件

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JPH0548123A (ja) * 1991-08-14 1993-02-26 Sharp Corp 光電変換素子
JP2009164544A (ja) * 2007-12-28 2009-07-23 Ind Technol Res Inst 太陽電池のパッシベーション層構造およびその製造方法
WO2011040489A1 (fr) * 2009-09-29 2011-04-07 京セラ株式会社 Elément de pile solaire et module de pile solaire

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JPH0548123A (ja) * 1991-08-14 1993-02-26 Sharp Corp 光電変換素子
JP2009164544A (ja) * 2007-12-28 2009-07-23 Ind Technol Res Inst 太陽電池のパッシベーション層構造およびその製造方法
WO2011040489A1 (fr) * 2009-09-29 2011-04-07 京セラ株式会社 Elément de pile solaire et module de pile solaire

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015144243A (ja) * 2013-12-25 2015-08-06 東京応化工業株式会社 表面被覆膜の形成方法及び表面被覆膜を有する太陽電池
JP2015191907A (ja) * 2014-03-27 2015-11-02 京セラ株式会社 太陽電池素子
JP2016006869A (ja) * 2014-05-28 2016-01-14 京セラ株式会社 太陽電池素子および太陽電池モジュール
JP2016092424A (ja) * 2014-11-04 2016-05-23 エルジー エレクトロニクス インコーポレイティド 太陽電池
JP2017059763A (ja) * 2015-09-18 2017-03-23 シャープ株式会社 光電変換素子及びその製造方法
EP4002495A4 (fr) * 2019-07-19 2023-07-19 Shangrao Jinko solar Technology Development Co., LTD Cellule solaire et son procédé de fabrication
CN118553798A (zh) * 2024-07-30 2024-08-27 隆基绿能科技股份有限公司 一种太阳能电池及其制备方法、光伏组件

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