WO2013190749A1 - 表面実装型圧電発振器 - Google Patents
表面実装型圧電発振器 Download PDFInfo
- Publication number
- WO2013190749A1 WO2013190749A1 PCT/JP2013/002095 JP2013002095W WO2013190749A1 WO 2013190749 A1 WO2013190749 A1 WO 2013190749A1 JP 2013002095 W JP2013002095 W JP 2013002095W WO 2013190749 A1 WO2013190749 A1 WO 2013190749A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- internal terminal
- base
- pads
- layer
- terminal pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/88—Mounts; Supports; Enclosures; Casings
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
- H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
- H03H9/0552—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement the device and the other elements being mounted on opposite sides of a common substrate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
- H03H9/0561—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement consisting of a multilayered structure
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders or supports
- H03H9/10—Mounting in enclosures
- H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
- H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
- H03H9/1021—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device the BAW device being of the cantilever type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
- H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
- H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
- H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/87—Electrodes or interconnections, e.g. leads or terminals
- H10N30/875—Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
- H01L2224/81207—Thermosonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- a package is constituted by a base having an opening on the upper surface and a housing portion inside, and a lid for sealing the opening, and the piezoelectric vibration element and the integrated circuit device are housed in the housing portion of the base.
- the present invention relates to a surface-mounted piezoelectric oscillator (hereinafter simply referred to as a piezoelectric oscillator), and more particularly to improving the package structure of a piezoelectric oscillator.
- a piezoelectric oscillator using a piezoelectric vibration element such as a quartz diaphragm can stably obtain a highly accurate oscillation frequency. Therefore, such a piezoelectric oscillator is used in various fields as a reference frequency source for electronic devices and the like.
- the integrated circuit element is disposed in a housing portion of an insulating base whose upper surface is opened, and the piezoelectric vibration element is supported and fixed above the integrated circuit element, and the inside of the base is hermetically sealed by a lid. It has been stopped.
- Such a configuration has a relatively small number of parts due to customization of a one-chip integrated circuit element incorporating an inverter amplifier such as a CMOS as an oscillation amplifier, and contributes to cost reduction.
- an inverter amplifier such as a CMOS as an oscillation amplifier
- the pad of the integrated circuit element is attached to the internal terminal pad of the ceramic base housing portion.
- flip chip bonding by ultrasonic thermocompression bonding using metal bumps such as gold has been increasing.
- FIG. 10 shows an example of a circuit of a piezoelectric oscillator housed in the base described above.
- 100 is an integrated circuit element
- 200 is a piezoelectric vibration element.
- the integrated circuit element 100 includes, for example, inverter amplifiers AMP1 and AMP2, a feedback resistor Rf, a limiting resistor Rd, and capacitors C1 and C2.
- P1 to P3 are signal input / output units on the integrated circuit element 100 side.
- P4 and P5 are signal input / output units on the piezoelectric vibration element 200 side.
- An alternating current or high frequency signal i1 is output from the output portion P3 of the integrated circuit element 100.
- An AC signal i2 flows between the input / output portions P5 and P4 of the piezoelectric vibration element 200 and the input / output portions P1 and P2 of the integrated circuit element 100.
- the input / output parts P1 to P5 of the signals i1 and i2 are connected in the base by means of an integrated circuit element pad, a base internal terminal pad, a piezoelectric vibration element pad, and a wiring pattern.
- an output wiring pattern or the like (an integrated circuit) is connected from an output internal terminal pad connected to an output pad of an integrated circuit element (a pad corresponding to the signal output unit P3 in FIG. 10).
- the operation of the piezoelectric oscillator is likely to be adversely affected by unnecessary radiation (hereinafter referred to as radiation noise) generated by alternating current or high-frequency signals flowing through the signal output section of the element.
- the frequency of the integrated circuit element signal flowing through the signal output section of the integrated circuit element, the internal terminal pad for input connecting the signal input / output section of the piezoelectric vibrating element, the wiring pattern connecting these, etc. piezoelectric vibration
- the frequency of the piezoelectric vibration element signal flowing through the element connection portion is the same, a phase difference or a potential difference due to a difference in signal waveform occurs between the two signals. For this reason, due to these differences, an operation failure may occur due to the interaction between the integrated circuit element signal and the piezoelectric vibration element signal.
- the piezoelectric vibration element signal is a sine wave at the connection part for the piezoelectric vibration element
- the integrated circuit element signal is a rectangular wave at the output part of the integrated circuit element.
- the signal contains high-frequency components that become radiation noise. This high frequency noise component is more likely to be radiated as an electromagnetic wave as the frequency of the piezoelectric oscillator becomes higher. This radiation may adversely affect the piezoelectric vibration element signal or the like serving as a transmission source.
- an object of the present invention is to provide a piezoelectric oscillator that has excellent electrical characteristics and high operational reliability as a structure that is hardly affected by radiation noise even if it is downsized.
- a plurality of ceramic substrate layers having a rectangular shape in plan view and laminated in three or more layers, and a castellation extending in the vertical direction is formed at each of the four corners of the rectangle of the plurality of ceramic substrate layers; and An insulating base having a storage portion in which a plurality of internal terminal pads are formed and an exterior portion in which four or more external terminals are formed on the outer bottom surface; An integrated circuit element electrically connected to some of the plurality of internal terminal pads, and electrically connected to another part of the plurality of internal terminal pads and electrically connected to the integrated circuit element A piezoelectric vibration element; A piezoelectric oscillator comprising: Of the external terminals, the four external terminals are formed close to each other in a state of not contacting the square castellations, One of the four external terminals constitutes an AC output external terminal, The part of the plurality of internal terminal pads and the other part are formed on the surfaces of the different ceramic substrate layers (
- the first castellation is a castellation opposed in the long side direction of the base to a third castellation at a corner close to the AC output external terminal among the four corners of the rectangle.
- the second castellation is characterized in that it is a corner castellation located in a diagonal direction on the rectangular plan view of the base with respect to the third castellation.
- a part of the wiring pattern connecting the first pad for the integrated circuit element and the second pad for the piezoelectric vibration element has a castellation of a pair of corners of the ceramic substrate layer of the intermediate layer.
- the externally exposed wiring pattern which is a conductive path that connects between different layer surfaces of the ceramic substrate layer, is opposed to a source of radiation noise when radiation noise is generated by an alternating current or high frequency signal flowing through the external terminal for alternating current output. Since the area is larger than other wiring patterns, it is a part that is strongly susceptible to the adverse effects. However, in the present invention, even if the radiation noise is generated, since the externally exposed wiring pattern is disposed at a position far from the AC output external terminal, it is possible to suppress the adverse effect due to the radiation noise as much as possible.
- the distance between the external terminal for AC output and the externally exposed wiring pattern is shortened while the formation positions of external terminals, wiring patterns, internal terminal pads, etc. are increasingly limited.
- the adverse effect of the radiation noise can be suppressed without hindering the downsizing of the surface mount piezoelectric oscillator.
- the externally exposed wiring pattern can also be used as an external measurement terminal for measuring the characteristics of the piezoelectric vibration element, a castellation is separately formed on the long side and the short side of the base in order to provide the external measurement terminal. There is no need.
- casters are formed on the long and short sides of the base, thereby narrowing the base housing, reducing the strength of the base, and increasing the sealing area with the lid. Although the problem that it is difficult to ensure becomes more prominent, these problems do not occur.
- measurement can be performed in the state of the final product, more accurate measurement can be performed.
- the four external terminals are formed close to each other without contacting the four corner castellations on the outer bottom surface of the base, and the externally exposed wiring pattern is formed only on the upper surfaces of the pair of corner castellations of the intermediate ceramic substrate layer. Therefore, even if the piezoelectric oscillator is solder-bonded to the circuit board, the solder does not crawl up along the base castellation, and the lid is bonded to the sealing region of the base with a metal-based sealing material. However, the sealing material does not hang down along the base castellation. For this reason, the external terminal and the external measurement terminal are not short-circuited, and the lid sealing material and the external measurement terminal are not short-circuited.
- the piezoelectric vibration element mounted on the storage portion of the base surrounds a central rectangular space.
- the uppermost ceramic substrate layer configured as a rectangular frame body is hermetically sealed with a lid over the bonding region on the upper surface of the uppermost ceramic substrate layer, and the uppermost ceramic substrate layer is formed on the outer four corners of the frame body. Only the castellations are formed, and chamfered portions or curved portions may be formed at four corners inside the frame body.
- the castellation of the uppermost ceramic substrate layer is only the outer four corners of the frame, and the inner corners of the frame close to the castellation are chamfered. Since the portion or the curvature portion is formed, it is possible to cope with further downsizing of the piezoelectric oscillator without improving the strength of the base and narrowing the joining region with the lid.
- a preferred embodiment is that, as shown in claim 3 of the present invention, in addition to the above-described configuration, the integrated circuit element has a rectangular shape and the one of the plurality of internal terminal pads on one main surface. And a pad to be flip-chip bonded via a bump and The pad of the integrated circuit element is close to two opposing first pads formed in proximity to the first side of the integrated circuit element and a second side of the integrated circuit element facing the first side. And two opposing second pads formed between the first pad and the second pad, and two opposing third pads formed between the first pad and the second pad, respectively.
- the plurality of internal terminal pads of the base are Two opposing first internal terminal pads that are electrically connected to the piezoelectric vibration element and are joined to the two opposing first pads of the integrated circuit element; and the two opposing second pads Two opposing second internal terminal pads and two opposing third pads that are joined to each of the two opposing third pads and interposed between the first internal terminal pad and the second internal terminal pad A third internal terminal pad that Two wirings extending from each of the two opposing third internal terminal pads and each of the two opposing third internal terminal pads along a part of the periphery of each of the two opposing first internal terminal pads
- the pattern is formed on the same surface to form a radiation noise blocking conductive path,
- the first internal terminal pad and the second internal terminal pad are separated from each other by the radiation noise blocking conductive path.
- the third internal terminal pad and the wiring pattern extending from the third internal terminal pad are flush with each other along a part of the periphery of the first internal terminal pad.
- the conductive path by the wiring pattern extending from the third internal terminal pad and the third internal terminal pad And is difficult to reach the first internal terminal pad connected to the piezoelectric vibration element that is more likely to be adversely affected on the same surface. That is, it is possible to suppress the influence of unnecessary radiation (radiation noise) generated from the AC output of the second internal terminal pad from reaching the piezoelectric vibration element electrically connected to the first internal electrode pad.
- the piezoelectric oscillator even when the frequency of the signal flowing through one AC output of the second internal terminal pad and the frequency of the signal flowing through the first internal terminal pad connecting the piezoelectric vibration element are the same, Since the phase is shifted and the potential difference is generated because the signal waveform is different, the difference is caused by the interaction between the AC output side of the second internal terminal pad and the first internal terminal pad. There was a cause.
- the first internal terminal pad electrically connected to the piezoelectric vibration element and the second internal terminal pad including the AC output on one side are connected to the third internal pad on the same plane. Since it is interrupted by the conductive path formed by the terminal pad and the wiring pattern extending from the third internal terminal pad, it is possible to suppress problems due to the interaction.
- the piezoelectric vibration element is an AT-cut crystal diaphragm.
- the base includes the bottom of the lowermost layer, the first bank portion of the intermediate layer, and the uppermost layer.
- the bottom of the lowermost layer is formed of a single plate in a rectangular shape in plan view made of a ceramic material, and the first bank of the intermediate layer is above the bottom of the lowermost layer.
- the storage portion of the lowermost base is formed by the first bank portion of the intermediate layer to store the integrated circuit element, and is formed by the second bank portion of the uppermost layer and the piezoelectric layer. And a plurality of internal terminal pads formed on the inner bottom surface of the first storage portion.
- the base includes the intermediate plate portion of the intermediate layer, the third bank portion of the upper layer, and the lower layer.
- the middle plate portion of the intermediate layer is of a single plate formed in a rectangular shape in plan view from a ceramic material
- the third ridge portion of the upper layer is the intermediate layer
- the lower fourth fourth bank portion is laminated in a plan view frame shape with a ceramic material below the intermediate plate portion of the intermediate layer, and is laminated on the middle plate portion in a plan view frame shape with the ceramic material.
- the storage portion is formed by the third bank portion of the upper layer and stores the piezoelectric vibration element, and is formed by the fourth bank portion of the lower layer and stores the integrated circuit element. 4 storage portions, and on the inner bottom surface of the fourth storage portion, the first to third Department terminal pads are formed.
- the two opposing first internal terminal pads are arranged in the four rectangular four corners of the base.
- two first wiring patterns extending respectively to the first and second castellations and the two opposing second internal terminal pads are opposed to the first and second castellations. From the two second wiring patterns extending to the remaining two castellations and the two wiring patterns extending from the two opposing third internal terminal pads to the end of the inner bottom surface of the base, And two noise-blocking wiring patterns extending in the short side direction of the base.
- the castellation of the ceramic substrate layer of the intermediate layer includes the uppermost layer and the lowermost layer. At least one of the ceramic substrate layers is recessed inward from the castellation.
- FIG. 2 is a plan view of the base before mounting the integrated circuit element and the piezoelectric vibration element of FIG. 1 in the first embodiment of the present invention.
- FIG. 2 is a bottom view of the base of FIG. 1 in the first embodiment of the present invention. It is a bottom view of the integrated circuit element applied to this invention.
- FIG. 6 is a bottom view of a base before mounting the integrated circuit element of FIG. 5 in a second embodiment of the present invention. It is a top view of the base before mounting an integrated circuit element and a piezoelectric vibration element concerning 3rd Example of this invention.
- It is sectional drawing which shows the 5th Example of this invention. It is a circuit diagram of a piezoelectric oscillator.
- FIG. 1 to 3 show a first embodiment of the present invention
- FIG. 4 is a bottom view of an integrated circuit element applied to the present invention
- 5 and 6 show a second embodiment of the present invention
- FIG. 7 shows a third embodiment of the present invention
- FIG. 8 shows a fourth embodiment of the present invention
- FIG. 9 shows a fifth embodiment of the present invention.
- An example is shown.
- common or corresponding parts are denoted by the same reference numerals.
- the piezoelectric oscillator is applied to a crystal oscillator.
- the crystal oscillator 6 is bonded to the base 1 having a recess, the integrated circuit element 2 accommodated below the recess of the base 1, the piezoelectric vibration element 3 accommodated above the recess of the base 1, and the opening of the base 1. And a lid 4 to be provided.
- the base 1 and the lid 4 constitute a package of the crystal oscillator 6.
- the base 1 and the lid 4 are joined using a sealing material 5.
- the piezoelectric vibration element 3 is configured by, for example, an AT-cut quartz crystal vibration plate.
- the inside of the base 1 is hermetically sealed by joining the sealing material 5.
- the crystal oscillator 6 only the upper part of the base 1 is open.
- the integrated circuit element 2 is accommodated in the inner bottom surface 10 a 1 of the base 1.
- the piezoelectric vibration element 3 is accommodated in the upper part of the base 7.
- the crystal oscillator 6 has a stacked arrangement in which the integrated circuit element 2 and the piezoelectric vibration element 3 are stacked.
- the base 1 is formed of three ceramic substrate layers and is a rectangular parallelepiped as a whole.
- the base 1 is composed of a bottom layer bottom portion 11, an intermediate layer bank portion 12, and a top layer bank portion 13.
- the bottom 11 is made of a single plate having a rectangular shape in plan view made of an insulating ceramic material such as alumina.
- the bank portions 12 and 13 are formed in a planar view frame shape from an insulating ceramic material such as alumina.
- the base 1 is formed in a box-like body having a storage portion 10 that is concave when viewed in cross section.
- the upper surface of the bank portion 13 is formed flat.
- the bank portions 12 and 13 constitute a side wall portion of the base 1.
- the upper surface of the bank portion 13 is the upper end surface of the base 1.
- the storage unit 10 has a rectangular shape in plan view, and includes a first storage unit 10a on the lower side and a second storage unit 10b on the upper side.
- the integrated circuit element 2 is accommodated in the first accommodating portion 10a.
- the piezoelectric vibration element 3 is stored in the second storage portion 10b.
- Curvature portions R1, R2, R3, R4 are formed at four corners inside the frame body of the bank portion 13.
- the base 1 has a three-layer structure including the bottom 11 and the bank portions 12 and 13, but may have a single-layer structure or a two-layer structure, or may have four or more layers, depending on the structure of the storage section 10 of the base 1.
- the upper surface of the bank portion 13 of the base 1 serves as a joining region 13a with the lid 4.
- the junction region 13a is made of a metal film.
- the bonding region 13a is a three-layer metal film including a metallized layer made of a metallized material such as tungsten or molybdenum, a nickel layer stacked on the metallized layer, and a gold layer stacked on the nickel layer. Consists of. Tungsten or molybdenum is integrally formed at the time of ceramic firing by metallization technology using thick film printing technology. A nickel layer and a gold layer are formed on the metallized layer by plating in this order.
- a plurality of castellations (dents) C1, C2, C3, and C4 extending in the vertical direction are formed in the rectangular squares on the outer peripheral wall of the base 1 that is rectangular in plan view.
- arc-shaped notches are formed in the vertical direction with respect to the outer peripheral wall of the base 1.
- the junction region 13a is formed by the outer bottom surface of the base 1 by at least one of the conductive via V2 that vertically connects the bank portions 12 and 13 of the base 1 and the wiring pattern (not shown) formed above the castellation C2. It is electrically led to the external terminal pad GT2 formed on 1a2.
- the metal lid 4 is grounded via the bonding region 13a, the conductive via, the wiring pattern above the castellation, and the like. This grounding provides the electromagnetic shielding effect of the crystal oscillator 6.
- a first storage portion 10 a having a substantially rectangular shape in plan view for storing the integrated circuit element 2 is formed by the bank portion 12.
- the inner side surfaces of the left and right sides of the bank portion 12 project inward from the bank portion 13, and the left projecting portion of the bank portion 12 serves as a holding base 10 c that holds one end of the piezoelectric vibration element 3.
- the protruding portion on the right side in the figure is a pillow portion 10d that faces the holding base 10c via the first storage portion 10a.
- a second storage portion 10b constituted by the bank portion 13 is formed above the first storage portion 10a.
- the first storage portion 10a is formed in a substantially rectangular shape in plan view having two specific sides 101a and 102a parallel to the parallel arrangement direction.
- a plurality of rectangular internal terminal pads NT (NT1 to NT6) connected to the pads of the integrated circuit element 2 are formed on the upper surface of the bottom 11 which is the lowermost layer of the base 1, that is, the inner bottom surface 10a1 of the first storage portion 10a.
- a wiring pattern H (a generic name of H1 to H6 to be described later) extending side by side.
- the internal terminal pad NT two pairs of first internal terminal pads NT1 and NT2 are illustrated for the piezoelectric vibration element 3 in which one is for AC input and the other is for AC output.
- the signal input pad and the signal output pad are electrically connected to each other and are connected to two pairs of first pads 21 and 22 of the integrated circuit element 2.
- One of the first pads 21 and 22 of the integrated circuit element 2 is connected to the signal input pad of the piezoelectric vibration element 3 via one of the first internal terminal pads NT1 and NT2, and the other is the first internal terminal pad NT1.
- NT2 is connected to the signal output pad of the piezoelectric vibration element 3 through the other of NT2.
- Two pairs of second internal terminal pads NT3 and NT4 are used for outputting an AC signal of the integrated circuit element 2 and for the other one for grounding the integrated circuit element 2, and a pair of second pads 23 of the integrated circuit element 2. , 24.
- the second pad 23 of the integrated circuit element 2 is a pad to which an AC signal is output from the integrated circuit element 2, and the output AC signal is output to the second internal terminal pad NT3.
- the two pairs of third internal terminal pads NT5 and NT6 are both pads to which a DC potential is applied, and are connected to the two pairs of third pads 25 and 26 of the integrated circuit element 2.
- the DC potential or the ground potential is applied from the integrated circuit element 2.
- the first wiring patterns H1 and H2 extend the first internal terminal pads NT1 and NT2, respectively.
- the second wiring patterns H3 and H4 extend the second internal terminal pads NT3 and NT4, respectively.
- Third wiring patterns H5 and H6 extend third internal terminal pads NT5 and NT6, respectively. Note that a DC potential is applied to both of the pair of third internal terminal pads NT5 and NT6, but they may be combined with a ground potential.
- the third internal terminal pad NT5 and the third wiring pattern H5 are formed along the periphery (partial periphery) of the two sides of the first internal terminal pad NT1, and the first internal terminal pad NT1 is formed.
- a third internal terminal pad NT6 and a third wiring pattern H6 are formed along the periphery (partial periphery) of the two sides of the terminal pad NT2.
- the third internal terminal pad NT5 and the third wiring pattern H5, and the third internal terminal pad NT6 and the third wiring pattern H6 are both radiated noise from the second pad 23 of the integrated circuit element 2 due to the first internal terminal pad NT1.
- a conductive path for blocking radiation noise is formed to block the NT2 side from reaching.
- the first internal terminal pads NT1, NT2 and the second internal terminal pads NT3, NT4 are separated from each other with the radiation noise blocking conductive path in between. Thereby, the radiation noise generated from the second pad 23 of the integrated circuit element 2 is suppressed from reaching the first internal terminal pads NT1, NT2. Since the radiation noise blocking conductive path has a function of blocking radiation noise, a DC potential is applied to the third internal terminal pads NT5 and NT6. This potential is applied from the integrated circuit element 2. Of course, it may be combined with the ground potential as described above.
- first internal terminal pads NT1 and NT2 and the second internal terminal pads NT3 and NT4 are more specific to the specific sides 101a and 102a of the first storage portion 10a than the third internal terminal pads NT5 and NT6 positioned therebetween. Widely formed in parallel directions.
- the internal terminal pads NT5 and NT6 are arranged opposite to each other substantially symmetrically.
- the third internal terminal pads NT5 and NT6 are disposed substantially opposite to each other along a virtual line L2 orthogonal to the specific sides 101a and 102a passing through the center point O of the first storage portion 10a.
- the third internal terminal pads NT5 are substantially L-shaped and substantially symmetrical with respect to the imaginary line L1 along the periphery of two sides with NT12 and NT22 which are one side closest to the facing bank portion 12.
- NT6 and third wiring patterns H5 and H6 are formed. That is, the third internal terminal pad NT5 and the third wiring pattern H5 are substantially L-shaped to form a first radiation noise blocking conductive path surrounding the first internal terminal pad NT1, and the third internal terminal pad.
- NT6 and the third wiring pattern H6 are substantially L-shaped to form a second radiation noise blocking conductive path surrounding the first internal terminal pad NT2.
- the first conductive path is formed along with the formation of each of the conductive paths.
- the first internal terminal pads NT1 and NT2 are securely surrounded by the conductive paths without unnecessarily increasing the area of the storage portion 10a, and the second internal terminal pads NT3 and NT3 are sandwiched between the conductive paths. Can be separated from NT4.
- a plurality of external terminal pads GT connected to external parts and external devices are formed on the lower surface of the bottom 11 (which constitutes a part of the exterior), which is the lowest layer of the base 1. Specifically, as shown in FIG. 3, the external terminal pads GT1, GT2, GT3, and GT4 are formed close to each other without contacting the four corner castellations C1, C2, C3, and C4 on the bottom surface of the base 1.
- the external terminal pads GT1, GT2, GT3, and GT4 are connected to the second wiring patterns H3 and H4 and the third wiring pattern H5 through the conductive vias V1, V2, V3, and V4 that penetrate the bottom portion 11 of the base 1 vertically.
- the second internal terminal pad NT3 and the second wiring pattern H3 are connected to the second pad 23 serving as an AC output of the integrated circuit element 2 to be described later, and the conductive material that vertically connects the bottom portion 11 of the base.
- the external terminal pad GT1 formed on the base bottom surface side by the via V1 it is finally configured as an AC output external terminal.
- a holding base 10c on which the piezoelectric vibration element 3 is mounted is formed on the top surface of the bank portion 12 (inner bottom surface of the second storage portion 10b) which is an intermediate layer of the base 1.
- the fourth wiring pattern H7 extended to the castellation C3 includes a portion extending from the first internal terminal pad NT1 to the castellation C3 at the corner of the bottom 11 by the first wiring pattern H1, Only two externally exposed wiring patterns H9 formed on the upper surface of the castellation C3 of the bank portion 12 excluding the bottom portion 11 are connected to two different layer surfaces (the upper surface of the bottom portion 11 being the lowest layer and the upper surface of the bank portion 12 being an intermediate layer). is doing.
- the fourth internal terminal pad NT8 connected to the other excitation electrode 32 of the piezoelectric vibration element 3 extends to the castellation C4 at the corner of the bank portion 12 by the fourth wiring pattern H8.
- the fourth wiring pattern H8 extending to the castellation C4 extends from the first internal terminal pad NT2 to the castellation C4 at the corner of the bottom 11 by the first wiring pattern H2, and the uppermost bank portion 13. And only the externally exposed wiring pattern H10 formed on the upper surface of the castellation C4 of the bank portion 12 of the intermediate layer excluding the bottom portion 11 of the lowermost layer (the upper surface of the bottom portion 11 which is the lowermost layer and the bank which is the intermediate layer) The upper surface of the part 12 is connected.
- the base 1 configured as described above is formed using a known ceramic lamination technique or metallization technique, and the internal terminal pads, the external terminal pads, and the wiring patterns are made of tungsten, molybdenum, or the like as in the formation of the bonding region 13a.
- Each of the nickel plating layer and the gold plating layer is formed on the upper surface of the metallized layer.
- the externally exposed wiring patterns H9 and H10 are formed on the castellations C3 and C4 located far from the AC output external terminal GT1. That is, the externally exposed wiring pattern H9 is formed on the castellation C3 that is opposite to the castellation C1 in the long side direction of the base 1, and the externally exposed wiring pattern H10 is diagonally opposite to the base 1 on the base 1.
- the castellation C4 is formed at the position.
- the integrated circuit element 2 is a one-chip integrated circuit element incorporating an inverter amplifier (oscillation amplifier) such as a C-MOS, and constitutes an oscillation circuit together with the piezoelectric vibration element 3.
- the pad of the integrated circuit element 2 is formed in, for example, a rectangular shape, and two opposing first pads 21 and 22 adjacent to the first side 2A of the integrated circuit element and the first side Two opposing second pads 23 and 24 close to the second side 2B opposing 2A and two opposing third pads 25 and 26 formed between the first pad and the second pad are formed.
- an inverter amplifier oscillation amplifier
- the two first pads 21 and 22 are electrically connected to the excitation electrodes 31 and 32 of the piezoelectric vibration element 3, and one of the two second pads 23 and 24 is configured to be an AC output.
- the integrated circuit element 2 has, for example, a plurality of pads 21 to 26 of the integrated circuit element 2 and internal terminal pads NT1 to NT6 for integrated circuit elements formed on the base 1 via metal bumps C such as gold. Electromechanical bonding is performed by a flip chip bonding method using sonic thermocompression bonding.
- the piezoelectric vibration element 3 is mounted above the integrated circuit element 2 with a predetermined interval.
- the piezoelectric vibration element 3 is, for example, a rectangular AT-cut quartz vibration plate, and a pair of rectangular excitation electrodes 31 and 32 and these extraction electrodes are formed facing the front and back surfaces thereof.
- These electrodes include, for example, a laminated thin film composed of a chromium or nickel base electrode layer, a silver or gold intermediate electrode layer, and a chromium or nickel upper electrode layer, a chromium or nickel base electrode layer, and silver Alternatively, it is a laminated thin film composed of a gold upper electrode layer.
- Each of these electrodes can be formed by a thin film forming means such as a vacuum deposition method or a sputtering method.
- Bonding of the piezoelectric vibration element 3 and the base 1 uses, for example, a silicone-based conductive resin adhesive (conductive bonding material) S that is in a paste form and contains fine metal pieces such as silver filler. As shown in FIG. 1, the conductive resin adhesive S is applied to the upper surfaces of the first internal terminal pads NT7 and the second internal terminal pads NT8. The conductive resin adhesive S is interposed between the piezoelectric vibration element 3 and the holding base 10c and hardens, thereby electrically and mechanically joining each other.
- a silicone-based conductive resin adhesive (conductive bonding material) S that is in a paste form and contains fine metal pieces such as silver filler.
- the conductive resin adhesive S is applied to the upper surfaces of the first internal terminal pads NT7 and the second internal terminal pads NT8.
- the conductive resin adhesive S is interposed between the piezoelectric vibration element 3 and the holding base 10c and hardens, thereby electrically and mechanically joining each other.
- one end of the piezoelectric vibration element 3 is joined to the holding base 10c while the other end of the piezoelectric vibration element 3 is opposed to the holding base 10c while providing a gap from the inner bottom surface of the first storage portion 10a of the base 1. Retained.
- the lid 4 that hermetically seals the base 1 has a configuration in which a metal brazing material (sealing material) is formed on a core material made of, for example, Kovar, and the sealing material 5 made of this metal brazing material is the base 1. It becomes the structure joined with the junction area
- the plan view outline of the metal lid 4 is substantially the same as or slightly smaller than the outline of the ceramic base.
- the bonding area 13a of the base 1 in which the integrated circuit element 2 and the piezoelectric vibration element 3 are stored in the storage unit 10 is covered with the lid 4, and the sealing material 5 of the lid 4 and the bonding area 13a of the base are melt-cured.
- the quartz oscillator 6 is completed by performing hermetic sealing.
- the crystal oscillator 8 of the second embodiment shown in FIGS. 5 and 6 accommodates the integrated circuit element 2 on the inner bottom surface of the lower recess of the base 7 having a recess having an upper and lower opening, and the inner bottom surface of the upper recess.
- the base 7 is constituted by a rectangular parallelepiped as a whole from the middle plate portion 71, the bank portion 72, and the bank portion 73.
- the middle plate portion 71 is made of a single plate having a rectangular shape in plan view made of an insulating ceramic material such as alumina as an intermediate layer.
- the bank portion 72 has a frame shape in plan view of the uppermost ceramic material laminated on the middle plate portion 71 (configured as a rectangular frame surrounding a central rectangular space).
- the bank portion 73 has a frame shape (configured as a rectangular frame surrounding the central rectangular space) of the lowermost ceramic material laminated under the middle plate portion 71.
- the base 7 has two storage portions 70a and 70b that are rectangular in plan view in the top and bottom, and is formed in a box-shaped body having a substantially H-shaped cross section.
- a bank portion (side wall portion) 72 is formed around the storage portion 70a.
- the upper surface (end surface) of the bank portion 72 is formed flat.
- a bank portion (side wall portion) 73 is formed around the storage portion 70b.
- the lower surface (end surface) of the bank portion 73 is formed flat.
- the piezoelectric vibration element 3 is accommodated in the accommodating portion 70a.
- the integrated circuit element 2 is accommodated in the lower accommodating portion 70b.
- the ceramic multilayer substrate is not limited to a base having a three-layer structure as in the present embodiment, and may be composed of four or more layers according to the structure of the storage portion of the base.
- the upper surface (end surface) of the bank portion 72 which is the uppermost layer of the base 1 is flat and is a joining region (metal film) 72a with the lid 4.
- the junction region 72a is composed of a metallized layer made of a metallized material such as tungsten or molybdenum, a nickel layer laminated on the metallized layer, and a gold layer laminated on the nickel layer.
- Tungsten or molybdenum is integrally formed at the time of ceramic firing by metallization technology by utilizing thick film printing technology, and nickel layer and gold layer are plated on the metallization layer in this order.
- a plurality of castellations C1, C2, C3, C4 extending in the vertical direction are formed at the four corners of the outer peripheral wall of the base 7.
- an arc-shaped cutout is formed in the vertical direction with respect to the outer peripheral wall of the base 7.
- the junction region 72a is formed on the bottom surface side of the base by at least one of a conductive via (not shown) and a wiring pattern (not shown) formed above the castellation C2 to vertically connect the base bank portion 72 and the middle plate portion 71. It is electrically led out to a part of the formed external terminal pad GT2.
- the metal lid is grounded via the bonding region 72a, the conductive via, the wiring pattern above the castellation, etc., and the electromagnetic shielding effect of the surface-mount crystal oscillator is obtained. Can do.
- the lower surface is formed with a bank portion (side wall portion) 73, and a second storage portion 70 b having a substantially rectangular shape in plan view for storing the integrated circuit element 2 is formed.
- a first storage portion 70 a that is configured by a side wall portion 72 and that stores the piezoelectric vibration element 3 and has a substantially rectangular shape in plan view is formed.
- the second storage portion 70b has two specific sides parallel to the direction in which the first internal terminal pads NT1 and NT2, the second internal terminal pads NT3 and NT4, and the third internal terminal pads NT5 and NT6 are arranged in parallel. It is formed in a substantially rectangular shape having 71b and 72b.
- a plurality of rectangular internal terminal pads NT connected to the integrated circuit element 2 and these are extended on the lower surface of the middle plate portion 71 (the inner bottom surface of the second storage portion 70b) which is an intermediate layer of the base 7.
- Wiring patterns H to be formed are formed side by side. Specifically, as shown in FIG. 6, as the internal terminal pad NT on the lower surface of the middle plate portion 71 (the inner bottom surface of the second storage portion 70 b) that is an intermediate layer of the base 7, And two opposing first internal terminal pads NT1, NT2 connected to the first pads 21, 22 of the integrated circuit element 2 and two pads connected to the second pads 23, 24 of the integrated circuit element 2.
- Second internal terminal pads NT3 and NT4 and two opposing third internal terminal pads NT5 and NT6 connected to the third pads 25 and 26 of the integrated circuit element 2 are formed.
- the wiring pattern H on the lower surface of the middle plate portion 71 that is the intermediate layer of the base 7 (the inner bottom surface of the second storage portion 70b) the first wiring patterns H1, extending the first internal terminal pads NT1, NT2, respectively.
- H5 a third internal terminal pad NT6 and a third wiring pattern H6 extending from the third internal terminal pad NT6 along the periphery (partial periphery) of the two sides of the first internal terminal pad NT2.
- the first internal terminal pads NT1, NT2 and the second internal terminal pads NT3, NT4 are separated from each other.
- first internal terminal pads NT1 and NT2 and the second internal terminal pads NT3 and NT4 are parallel to the specific sides 71b and 72b of the second storage portion 70b from the third internal terminal pads NT5 and NT6 positioned therebetween. It is wide in any direction. Further, two first internal terminal pads NT1, NT2 and 2 for the virtual line L1 parallel to the specific sides 71b, 72b passing through the center point O of the second storage portion 70b (integrated circuit element storage portion). The two second internal terminal pads NT3 and NT4 and the two third internal terminal pads NT5 and NT6 are disposed substantially symmetrically opposite to each other, and the two third internal terminal pads NT5 and NT6 are disposed in the second storage portion 70b. They are disposed substantially opposite to each other along a virtual line L2 orthogonal to the specific sides 71b and 72b passing through the center point O.
- first internal terminal pads NT1 and NT2 formed in a rectangular shape, NT11 and NT21 which are one side closest to the second internal terminal pads NT3 and NT4 and the bank 73 facing the external environment are closest.
- the third internal terminal pads NT5 and NT6 and the third internal terminal pads NT5 and NT6 are substantially L-shaped along the periphery of two sides of NT12 and NT22, which are one side, and are substantially symmetrical with respect to the virtual line L1.
- the two first internal terminals can be formed without unnecessarily increasing the area of the second storage portion 70b with the formation of the third wiring patterns H5 and H6.
- the pads NT1 and NT2 can be reliably enclosed, and can be separated from the second internal terminal pads NT3 and NT4.
- the bottom surface of the bank portion 73 is flat, and a plurality of mounting external terminal pads GT connected to external components and external devices are formed. Specifically, as shown in FIG. 6, the external terminal pads GT1, GT2, GT3, and GT4 are formed close to each other without contacting the four corner castellations C1, C2, C3, and C4 on the bottom surface of the base 7, An external terminal pad GT5 is formed between the external terminal pad GT1 and the external terminal pad GT3 in the long side direction of the base, and an external terminal pad GT6 is formed between the external terminal pad GT2 and the external terminal pad GT4.
- the external terminal pads GT1 to GT4 are connected to the second internal terminal pad via the second wiring patterns H3 and H4 and the third wiring patterns H5 and H6 through conductive vias (not shown) penetratingly connected to the upper portion. It is electrically derived to any of NT3, NT4 and third internal terminal pads NT5, NT6.
- the second internal terminal pad NT3 and the second wiring pattern H3 are connected to the second pad 23 serving as an AC output of the integrated circuit element 2, and conductively connecting through the base bank portion 73 vertically.
- Fourth inner terminal pads NT7 and NT8 are provided on the upper surface of the middle plate portion 71 (the inner bottom surface of the first storage portion 70a) which is an intermediate layer of the base 7. Only, and fourth wiring patterns H7 and H8 extending from the fourth internal terminal pads NT7 and NT8, respectively. More specifically, the fourth internal terminal pad NT7 connected to the excitation electrode 31 of the piezoelectric vibration element 3 extends to the corner castellation C3 of the middle plate portion 71 by the fourth wiring pattern H7.
- the fourth wiring pattern H7 extended to the castellation C3 has a portion extending from the first internal terminal pad NT1 to the castellation C3 at the corner of the middle plate portion 71 by the first wiring pattern H1, and the uppermost layer. Only two externally exposed wiring patterns H9 formed on the upper surface of the castellation C3 of the intermediate plate portion 71 of the intermediate layer excluding the bank portion 72 and the lowermost bank portion 73 (the intermediate plate portion 71 being the intermediate layer) Are connected. Further, the fourth internal terminal pad NT8 connected to the excitation electrode 32 of the piezoelectric vibration element 3 is extended to the castellation C4 at the corner of the middle plate portion 72 which is an intermediate layer of the ceramic substrate by the fourth wiring pattern H8.
- the fourth wiring pattern H8 extending to the castellation C4 has a portion extending from the first internal terminal pad NT2 to the castellation C4 at the corner of the middle plate portion 71 by the first wiring pattern H2, and the uppermost layer. Only two externally-exposed wiring patterns H10 formed on the upper surface of the castellation C4 of the intermediate plate portion 71 of the intermediate layer excluding the bank portion 72 and the lowermost bank portion 73 (the intermediate plate portion 71 being the intermediate layer) Are connected.
- the base 7 configured as described above is formed by using a known ceramic lamination technique or metallization technique, and each of the internal terminal pads, the mounting external terminal pads, and the wiring pattern is made of tungsten or the same as in the formation of the bonding region 72a.
- a nickel plating layer and a gold plating layer are formed on the upper surface of the metallized layer made of molybdenum or the like.
- the externally exposed wiring patterns H9 and H10 are formed on a pair of corner castellations C3 and C4 located far from the AC output external terminal GT1. That is, the corner castellation C1 in which the externally exposed wiring pattern H9 is located in the vicinity of the AC output external terminal GT1 is formed in the castellation C3 at the opposite position in the long side direction of the base 1, and the externally exposed wiring pattern H10 is The corner castellation C1 located in the vicinity of the AC output external terminal GT1 is formed in the castellation C4 at the diagonal position of the base 1.
- the integrated circuit element 2 includes a plurality of pads 21 to 26 of the integrated circuit element 2 and internal terminal pads NT1 to NT6 formed on the base 7 through metal bumps C such as gold. For example, it is joined electromechanically by a flip chip bonding method using ultrasonic thermocompression bonding.
- Bonding of the piezoelectric vibration element 3 and the base 7 uses, for example, a silicone-based conductive resin adhesive (conductive bonding material) S that is in the form of a paste and contains fine metal pieces such as silver filler. As shown in FIG. 5, the adhesive S is applied to the upper surfaces of the first internal terminal pad NT7 and the second internal terminal pad NT8, and the adhesive S is applied to the first and second piezoelectric vibration elements 3 and the base 7. By interposing and curing between the inner bottom surfaces of the storage portion 70a, they are electrically and mechanically joined to each other.
- a silicone-based conductive resin adhesive (conductive bonding material) S that is in the form of a paste and contains fine metal pieces such as silver filler.
- one end of the piezoelectric vibration element 3 is provided with a gap from the inner bottom surface of the first storage part 70 a of the base 7, and the other opposite end of the piezoelectric vibration element 3 is connected to the first storage part 70 a of the base 7. Joined to the inner bottom and cantilevered.
- the lid 4 has a configuration in which a metal brazing material (sealing material) is formed on a core material made of, for example, Kovar, and the sealing material 5 made of this metal brazing material is a joining region (metal film) 72a of the base 1. It becomes the composition joined.
- the external shape of the metal lid in plan view is substantially the same as or slightly smaller than that of the ceramic base.
- the integrated circuit element 2 is stored in the second storage portion 70b of the base 7, and the bonding region 72a of the base 7 is covered with the lid 4 in a state where the piezoelectric vibration element 3 is stored in the first storage portion 70a.
- the crystal oscillator 8 is completed by melt-curing the sealing material 5 of the lid 4 and the joining region 72a of the base and hermetically sealing the piezoelectric vibration element 3.
- the different layer surfaces are connected only by the externally exposed wiring patterns H9 and H10 formed on the upper surfaces of the pair of corner castellations C3 and C4. For this reason, between two different layers of the conductive paths (wiring patterns H1, H2, H7, H8 and externally exposed wiring patterns H9, H10) connecting the internal terminal pads NT1, NT2 and the internal terminal pads NT7, NT8. Since the conductive paths (externally exposed wiring patterns H9, H10) to be connected can be arranged at a position far from the AC output external terminal GT1, adverse effects due to radiation noise can be suppressed as much as possible.
- the adverse effect of radiation noise can be suppressed without hindering the miniaturization of the piezoelectric oscillator 6 or 8.
- the externally exposed wiring patterns H9 and H10 formed on the upper surfaces of the castellations C3 and C4 can be used as an external measurement terminal for measuring the characteristics of only the piezoelectric vibration element 3, a base for providing an external measurement terminal There is no need to separately form a castellation on the long side or the short side, and the strength of the base 1 or 7 is not lowered, and it is not difficult to secure a sealing region with the lid 4.
- four external terminal pads GT1, GT2, GT3, and GT4 formed close to the four corner castellations C1, C2, C3, and C4 on the bottom surface of the base are formed into four corner castellations C1, C2, C3, and C4. Since the externally exposed wiring patterns H9 and H10 are formed close to each other without being in contact with each other, and are formed only on the upper surface of the pair of corner castellations C3 and C4 of the bank portion 12 or the middle plate portion 71, the circuit board Even if the piezoelectric oscillator 6 or 8 is soldered together, the solder does not crawl up along the castellations C3 and C4 of the base, and the lid 4 is sealed with a sealing material 5 made of a metal brazing material in the sealing region of the base.
- the sealing material 5 does not hang down along the castellations C3 and C4 of the base. Therefore, the external terminal and the external measurement terminal are not short-circuited, and the lid sealing material and the external measurement terminal are not short-circuited.
- the castellations C1, C2, C3, and C4 of the bank portion 13 or the bank portion 72 are only the four corners on the outer side of the frame body, and the four corners on the inner side of the frame body near the castellations C1, C2, C3, and C4. Since the chamfered portions M1, M2, M3, and M4 or the curved portions R1, R2, R3, and R4 are formed, the piezoelectric oscillator 6 can be formed without reducing the joining region 13a or 72a with the lid 4 while improving the strength of the base. Or it can respond to the further size reduction of 8.
- the piezoelectric vibration element 3 and The electrically connected first internal terminal pads NT1 and NT2 and the AC output second internal terminal pad NT3 are separated from each other via the third internal terminal pads NT5 and NT6 and the third wiring patterns H5 and H6. Can do.
- the first internal terminal pads NT1, NT2 electrically connected to the piezoelectric vibration element 3 and the second internal terminal pad NT3 for AC output are formed by the third internal terminal pads NT5, NT6 and the third wiring patterns H5, H6. Since it is interrupted by the conductive path, it is possible to suppress problems due to the interaction between the first internal electrode pads NT1, NT2 and the second internal terminal pad NT3.
- the positional deviation of the bumps C with respect to the pads or the pads and The misalignment with the internal terminal pads can be absorbed by the wide first internal terminal pads NT1 and NT2 and the second internal terminal pads NT3 and NT4, and the bump C protrudes from the internal terminal pads NT1 to NT6 and is joined. Also disappear. Further, the first internal terminal pads NT1, NT2 and the second internal terminal pads NT3, NT4 are formed wider than the third internal terminal pads NT5, NT6, so that the plane areas are slightly different or the positions of the pads are slightly different.
- the distance between the first internal terminal pads NT1 and NT2 and the second internal terminal pads NT3 and NT4 is made close to each other to reduce the size of the piezoelectric oscillators 6 and 8. It can correspond to the conversion. That is, the present invention can simultaneously improve the mountability, the reliability of bonding, and the versatility when the integrated circuit element 2 is flip-chip bonded while corresponding to the miniaturization of the piezoelectric oscillators 6 and 8.
- first internal terminal pads NT1, NT2, the second internal terminal pads NT3, NT4, and the third internal terminal pads NT5, NT6 are parallel to a specific side passing through the center point O of the storage portion for the integrated circuit element. Opposite to the virtual line L1.
- the two first pads 21 and 22 and the two first internal terminals NT1 and NT2 and the second second are paired with respect to the warp in the direction orthogonal to the specific side of the storage portion for the integrated circuit element. It is possible to make uniform the height variation due to the warpage of each of the pads 23 and 24 and the two second internal terminals NT3 and NT4, and the two third pads 25 and 26 and the two third internal terminals NT5 and NT6. it can.
- the pair of first pads 21 and 22 and the first internal terminals NT1 and NT2, second pads 23 and 24, second internal terminals NT3 and NT4, third pads 25 and 26, and third internal terminals NT5 and NT6 are pressed against a pair of bumps C.
- the variation in strength does not occur.
- the two third internal terminal pads NT5 and NT6 are disposed substantially opposite to each other along a virtual line L2 orthogonal to the specific side passing through the center point O of the integrated circuit element housing portion. .
- the storage portion for the integrated circuit element 2 can be arranged in the vicinity of the apex of the warp in both the specific side direction and the direction orthogonal to the specific side direction (near the central point O in this embodiment).
- the first pads 21, 22, the first internal terminals NT1, NT2, the second pads 23, 24, the third pads 25, 26 of the second internal terminals NT3, NT4, and the first pads 3 The pressing force against the bumps C and the pressing strength at the six internal terminals NT5 and NT6 in total are made uniform, and the bonding strength can be made more stable and reliable.
- the bonding strength of the bump C when the integrated circuit element 2 is flip-chip bonded is stabilized while corresponding to the miniaturization of the piezoelectric oscillators 6 and 8, and the electromechanical bonding can be performed more reliably. .
- the AT cut crystal diaphragm is used as the piezoelectric vibration element, the present invention is not limited to this, and a tuning fork type crystal diaphragm may be used.
- quartz is used as the piezoelectric vibration element, the present invention is not limited to this, and a piezoelectric single crystal material such as piezoelectric ceramics or LiNbO3 may be used. That is, any piezoelectric vibration element can be applied.
- the example in which the piezoelectric vibration element is cantilevered is taken as an example, a configuration in which both ends of the piezoelectric vibration element are retained may be employed.
- the silicone type conductive resin adhesive is taken as an example of the conductive bonding material, other conductive resin adhesives may be used, and bump materials, brazing materials, etc. of metal bumps and metal plating bumps may be used.
- the piezoelectric vibration element 3 and the integrated circuit element 2 are used, it is not limited to this, The number of the piezoelectric vibration elements 3 can be set arbitrarily, and in addition to the integrated circuit element 2, other The circuit parts may be mounted.
- the electrical connection between the integrated circuit element and the base is not limited to the flip chip bonding method by ultrasonic thermocompression bonding, and other connection methods such as wire bonding may be employed.
- an oscillation circuit configuration using a one-chip integrated circuit element incorporating a C-MOS inverter amplifier as an oscillation amplifier is taken as an example, an oscillation circuit configuration including other oscillation amplifiers may be used.
- FIG. 7 relates to the third embodiment of the present invention, and is a plan view of the dam portions 12 and 13 of the base 1 before the integrated circuit element 2 and the piezoelectric vibration element 2 are mounted for convenience of illustration. is there.
- noise blocking wiring patterns H11 and H12 extend in the short side direction of the base 1 from the fifth and sixth wiring patterns H5 and H6 to the end portions 1a3 and 1a4 of the inner bottom surface 10a1 of the base 1. Has been issued.
- the noise blocking wiring patterns H11 and H12 are arranged in the middle of the long side direction of the first wiring patterns H1 and H2 on both sides of the base 1 in the long side direction and the second wiring patterns H3 and H4.
- Mutual interference of flowing signals can be prevented.
- FIG. 8 relates to a fourth embodiment of the present invention.
- upper surfaces C31 and C41 intermediate layer upper surfaces corresponding to the bank portion 12 of the intermediate layer and the uppermost layer are shown.
- the upper surfaces C33 and C43 uppermost layer upper surface corresponding to the lower base 11 are recessed inwardly relative to the upper surfaces C32 and C42 (uppermost layer upper surface) corresponding to the uppermost bank portion 13.
- the externally exposed wiring patterns H9 and H10 formed on the upper surface C31 and C41 of the intermediate layer are made difficult to come into contact with fingers or a carrying jig when carrying the crystal oscillator, etc., thereby protecting the externally exposed wiring patterns H9 and H10. Yes.
- intermediate layer upper surfaces C31 and C41 of the castellations C3 and C4 of the intermediate layer bank portion 12 correspond to the uppermost layer upper surfaces C32 and C42 corresponding to the uppermost bank portion 13 and the lowermost base 11 respectively.
- the uppermost layer upper surfaces C33 and C43 may be recessed relatively inwardly.
- FIG. 9 relates to a fifth embodiment of the present invention.
- the formation positions of the conductive vias V1 and V2 that vertically connect the bottom portion 11 of the base 1 are indicated by solid lines. It is not limited to the intermediate position of the pillow part 10d, as long as it is allowable in terms of strength, as long as it is between the intermediate position of the pillow part 10d and the position indicated by the dotted line on the lower inner side surface of the pillow part 10d, as indicated by the arrow. Good.
- the formation position of the conductive vias V3 and V4 that vertically connect the bottom portion 11 of the base 1 is not limited to the intermediate position of the holding base 10c indicated by the solid line, as indicated by the arrow as long as it is permissible in terms of strength.
- the intermediate position of the holding table 10c and the position indicated by the dotted line at the lower part of the inner side surface of the holding table 10c may be between the various positions without departing from the concept or main features of the present invention. Can be implemented.
- the above-described embodiment is merely an example in all respects and should not be interpreted in a limited manner.
- the scope of the present invention is indicated by the claims, and is not restricted by the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.
- the present invention can be applied to a surface mount type piezoelectric oscillator.
Landscapes
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Wire Bonding (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
Description
平面視外形が矩形形状で3層以上に積層された複数のセラミック基板層からなり、かつ、前記複数のセラミック基板層の前記矩形の4角それぞれに上下方向に伸長するキャスタレーションが形成され、かつ、複数の内部端子パッドが形成された収納部と、外底面に4つ以上の外部端子が形成された外装部とを有する絶縁性のベースと、
前記複数の内部端子パッドの一部と電気的に接続される集積回路素子と、前記複数の内部端子パッドの他の一部と電気的に接続され、前記集積回路素子と電気的に接続される圧電振動素子と、
を有する圧電発振器であって、
前記外部端子のうち、前記4つの外部端子は、前記4角のキャスタレーションに接しない状態で近接して形成されており、
前記4つの外部端子のうちの1つが、交流出力用外部端子を構成しており、
前記複数の内部端子パッドの前記一部と前記他の一部は、異なるセラミック基板層それぞれの面(以下、異層面)に形成されており、
前記複数の内部端子パッドの前記一部と前記他の一部とを接続する外部露出配線パターンが、前記3層以上のセラミック基板層のうち、最上層のセラミック基板層と最下層のセラミック基板層との間にある中間層のセラミック基板層の前記矩形の4角のうちの一対の角の一方の第1キャスタレーションの上面と第2キャスタレーションの上面とのみに形成されており、
前記第1キャスタレーションは、該矩形の4角のうち前記交流出力用外部端子に近接する角の第3キャスタレーションに対して前記ベースの長辺方向で対向するキャスタレーションであり、
前記第2キャスタレーションは、前記第3キャスタレーションに対して前記ベースの前記平面視矩形上で対角線方向に位置する角のキャスタレーションであることを特徴とする。
前記集積回路素子の前記パッドは、前記集積回路素子の第1辺に近接して形成された2つの対向する第1パッドと、前記集積回路素子の前記第1辺に対向する第2辺に近接して形成された2つの対向する第2パッドと、前記第1パッドと前記第2パッドとの間に各々形成された2つの対向する第3パッドとを有し、前記2つの第2パッドのうちの一方が交流出力となり、
前記ベースの前記複数の内部端子パッドは、
前記圧電振動素子と電気的に接続されるとともに前記集積回路素子の前記2つの対向する第1パッドと接合される2つの対向する第1内部端子パッドと、前記2つの対向する第2パッドと接合される2つの対向する第2内部端子パッドと、前記2つの対向する第3パッドそれぞれと接合されるもので前記第1内部端子パッドと前記第2内部端子パッドとの間に介在する2つの対向する第3内部端子パッドとを有し、
前記2つの対向する第1内部端子パッドそれぞれの周囲の一部に沿って、前記2つの対向する第3内部端子パッドそれぞれと当該2つの対向する第3内部端子パッドそれぞれを延出する2つの配線パターンとが同一面に形成されて輻射ノイズ遮断用導電路が構成され、
前記第1内部端子パッドと前記第2内部端子パッドとが前記輻射ノイズ遮断用導電路を間にして隔てられている。
前記最下層のベースの収納部は、前記中間層の第1堤部により形成されて前記集積回路素子が収納される第1収納部と、前記最上層の第2堤部により形成されて前記圧電振動素子が収納される第2収納部とを有し、前記第1収納部の内底面に、前記複数の内部端子パッドが形成されている。
図7は、本発明の第3の実施例に係り、図解の都合で集積回路素子2と圧電振動素子2とを搭載する前のベース1の堤部12,13を透視した状態の平面図である。第3の実施例では、第5および第6の配線パターンH5,H6からベース1の内底面10a1の端部1a3,1a4まで、ベース1の短辺方向にノイズ遮断用配線パターンH11,H12が延出されている。ノイズ遮断用配線パターンH11,H12は、ベース1の長辺方向両側の第1配線パターンH1,H2と、第2配線パターンH3,H4との長辺方向中間に配置されている。ノイズ遮断用配線パターンH11,H12により、キャスタレーションC3,C4まで延出された第1配線パターンH1,H2と、キャスタレーションC1,C2まで延出された第2配線パターンH3,H4とのそれぞれを流れる信号の相互干渉を防止できる。
なお、本発明は、その思想または主要な特徴から逸脱することなく、他のいろいろな形で実施することができる。そのため、上述の実施例はあらゆる点で単なる例示にすぎず、限定的に解釈してはならない。本発明の範囲は特許請求の範囲によって示すものであって、明細書本文には、なんら拘束されない。さらに、特許請求の範囲の均等範囲に属する変形や変更は、全て本発明の範囲内のものである。
2 集積回路素子
3 圧電振動素子
6、8 水晶発振器
10 収納部
11 底部
12 堤部
13 堤部
NT1,NT2 第1内部端子パッド
NT3,NT4 第2内部端子パッド
NT5,NT6 第3内部端子パッド
H1,H2 第1配線パターン
H3,H4 第2配線パターン
H5,H6 第3配線パターン
Claims (8)
- 平面視外形が矩形形状で3層以上に積層された複数のセラミック基板層からなり、かつ、前記複数のセラミック基板層の前記矩形の4角それぞれに上下方向に伸長するキャスタレーションが形成され、かつ、複数の内部端子パッドが形成された収納部と、外底面に4つ以上の外部端子が形成された外装部とを有する絶縁性のベースと、
前記複数の内部端子パッドの一部と電気的に接続される集積回路素子と、前記複数の内部端子パッドの他の一部と電気的に接続され、前記集積回路素子と電気的に接続される圧電振動素子と、
を有する圧電発振器であって、
前記外部端子のうち、前記4つの外部端子は、前記4角のキャスタレーションに接しない状態で近接して形成されており、
前記4つの外部端子のうちの1つが、交流出力用外部端子を構成しており、
前記複数の内部端子パッドの前記一部と前記他の一部は、異なるセラミック基板層それぞれの面(以下、異層面)に形成されており、
前記複数の内部端子パッドの前記一部と前記他の一部とを接続する外部露出配線パターンが、前記3層以上のセラミック基板層のうち、最上層のセラミック基板層と最下層のセラミック基板層との間にある中間層のセラミック基板層の前記矩形の4角のうちの一対の角の一方の第1キャスタレーションの上面と第2キャスタレーションの上面とのみに形成されており、
前記第1キャスタレーションは、該矩形の4角のうち前記交流出力用外部端子に近接する角の第3キャスタレーションに対して前記ベースの長辺方向で対向するキャスタレーションであり、
前記第2キャスタレーションは、前記第3キャスタレーションに対して前記ベースの前記平面視矩形上で対角線方向に位置する角のキャスタレーションであることを特徴とする圧電発振器。 - 前記ベースの収納部に搭載された圧電振動素子は、中央の矩形状の空間を囲う矩形状の枠体として構成された最上層のセラミック基板層の上面の接合領域に蓋を被せて気密封止されており、
前記最上層のセラミック基板層における前記枠体の外側の4角にのみ前記キャスタレーションが形成されており、
前記最上層のセラミック基板層における前記枠体の内側の4角に面取り部あるいは曲率部が形成されている、請求項1に記載の圧電発振器。 - 前記集積回路素子は矩形状で一主面に前記複数の内部端子パッドの前記一部とバンプを介してフリップチップボンディングされるパッドを有しており、
前記集積回路素子の前記パッドは、前記集積回路素子の第1辺に近接して形成された2つの対向する第1パッドと、前記集積回路素子の前記第1辺に対向する第2辺に近接して形成された2つの対向する第2パッドと、前記第1パッドと前記第2パッドとの間に各々形成された2つの対向する第3パッドとを有し、前記2つの第2パッドのうちの一方が交流出力となり、
前記ベースの前記複数の内部端子パッドは、
前記圧電振動素子と電気的に接続されるとともに前記集積回路素子の前記2つの対向する第1パッドと接合される2つの対向する第1内部端子パッドと、前記2つの対向する第2パッドと接合される2つの対向する第2内部端子パッドと、前記2つの対向する第3パッドそれぞれと接合されるもので前記第1内部端子パッドと前記第2内部端子パッドとの間に介在する2つの対向する第3内部端子パッドとを有し、
前記2つの対向する第1内部端子パッドそれぞれの周囲の一部に沿って、前記2つの対向する第3内部端子パッドそれぞれと当該2つの対向する第3内部端子パッドそれぞれを延出する2つの配線パターンとが同一面に形成されて輻射ノイズ遮断用導電路が構成され、
前記第1内部端子パッドと前記第2内部端子パッドとが前記輻射ノイズ遮断用導電路を間にして隔てられている、請求項1または2に記載の圧電発振器。 - 前記圧電振動素子は、ATカットされた水晶振動板である請求項1ないし3のいずれか一項に記載の圧電発振器。
- 前記ベースは、最下層の底部と、中間層の第1堤部と、最上層の第2堤部と、から構成され、前記最下層の底部は、セラミック材料からなる平面視矩形状の一枚板で構成され、前記中間層の第1堤部は、前記最下層の底部上にセラミック材料により平面視枠形状に積層され、前記最上層の第2堤部は、前記中間層の第1堤部上にセラミック材料により平面視枠形状に積層され、
前記最下層のベースの収納部は、前記中間層の第1堤部により形成されて前記集積回路素子が収納される第1収納部と、前記最上層の第2堤部により形成されて前記圧電振動素子が収納される第2収納部とを有し、前記第1収納部の内底面に、前記複数の内部端子パッドが形成されている、請求項1に記載の圧電発振器。 - 前記ベースは、中間層の中板部と、上層の第3堤部と、下層の第4堤部とから構成され、前記中間層の中板部は、セラミック材料により平面視矩形状に形成された一枚板のものであり、前記上層の第3堤部は、前記中間層の中板部の上にセラミック材料により平面視枠形状に積層され、前記下層の第4堤部は、前記中間層の中板部の下にセラミック材料により平面視枠形状に積層され、前記ベースの収納部は、前記上層の第3堤部により形成されて前記圧電振動素子が収納される第3収納部と、前記下層の第4堤部により形成されて前記集積回路素子が収納される第4収納部とにより形成され、前記第4収納部の内底面に、前記第1~第3内部端子パッドが形成されている、請求項1に記載の圧電発振器。
- 前記2つの対向する第1内部端子パッドを前記ベースの前記矩形4角の4つのキャスタレーションのうち、前記第1および前記第2キャスタレーションにそれぞれ延出する2つの第1配線パターンと、前記2つの対向する第2内部端子パッドを前記第1および前記第2キャスタレーションに対向する残り2つのキャスタレーションにそれぞれ延出する2つの第2配線パターンと、前記2つの対向する第3内部端子パッドそれぞれを延出する前記2つの配線パターンから前記ベースの内底面の端部にまで、前記ベースの短辺方向に延出された2つのノイズ遮断用配線パターンと、を有する、請求項3に記載の圧電発振器。
- 前記中間層の前記セラミック基板層のキャスタレーションが、前記最上層と前記最下層の前記セラミック基板層それぞれのうちの少なくとも一方のキャスタレーションより相対的に内奥に凹んでいる、請求項1に記載の圧電発振器。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014520871A JP6075375B2 (ja) | 2012-06-19 | 2013-03-27 | 表面実装型圧電発振器 |
| CN201380025011.9A CN104285372B (zh) | 2012-06-19 | 2013-03-27 | 表面安装型压电振荡器 |
| US14/406,317 US9831414B2 (en) | 2012-06-19 | 2013-03-27 | Surface mounted piezoelectric vibrator |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012137447 | 2012-06-19 | ||
| JP2012-137447 | 2012-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2013190749A1 true WO2013190749A1 (ja) | 2013-12-27 |
Family
ID=49768364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2013/002095 Ceased WO2013190749A1 (ja) | 2012-06-19 | 2013-03-27 | 表面実装型圧電発振器 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9831414B2 (ja) |
| JP (1) | JP6075375B2 (ja) |
| CN (1) | CN104285372B (ja) |
| TW (1) | TWI521872B (ja) |
| WO (1) | WO2013190749A1 (ja) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015053536A (ja) * | 2013-09-05 | 2015-03-19 | 日本電波工業株式会社 | 電子部品及び電子部品パッケージ |
| JP2015211361A (ja) * | 2014-04-28 | 2015-11-24 | 日本電波工業株式会社 | 圧電デバイス |
| JP2015226189A (ja) * | 2014-05-28 | 2015-12-14 | 株式会社大真空 | 表面実装型圧電デバイス |
| JP2016082548A (ja) * | 2014-10-22 | 2016-05-16 | Ngkエレクトロデバイス株式会社 | 電子部品収納用パッケージ及びこれを用いる圧電発振器の製造方法 |
| JP2017034328A (ja) * | 2015-07-29 | 2017-02-09 | 株式会社大真空 | 圧電振動デバイス |
| JP2020022017A (ja) * | 2018-07-31 | 2020-02-06 | 株式会社大真空 | 圧電振動デバイス |
| JP2020156008A (ja) * | 2019-03-22 | 2020-09-24 | 日本電波工業株式会社 | 水晶発振器 |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6167494B2 (ja) * | 2012-09-26 | 2017-07-26 | セイコーエプソン株式会社 | 電子デバイス用容器の製造方法、電子デバイスの製造方法、電子デバイス、電子機器及び移動体機器 |
| US9293683B2 (en) * | 2014-05-12 | 2016-03-22 | Panasonic Intellectual Property Management Co., Ltd. | Method for connecting piezoelectric element and cable substrate, piezoelectric element having cable substrate, and inkjet head including piezoelectric element with cable substrate |
| JP6338205B2 (ja) * | 2015-11-05 | 2018-06-06 | 株式会社村田製作所 | 圧電発振器及び圧電発振デバイス |
| US9825597B2 (en) | 2015-12-30 | 2017-11-21 | Skyworks Solutions, Inc. | Impedance transformation circuit for amplifier |
| US10062670B2 (en) | 2016-04-18 | 2018-08-28 | Skyworks Solutions, Inc. | Radio frequency system-in-package with stacked clocking crystal |
| US10362678B2 (en) * | 2016-04-18 | 2019-07-23 | Skyworks Solutions, Inc. | Crystal packaging with conductive pillars |
| US10297576B2 (en) | 2016-04-18 | 2019-05-21 | Skyworks Solutions, Inc. | Reduced form factor radio frequency system-in-package |
| JP1565481S (ja) * | 2016-05-25 | 2016-12-19 | ||
| USD857020S1 (en) * | 2016-05-25 | 2019-08-20 | Tdk Corporation | Piezoelectric element |
| US11152911B2 (en) * | 2016-09-16 | 2021-10-19 | Daishinku Corporation | Piezoelectric resonator device |
| WO2018092572A1 (ja) * | 2016-11-16 | 2018-05-24 | 株式会社大真空 | 水晶振動デバイス |
| TWI859783B (zh) | 2016-12-29 | 2024-10-21 | 美商天工方案公司 | 前端系統、無線通信裝置及封裝前端模組 |
| US10515924B2 (en) | 2017-03-10 | 2019-12-24 | Skyworks Solutions, Inc. | Radio frequency modules |
| AU2019225148B2 (en) * | 2018-02-22 | 2024-08-15 | Dexcom, Inc. | Sensor interposers employing castellated through-vias |
| JP2019153851A (ja) * | 2018-02-28 | 2019-09-12 | セイコーエプソン株式会社 | 発振器、電子機器および移動体 |
| CN108982668B (zh) * | 2018-08-02 | 2021-09-24 | 武汉科技大学 | 传播方向可选、谐振频率可调的压电智能骨料 |
| KR102775371B1 (ko) * | 2019-10-30 | 2025-03-04 | 삼성전자 주식회사 | 발진기 구조체 및 발진기 구조체를 포함하는 전자 장치 |
| JP2022134786A (ja) * | 2021-03-04 | 2022-09-15 | セイコーエプソン株式会社 | 振動デバイス |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000151283A (ja) * | 1998-08-31 | 2000-05-30 | Kyocera Corp | 表面実装型水晶発振器 |
| JP2002100932A (ja) * | 2000-09-22 | 2002-04-05 | Kyocera Corp | 圧電発振器 |
| JP2002176318A (ja) * | 2000-09-27 | 2002-06-21 | Citizen Watch Co Ltd | 圧電発振器及びその実装構造 |
| JP2003133857A (ja) * | 2001-10-22 | 2003-05-09 | Citizen Watch Co Ltd | 発振器 |
| JP2005198227A (ja) * | 2003-03-20 | 2005-07-21 | Seiko Epson Corp | 圧電振動子 |
| JP2006101276A (ja) * | 2004-09-30 | 2006-04-13 | Epson Toyocom Corp | 圧電発振器 |
| JP2007235544A (ja) * | 2006-03-01 | 2007-09-13 | Daishinku Corp | 圧電振動デバイスおよびその製造方法 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229249B1 (en) * | 1998-08-31 | 2001-05-08 | Kyocera Corporation | Surface-mount type crystal oscillator |
| JP2001291742A (ja) * | 2000-04-06 | 2001-10-19 | Nippon Dempa Kogyo Co Ltd | Icチップの接合方法及びこれを用いた水晶発振器 |
| US6587008B2 (en) | 2000-09-22 | 2003-07-01 | Kyocera Corporation | Piezoelectric oscillator and a method for manufacturing the same |
| US6703768B2 (en) | 2000-09-27 | 2004-03-09 | Citizen Watch Co., Ltd. | Piezoelectric generator and mounting structure therefor |
| DE60238959D1 (de) * | 2001-04-18 | 2011-02-24 | Epson Toyocom Corp | Piezoelektrischer Oszillator und Verfahren zu dessen Herstellung |
| US7266869B2 (en) * | 2003-07-30 | 2007-09-11 | Kyocera Corporation | Method for manufacturing a piezoelectric oscillator |
| JP4395044B2 (ja) | 2003-10-22 | 2010-01-06 | パナソニック株式会社 | 変調装置及び変調方法 |
| US7098580B2 (en) * | 2004-01-29 | 2006-08-29 | Kyocera Corporation | Piezoelectric oscillator |
| JP3841304B2 (ja) * | 2004-02-17 | 2006-11-01 | セイコーエプソン株式会社 | 圧電発振器、及びその製造方法 |
| JP5034947B2 (ja) * | 2005-09-30 | 2012-09-26 | 株式会社大真空 | 圧電振動デバイス |
| US7602107B2 (en) * | 2005-11-30 | 2009-10-13 | Nihon Dempa Kogyo Co., Ltd. | Surface mount type crystal oscillator |
| JP5059478B2 (ja) * | 2007-04-26 | 2012-10-24 | 日本電波工業株式会社 | 表面実装用の圧電発振器及び圧電振動子 |
| US8279610B2 (en) * | 2007-08-23 | 2012-10-02 | Daishinku Corporation | Electronic component package, base of electronic component package, and junction structure of electronic component package and circuit substrate |
| JP5731880B2 (ja) * | 2010-10-15 | 2015-06-10 | 日本電波工業株式会社 | 圧電デバイス及び圧電デバイスの製造方法 |
| CN202535316U (zh) * | 2011-03-09 | 2012-11-14 | 精工爱普生株式会社 | 振动元件、振子、振荡器以及电子设备 |
-
2013
- 2013-03-27 JP JP2014520871A patent/JP6075375B2/ja active Active
- 2013-03-27 US US14/406,317 patent/US9831414B2/en active Active
- 2013-03-27 WO PCT/JP2013/002095 patent/WO2013190749A1/ja not_active Ceased
- 2013-03-27 CN CN201380025011.9A patent/CN104285372B/zh active Active
- 2013-04-19 TW TW102113928A patent/TWI521872B/zh active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000151283A (ja) * | 1998-08-31 | 2000-05-30 | Kyocera Corp | 表面実装型水晶発振器 |
| JP2002100932A (ja) * | 2000-09-22 | 2002-04-05 | Kyocera Corp | 圧電発振器 |
| JP2002176318A (ja) * | 2000-09-27 | 2002-06-21 | Citizen Watch Co Ltd | 圧電発振器及びその実装構造 |
| JP2003133857A (ja) * | 2001-10-22 | 2003-05-09 | Citizen Watch Co Ltd | 発振器 |
| JP2005198227A (ja) * | 2003-03-20 | 2005-07-21 | Seiko Epson Corp | 圧電振動子 |
| JP2006101276A (ja) * | 2004-09-30 | 2006-04-13 | Epson Toyocom Corp | 圧電発振器 |
| JP2007235544A (ja) * | 2006-03-01 | 2007-09-13 | Daishinku Corp | 圧電振動デバイスおよびその製造方法 |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015053536A (ja) * | 2013-09-05 | 2015-03-19 | 日本電波工業株式会社 | 電子部品及び電子部品パッケージ |
| JP2015211361A (ja) * | 2014-04-28 | 2015-11-24 | 日本電波工業株式会社 | 圧電デバイス |
| JP2015226189A (ja) * | 2014-05-28 | 2015-12-14 | 株式会社大真空 | 表面実装型圧電デバイス |
| JP2016082548A (ja) * | 2014-10-22 | 2016-05-16 | Ngkエレクトロデバイス株式会社 | 電子部品収納用パッケージ及びこれを用いる圧電発振器の製造方法 |
| JP2017034328A (ja) * | 2015-07-29 | 2017-02-09 | 株式会社大真空 | 圧電振動デバイス |
| JP2020022017A (ja) * | 2018-07-31 | 2020-02-06 | 株式会社大真空 | 圧電振動デバイス |
| JP7044005B2 (ja) | 2018-07-31 | 2022-03-30 | 株式会社大真空 | 圧電振動デバイス |
| JP2020156008A (ja) * | 2019-03-22 | 2020-09-24 | 日本電波工業株式会社 | 水晶発振器 |
| JP7307569B2 (ja) | 2019-03-22 | 2023-07-12 | 日本電波工業株式会社 | 水晶発振器 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104285372B (zh) | 2017-07-04 |
| TW201401772A (zh) | 2014-01-01 |
| CN104285372A (zh) | 2015-01-14 |
| JPWO2013190749A1 (ja) | 2016-02-08 |
| US20150162521A1 (en) | 2015-06-11 |
| JP6075375B2 (ja) | 2017-02-08 |
| TWI521872B (zh) | 2016-02-11 |
| US9831414B2 (en) | 2017-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6075375B2 (ja) | 表面実装型圧電発振器 | |
| JP6107810B2 (ja) | 表面実装型圧電発振器 | |
| JP4795602B2 (ja) | 発振器 | |
| TWI559583B (zh) | Electronic components for the package and piezoelectric vibration components | |
| JP6020663B2 (ja) | 発振器 | |
| JP2010062959A (ja) | 表面実装型圧電発振器およびその特性測定方法 | |
| JP5910351B2 (ja) | 表面実装型圧電発振器 | |
| JP7605025B2 (ja) | 圧電振動デバイス | |
| JP2014187641A (ja) | 表面実装型圧電発振器 | |
| JP6098255B2 (ja) | 表面実装型圧電発振器 | |
| JP6131798B2 (ja) | 表面実装型圧電発振器 | |
| JP2013172258A (ja) | 水晶発振器 | |
| JP6098224B2 (ja) | 表面実装型圧電発振器 | |
| JP2018074350A (ja) | 表面実装型圧電発振器とその回路基板への搭載構造 | |
| JP6024514B2 (ja) | 表面実装型圧電発振器 | |
| JP2023046287A (ja) | 表面実装型圧電発振器 | |
| JP2013207512A (ja) | 表面実装型圧電発振器 | |
| JP2013207511A (ja) | 表面実装型圧電発振器 | |
| JP2017046265A (ja) | 表面実装型圧電フィルタ | |
| JP2019047308A (ja) | 圧電発振器 | |
| JP2017046267A (ja) | 表面実装型圧電フィルタ | |
| JP2017046266A (ja) | 表面実装型圧電フィルタ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13806265 Country of ref document: EP Kind code of ref document: A1 |
|
| ENP | Entry into the national phase |
Ref document number: 2014520871 Country of ref document: JP Kind code of ref document: A |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 14406317 Country of ref document: US |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 13806265 Country of ref document: EP Kind code of ref document: A1 |