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WO2013183531A1 - Dispositif d'affichage et son procédé de pilotage - Google Patents

Dispositif d'affichage et son procédé de pilotage Download PDF

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Publication number
WO2013183531A1
WO2013183531A1 PCT/JP2013/064998 JP2013064998W WO2013183531A1 WO 2013183531 A1 WO2013183531 A1 WO 2013183531A1 JP 2013064998 W JP2013064998 W JP 2013064998W WO 2013183531 A1 WO2013183531 A1 WO 2013183531A1
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WIPO (PCT)
Prior art keywords
voltage
power supply
gate
tft
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2013/064998
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English (en)
Japanese (ja)
Inventor
正史 大坪
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • the present invention relates to a display device, and more particularly, to a technique for discharging charges accumulated in each display pixel when a power interruption occurs.
  • a liquid crystal display device is known as an example of a display device.
  • a liquid crystal display device a system in which a plurality of pixel electrodes are driven by thin film transistors (TFTs) is widely adopted.
  • TFTs thin film transistors
  • Such a method is called an active matrix method.
  • Such an active matrix type liquid crystal display device includes a gate wiring arranged on a substrate for supplying a signal to a thin film transistor, and a plurality of source wirings arranged above the gate wiring so as to cross the gate wiring.
  • Patent Document 1 discloses a display in which a plurality of display pixels are two-dimensionally arranged in the vicinity of intersections of a plurality of gate lines and a plurality of source lines arranged orthogonal to each other.
  • a display device including a source driver for applying a display signal voltage is disclosed.
  • a display device generates a plurality of drive voltages defining at least the voltage levels of a scanning signal and a display signal voltage based on a predetermined drive power, and a gate driver And a power supply voltage supply circuit for supplying the source driver.
  • the power supply voltage supply circuit generates a drive voltage having a ground potential and supplies it to the gate driver when the supply of drive power is cut off due to the power supply battery dropping off or the like.
  • a scanning signal having a ground potential is supplied to all the gate wirings constituting the display panel, all the display pixels are set to a selected state, and the electric charge accumulated in each display pixel is set to a predetermined potential (common signal). Voltage).
  • the power supply voltage supply circuit uses a negative voltage as a drive voltage to the gate driver in a state in which display drive is performed in which drive power is normally supplied from the power supply battery.
  • the driving voltage having a negative voltage is quickly transferred to the ground potential, and the pixel transistor (pixel TFT) provided in each display pixel
  • the voltage level of the scanning signal applied to the gate wiring is controlled so as to turn on. As a result, the electric charge accumulated in each display pixel is discharged, and the occurrence of an afterimage in which the display image gradually disappears with the occurrence of power interruption is suppressed.
  • a turn-on operation of the pixel transistor can be promoted by applying a scanning signal having a positive voltage to the pixel transistor due to the characteristics of the TFT.
  • a scanning signal having a positive voltage to the pixel transistor due to the characteristics of the TFT.
  • Patent Document 1 described above, even in the case where a power interruption occurs, the configuration for controlling the voltage level of the scanning signal applied from the gate driver to the gate wiring is controlled according to the specifications of the gate driver. The voltage level of possible scanning signals is limited. As a result, it has been difficult to quickly discharge the charge accumulated in each display pixel.
  • the present invention has been made to solve such problems, and an object of the present invention is to quickly store charges accumulated in each display pixel when a power interruption occurs in an active matrix display device. It is to discharge.
  • a display device includes a plurality of gate wirings and a plurality of source wirings arranged orthogonal to each other, and a plurality of display devices arranged corresponding to intersections of the plurality of gate wirings and the plurality of source wirings.
  • a display panel including a display pixel, a gate driver that sets each display pixel to a selected state by sequentially applying a scanning signal to a plurality of gate wirings, and a selected state through each source wiring
  • a source driver that applies a display signal voltage to a display pixel, and a power supply voltage that generates a drive voltage having a voltage level that sets at least the display pixel to a selected state using a power supply voltage supplied from the power supply and supplies the drive voltage to the gate driver
  • a generator, a monitoring unit that monitors the power supply voltage, and a plurality of gate wirings and a power supply voltage generating unit are provided, respectively.
  • the active matrix display device it is possible to quickly discharge the electric charge accumulated in each display pixel when the power is cut off.
  • FIG. 2 is a configuration diagram of an analog power supply generation unit, a power supply monitoring circuit, and a SW_TFT control signal generation unit shown in FIG. 1. It is a figure explaining operation
  • FIG. It is a block diagram which shows one Embodiment of the liquid crystal display device to which the display apparatus by Embodiment 2 of this invention is applied. It is a figure which shows the time change of the voltage applied to pixel TFT and switch TFT.
  • FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device to which a display device according to Embodiment 1 of the present invention is applied.
  • a liquid crystal display device 100 includes a display panel 10 in which a plurality of display pixels 1 are arranged in a matrix, a gate driver 20, a source driver 30, a timing controller 40, a power supply 50, an analog, and the like.
  • a power generation unit 60 is provided.
  • the display panel 10 includes a plurality of gate wirings 12 and a plurality of source wirings 14, a plurality of gate wirings 12, and a plurality of source wirings 14 that are disposed between opposing transparent substrates (not shown). And a plurality of display pixels 1 arranged corresponding to the intersections.
  • Each display pixel 1 includes a pixel electrode 4, an auxiliary capacitance electrode 6, and a thin film transistor (TFT) 2.
  • the TFT 2 has a drain electrode connected to the pixel electrode 4, a source electrode connected to the source wiring 14, and a gate electrode connected to the gate wiring 12.
  • the display pixel 1 is connected in parallel to a liquid crystal capacitor composed of liquid crystal molecules filled and held between the pixel electrode 4 and a common electrode (counter electrode) disposed opposite to the pixel electrode 4, And a storage capacitor for holding a signal voltage applied to the liquid crystal capacitor.
  • the gate driver 20 sequentially scans the display pixel group in each row of the display panel 10 and sets it to the selected state.
  • the source driver 30 collectively outputs display signal voltages based on the video signal to the display pixel group in the row set to the selected state.
  • the gate driver 20 sequentially applies a scanning signal (hereinafter also referred to as “gate driver output”) to the plurality of gate wirings 12 to set the display pixel group in each row to a selected state.
  • the source driver 30 applies a display signal voltage (hereinafter also referred to as “source driver output”) to each display pixel 1 via each source line 14 in synchronization with the timing at which the display pixel group in each row is selected. Supply all at once.
  • a common signal voltage Vcom having an inverted polarity with respect to the display signal voltage is applied to the counter electrode.
  • the timing controller 40 controls the operation timing of the gate driver 20 and the source driver 30 based on a video signal input from the outside of the apparatus. Note that the timing controller 40 and the source driver 30 are connected via a data signal line 32 constituted by a pair of operation signal lines. A differential digital data signal is supplied from the timing controller 40 to the source driver 30 via the data signal line 32.
  • the desired image information based on the video signal is displayed on the display panel 10 by repeatedly executing the series of operations described above for each row for one screen.
  • the TFT 2 is used as a switching element (hereinafter also referred to as “pixel transistor”) for supplying a display signal voltage to the pixel electrode 4, hereinafter, the TFT 2 is referred to as “pixel TFT (or , LCD_TFT) ”.
  • the power supply 50 is a DC power supply whose negative electrode side is connected to the ground voltage (0 V), and supplies a power supply voltage Vpower (for example, 3.3 V) to the gate driver 20, source driver 30, and analog power supply generation unit 60. To do.
  • Vpower for example, 3.3 V
  • the analog power generation unit 60 uses the power supply voltage Vpower supplied from the power supply 50 to generate a drive voltage necessary for display driving of the display panel 10. For example, the analog power supply generation unit 60 generates the drive voltage VGH from the power supply voltage Vpower and supplies it to the gate driver 20.
  • the gate driver 20 is based on the drive voltage VGH supplied from the analog power supply generation unit 60, the voltage (ON voltage: positive voltage) VGH that defines the high level of the scanning signal, and the voltage that defines the low level of the scanning signal ( Off-voltage: negative voltage) VGL.
  • the display device 100 performs the display drive of the image information described above based on the power supply voltage Vpower supplied from the power supply 50.
  • the power supply voltage Vpower supplied from the power supply 50 to the gate driver 20, the source driver 30 and the analog power supply generation unit 60 shifts to the ground voltage.
  • the drive voltage VGH supplied from the analog power generation unit 60 to the gate driver 20 also gradually shifts to the ground voltage.
  • the drive voltage VGH reaches the ground voltage at a speed slower than the power supply voltage Vpower due to free discharge of the capacitor and load capacitance provided in the analog power supply generation unit 60.
  • the scanning signal applied to the gate wiring 12 is set to the off voltage VGL (negative voltage) after the power supply is cut off.
  • VGL negative voltage
  • the pixel TFT2 is controlled to be in an OFF state, so that charges accumulated in each display pixel (liquid crystal capacitor, storage capacitor) for displaying image information are held.
  • the scanning drive of the display panel 10 is stopped for a relatively long time after the power supply is cut off, and the accumulated charge is held in the display pixel 1, and the image information is gradually increased along with the discharge of the accumulated charge. An afterimage disappears. Thereby, display quality deteriorates.
  • the display device 100 includes a SW_TFT block 90 disposed adjacent to the display panel 10 in the row direction as a configuration for discharging the accumulated charge of each display pixel 1 after the power is shut off, A monitoring circuit 70 and a SW_TFT control signal generation unit 80 are further provided.
  • the SW_TFT block 90 includes a plurality of TFTs 92 arranged in the column direction of the display panel 10, and gate wirings 94 and source wirings 96 arranged in parallel with the plurality of source wirings 14.
  • Each TFT 92 is disposed at the intersection of each gate line 12 and source line 96.
  • the TFT 92 has a drain connected to the gate wiring 12, a source connected to the source wiring 96, and a gate connected to the gate wiring 94.
  • the TFT 92 is formed on the same substrate as the pixel TFT 2 included in the display pixel 1.
  • the TFT 92 can be integrally formed with the same structure and the same process as the pixel TFT 2.
  • the gate wiring 94 is connected to the SW_TFT control signal generation unit 80.
  • the gate wiring 94 applies a control signal supplied from the SW_TFT control signal generation unit 80 to the gate of the TFT 92.
  • the source wiring 96 is connected to the analog power supply generation unit 60. As shown in FIG. 1, the drive voltage VGH generated by the analog power supply generation unit 60 is supplied to the gate driver 20 and the source wiring 96.
  • the source wiring 96 applies the supplied drive voltage VGH to the source of the TFT 92.
  • each TFT 92 included in the SW_TFT block 90 transmits the driving voltage VGH output from the analog power supply generation unit 60 to the gate wiring 12 when turned on in response to the control signal.
  • the drive voltage VGH corresponds to the on-voltage (positive voltage) of the scanning signal output from the gate driver 20 during the display drive. Accordingly, the pixel TFT2 receives the drive voltage VGH (on voltage) and is driven to an on state.
  • the TFT 92 is used as a transistor (hereinafter also referred to as “switch transistor”) for controlling the signal level of the scanning signal supplied to the gate wiring 12 instead of the gate driver 20.
  • the TFT 92 is also referred to as “switch TFT (or SW_TFT)” in order to distinguish it from the pixel TFT 2.
  • the power supply monitoring circuit 70 includes a detection circuit that detects the power supply voltage Vpower supplied from the power supply 50.
  • the power monitoring circuit 70 generates a reference voltage Vref based on the detected value of the power supply voltage Vpower, and outputs the generated reference voltage Vref to the SW_TFT control signal generator 80.
  • the reference voltage Vref generated by the power supply monitoring circuit 70 is variably set according to the voltage level of the power supply voltage Vpower. Specifically, when the voltage level of the power supply voltage Vpower is lowered, the reference voltage Vref is set low.
  • the SW_TFT control signal generation unit 80 receives the drive voltage (VGH + ⁇ ) from the analog power supply generation unit 60 and the reference voltage Vref from the power supply monitoring circuit 70.
  • the drive voltage (VGH + ⁇ ) corresponds to the output voltage of the charge pump circuit included in the analog power supply generation unit 60, as will be described later.
  • the control signal generated by the SW_TFT control signal generation unit 80 is supplied to the gate wiring 94. That is, the voltage of the control signal is the gate voltage of the switch TFT 92 (hereinafter also referred to as “VG (SW_TFT)”).
  • the analog power supply generation unit 60, the power supply monitoring circuit 70, and the SW_TFT control signal generation unit 80 will be further described.
  • Analog power generation unit 60 includes a DC / DC converter 62, a charge pump circuit 64, a resistor R1, and a Zener diode ZD.
  • the DC / DC converter 62 is configured by, for example, a boost chopper circuit.
  • DC / DC converter 62 includes a reactor L1, a transistor Tr0, a diode D0, a capacitor C0, and a resistor R0.
  • the transistor Tr0, the capacitor C0, and the resistor R0 are connected in parallel between the positive terminal and the negative terminal of the DC power source that constitutes the power source 50.
  • Reactor L1 is connected between the positive terminal of the DC power supply and the collector of transistor Tr0.
  • the diode D0 is connected between the collector of the transistor Tr0 and one end of the capacitor C0.
  • the transistor Tr0 performs a switching operation in response to a switching command from a control unit (not shown), thereby generating a voltage V2 that is a voltage obtained by boosting the power supply voltage Vpower. More specifically, since the power supply voltage Vpower is short-circuited through the reactor L1 and a current flows during the ON period of the transistor Tr0, the magnetic flux level of the reactor L1 rises. During the off period of the transistor Tr0, a voltage is generated in the reactor L1, and the voltage is added to the power supply voltage Vpower, so that the diode D0 is turned on. As a result, the voltage V2 is raised from the power supply voltage Vpower. This voltage V2 is supplied to the charge pump circuit 64 together with the voltage V1 at the connection node of the reactor L1 and the diode D0.
  • the charge pump circuit 64 includes capacitors C1, C2, C3 and diodes D1, D2.
  • One end of capacitor C1 is connected to a connection node of reactor L1 and diode D0, and the other end is connected to an anode (anode) of diode D1 and a cathode (cathode) of diode D2.
  • One end of the capacitor C2 is connected to the cathode of the diode D1, and the other end is connected to the anode of the diode D2.
  • One end of the capacitor C3 is connected to the anode of the diode D2, and the other end is connected to the cathode of the diode D0 of the DC / DC converter 62.
  • the charge pump circuit 64 receives the voltage V1 at one end of the capacitor C1 and the voltage V2 at the other end of the capacitor C3.
  • the charge pump circuit 64 repeatedly performs a charging operation and a discharging operation in accordance with a difference between the voltage V2 and the voltage V1 that changes in a rectangular wave shape according to the switching operation of the transistor Tr0, whereby a predetermined voltage ⁇ is obtained from the driving voltage VGH.
  • the charge pump circuit 64 outputs the generated drive voltage (VGH + ⁇ ) to the output line 66.
  • a series circuit composed of a resistor R1 and a Zener diode ZD is connected between an output line 66 to which a drive voltage (VGH + ⁇ ) is applied and a ground node 8 to which a ground voltage (0 V) is applied.
  • Zener diode ZD has a cathode connected to resistor R 1 and an anode connected to ground node 8.
  • a connection node (corresponding to a node N1 in the drawing) of the resistor R1 and the Zener diode ZD constitutes an output node of the analog power supply generation unit 60.
  • the output node N1 is electrically connected to the gate driver 20 and the source wiring 96 (FIG. 1).
  • the Zener diode ZD uses the drive voltage VGH as the breakdown voltage. Therefore, the voltage of the Zener diode ZD is almost constant (drive voltage VGH) even if the reverse current changes. As a result, a constant voltage (drive voltage VGH) is output to the output node N1 of the analog power supply generation unit 60.
  • the gate driver 20 generates an on-voltage of the scanning signal based on the driving voltage VGH. That is, the drive voltage VGH is the gate voltage of the pixel TFT 2 (hereinafter also referred to as “VG (LCD_TFT)”). Further, the drive voltage VGH is supplied to the source wiring 96 to become the source voltage of the switch TFT 92 (hereinafter also referred to as “VS (SW_TFT)”).
  • SW_TFT control signal generator 80 is connected to the output line 66 of the charge pump circuit 64.
  • SW_TFT control signal generator 80 includes a resistor R4 and a transistor Tr1 connected in series between output line 66 and ground node 8.
  • the transistor Tr1 has a collector connected to the resistor R4, an emitter connected to the ground node 8, and a base connected to the output node (corresponding to the node N3 in the figure) of the power supply monitoring circuit 70.
  • a connection node (corresponding to a node N2 in the drawing) of the resistor R4 and the transistor Tr1 constitutes an output node of the SW_TFT control signal generation unit 80.
  • Power supply monitoring circuit 70 includes resistors R2 and R3 connected in series between power supply node 9 that receives power supply voltage Vpower from power supply 50 and ground node 8. Connection node N3 of resistors R2 and R3 constitutes an output node of power supply monitoring circuit 70.
  • the power supply monitoring circuit 70 divides the power supply voltage Vpower to generate a reference voltage Vref proportional to the power supply voltage Vpower.
  • the reference voltage Vref generated by the power supply monitoring circuit 70 is input to the base of the transistor Tr1 of the SW_TFT control signal generation unit 80 via the output node N3.
  • the base-emitter voltage VBE when the transistor Tr1 is turned on is Vf (for example, 0.7V)
  • Vref the reference voltage
  • Vref> Vf the reference voltage
  • the transistor Tr1 is turned on.
  • a control signal having a ground voltage is output from the output node N2.
  • the reference voltage Vref can be variably set by adjusting the resistance values of the resistors R2 and R3.
  • determination value Vpower_th is set for power supply voltage Vpower.
  • This determination value Vpower_th is a threshold value (for example, 2.7 V) for determining whether or not the power supply is shut off.
  • the power supply monitoring circuit 70 compares the power supply voltage Vpower and the determination value Vpower_th, and detects power interruption based on the comparison result.
  • the reference voltage Vref becomes higher than Vf, so that the transistor Tr1 is turned on and the SW_TFT control signal A control signal having a ground voltage is output from output node N2 of generation unit 80.
  • the SW_TFT control signal generation unit 80 generates a control signal for controlling on / off of the switch TFT 92 by using the drive voltage (VGH + ⁇ ) generated by the analog power supply generation unit 60 and outputs the control signal to the gate wiring 94.
  • FIG. 3 shows the display panel 10 and the SW_TFT block 90 extracted from the display device according to the first embodiment.
  • one display pixel 1 is representatively shown in the display panel 10
  • one switch TFT 92 is representatively shown in the SW_TFT block 90.
  • a scanning signal (gate driver output) applied from gate driver 20 (FIG. 1) to gate wiring 12.
  • the display signal voltage (source driver output) is applied to the display pixel 1 via the source line 14.
  • a common signal voltage Vcom having an inverted polarity with respect to the display signal voltage is applied to the counter electrode.
  • the power supply voltage Vpower and the drive voltage VGH supplied to the gate driver 20 shift to the ground voltage.
  • the gate driver output is set to the drive voltage VGL. Since the drive voltage VGL corresponds to the off voltage (negative voltage) of the scanning signal, the pixel TFT 2 is controlled to be in the off state. Therefore, the charge accumulated in each display pixel 1 is held.
  • FIG. 4 is a diagram showing temporal changes in voltages applied to the pixel TFT 2 and the switch TFT 92.
  • the power supply voltage Vpower starts to decrease from the time when the power cut-off occurs (time t1) and the power supply voltage Vpower reaches the determination value Vpower_th at the subsequent time t2
  • the drive voltage from the SW_TFT control signal generator 80 to the gate wiring 94 is set.
  • a control signal having a voltage equal to (VGH + ⁇ ) is supplied.
  • the gate voltage VG (SW_TFT) of the switch TFT 92 changes from the ground voltage to the drive voltage (VGH + ⁇ ).
  • VG control signal
  • VGH ON voltage
  • the driving voltage VGH (on-voltage) is applied from the analog power generation unit 60 to the gate wiring 12 via the switch TFT 92 that is driven to be turned on by detecting power-off. ).
  • the driving voltage VGH ON voltage
  • the driving voltage VGH ON voltage
  • FIG. 5 and 6 are diagrams for explaining the operation of the display pixel 1 when the power is shut off in the conventional display device.
  • FIG. 5 shows an extracted display panel 10 of a conventional display device.
  • one display pixel 1 is shown as a representative.
  • FIG. 6 shows temporal changes in the voltage applied to the pixel TFT 2 in FIG.
  • the configuration of the display panel 10 is the same as that shown in FIG. 1, and therefore detailed description will not be repeated. Further, the operation of the display pixel 1 during normal driving is the same as that in the first embodiment, and thus detailed description will not be repeated.
  • the scanning signal supplied from the gate driver (not shown) to each gate line 12 is set to the off voltage (VGL).
  • VGL the off voltage
  • the drain voltage of the pixel TFT 2 (hereinafter also referred to as “VD (LCD_TFT)”) is held at the voltage level VLS corresponding to the accumulated charge.
  • the source voltage VS (LCD_TFT) of the pixel TFT2 is a ground voltage. Note that the drain voltage VD (LCD_TFT) gradually decreases from the voltage VLS (corresponding to the line k1 in FIG. 6) due to the spontaneous discharge of the accumulated charge after the power is shut off.
  • a power supply voltage supply circuit (not shown) that generates a drive voltage to be supplied to the gate driver and the source driver based on the power supply voltage supplied from the power supply supplies the gate driver to the gate driver when detecting a power shutdown (time t2).
  • the drive voltage is controlled to be equal to or higher than the ground voltage.
  • the pixel TFT 2 is turned on due to an increase in the voltage level of the scanning signal, the charge accumulated in each display pixel 1 is discharged to the common signal voltage Vcom via the pixel TFT 2 and the source line 14.
  • the drain voltage VD (LCD_TFT) of the pixel TFT2 decreases at a faster rate than the natural discharge (corresponding to the line k2 in FIG. 6).
  • the gate driver needs to perform an operation for supplying a desired voltage to the gate wiring 12 even when the power is cut off.
  • a gate driver that is widely used in a display device cannot control the voltage level of the scanning signal in a state where the power supply from the power source is cut off. Therefore, it is necessary to provide a dedicated gate driver in order to realize the above-described operation.
  • the general-purpose gate driver is equipped with a shift register, and is configured to sequentially apply scanning signals from the shift register to the plurality of gate wirings 12 so as to select the display pixel group in each row. Therefore, it is not possible to apply scanning signals to the plurality of gate lines 12 all at once. Therefore, there is a certain limit to the rapidity of discharging the accumulated charge.
  • the gate driver has a function of simultaneously applying a scanning signal to the plurality of gate wirings 12, the number of currents that flow during normal driving when the scanning signal is applied to the plurality of gate wirings 12. Since a hundred times larger current flows through the gate driver, it is necessary to design the circuit scale and wiring space of the gate driver so as to withstand a large current.
  • each switch TFT 92 in the SW_TFT block 90 is used instead of the gate driver 20. Supplies the on-voltage (VGH) to each gate line 12, so that the problem in the gate driver described above can be avoided.
  • VGH on-voltage
  • FIG. 7 collectively describes the operations of the display device 100 according to the first embodiment described above.
  • FIG. 7 shows temporal changes in the voltage applied to the pixel TFT2 and the switch TFT 92, the reference voltage Vref, and the power supply voltage Vpower.
  • the scanning signal supplied from the gate driver 20 to each gate wiring 12 is set to the off voltage (VGL).
  • VGL off-voltage
  • the pixel TFT2 is turned off, the accumulated charge of the display pixel 1 is held. Therefore, the drain voltage VD (LCD_TFT) of the pixel TFT2 is held at the voltage level VLS corresponding to the accumulated charge.
  • the charge accumulated in the display pixel 1 is discharged to a predetermined voltage (common signal voltage Vcom) via the pixel TFT2 and the source line 14. Is done.
  • the drain voltage VD (LCD_TFT) of the pixel TFT2 decreases at a faster speed (corresponding to the line k3 in FIG. 6) than the natural discharge (corresponding to the line k1 in FIG. 6).
  • the on-voltage can be supplied to the gate of the pixel TFT of each display pixel without going through the gate driver.
  • the pixel TFT can be quickly turned on after the power is shut off, and the electric charge accumulated in each display pixel can be discharged.
  • application of a DC voltage to the liquid crystal molecules can be prevented, deterioration of the display panel can be suppressed.
  • the pixel TFTs of the respective display pixels can be simultaneously controlled to be on without using a gate driver, it is possible to easily construct the display device according to the first embodiment using a general-purpose gate driver. It becomes possible.
  • the gate driver employs a configuration in which the scanning signal is supplied to the pixel TFT of each display pixel.
  • the rise of the scanning signal at this time is determined by the operating speed of the gate driver. For this reason, the rising waveform of the scanning signal cannot be adjusted according to the state of the accumulated charge of each display pixel at the time when the power interruption occurs.
  • rapid discharge cannot be performed, and there is a risk that suppression of afterimage generation will be insufficient.
  • the display device can supply a scanning signal to the pixel TFT of each display pixel without using a gate driver, so that the rising waveform of the scanning signal at the time when the power-off is detected can be arbitrarily set. Can be adjusted.
  • a display device capable of adjusting a rising waveform of a scanning signal will be described.
  • FIG. 8 is a block diagram showing an embodiment of a liquid crystal display device to which the display device according to Embodiment 2 of the present invention is applied.
  • liquid crystal display device 100A according to the second embodiment further includes power supply circuit 84 and switch 86, as compared with liquid crystal display device 100 according to the first embodiment shown in FIG.
  • the power supply circuit 84 is electrically connected to the source wiring 96 and is configured to be able to control the drive voltage supplied to the source wiring 96 to an arbitrary voltage.
  • the power supply monitoring circuit 70 divides the power supply voltage Vpower to generate a reference voltage Vref proportional to the power supply voltage Vpower.
  • the power monitoring circuit 70 outputs the generated reference voltage Vref to the SW_TFT control signal generation unit 80 and the switch 86.
  • the switch 86 is connected to the source wiring 96.
  • the switch 86 is turned on / off according to the reference voltage Vref from the power supply monitoring circuit 70.
  • the switch 86 is used as a representative example of an “opening / closing device” that can cut off the transmission path of the driving voltage to the source wiring 96.
  • the switch 86 is turned on.
  • a driving voltage is supplied from the power supply circuit 84 to the source wiring 96. This drive voltage is the source voltage VS (SW_TFT) of the switch TFT 92.
  • the power supply circuit 84 can adjust the rising waveform of the drive voltage supplied to the source wiring 96.
  • the power supply circuit 84 can adjust the rising speed of the drive voltage.
  • the discharge rate of the accumulated charge in each display pixel increases.
  • FIG. 9 shows temporal changes in the voltages applied to the pixel TFT2 and the switch TFT 92 in FIG.
  • LCD_TFT also increases gradually. In other words, by slowing down the rising speed of the drive voltage, the discharge rate of the accumulated charge in each display pixel can be reduced.
  • the discharge rate of the accumulated charges in the display pixel 1 can be controlled. Therefore, for example, when there is a possibility that a large current flows in the display panel 10 when the accumulated charges of the display pixels 1 are discharged all at once, the power supply circuit 84 slows the rising speed of the drive voltage. Therefore, it is possible to prevent the circuit and wiring in the display panel 10 from being damaged by a large current.
  • the output waveform of the drive voltage supplied to the gate wiring via the switch TFT can be adjusted, so that it depends on the state of accumulated charge in the display pixel. Therefore, it is possible to appropriately discharge the accumulated charge.
  • analog power supply generation unit 60 corresponds to an example of “power supply voltage generation unit” in the present invention
  • power supply monitoring circuit 70 corresponds to “monitoring unit” in the present invention
  • the switch TFT 92 corresponds to one embodiment of the “switch transistor” in the present invention
  • the gate line 94 corresponds to an example of “first signal line” in the present invention
  • the source line 96 corresponds to an example of “second signal line” in the present invention
  • the power supply circuit 84 corresponds to the “power supply circuit” in the present invention.
  • oxide semiconductor TFTs have higher field-effect mobility that indicates the ease of movement of evangelistic carriers in the active layer, so they can operate at higher speeds and have higher drive frequencies, resulting in higher definition. It is suitable for application to a drive device for a next-generation display device that is required.
  • the oxide semiconductor film can be formed at room temperature and is in an amorphous state that does not include any crystal grain boundary, transistor characteristics (subthreshold value, current on / off (On / Off) between TFT elements). ) Ratio etc.) variation is small. Therefore, since a TFT having a uniform characteristic even in a large area can be manufactured, application as a driving switching TFT for a large area flat display is promising.
  • the oxide semiconductor in addition to the above-described In—Ga—Zn—O system, a Zn—O system (ZnO), an In—Zn—O system (IZO), a Zn—Ti—O system (ZTO), and the like can be used. Preferably mentioned.
  • the configuration in which the oxide semiconductor TFT is applied to the pixel TFT has a characteristic that the charge accumulated in the display pixel is less likely to be spontaneously discharged than the configuration in which the amorphous silicon TFT is applied.
  • the field effect mobility of the oxide semiconductor TFT is about 10 cm 2 (Vs) ⁇ 1 or more, which is 10 times higher than that of the amorphous silicon TFT, and the on / off ratio is about 10 8 or more.
  • the oxide semiconductor TFT is different from the amorphous silicon TFT in the threshold shift characteristic due to external stress (bias condition, temperature, etc.). Therefore, when an oxide semiconductor TFT is applied to a pixel TFT, it may be difficult to control a scanning signal (gate voltage) applied to the pixel TFT via a gate driver as in a conventional display device. There is.
  • the scanning signal can be controlled without using a gate driver, and the output waveform of the scanning signal can be arbitrarily adjusted. Therefore, the effect of rapid discharge of accumulated charges can be exhibited.
  • the switch TFT in the OFF state during normal driving.
  • the on / off ratio of the oxide semiconductor TFT is as high as about 10 8 or more, it can be easily realized by applying the oxide semiconductor TFT to this switch TFT.
  • the switch TFT is controlled to be in an off state during normal driving, and is controlled to be in an on state when the power is shut off.
  • an oxide semiconductor TFT having a high field effect mobility to the switch TFT, effective switching can be performed.

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Cited By (4)

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CN105301859A (zh) * 2015-11-25 2016-02-03 昆山龙腾光电有限公司 阵列基板和液晶显示装置
CN108281118A (zh) * 2018-01-09 2018-07-13 昆山龙腾光电有限公司 显示面板及液晶显示装置
CN109410878A (zh) * 2018-12-18 2019-03-01 惠科股份有限公司 一种驱动电路、驱动装置以及显示装置
WO2020124703A1 (fr) * 2018-12-18 2020-06-25 惠科股份有限公司 Circuit d'attaque, dispositif d'attaque et dispositif d'affichage

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JP2007011346A (ja) * 2005-06-27 2007-01-18 Samsung Electronics Co Ltd 表示装置及び表示装置用駆動装置
JP2009003207A (ja) * 2007-06-22 2009-01-08 Sharp Corp 表示装置ならびにその駆動回路
WO2009034749A1 (fr) * 2007-09-12 2009-03-19 Sharp Kabushiki Kaisha Registre à décalage

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JP2007011346A (ja) * 2005-06-27 2007-01-18 Samsung Electronics Co Ltd 表示装置及び表示装置用駆動装置
JP2009003207A (ja) * 2007-06-22 2009-01-08 Sharp Corp 表示装置ならびにその駆動回路
WO2009034749A1 (fr) * 2007-09-12 2009-03-19 Sharp Kabushiki Kaisha Registre à décalage

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Publication number Priority date Publication date Assignee Title
CN105301859A (zh) * 2015-11-25 2016-02-03 昆山龙腾光电有限公司 阵列基板和液晶显示装置
CN105301859B (zh) * 2015-11-25 2018-09-18 昆山龙腾光电有限公司 阵列基板和液晶显示装置
CN108281118A (zh) * 2018-01-09 2018-07-13 昆山龙腾光电有限公司 显示面板及液晶显示装置
CN109410878A (zh) * 2018-12-18 2019-03-01 惠科股份有限公司 一种驱动电路、驱动装置以及显示装置
WO2020124703A1 (fr) * 2018-12-18 2020-06-25 惠科股份有限公司 Circuit d'attaque, dispositif d'attaque et dispositif d'affichage
US11335290B2 (en) 2018-12-18 2022-05-17 HKC Corporation Limited Drive circuit, drive device and display device
CN109410878B (zh) * 2018-12-18 2024-05-03 惠科股份有限公司 一种驱动电路、驱动装置以及显示装置

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