Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0008—Arrangements for reducing power consumption
  • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00323—Delay compensation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
  • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

• the field of this invention relates to a sequential logic circuit and a method of providing setup timing violation tolerance within a sequential logic circuit.
• Modern integrated circuit (IC) devices are often required to provide high speed performance, whilst also providing low power consumption.
• power management techniques are typically implemented to enable an IC device to be configured to operate in a plurality of modes depending on the current system requirements.
• an IC device may be configurable to operate in a high speed (high power consumption) mode when high performance is required/desired, and to operate in a low power consumption (low speed) mode when reduced power consumption is required/desired, and/or when high performance is not required.
• a challenge faced when designing digital synchronous systems is to maximise the operating speeds of the digital components whilst ensuring setup and timing violations are avoided.
• This challenge is particularly difficult when implementing a power management technique, since the operating conditions (e.g. voltage, etc.) that affect the ability of a digital system to operate at a certain speed are not constant. Accordingly, it is known to implement setup violation tolerant designs that are able to tolerate minor setup and timing violations.
• FIG. 1 illustrates a simplified block diagram of an example of a typical Razor latch design 100.
• FIG. 2 illustrates a gate level circuit diagram of the Razor latch 100 of FIG. 1.
• Razor latches 100 may be provided within critical paths of an IC device, and often a plurality of such latches may be provided sequentially within a critical path.
• Each Razor latch 100 comprises a main flip-flop 1 10 arranged to receive input data 1 15 during normal operation of the Razor latch 100, and to sample and latch the input data 1 15 upon an active edge (e.g.
• the Razor latch 100 further comprises a shadow latch 125 also arranged to receive the input data 1 15 during normal operation of the Razor latch 100.
• the shadow latch 125 is arranged to sample and latch the input data 1 15 upon an active edge of a clock signal that is delayed with respect to that of the main flip-flop 1 10. In the illustrated example, this is achieved by way of the shadow latch 125 sampling and latching the input data 1 15 on the opposing edge of the clock signal 120 to that of the main flip-flop 1 10 (e.g. the falling edge).
• the outputs of the main flip-flop 1 10 and the shadow latch 125 are provided to a comparator 130, which is arranged to output an error signal upon a mismatch being detected between the outputs of the main flip-flop 1 10 and the shadow latch 125.
• the main flip-flop 1 10 will output the Old' data, resulting in a setup timing violation.
• the shadow latch 125 is arranged to sample and latch the input signal data on a delayed clock edge, assuming the late data is received prior to this late clock edge, the shadow latch 125 will sample and latch the late, 'new' data.
• the output of the shadow latch 125 will differ from the output of the main flip-flop 1 10 (assuming the late data comprises a change of state), which will cause the comparator 130 to output an error signal indicating the detection of late data at the input signal 1 15.
• the Razor latch 100 further comprises a local meta detector arranged to detect meta-stability in the output of the main flip-flop 1 10, for example as a result of a rising clock edge and a data signal arriving at the input thereof substantially simultaneously, and to output an error signal upon detection of such meta-stability.
• the outputs of the local meta detector 135 and the comparator 130 are provided to an OR gate 140, which outputs an error signal indicating an error within the Razor latch 100 caused by either the late receipt of input data or by meta-stability at the output of the main flip-flop 1 10.
• each Razor latch 100 within a signal path may then be provided to a further OR gate 145, which may then output a restore signal 150 arranged to indicate whenever one of the Razor latches 100 within the signal path detects an error.
• This restore signal 150 may then be fed back to a multiplexor 160 within each Razor latch 100 in the signal path to cause the output value of the respective shadow latch 125 to replace the input signal 1 15.
• the Razor latch 100 is held in its current correct state (i.e. even if late data is received, this 'correct' data is used). In this manner, the signal path is allowed to stabilize following a setup timing violation.
• the restore signal 150 may further be used to indicate to a clock driver that a setup timing violation has been detected. For example, and as illustrated in FIG. 3, upon detection of a setup timing violation at a first Razor latch 310, the error signal output by the Razor latch 310 is propagated through an error detect tree to the clock driver 320. Upon receipt of the error signal, the clock driver 320 may then delay the next clock edge to allow the signal path to stabilise following the detection of a setup timing violation, and to prevent corrupted data from propagating to the next latch 330 along the signal path. The clock driver 320 may also be arranged to reconfigure the clock frequency to a lower clock frequency in order to prevent such setup timing violations occurring again. Alternatively, if such setup timing violations occur only occasionally at the current clock frequency, it may be deemed acceptable for the occasional setup timing violation to occur (and be recovered from as described above) in order to achieve a higher system operating frequency.
• a problem with the use of such Razor latches in this manner to recover from setup timing violations is that the clock edge immediately following a setup timing violation must be postponed in order to enable late data to stabilize, and the short window of opportunity for postponing the next clock edge.
• the window of opportunity for delaying the next clock edge is made even shorter due to the time required for the signals to propagate through these trees.
• the use of a Razor latch at a downstream end of a signal path may be made unfeasible due to there being insufficient time between the detection of a setup timing violation at that latch, and the ability to delay the next clock edge for latches located towards the upstream end of the signal path.
• the present invention provides a sequential logic circuit, digital synchronous system comprising at least one such sequential logic circuit, and a method of providing setup timing violation tolerance within a sequential logic circuit as described in the accompanying claims.
• FIG. 1 illustrates a simplified block diagram of an example of a typical Razor latch design.
• FIG. 2 illustrates a gate level circuit diagram of the Razor latch of FIG. 1.
• FIG. 3 illustrates a simplified block diagram of a signal path within a digital synchronous system comprising Razor latches.
• FIG. 4 illustrates a simplified circuit diagram of an example of a sequential logic circuit.
• FIG. 5 illustrates a simplified signal timing diagram for the sequential logic circuit of FIG. 4.
• FIG. 6 illustrates a simplified block diagram of an example of a part of a signal path within a synchronous digital system.
• FIG. 7 illustrates a simplified flowchart of an example of a method of providing setup timing violation tolerance within a sequential logic circuit.
• the sequential logic circuit comprises a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state.
• the sequential logic circuit further comprises a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state.
• the sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.
• the sequential logic circuit 400 comprises a first latch component 410 comprising a data input 412 arranged to receive an input signal, and a data output 414 arranged to output a current logical state of the first latch component 410; for example either a logical (high) state or a logical '0' (low) state.
• the first latch component 410 is further arranged to receive at a clock input 417 thereof a clock signal 420, and is arranged to comprise a transparent state upon the clock signal 420 comprising a first logical state, and to comprise a latched state upon the clock signal 420 comprising a second logical state.
• the current logical state of the first latch component 410 is determined by the logical state of an input signal received at the data input 412 thereof.
• the data output 414 of the first latch component 410 outputs a logical state equal to the logical state of an input signal received at the data input 412.
• the current logical state of the first latch component 410 is 'latched' and maintained irrespective of the logical state of an input signal received at the data input 412 thereof.
• the first latch component 410 comprises a transparent state such that the current logical state of the first latch component 410 is equal to the current logical state of the input signal received at the data input 412 thereof. Accordingly, the signal output by the data output 414 of the first latch component 410 is also equal to the current logical state of the input signal received at the data input 412. Conversely, when the clock signal 420 transitions to the second logical state (e.g.
• the first latch component 410 comprises a latched state, wherein the logical state of the input signal received at the data input 412 is sampled and latched within the first latch component 410. Accordingly, whilst in this latched state, the current logical state of the first latch component 410 will remain equal to the last sampled logical state of the input signal received at the data input 412 upon the transitioning of the clock signal from the first logical state to the second logical state (e.g. on a rising clock edge in the one example), and the signal output by the data output 414 of the first latch component 410 will be equal to this sampled and latched logical state.
• the first latch component 410 illustrated in FIG. 4 comprises a clocked transfer gate 416 arranged to comprise an Open' (transparent) configuration when the clock signal 420 comprises the first logical state and a 'closed' configuration when the clock signal 420 comprises the second logical state.
• the clocked transfer gate 416 is operably coupled between the data input 412 of the first latch component 410 and a latch circuit 418 comprising, in the illustrated example, a pair of cross-coupled inverting elements operably coupled in series.
• a further inverting element 419 is operably between the latch circuit 418 and the data output 414 to counter the inverting effect of the latch circuit 418.
• Such a latch implementation is well known to those skilled in the art, and thus will not be described in any greater detail herein.
• the sequential logic circuit 400 comprises a second latch component 430 comprising a data input 432 arranged to receive an input signal, and a data output 434 arranged to output a current logical state of the second latch component 430.
• the output 434 of the second latch component 430 is operably coupled to (i.e. provides) an output 404 of the sequential logic circuit 400.
• the second latch component 430 is further arranged to receive at a clock input 437 thereof a clock signal, and is arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a first logical state.
• the current logical state of the second latch component 430 is determined by the logical state of an input signal received at the data input 432 thereof.
• the data output 434 of the second latch component 430 outputs a logical state equal to the logical state of an input signal received at the data input 432.
• the current logical state of the second latch component 430 is 'latched' and maintained irrespective of the logical state of an input signal received at the data input 432 thereof.
• the clock signals provided to the first and second latch components 410, 430 are such that a transition of the second latch component 430 from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component 410 from a transparent state to a latched state for a time period for receiving late data.
• this is achieved by way of the second latch component 430 being arranged to receive the same clock signal 420 as received by the first latch component 410, but being arranged to comprise transparent and latched states upon opposing logical states of the clock signal 420 relative to the first latch component 410.
• a time period for receiving late data is provided comprising, in this example, a duty cycle of the clock signal 420 (e.g.
• any other suitable arrangement of clock signals for the latch components 410, 420 may be implemented for providing a suitable delay time period for receiving late data, whereby such a time period is sufficiently long to allow late data to be received (and detected as described below), whilst sufficiently short (relative to a duration of a clock cycle) to provide a suitably long subsequent time period within the same clock cycle to receive new data.
• the second latch component 430 comprises a transparent state such that the current logical state of the second latch component 430 is equal to the current logical state of the input signal received at the data input 432. Accordingly, the signal output by the data output 434 of the second latch component 430 is also equal to the current logical state of the input signal received at the data input 432 of the second latch component 430. Conversely, when the clock signal 420 transitions to the first logical state (e.g.
• the second latch component 430 comprises a latched state, wherein the logical state of the input signal received at the data input 432 is sampled and latched within the second latch component 430. Accordingly, whilst in this latched state, the current logical state of the second latch component 430 will remain equal to the sampled logical state of the input signal received at the data input 432 upon the transitioning of the clock signal 420 from the second logical state thereof to the first logical state thereof (e.g. on a falling clock edge in this example), and the signal output by the data output 434 of the second latch component 430 will be equal to this sampled and latched logical state.
• the second latch component 430 illustrated in FIG. 4 comprises a clocked transfer gate 436 arranged to comprise an Open' (transparent) configuration when the clock signal 420 comprises the second logical state and a 'closed' configuration when the clock signal 420 comprises the first logical state.
• the clocked transfer gate 436 is operably coupled between the data input 432 of the second latch component 430 and a latch circuit 438 comprising a pair of cross-coupled inverting elements.
• a further inverting element 439 is operably between the latch circuit 438 and the data output 434 to counter the inverting effect of the latch circuit 438.
• such a latch implementation is well known to those skilled in the art, and thus will not be described in any greater detail herein.
• first and second latch components 410, 430 may be implemented by way of any suitable alternative latch circuits, for example comprising NOR gates and/or NAND gates as are well known in the art.
• the sequential logic circuit 400 of FIG. 4 is arranged to operate in a first operating mode in which the data input 412 of the first latch component 410 and the data input 432 of the second latch component 430 are operably coupled to a first input 402 of the sequential logic circuit 400.
• the data input 412 of the first latch component 410 is operably coupled to the first input 402 of the sequential logic circuit 400 via a first multiplexer component 450.
• the first multiplexer component 450 comprises a first data input 451 operably coupled to the first input 402 of the sequential logic circuit 400, a second data input 452 operably coupled to a second input 406 of the sequential logic circuit 400, an output 454 operably coupled to the data input 412 of the first latch component 410, and a control input 453 arranged to receive a control signal 460.
• the first multiplexer component 450 is arranged to selectively output to the first latch component 410 a logical state of one of the first input 402 of the sequential logic circuit 400 and the second input 406 of the sequential logic circuit 400 in accordance with the control signal 460 received thereby.
• the data input 432 of the second latch component 430 is operably coupled to the first input 402 of the sequential logic circuit 400 via a second multiplexer component 455.
• the second multiplexer component 455 comprises a first data input 456 operably coupled to the first input 402 of the sequential logic circuit 400, a second data input 457 operably coupled to the output 414 of the first latch component 410, an output 459 operably coupled to the data input 432 of the second latch component 430, and a control input 458 arranged to receive the control signal 460.
• the second multiplexer component 455 is arranged to selectively output to the second latch component 430 a logical state of one of the first input 402 of the sequential logic circuit 400 and the output 414 of the first latch component 410 in accordance with the control signal 460 received thereby.
• both the first and second latch components 410, 430 receive at their respective inputs 412, 432 a data signal received at the first input 402 of the sequential logic circuit 400.
• the first latch component 410 is arranged to sample and latch data received at its input 412 upon a transition of the clock signal 420 from a first logical state (e.g. a low logical state in one example) to a second logical state (e.g. a high logical state in the one example), for example on a rising clock edge.
• the second latch component 430 is arranged to sample and latch data received at its input 432 upon a transition of the clock signal 420 from the second logical state (e.g. a high logical state in the one example) to a first logical state (e.g. a low logical state in the one example), for example on a falling clock edge.
• the second logical state e.g. a high logical state in the one example
• a first logical state e.g. a low logical state in the one example
• FIG. 5 there is illustrated a simplified signal timing diagram 500 of an example of signal states within the sequential logic circuit 400 of FIG. 4 when configured to operate in this first operating mode.
• the clock signal 420 comprises regular transitions between a first logical state, which in the illustrated example comprises a high logical state, and a second logical state, which in the illustrated example comprises a logical low state.
• the clock signal 420 starts with a low logical state.
• the first latch component 410 comprises a transparent state.
• the output 414 of the first latch component 410 comprises a logical state equal to the initial logical state (S1 ) of the input signal 402 of the sequential logic circuit 400.
• the output 414 of the first latch component 410 initially comprises the logical state S1.
• the second latch component 430 initially comprises a latched state, due to the clock signal 420 comprising a logical low state.
• the input signal 402 comprised the logical state S1 , which was sampled and latched at that point by the second latch component 430.
• the output 434 of the second latch component 430 also initially comprises the logical state S1 , and thereby so does the output 404 of the sequential logic circuit 400.
• the sequential logic circuit 400 is arranged to comprise a rising edge triggered flip-flop circuit.
• data is expected to be received in advance of a rising edge within the clock signal 420 (i.e. changes in logical state at the first input 402 of the sequential logic circuit 400 are expected to occur and settle in advance of a transition from a low logical state to a high logical state within the clock signal 420).
• changes in logical state at the first input 402 of the sequential logic circuit 400 are expected to occur and settle in advance of a transition from a low logical state to a high logical state within the clock signal 420.
• Such a change in logical state of the first input 402 of the sequential logic circuit 400 from the initial logical state S1 to a second logical state S2 is illustrated at 510.
• the output 414 of the first latch component 410 also changes logical state at the same time, from the first logical state S1 to the second logical state S2.
• the output 434 of the second latch component 430 remains at the first logical state S1.
• the first latch component 410 samples and latches the signal received at its input 412; i.e. the first component 410 samples and latches the second logical state S2 of the input signal 402.
• the second latch component 430 switches from a latched state to a transparent state.
• the output 434 of the second latch component 430 changes from the previously latched first logical state S1 to the second logical state S2 of the input signal 402.
• the output 404 of the sequential logic circuit 400 takes on the current logical state of the input signal 402 upon the rising edge of the clock signal 420.
• the first latch component 410 switches from a latched state to a transparent state.
• the output 414 of the first latch component 410 remains at the second logical state S2 of the input signal 402.
• the second latch component 430 samples and latches the signal received at its input 432; i.e. the second logical state S2 of the input signal 402.
• the logical state of the output 404 of the sequential logic circuit 400 is latched at the current logical state of the input signal 402 (S2) until the next rising edge of the clock signal 420.
• This enables new data to be received at the input 402 of the sequential logic circuit 400 in advance of the next rising edge of the clock signal 420 without affecting the logical state of the output 404 of the sequential logic circuit 400.
• the first latch component 410 switches from a transparent state to a latched state. Since no change in logical state has occurred at the input 402 of the sequential logic circuit 400, the output 414 of the first latch component 410 samples and latches the second logical state S2 of the input signal 402 once again. At the same time, the second latch component 430 switches from a latched state to a transparent state. Again, since no change in logical state has occurred at the input 402 of the sequential logic circuit 400, the output 434 of the second latch component 430 remains at the second logical state S2 of the input signal 402.
• a subsequent change in logical state of the first input 402 of the sequential logic circuit 400 from the second logical state S2 to a third logical state S3 is illustrated at 550.
• this change in logical state 550 at the input 402 of the sequential logic circuit 400 occurs just after the transition of the clock signal 420 from a low logical state back to a high logical state, as illustrated at 540.
• this 'late' change in logical state 550 at the input 402 of the sequential logic circuit 400 represents a late arrival of data, and thus comprises a setup timing violation.
• the output 414 of the first latch component 410 remains latched at the second logical state S2.
• the second latch component 430 comprises a transparent state when the late change in logical state 550 occurs at the first input 402 of the sequential logic circuit
• the output 434 of the second latch component 430 changes from the second logical state S2 to the third logical state S3 substantially simultaneously with the first input 402 of the sequential logic circuit 400.
• the output 404 of the sequential logic circuit 400 also changes from the second logical state S2 to the third logical state S3 substantially simultaneously with the first input 402 of the sequential logic circuit 400, as illustrated at 560.
• data arriving late at the first input 402 of the sequential logic circuit 400 may be forwarded along a respective signal path substantially immediately upon receipt by the sequential logic circuit 400, despite arriving after the rising edge of the clock signal 420.
• the first latch component 410 switches from a latched state to a transparent state. Since a change in logical state 550 has occurred at the input 402 of the sequential logic circuit 400, the output 414 of the first latch component 410 changes from the second logical state S2 to the third logical state S3 of the input signal 402. At the same time, the second latch component 430 samples and latches the signal received at its input 432; i.e. the third logical state S3 of the input signal 402. In this manner, the logical state of the output 404 of the sequential logic circuit 400 is latched at the current (late arriving) logical state of the input signal 402 (S3) until the next rising edge of the clock signal 420.
• the clock signals provided to the first and second latch components 410, 430 are such that a transition of the second latch component 430 from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component 410 from a transparent state to a latched state for a time period for receiving late data.
• this is achieved by way of the second latch component 430 being arranged to receive the same clock signal 420 as received by the first latch component 410, but being arranged to comprise transparent and latched states upon opposing logical states of the clock signal 420 relative to the first latch component 410.
• a time period for receiving late data comprising, in this example, a duty cycle of the clock signal 420 (e.g. a half a clock cycle for a symmetrical clock signal 420), as illustrated at 580 in FIG. 5.
• a duty cycle of the clock signal 420 e.g. a half a clock cycle for a symmetrical clock signal 420
• late data that is received within this time period 580 is forwarded substantially immediately along the respective signal path.
• the signal path 610 comprises a plurality of sequential logic components, such as those illustrated at 620, 630, 640, one or more of which may be implemented by way of the sequential logic circuit 400 of FIG. 4.
• the sequential logic components 620, 630, 640 are sequentially coupled one after the other within the signal path 610, and arranged to receive a clock signal 650 output by a clock driver component 652, and propagated to the sequential logic components 620, 630, 640 via a clock distribution network, or tree, 655.
• the signal path 610 may comprise further logic, such as combinational logic, between each sequential logic component 620, 630, 640, such as illustrated generally at 625, 635.
• a data signal is synchronously propagated along the signal path 610 in accordance with the clock signal 650, whereby each sequential logic component 620, 630, 640 is arranged to forward the received data signal to the next sequential logic component 620, 630, 640 upon receipt of, in one example, a rising edge of the clock signal. In this manner, a data signal is propagated from one sequential logic component 620, 630, 640 to the next each clock cycle.
• sequential logic component 620 is implemented by way of the sequential logic circuit 400 of FIG. 4, if a setup timing violation occurs at sequential logic component 620, whereby a data signal arrives late at an input thereof as described above in relation to FIG. 4, the late data may be forwarded along the signal path 610 substantially immediately to the next sequential logic component 630 upon receipt by the sequential logic component 620. In this manner, even though the data arrived late at the first sequential logic component 620, it is still forwarded on to the second sequential logic component 630 within the relevant clock cycle.
• the sequential logic components 620, 630, 640 may be arranged to detect the late arrival of data, and to generate error signals upon detection of the late arrival of data. Accordingly, and as illustrated in FIG. 6, one or more of the sequential logic components 620, 630, 640 may be arranged to output an error signal 660 upon detection of the late arrival of data thereby, with the respective error signals 660 being provided to the clock driver component 652 via an error detect network, or tree, 665. For example, and as illustrated in FIG.
• the error detect network 665 may comprise an OR gate 670 arranged to receive at inputs thereof error signals 660 output by the sequential logic components 620, 630, 640, and to output to the clock driver component 652 an indication 675 of whether at least one of the sequential logic components 620, 630, 640 within the signal path 610 has detected the late arrival of data.
• the clock driver component 652 may postpone a next active clock edge (e.g. rising clock edge in the one example) of the clock signal 650 in order to extend a current clock cycle.
• the signal path 600 is provided with additional time to stabilize after the detection of the late arrival of data at one of the sequential logic components 620, 630, 640.
• the late data may be forwarded along the signal path 610 to the next sequential logic component 630 substantially immediately upon receipt by the sequential logic component 620.
• the late data may be allowed to 'catch up' and reach the second sequential logic component 630 before the end of the (extended) current clock cycle, thereby allowing the signal path 610 to stabilize following the late arrival of data at the first sequential logic component 620.
• the correct data may be maintained within the data path 610, albeit slightly delayed relative to the clock signal 650. Additionally, by postponing the clock signal 650 upon detection of late data, the signal path 610 is able to be stabilized to allow late data to catch up, maintaining the integrity of the data within the signal path 610. Accordingly, there is no need to 'flush' the data path 610, or to restore correct data to sections of the data path 610 in order to avoid corrupted data from propagating to other parts of the synchronous digital system 600.
• the time required for the clock signal 650 and error detect signal 660 to propagate through their respective networks 655, 665 may be such that an insufficiently short window of opportunity for postponing the next clock edge may exist.
• the arrival of late data may be detected by the first sequential logic component 620. Accordingly, the first sequential logic component 620 forwards the late data on to the second sequential logic component 630, and outputs an error detect signal 660.
• the sequential logic components 620, 630 are located at, say, a downstream end of the signal path 610, there may be insufficient time from the detection of the late data at the first sequential logic component 620 for the error detect signal 660 output thereby to propagate through the error detect network 665 to the clock driver component 652 early enough to enable the clock driver component 652 to delay the next clock edge following the detection of the late data for sequential logic components located, say, towards the upstream end of the signal path 610. Accordingly, two (or more) clock cycles may occur between the late arrival of data being detected at one of the sequential logic components 620, 630, 640, and the clock driver component 652 delaying a 'next' clock edge.
• the forwarded late data may reach the second sequential logic component 630 in time before the (non-postponed) next clock edge.
• the delay in forwarding the late data to the second sequential logic component 630 may result in that data also arriving late at the second sequential logic component 630, if the next clock edge is not postponed.
• the sequential logic component 630 (and subsequent sequential logic components) is (are) also implemented by way of the sequential logic circuit 400 of FIG.
• the late data may also be forwarded on by the second (and subsequent) sequential logic components 630.
• late data arriving may be forwarded through Subsequent sequential logic components implemented by way of the sequential logic circuit 400 of FIG. 4 even though a clock edge has not been postponed.
• the window of opportunity for postponing a clock edge of the clock signal 650 may be extended.
• data arriving late at the first sequential logic component 620 may be forwarded on by the first sequential logic component 620 within the relevant clock cycle.
• the delayed data may also be forwarded on by the second sequential logic component 630 within the relevant (subsequent) clock cycle to the third sequential logic component 640.
• the window of opportunity for postponing a clock edge of the clock signal 650 may be extended by a full clock cycle, since it is not necessary to delay a clock edge until the late data reaches third sequential logic component 640.
• the third sequential logic component 640 is also implemented by way of the sequential logic circuit 400 of FIG. 4, then that too would be able to forward the late data to a next subsequent sequential logic component (not shown), further extending the window of opportunity for postponing a clock edge of the clock signal 650 by a further full clock cycle.
• the window of opportunity for postponing a clock edge in order to enable the signal path 610 to stabilize following the detection of late data may be extended by a number of clock cycles, whereby the number of clock cycles up to which the window of opportunity may be extended is equal to the number of subsequent successive sequential logic components capable of forwarding late data (e.g. such as implemented by way of the sequential logic circuit 400 of FIG. 4), located downstream of the sequential logic component at which the late arrival of data is initially detected.
• the sequential logic circuit 400 of FIG. 4 enables a multi-level setup tolerant design in which a sequential logic component implementing the the sequential logic circuit 400 of FIG. 4 may be located, say, at a downstream end of a critical path within the synchronous digital system 600.
• a maximum possible delay for the propagation of error detect signals 660 and the clock signal 650 for (at least) the first sequential logic component 620 may be estimated from static timing analysis for the synchronous digital system 600 to identify a desired/required window of opportunity for postponing a clock edge in order to enable the signal path 610 to stabilize following the detection of late data by the sequential logic component at the downstream end of the critical path.
• One or more subsequent sequential logic components capable of forwarding late data may then be implemented immediately downstream of the first sequential logic component 620 as required in order to achieve the desired/required window of opportunity for postponing a clock edge.
• the sequential logic circuit 400 of FIG. 4 enables late data to be forwarded along the signal data path, substantially alleviating the need for data recovery following the late arrival of data.
• a multi-level setup of successive sequential logic components implementing such a sequential logic circuit may be provided to achieve a desired/required window of opportunity for delaying a clock edge in order to stabilize the signal path following the detection of late data.
• the sequential logic components 620, 630, 640 may be arranged to detect the late arrival of data, and to generate error signals upon detection of the late arrival of data.
• the sequential logic circuit 400 further comprises a comparator component 440, which in the illustrated example comprises an XOR (exclusive OR) gate.
• the comparator component 440 comprises a first input 442 operably coupled to the first latch component 410, in particular in the illustrated example to the output 414 of the first latch component 410, and arranged to receive an indication of a current logical state of the first latch component 410.
• the comparator component 440 further comprises a second input 444 operably coupled to the second latch component 430, between the clocked transfer gate 436 and latch circuit 438 thereof.
• the second input 444 of the comparator component 440 is arranged to receive an indication of a logical state of the first input 402 of the sequential logic circuit 400 when the second latch component 430 is in a transparent state.
• An output 446 of the comparator component 440 is arranged to provide an indication of whether the logical states of the signals received at the inputs 442, 444 thereof differ from one another.
• the output 446 of the comparator component 440 comprises a high logical state whenever the logical states of the two inputs 442, 444 thereof are not equal.
• the output 446 of the comparator component 440 comprises a high logical state upon the next falling clock edge of the clock signal 420, as illustrated at 590. Accordingly, by sampling and latching the output 446 of the sequential logic circuit 400 on the falling clock edge of the clock signal 420, the output 446 of the comparator component 440 may be used to provide the error detect signal 660 of a respective sequential logic component 620, 630, 640 of FIG. 6.
• the latching of the (or each) comparator output signal 446 of a sequential logic component 420, 430, 440 may be implemented either within the respective sequential logic component 420, 430, 440, or may be implemented at a later stage in the error detect network 665, or within the clock driver component 652. Alternatively, the output 446 may be filtered through a further AND gate, along the clock signal 420.
• the sequential logic circuit 400 is configurable to operate in a further mode of operation in which the data input 412 of the first latch component 410 is operably coupled to a second input 406 of the sequential logic circuit 400, and the data input 432 of the second latch component 430 is operably coupled to the output 414 of the first latch component 410.
• the data input 412 of the first latch component 410 is operably coupled to the second input 406 of the sequential logic circuit 400 via the first multiplexer component 450
• the data input 432 of the second latch component 430 is operably coupled to the output 414 of the first latch component 410 via the second multiplexer component 450.
• the first multiplexer component 450 is arranged to selectively output to the first latch component 410 a logical state of one of the first input 402 of the sequential logic circuit 400 and the second input 406 of the sequential logic circuit 400 in accordance with the control signal 460 received thereby
• the second multiplexer component 455 is arranged to selectively output to the second latch component 430 a logical state of one of the first input 402 of the sequential logic circuit 400 and the output 414 of the first latch component 410 in accordance with the control signal 460 received thereby.
• the sequential logic circuit 400 when configured to operate in the further operating mode, for example by way of the control signal 460 comprising, say, a logical state, the first latch component 410 receives at its data input 412 a data signal received at the second input 406 of the sequential logic circuit 400, and the second latch component 430 receives at its data input 432 a data signal output by the first latch component 410.
• the first and second latch component 410, 430 are configured in a conventional flip-flop arrangement, and the second input 406 may be used for, say, a scan chain implementation.
• the sequential logic circuit 400 further comprises a third latch component 470 comprising a data input/output 472 operably coupled to the second latch component 430, and a clock input 477 arranged to receive a clock signal, which in the illustrated example is the same clock signal 420 provided to the second latch component 430.
• the third latch component 470 is arranged to comprise a transparent state in which the third latch component 470 receives an indication of a current logical state of the second latch component 430 via the data input/output 472 thereof, upon the clock signal 420 received thereby comprising a first logical state, and a latched state in which the third latch component 470 outputs its current logical state to the second latch component 430 via the data input/output 472 thereof, upon the clock signal 420 received thereby comprising a second logical state.
• the third latch component 470 enables a previous cycle logical state for the sequential logic circuit 400 to be maintained, for example during state retention power gating (SRPG) or the like.
• SRPG state retention power gating
• FIG. 7 there is illustrated a simplified flowchart 700 of an example of a method of providing setup timing violation tolerance within a sequential logic circuit, such as may be implemented within the sequential logic circuit 400 of FIG. 4, and/or in one or more of the sequential logic components 620, 630, 640 of FIG. 6.
• the method starts at 710 and moves on to 720 with the receipt of an active clock edge, for example such as a rising clock edge in one example.
• an active clock edge for example such as a rising clock edge in one example.
• the method moves on to sampling a logical state at an input of the sequential logic circuit at 730, for example as performed by the first latching component 410 of FIG.
• the method moves on to 760 where a logical state at the output of the sequential logic circuit is latched, for example as performed by the second latching component 430 of FIG. 4.
• the time period for receiving late data may comprise a period equal to half a clock cycle period, for example whereby the output of the sequential logic circuit is latched upon receipt of a 'non-active' clock edge, for example such as a falling edge in the one example. The method then loops back to 720.
• the sequential logic circuit comprises a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby comprising a clock signal;
• the sequential logic circuit is arranged to operate in at least a first operating mode in which the data input of the first latch component and the data input of the second latch component are operably coupled to a first input of the sequential logic circuit, and in which the clock signals provided to the first and second latch components are such that a transition of the second latch component from a transparent state to a latched state is delayed relative to a corresponding transition of the first latch component from a transparent state to a latched state for a time period for receiving late data.
• the sequential logic circuit may further comprise a comparator component, such as an exclusive OR, XOR, gate, the comparator component being arranged to, at least when the sequential logic circuit is operating in the first operating mode and during the time period for receiving late data, receive at a first input thereof an indication of a latched logical state of the first latch component, receive at a second input thereof an indication of a logical state of the first input of the sequential logic circuit, and output from an output thereof an indication of whether the logical state of the first input of the sequential logic circuit differs from the latched logical state of the first latch component.
• the second input of the comparator component may be operably coupled to the second latch component and arranged to receive an indication of a current logical state of the second latch component.
• the sequential logic circuit may be configurable to operate in at least one further mode of operation in which the data input of the first latch component is operably coupled to a second input of the sequential logic circuit.
• the sequential logic circuit may comprise a first multiplexer component comprising a first data input operably coupled to the first input of the sequential logic circuit, a second data input operably coupled to the second input of the sequential logic circuit, an output operably coupled to the data input of the first latch component, and a control input arranged to receive a control signal.
• the first multiplexer component may be arranged to selectively output to the first latch component a logical state of one of the first input of the sequential logic circuit and the second input of the sequential logic circuit in accordance with the control signal received thereby.
• the sequential logic circuit may be configurable to operate in at least one further mode of operation in which the data input of the second latch component is operably coupled to the output of the first latch component.
• the sequential logic circuit may comprise a second multiplexer component comprising a first data input operably coupled to the first input of the sequential logic circuit, a second data input operably coupled to the output of the first latch component, an output operably coupled to the data input of the second latch component, and a control input arranged to receive a control signal.
• the second multiplexer component may be arranged to selectively output to the second latch component a logical state of one of the first input of the sequential logic circuit and the output of the first latch component in accordance with the control signal received thereby.
• the sequential logic circuit may further comprise a third latch component comprising a data input/output operably coupled to the second latch component, and a clock input arranged to receive a clock signal.
• the third latch component may be arranged to comprise a transparent state in which the third latch component receives an indication of a current logical state of the second latch component via the data input/output thereof, upon the clock signal received thereby comprising a first logical state, and a latched state in which the third latch component outputs its current logical state to the second latch component via the data input/output thereof, upon the clock signal received thereby comprising a second logical state.
• connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections.
• the connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa.
• plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner.
• single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.
• Each signal described herein may be designed as positive or negative logic.
• the signal In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero.
• the signal In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one.
• any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.
• any arrangement of components to achieve the same functionality is effectively 'associated' such that the desired functionality is achieved.
• any two components herein combined to achieve a particular functionality can be seen as 'associated with' each other such that the desired functionality is achieved, irrespective of architectures or intermediary components.
• any two components so associated can also be viewed as being 'operably connected', or 'operably coupled', to each other to achieve the desired functionality.
• any reference signs placed between parentheses shall not be construed as limiting the claim.
• the word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim.
• the terms 'a' or 'an,' as used herein, are defined as one or more than one.

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• 2012
  • 2012-05-30 US US14/398,868 patent/US9112489B2/en not_active Expired - Fee Related
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